MR0A16A | DigiCamel IC Datasheet

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MR0A16A EVERSPIN | Alldatasheet

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PDF pages: 22

Technical content

One memory replaces FLASH, SRAM, EEPROM and BBSRAM in system for simpler, more efficient designs
Improves reliability by replacing battery-backed SRAM
Automatic data protection on power loss

FEATURES

3.3 Volt power supply
Fast 35ns read/write cycle
SRAM compatible timing
Unlimited read & write endurance
Commercial, Industrial, and Extended Temperatures
Data non-volatile for >20 years at temperature
RoHS-compliant TSOP2 and BGA packages available
All products meet MSL-3 moisture sensitivity level
Automotive AEC-Q100 Grade 1 option available 64K x 16 MRAM Memory The MR0A16A is a 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as 65,536 words of 16 bits. The MR0A16A offers SRAM compatible 35 ns read/write timing with unlimited en- durance. Data is always non-volatile for greater than 20 years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. MR0A16A is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR0A16B is available in a small footprint 48-pin ball grid array (BGA) package and a 44-pin thin small outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM products and other nonvolatile RAM products. The MR0A16A provides highly reliable data storage over a wide range of temperatures. The product is avail- able with commercial temperature (0 to +70 °C), industrial temperature (-40 to +85 °C), extended tempera- ture (-40 to +105 °C), and Automotive AEC-Q100 Grade 1 (-40 to +125°) temperature range options. INTRODUCTION BENEFITS 44-pin TSOP2 48-ball BGA RoHS

MR0A16A Rev. 8.3 3/2018 Copyright © 2018 Everspin Technologies MR0A16A Figure 1 – Block Diagram Table 1 – Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable UB Upper Byte Enable LB Lower Byte Enable DQ Data I/O VDD Power Supply VSS Ground DC Do Not Connect NC No Connection BLOCK DIAGRAM AND PIN ASSIGNMENTS CHIP ENABLE BUFFER OUTPUT ENABLE BUFFER ADDRESS BUFFER WRITE ENABLE BUFFER G E UPPER BYTE OUTPUT ENABLE LOWER BYTE OUTPUT ENABLE 64K x 16 BIT MEMORY ARRAY ROW DECODER COLUMN DECODER SENSE AMPS LOWER BYTE WRITE DRIVER LOWER BYTE OUTPUT BUFFER UPPER BYTE OUTPUT BUFFER FINAL WRITE DRIVERS UPPER BYTE WRITE ENABLE LOWER BYTE WRITE ENABLE W BYTE ENABLE BUFFER UB A[15:0] 816 DQL[7:0]

8 DQU[15:8]

Copyright © 2018 Everspin Technologies MR0A16A Rev. 8.3 3/2018 44-Pin TSOP Type 2 48-Pin BGA Table 2 – Operating Modes E 1 G 1 W 1 LB 1 UB 1 Mode VDD Current DQL[7:0] 2 DQU[15:8] 2 H X X X X Not selected ISB1, ISB2 Hi-Z Hi-Z L H H X X Output disabled IDDR Hi-Z Hi-Z L X X H H Output disabled IDDR Hi-Z Hi-Z L L H L H Lower Byte Read IDDR DOut Hi-Z L L H H L Upper Byte Read IDDR Hi-Z DOut L L H L L Word Read IDDR DOut DOut L X L L H Lower Byte Write IDDW Din Hi-Z L X L H L Upper Byte Write IDDW Hi-Z Din L X L L L Word Write IDDW Din Din Notes: 1. H = high, L = low, X = don’t care 2. Hi-Z = high impedance A A A VDD E VSS W A A A 22 44 A G VSS VDD DC A A A A A A A A A DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 VDD VSS DQU8 DQU9 DQU10 DQU11 DQU12 DQU13 UB LB DQU14 DQU15 1 2 3 4 5 6 LB G A0 A1 A2 NC A DQU8 UB A3 A4 E DQL0 B DQU9 DQU10 A5 A6 DQL1 DQL2 C VSS DQU11 A13 DQL3 VDD D VDD DQU12 NC A14 DQL4 VSS E DQU14 DQU13 A12 A11 DQL5 DQL6 F DQU15 A A15 W DQL7 G

7 A 9A 8

Figure 2 – MR0A16A Package Pinouts OPERATING MODES

MR0A16A Rev. 8.3 3/2018 Copyright © 2018 Everspin Technologies MR0A16A This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, normal precautions should be taken to avoid application of any voltage greater than maximum rated voltages to these high- impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 1 Symbol Parameter Temp Range Package Value Unit VDD Supply voltage 2 - - -0.5 to 4.0 V VIN Voltage on any pin 2 - - -0.5 to VDD + 0.5 V IOUT Output current per pin - - ±20 mA TBIAS Temperature under bias Commercial - -10 to 85 Industrial - -45 to 95 Extended - -45 to 110 AEC Q-100 Grade 1 - -45 to 130 Tstg Storage Temperature - - -55 to 150 °C TLead Lead temperature during solder (3 minute max) - - 260 °C Hmax_write Maximum magnetic field during write Commercial TSOP2, BGA 2,000 A/mIndustrial, Ex- tended BGA 2,000 TSOP2 10,000 AEC-Q100 Grade 1 TSOP2 2,000 Hmax_read Maximum magnetic field during read or standby Commercial TSOP2, BGA 8,000 A/mIndustrial, Ex- tended BGA 8,000 TSOP2 10,000 AEC-Q100 Grade 1 TSOP2 8,000 Table 3 – Absolute Maximum Ratings ABSOLUTE MAXIMUM RATINGS Notes appear on the next page.

Copyright © 2018 Everspin Technologies MR0A16A Rev. 8.3 3/2018 Notes: for MR0A16A Absolute Maximum Ratings: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2. All voltages are referenced to VSS. 3. Power dissipation capability depends on package characteristics and use environment. Symbol Parameter Temp Range Min Typical Max Unit VDD Power supply voltage 1 All 3.0 3.3 3.6 V VWI Write inhibit voltage All 2.5 2.7 3.0 1 V VIH Input high voltage All 2.2 - VDD + 0.3 2 V VIL Input low voltage All -0.5 3 - 0.8 V TA Ambient Temperature under bias Commercial 0 70 Industrial -40 85 Extended -40 105 AEC Q-100 Grade 1 4 -40 125 Table 4 – Operating Conditions OPERATING CONDITIONS Notes: 1. There is a 2 ms startup time once VDD exceeds VDD,(min). See Power Up and Power Down Sequencing below. 4. AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2 years out of 20 years life.)

MR0A16A Rev. 8.3 3/2018 Copyright © 2018 Everspin Technologies MR0A16A Figure 3 – Power Up and Power Down Timing The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be observed when power returns above VDD(min). Power Up and Power Down Sequencing BROWNOUT or POWER LOSS NORMAL OPERATION VDD READ/WRITE INHIBITED VWI 2 ms READ/WRITE INHIBITED VIH STARTUP NORMAL OPERATION 2 ms E W RECOVER VIH

Copyright © 2018 Everspin Technologies MR0A16A Rev. 8.3 3/2018 Symbol Parameter Condition Min Max Unit Ilkg(I) Input leakage current All - ±1 μA Ilkg(O) Output leakage current All - ±1 μA VOL Output low voltage IOL = +4 mA - 0.4 V IOL = +100 μA VSS + 0.2 VOH Output high voltage IOH = -4 mA 2.4 - V IOH = -100 μA VDD - 0.2 Table 5 – DC Characteristics Table 6 – Power Supply Characteristics Symbol Parameter Condition Temp Range Typical Max Unit IDDR AC active supply current - read modes 1 IOUT= 0 mA, VDD= max All 55 80 mA IDDW AC active supply current - write modes1 VDD= max Commercial 105 155 mA Industrial 105 165 Extended 105 165 AEC-Q100 Grade 1 105 165 ISB1 AC standby current VDD= max, E = VIH No other restrictions on other inputs All 18 28 mA ISB2 CMOS standby current E ≥ VDD - 0.2 V and VIn ≤ VSS + 0.2 V or ≥ VDD - 0.2 V VDD = max, f = 0 MHz 9 12 mA Notes: 1. All active current measurements are measured with one address transition per cycle and at minimum cycle time. DC CHARACTERISTICS

Copyright © 2018 Everspin Technologies MR0A16A Rev. 8.3 3/2018 Symbol Parameter 1 Min Max Unit tAVAV Read cycle time 35 - ns tAVQV Address access time - 35 ns tELQV Enable access time 2 - 35 ns tGLQV Output enable access time - 15 ns tBLQV Byte enable access time - 15 ns tAXQX Output hold from address change 3 - ns tELQX Enable low to output active 3 3 - ns tGLQX Output enable low to output active 3 0 - ns tBLQX Byte enable low to output active 3 0 - ns tEHQZ Enable high to output Hi-Z 3 0 15 ns tGHQZ Output enable high to output Hi-Z3 0 10 ns tBHQZ Byte high to output Hi-Z3 0 10 ns Table 9 – Read Cycle Timing Notes: 1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. 2. Addresses valid before or at the same time E goes low. 3. This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage.

Copyright © 2018 Everspin Technologies MR0A16A Rev. 8.3 3/2018 Symbol Parameter 1 Min Max Unit tAVAV Write cycle time 2 35 - ns tAVWL Address set-up time 0 - ns tAVWH Address valid to end of write (G high) 18 - ns tAVWH Address valid to end of write (G low) 20 - ns tWLWH tWLEH Write pulse width (G high) 15 - ns tWLWH tWLEH Write pulse width (G low) 15 - ns tDVWH Data valid to end of write 10 - ns tWHDX Data hold time 0 - ns tWLQZ Write low to data Hi-Z 3 0 12 ns tWHQX Write high to output active 3 3 - ns tWHAX Write recovery time 12 - ns Table 10 – Write Cycle Timing 1 (W Controlled) Notes: 1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. All write cycle timings are referenced from the last valid address to the first transition address. 3. This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given voltage or temperate, tWLQZ(max) < tWHQX(min)

MR0A16A Rev. 8.3 3/2018 Copyright © 2018 Everspin Technologies MR0A16A W (WRITE ENABLE) A (ADDRESS) E (CHIP ENABLE) UB, LB (BYTE ENABLED) t AVAV t AVWH t WHAX t AVWL t WLEH t WLWH DATA VALID t DVWH t WHDX Q (DATA OUT) D (DATA IN) t WLQZ t WHQX Hi -Z Hi -Z Figure 8 – Write Cycle Timing 1 (W Controlled)

Copyright © 2018 Everspin Technologies MR0A16A Rev. 8.3 3/2018 Symbol Parameter 1 Min Max Unit tAVAV Write cycle time 2 35 - ns tAVEL Address set-up time 0 - ns tAVEH Address valid to end of write (G high) 18 - ns tAVEH Address valid to end of write (G low) 20 - ns tELEH tELWH Enable to end of write (G high) 15 - ns tELEH tELWH Enable to end of write (G low) 3 15 - ns tDVEH Data valid to end of write 10 - ns tEHDX Data hold time 0 - ns tEHAX Write recovery time 12 - ns A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) Q (DATA OUT) D (DATA IN) tAVAV tAVEH tEHAX tELEH tEHDXtDVEH tAVEL Hi-Z tELWH Data Valid UB, LB (BYTE ENABLE) Table 11 – Write Cycle Timing 2 (E Controlled) Notes: 1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. All write cycle timings are referenced from the last valid address to the first transition address. 3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. Figure 9 – Write Cycle Timing 2 (E Controlled)

MR0A16A Rev. 8.3 3/2018 Copyright © 2018 Everspin Technologies MR0A16A Symbol Parameter 1 Min Max Unit tAVAV Write cycle time 2 35 - ns tAVBL Address set-up time 0 - ns tAVBH Address valid to end of write (G high) 18 - ns Address valid to end of write (G low) 20 - ns tBLEH tBLWH Write pulse width (G high) 15 - ns tBLEH tBLWH Write pulse width (G low) 15 - ns tDVBH Data valid to end of write 10 - ns tBHDX Data hold time 0 - ns tBHAX Write recovery time 12 - ns W (WRITE ENABLE) A (ADDRESS) E (CHIP ENABLE) UB, LB (BYTE ENABLED) t AVAV t AVEH t BHAX t AVBL t BLEH t BLWH Data Valid t DVBH t BHDX Q (DATA OUT) D (DATA IN) Hi -Z Hi -Z Table 12 – Write Cycle Timing 3 (LB/UB Controlled) Notes: 1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after Wgoes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2. All write cycle timings are referenced from the last valid address to the first transition address. Figure 10 – Write Cycle Timing 3 (UB/LB Controlled)

ORDERING INFORMATION

Table 13 – Part Numbering System

MR0A16A Rev. 8.3 3/2018 Copyright © 2018 Everspin Technologies MR0A16A Table 14 – MR0A16A Ordering Part Numbers Temp Grade Temp Package Shipping Ordering Part Number Commercial 0 to +70 °C 44-TSOP2 Tray MR0A16AYS35 Tape and Reel MR0A16AYS35R 48-BGA Tray MR0A16AMA35 Tape and Reel MR0A16AMA35R Industrial -40 to +85 °C 44-TSOP2 Tray MR0A16ACYS35 Tape and Reel MR0A16ACYS35R 48-BGA Tray MR0A16ACMA35 Tape and Reel MR0A16ACMA35R Extended -40 to +105 °C 44-TSOP2 Tray MR0A16AVYS35 Tape and Reel MR0A16AVYS35R 48-BGA Tray MR0A16AVMA35 Tape and Reel MR0A16AVMA35R AEC-Q100 Grade 1 -40 to 125 °C 44-TSOP2 Tray MR0A16AMYS35 Tape and Reel MR0A16AMYS35R

Copyright © 2018 Everspin Technologies MR0A16A Rev. 8.3 3/2018 Notes: 1. Dimensions and tolerances per ASME Y14.5M - 1994. 2. Dimensions in Millimeters. 3. Dimensions do not include mold protru- sion. 4. Dimension does not include DAM bar protrusions. 5. DAM Bar protrusion shall not cause the lead width to exceed 0.58. PACKAGE OUTLINE DRAWINGS Figure 11 – 44-pin TSOP2

MR0A16A Rev. 8.3 3/2018 Copyright © 2018 Everspin Technologies MR0A16A Figure 12 – 48-ball BGA Package Outline Notes: 1. Dimensions in Millimeters. 2. Dimensions and tolerances per ASME Y14.5M - 1994. 3. Maximum solder ball diameter measured paral- lel to DATUM A 4. DATUM A, the seating plane is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any ef- fect of mark on top surface of package.

0 Jun 18, 2007 Initial Advanced Information Release

1 Sept 21, 2007 Table 6, Applied Values to TBD’s in IDD Specifications

2 Nov 12, 2007 Table 2, Changed IDDA to IDDR or IDDW

3 Sep 12, 2008

Reformat Datasheet for EverSpin, Add BGA Packaging Information, Add Tape & Reel Part Numbers, Add Power Sequencing Info, Correct IOH spec of VOH to -100 uA, Correct ac Test Conditions. 4 Feb 28, 2011 Add TSOPII Lead Cross-Section, Add Production Note. Converted to new document format. 5 Dec 9, 2011 Figure 2.1 cosmetic update. Figure 5.2 BGA package outline drawing revised for ball size. Updated logo and contact information.

6 August 6, 2012

Revised Table 1 and Figure 1 to be correct for x16 device. Revised magnetic immunity ratings for TSOP2 Industrial Grade. Revised figure 3. Complete document reformat and restructure.

7 October 14,

2013 Added AEC-Q100 Grade 1 product option.

8 February 19,

2015 Revised package outline for BGA. Ball size to 0.25 / 0.35 mm. 8.1 May 19, 2015 Revised contact information on Contact Us page. 8.2 June 11, 2015 Correction to Japan Sales Office telephone number. 8.3 March 23, 2018 Revised contact information on Contact Us page.

REVISION HISTORY

MR0A16A Rev. 8.3 3/2018 Copyright © 2018 Everspin Technologies MR0A16A Everspin Technologies, Inc. Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representa- tion or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or inci- dental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/or specifications can and do vary in differ- ent applications and actual performance may vary over time. All operating parameters including “Typicals” must be validated for each customer ap- plication by customer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other ap- plication in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Tech- nologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. Copyright © Everspin Technologies, Inc. 2018 How to Reach Us: Home Page: www.everspin.com World Wide Information Request WW Headquarters - Chandler, AZ 5670 W. Chandler Blvd., Suite 100 Chandler, Arizona 85226 Tel: +1-877-480-MRAM (6726) Local Tel: +1-480-347-1111 Fax: +1-480-347-1175 support@everspin.com orders@everspin.com sales@everspin.com Europe, Middle East and Africa Everspin Europe Support support.europe@everspin.com Japan Everspin Japan Support support.japan@everspin.com Asia Pacific Everspin Asia Support support.asia@everspin.com Filename: EST00354_MR0A16A_Datasheet_Rev8.3 032318 HOW TO CONTACT US

Product Information

MR0A16A specifications and overview.

Summary

64K x 16 MRAM Memory Rev. 8.3 3/2018

Description

64K x 16 MRAM Memory Rev. 8.3 3/2018

Source title MR0A16A Datasheet(PDF) - Everspin Technologies Inc.

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