MM54C14 SS | Alldatasheet

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CMOS High Voltage Logic – MM54C14 Hex Schmitt Trigger Inverter in bare die form  Wide supply voltage range: 3V to 15V  High noise immunity: 0.70 V CC (typ.)  Low power TTL compatibility: o 0.40 V CC (typ.) o 0.20 V CC (guaranteed)  Hysteresis: o 0.40 V CC (typ.) o 0.20 V CC (guaranteed). Rev 1.0 17/02/2023 Features: The MM54C14 Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N-channel and P-channel enhancement transistors. The positive and negative going threshold voltages, VT+ and VT- , show low variation with respect to temperature (typ. 0.0005V/°C at VCC = 10V), and hysteresis, VT+ - VT- ≥ 0.2 VCC is guaranteed. All inputs are protected from damage due to static discharge by diode clamps to VCC and GND.

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The following part suffixes apply:  No suffix - MIL-STD-883 /2010B Visual Inspection  “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT  “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Die Dimensions in µm (mils) 1680 (66) 1070 (42) Die Size (Unsawn) 1680 x 1070 66.14 x 42.13 µm mils Minimum Bond Pad Size 105 x 105 4.713 x 4.13 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si Supply Formats: Mechanical Specification  Default – Die in Waffle Pack (100 per tray capacity)  Sawn Wafer on Tape – On request  Unsawn Wafer – On request  Die Thickness <> 350µm(14 Mils) – On request  Assembled into Ceramic Package – On request Page 1 of 5 www.siliconsupplies.com A ll data sheet.com

d CMOS High Voltage Logic – MM54C14 Rev 1.0 17/02/2023 Pad Layout and Functions Logic Diagram Function Table INPUT A OUTPUT Y L H H L Pad 14 = VCC Pad 7 = GND COORDINATES (µm) DIE ID PAD FUNCTION X Y 1 1A 90 75 2 1Y 435 85 3 2A 600 75 4 2Y 885 85 5 3A 1135 80 6 3Y 1485 210

7 GND 1485 390

14 VCC 95 625

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www.siliconsupplies.com Rev 1.0 17/02/2023 CMOS High Voltage Logic – MM54C14 Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT Voltage at any input pin VIN -0.3 to VCC + 0.3 V Voltage at any output pin VOUT -0.3 to VCC + 0.3 V Operating VCC range VCC 3 to 15 V Absolute maximum VCC V CC(MAX) 18 V Maximum Power Dissipation2 P D 700 mW Operating Temperature Range TA -55 to +125 °C Storage Temperature Range TSTG -65 to +150 °C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CMOS TO CMOS VCC = 5V 3.0 3.6 4.3 V VCC = 10V 6.0 6.8 8.6 V Positive Going Threshold Voltage VT+ VCC = 15V 9.0 10.0 12.9 V VCC = 5V 0.7 1.4 2.0 V VCC = 10V 1.4 3.2 4.0 V Negative Going Threshold Voltage VT- VCC = 15V 2.1 5.0 6.0 V VCC = 5V 1.0 2.2 3.6 V VCC = 10V 2.0 3.6 7.2 V Hysteresis VT+ - VT- VCC = 15V 3.0 5.0 10.8 V VCC = 5V, IO = -10µA 4.5 - - V Logical “1” Output Voltage VOUT(1) VCC = 10V, IO = -10µA 9.0 - - V VCC = 5V, IO = 10µA - - 0.5 V Logical “0” Output Voltage VOUT(0) VCC = 10V, IO = 10µA - - 1.0 V Logical “1” Input Current IIN(1) VCC = 15V, VIN = 15V - 0.005 1.0 µA Logical “0” Input Current IIN(0) VCC = 15V, VIN = 0V -1.0 -0.005 - µA Supply Current ICC VCC =15V,VIN=0V/15V - 0.05 15 µA VCC = 5V, VIN = 2.5V - 20 - µA VCC = 10V, VIN = 5V - 200 - µA Supply Current3 ICC VCC = 15V, VIN = 7.5V - 600 - µA 3. Only one of the six inputs is at ½ VCC; the others are either at VCC or GND. 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic DIP package, results in die form are dependent on die attach and assembly method. A ll data sheet.com

www.siliconsupplies.com Rev 1.0 16/07/2021 CMOS High Voltage Logic – MM54C14 4. ot production tested in die fo rm, characterized by chip design. N 5. Used to determine the no-load dynamic power consumption: PD = CPD VCC f + ICC VCC. Figure 1 – Transfer Characteristics Figure 2 – Guaranteed Trip Point Range PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CMOS/LPTTL INTERFACE Logical “1” Input Voltage VIN(1) VCC = 5V 4.3 - - V Logical “0” Input Voltage VIN(0) VCC = 5V - - 0.7 V Logical “1” Output Voltage VOUT(1) VCC= 4.5V,IO= -360µA 2.4 - - V Logical “0” Output Voltage VOUT(0) VCC =4.5V, IO = 360µA - - 0.4 V OUTPUT DRIVE CURRENT TA = 25°C VCC = 5V, VOUT = 0V -1.75 -3.3 - mA Output Source Current (P-Channel) ISOURCE VCC = 10V, VOUT = 0V -8.0 -15 - mA VCC = 5V, VOUT = VCC 1.75 3.6 - mA Output Source Current (N-Channel) ISINK VCC = 10V, VOUT = VCC 8.0 16 - mA DYNAMIC ELECTRICAL CHARACTERISTICS4 TA = 25°C, CL = 50pF unless otherwise stated VCC = 5V - 220 400 ns Propagation Delay from Input to Output tPD0, tPD1 VCC = 10V - 80 200 ns Input Capacitance CIN Any Input - 5.0 - pF Power Dissipation Capacitance5 CPD Per Gate - 20 - pF Typical Characteristics A ll data sheet.com

www.siliconsupplies.com CMOS High Voltage Logic – MM54C14 Rev 1.0 16/07/2021 Typical Characteristics continued Figure 3 – Waveform DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. A ll data sheet.com