MK32VT864

MK32VT864 OKI | Alldatasheet

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MK32VT864-10YE (98.07.24) Page 1/11 Semiconductor MK32VT864-10YE 8,388,608 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK):

DESCRIPTION

The Oki MK32VT864-10YE is a fully decoded, 8,388,608 x 64bit synchronous dynamic random access memory composed of eight 64Mb DRAMs (4Mx16) in TSOP packages mounted with decoupling capacitors on a 144-pin glass epoxy Small-outline Dual-in-Line Package supports any application where high density and large capacity of storage memory are required, like for example Mobile PC or PDAs.

FEATURES

8-Meg Word x 64-bit (2Bank 8Byte) organization 144-pin Small-Outline Dual Inline Memory Module Single 3.3V power supply, ±0.3V tolerance Input :LVTTL compatible Output :LVTTL compatible Refresh : 4,096 cycles / 64 ms Programmable data transfer mode

• /CAS latency (2, 3)
• Burst length (2, 4, 8)
• Data scramble (sequential, interleave) /CAS before /RAS auto-refresh, Self-refresh capability Serial Presence Detect (SPD) With EEPROM PRODUCT ORGANIZATION Operation Access Time (Max.) Product Name Frequency (Max.) tAC2 tAC3 MK32VT864-10YE

100 MHz

9.0ns 9.0ns Note. Specification are subject to change without notice.

MK32VT864-10YE (98.07.24) Page 2/11 BLOCK DIAGRAM CLK0 CLK1 /CS0 CKE0 DQMB0 DQMB4 DQ0 DQ7 DQ8 DQ15 DQMB1 UDQM DQ40 DQ47 DQMB5 DQMB2 DQMB6 DQ0 DQ7 DQ16 DQ23 DQ0 DQ7 DQ48 DQ55 DQMB7 DQ0 DQ7 DQ24 DQ31 DQ0 DQ7 DQ56 DQ63 DQMB3 DQ0 DQ7 LDQM CKE /CS DQ32 DQ39 Vcc Vss SDRAMs 0.22uF x8 /RAS,/CAS,/WE A0-A11,BA0,BA1 á SCL SDA A0 A1 Serial PD DQ15 DQ8 UDQM DQ1 DQ8 LDQM DQ16 DQ9 CKE /CS UDQM DQ1 DQ8 LDQM CKE /CS DQ16 DQ9 UDQM DQ1 DQ8 LDQM DQ16 DQ9 CKE /CS DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 UDQM LDQM CKE /CS LDQM UDQM CKE /CS LDQM DQ0 DQ7 UDQM CKE /CS DQ15 DQ8 LDQM UDQM CKE /CS /CS1 CKE1 DQ0 DQ7 DQ15 DQ8 DQ0 DQ7 DQ15 DQ8 DQ0 DQ7 DQ15 DQ8 Note. The Value of all resistors is 10Ω. MODULE OUTLINE (Front) (Back) 143 144

MK32VT864-10YE (98.07.24) Page 3/11 PIN CONFIGURATION Front Back side Front side Back side Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name Vss Vss N.C CLK1 DQ0 DQ32 Vss Vss DQ1 DQ33 N.C N.C DQ2 DQ34 N.C N.C DQ3 DQ35 Vcc Vcc Vcc Vcc DQ16 DQ48 DQ4 DQ36 DQ17 DQ49 DQ5 DQ37 DQ18 DQ50 DQ6 DQ38 DQ19 DQ51 DQ7 DQ39 Vss Vss Vss Vss DQ20 DQ52 DQMB0 DQMB4 DQ21 DQ53 DQMB1 DQMB5 DQ22 DQ54 Vcc Vcc DQ23 100 DQ55 101 Vcc 102 Vcc 103 104 105 106 BA0 Vss Vss 107 Vss 108 Vss DQ8 DQ40 109 110 BA1 DQ9 DQ41 111 A10 112 A11 DQ10 DQ42 113 Vcc 114 Vcc DQ11 DQ43 115 DQMB2 116 DQMB6 Vcc Vcc 117 DQMB3 118 DQMB7 DQ12 DQ44 119 Vss 120 Vss DQ13 DQ45 121 DQ24 122 DQ56 DQ14 DQ46 123 DQ25 124 DQ57 DQ15 DQ47 125 DQ26 126 DQ58 Vss Vss 127 DQ27 128 DQ59 N.C N.C 129 Vcc 130 Vcc N.C N.C 131 DQ28 132 DQ60 CLK0 CKE0 133 DQ29 134 DQ61 Vcc Vcc 135 DQ30 136 DQ62 /RAS /CAS 137 DQ31 138 DQ63 /WE CKE1 139 Vss 140 Vss /CS0 N.C 141 SDA 142 SCL /CS1 N.C 143 Vcc 144 Vcc Pin Name Function Pin Name Function Vcc Power Supply (3.3V) /RAS Row Address Strobe Vss Ground (0V) /CAS Column Address Strobe CLK# System Clock /WE Write Enable /CS# Chip Select DQMB# Data Input / Output Mask CKE# Clock Enable DQ# Data Input / Output A0-A11 Address SDA Data I/O for SPD BA0, BA1 Bank Select Address SCL CLK input for SPD N.C No Connection

MK32VT864-10YE (98.07.24) Page 4/11 SERIAL PRESENCE DETECT Byte No. SPD Hex Value Remark Notes Defines the number of bytes written into SPD memory 128 byte Total number of bytes of SPD memory 256 byte Fundamental memory type SDRAM Number of rows 12 rows Number of columns 8 columns Number of module banks 2 bank Data width of this assembly 64 bits ... Data width continuation 0 bits Voltage interface level LVTTL Cycle time (CL=3) CL=3 tCC=10ns Access time from CLK (CL=3) CL=3 tAC3=9ns DIMM configuration type Non Parity Refresh rate / type Normal / Self Primary SDRAM width x16 Error checking SDRAM width Minimum CLK delay tCCD: 1 CLK Burst lengths supported 2, 4, 8 Number of banks on each SDRAM 4 banks /CAS latency 2,3 /CS latency /WE latency SDRAM module attributes SDRAM device attributes : General Cycle time (CL=2) CL=2 tCC2=15ns Access time from CLK (CL=2) CL=2 tAC2=9ns Cycle time (CL=1) Not support Access time from CLK (CL=1) Not support Minimum ROW pulse width tRP=30ns /RAS to /RAS bank delay tRRD=20ns /RAS to /CAS delay tRCD=30ns Minimum /RAS precharge time tRAS=60ns Density of each bank on module 64MB Command and Address Signal Input Setup Time 3ns Command and Address Signal Input Hold Time 1ns Data Signal Input Setup Time 3ns Data Signal Input Hold Time 1ns 36-61 00-00 R.F.U SPD data revision code 0.2 Checksum for byte 0-62 64-71 Manufacturer’s JEDEC ID code Manufacturing location 73-90 Manufacturer’s part number MK32VT864-10YE 91, 92 20, 20 Revision code 93-125 XX-XX R.F.U 126 Intel specification frequency 66MHz 127 Intel specification /CAS latency CL=2, 3 128-255 FF-FF Unused storage locations

MK32VT864-10YE (98.07.24) Page 5/11

ELECTRICAL CHARACTERISTICS

Voltage on any pin relative to Vss VIN, VOUT -0.5 to Vcc + 0.5 V Vcc supply voltage Vcc, VccQ -0.5 to 4.6 V Storage temperature Tstg - 55 to 125 Power dissipation PD* W Short circuit current IOS mA Operating temperature Topr 0 to 70 *: Ta=25°C Recommended Operating Conditions (Voltages referenced to Vss = 0V) Parameter Symbol Min. Typ. Max. Unit Power supply voltage Vcc, VccQ 3.0 3.3 3.6 V Input high voltage VIH 2.0 Vcc + 0.3 V Input low voltage VIL -0.3 0.8 V Capacitance (Vcc = 3.3V ± 0.3 V , Ta = 25°C f = 1MHz) Parameter Symbol Max. Unit Input capacitance(A0-A11, BA0, BA1) CIN1 pF Input capacitance(/CS0, /RAS, /CAS, /WE, CKE0, UDQM, LDQM) CIN2 pF I/O capacitance(DQ0 - DQ63 ) CI/O pF

MK32VT864-10YE (98.07.24) Page 6/11 DC CHARACTERISTICS (Vcc = 3.3V ± 0.3V, Ta = 0 to 70°C) Condition Module Spec. Parameter Symbol CKE Others Min. Max. Unit Note Output High Voltage VOH IOH = -2.0mA 2.4 V Output Low Voltage VOL IOL = 2.0mA 0.4 V Input Leakage Current ILI -40 µA Output Leakage Current ILO -20 µA Average Power Supply Current (Operating) ICC1 CKE ≥ VIH tCC=min. tRC=min. No Burst 740 mA 1, 2 Power Supply Current (Stand by) ICC2 CKE ≥ VIH tCC=min. 320 mA Average Power Supply Current (Clock Suspension) ICC3S CKE ≤ VIL tCC=min. 220 mA Average Power Supply Current (Active Stand by) ICC3 CKE ≥ VIH, /CS ≥ VIH tCC=min. 540 mA Power Supply Current (Burst) ICC4 CKE ≥ VIH tCC=min. 1000 mA 1, 2 Power Supply Current (Auto-Refresh) ICC5 CKE ≥ VIH tCC=min. tRC=min. 900 mA Average Power Supply Current (Self-Refresh) ICC6 CKE ≤ 0.2V tCC=min. mA Average Power Supply Current (Power down) ICC7 CKE ≤ VIL tCC=min. mA Notes: 1. Measured with the output open. 2. Address and data can be changed once or not be changed during one cycle. 3. Address and data can be changed once or not be changed during two cycle. MODE SET ADDRESS KEYS /CAS Latency Burst Type Burst Length CL BT BT=0 BT=1 Reserved Sequential Reserved Reserved Reserved Interleave Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Note: A7, A8, A9, A10, A11, BA0, BA1 and All should stay "L" during mode set cycle.

MK32VT864-10YE (98.07.24) Page 7/11 POWER ON SEQUENCE 1. With inputs in NOP state, turn on the power supply and enter the system clock. 2. After the Vcc voltage has reached the specified level, take a pause of 200µs or more with the input being NOP. 3. Enter the precharge all bank command. 4. Apply CBR auto-refresh eight or more times. 5. Enter the mode register setting command.

MK32VT864-10YE (98.07.24) Page 8/11 AC CHARACTERISTIC NOTE 1, 2 . Parameter Symbol Module Spec. Unit Note Min. Max. Clock Cycle Time CL=3 tCC ns CL=2 ns Access Time from Clock CL=3 tAC ns 3, 4 CL 2 ( 3.3+0.3 ns 3, 4 Clock "H" Pulse Time tCH ns Clock "L" Pulse Time tCL ns Input Setup Time tSI ns Input Hold Time tHI ns Output Low Impedance Time from Clock tOLZ ns Output High Impedance Time from Clock tOHZ ns Output Hold from Clock tOH ns /RAS Cycle Time tRC ns /RAS Precharge Time tRP ns /RAS Active Time tRAS 1,000,000 ns /RAS to /CAS Delay Time tRCD ns Write Recovery Time tWR ns /RAS to /RAS Bank Active Delay Time tRRD ns Refresh Time tREF ms Power-down Exit Set-up Time tPDE tSI+1CLK ns Input Level Transition Time tT ns /CAS to /CAS Delay Time (Min) ICCD Cycle Clock Disable Time from CKE ICKE Cycle Data Output High Impedance Time from UDQM, LDQM IDOZ Cycle Data Input Mask Time from DQMB IDOD Cycle Data Input Time from Write Command IDWD Cycle Data Output High Impedance Time from Precharge Command. IROH Cycle Active Command Input Time from MODE Register Set Command Input (Min) IMRD Cycle Write Command Input Time from Output IOWD Cycle NOTES: 1) AC measurements assume tT=1ns. 2) The reference level for timing of input signals is 1.4V. 3) This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF (RLoad is 50ohm). 4) An access time is measured at 1.4V. 5) If tT is longer than 1ns, the reference level for timing of input signals are VIH and VIL. OUTPUT 50pF OUTPUT LOAD 50Ω 1.4v

MK32VT864-10YE (98.07.24) Page 9/11 FUNCTION TRUTH TABLE (Table1) (1/2) Current State /CS /RAS /CAS /WE BA ADDR Action Idle H X X X X X NOP L H H H X X NOP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA Row Active L L H L BA A10 NOP 4 L L L H X X Auto-Refresh or Self-Refresh 5 L L L L L OP Code Mode Register write Row Active H X X X X X NOP L H H X X X NOP L H L H BA CA, A10 Read L H L L BA CA, A10 Write L L H H BA RA ILLEGAL 2 L L H L BA A10 Precharge L L L X X X ILLEGAL Read H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L BA X Burst Stop L H L H BA CA, A10 Term Burst, start new Burst Read 3 L H L L BA CA, A10 Term Burst, start new Burst Write 3 L L H H BA RA ILLEGAL 2 L L H L BA A10 Term Burst, execute Row Precharge L L L X X X ILLEGAL Write H X X X X X NOP (Continue Row Active after Burst ends) L H H H X X NOP (Continue Row Active after Burst ends) L H H L BA X Burst Stop L H L H BA CA, A10 Term Burst, start new Burst Read 3 L H L L BA CA, A10 Term Burst, start new Burst Write 3 L L H H BA RA ILLEGAL 2 L L H L BA A10 Term Burst, execute Row Precharge 3 L L L X X X ILLEGAL Read with H X X X X X NOP (Continue Burst to End and enter Row Precharge) Auto Precharge L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 L H L H BA CA, A10 ILLEGAL 2 L H L L X X ILLEGAL L L H X BA RA, A10 ILLEGAL 2 L L L X X X ILLEGAL Write with H X X X X X NOP (Continue Burst to End and enter Row Precharge) Auto Precharge L H H H X X NOP (Continue Burst to End and enter Row Precharge) L H H L BA X ILLEGAL 2 L H L H BA CA, A10 ILLEGAL 2 L H L L X X ILLEGAL L L H X BA RA, A10 ILLEGAL 2 L L L X X X ILLEGAL

MK32VT864-10YE (98.07.24) Page 10/11 FUNCTION TRUTH TABLE (Table1) (2/2) Current State /CS /RAS /CAS /WE BA ADDR Action Precharge H X X X X X NOP Æ Idle after tRP L H H H X X NOP Æ Idle after tRP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 NOP 4 L L L X X X ILLEGAL Write H X X X X X NOP Recovery L H H H X X NOP L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 L L L X X X ILLEGAL Row Active H X X X X X NOP Row Active after tRCD L H H H X X NOP Row Active after tRCD L H H L BA X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10 ILLEGAL 2 L L L X X X ILLEGAL Refresh H X X X X X NOP Æ Idle after tRC L H H X X X NOP Æ Idle after tRC L H L X X X ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL Auto Resister H X X X X X NOP Access L H H H X X NOP L H H L X X ILLEGAL L H L X X X ILLEGAL L L X X X X ILLEGAL ABBREVIATIONS RA = Row Address BA = Bank Address NOP = No Operation command CA = Column Address AP = Auto Precharge Notes: 1. All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. Satisfy the timing of tCCD and tWR to prevent bus contention. 4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10. 5. Illegal if any bank is not idle.

MK32VT864-10YE (98.07.24) Page 11/11 FUNCTION TRUTH TABLE (CKE) (Table2) Current State(n) CKEn-1 CKEn /CS /RAS /CAS /WE ADDR Action Self Refresh H X X X X X X INVALID L H H X X X X Exit Self Refresh Æ ABI L H L H H H X Exit Self Refresh Æ ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self Refresh) Power Down H X X X X X X INVALID L H H X X X X Exit Power Down Æ ABI L H L H H H X Exit Power Down Æ ABI L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L X X X X ILLEGAL 6 L L X X X X X NOP (Continue power down mode) All Banks idle 6 H H X X X X X Refer to Table 1 (ABI) H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H L X ILLEGAL H L L L L H X Enter Self Refresh H L L L L L X ILLEGAL L L X X X X X NOP Any State H H X X X X X Refer to Operations in Table 1 Other than H L X X X X X Begin Clock Suspend Next Cycle Listed Above L H X X X X X Enable Clock of Next Cycle L L X X X X X Continue Clock Suspension Notes: 6. Power-down and self refresh can be entered only when all the banks are in an idle state.