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Technical content
Datasheet sections
Features
High-Performance/High Memory Content ■ ARM Cortex R4, 8KB D-Cache, 8KB I-Cache ■ 32-Bit ARMv7 architecture ■ 205 DMIPS ■ 2MB Internal Flash ■ 48KB Internal EEFlash (Data Flash) ■ 208KB Internal RAM with ECC Graphics ■ 2D-Graphics Engine ■ 1MB Embedded VRAM ■ Max Resolution: 1024 pixel hor. x 1024 pixel ver. ■ 4 Display Layer plus Alpha blending layer ■ Display Controller/TCON ■ Max. Pixel clock of 40MHz ■ Bit Blitter ■ Signature Unit ■ Command Sequencer ■ TTL and RSDS Output (RGB888) ■ Dithering for Display with low color resolution Connectivity ■ 2x CAN, 2 x LIN-USART, 3 x SPI, 1 x I2C, 2 x I2S ■ Up to six Stepper Motor Control (SMC) outputs ■ HS-SPI (memory mapped access) Safety Features/Security Features ■ Multiple Memory Production Units (MPU) ■ Peripheral Protection Units (PPU) ■ Timing Protection Unit (TPU) ■ Cyclic Redundancy Checks (CRC of Flash, Cache and RAM) ■ Watchdog ■ Flash-, Debug- and Test-Security ■ Secure Hardware Extension (SHE) ❐ Self-contained secure area ❐ Random Number generator ❐ Secure repository for cryptographic keys ❐ AES encryption/decryption block Other Features ■ Up/Down Counters ■ Programmable Pulse Generators ■ Analog-to-Digital Converters - 50 channels ■ Sound Generator ■ Free Running/Reload Timers ■ Real Time Clock (RTC) ■ Input Capture Units, Output Compare units ■ 32 external Interrupts Low Power ■ Switchable Power Domains ■ 16KB Retention RAM ■ Flexible Clock Control ■ Debugging/Testing ■ ARM Coresight Debug and Trace ■ Debugging via JTAG Interface ■ Boundary Scan Characteristics ■ 5V and 3.3V capable IOs ■ Ta: 40 °C to +105 °C ■ Package: LQFP-176
Applications
■ Hybrid Automotive Instruments Cluster with pointers and TFT display ■ Classical Automotive Instruments Cluster with pointers Errata: For information on silicon errata, see Errata on page 389. Details include trigger conditions, devices affected, and proposed workaround.
Document Number: 002-05678 Rev. *A Page 2 of 418 MB9EF226 - Titan Block Diagram Power Domain Power Domain Modules PD1 Clockgroup (Osc, PLL, CSV), Contro lgroup (EIC, NMI, RTC, SYSC, WDG, TPU, IRQ Control, Power Control) PD2 Peripheral bus 0 (ADC, FRT, ICU, OCU, USART, I2C, SMC, PPG), Peripheral bus 1 (SG, CAN, USART, FRT, ICU, OCU, PPG), Peripheral bus 3 (RLT, UDC, GPIO, PPU), Peripheral bus 4 (SPI, I2S), On-Chip Debug, Trace, SRAM, CRC, Cortex R4, SHE, MPU, I-Cache, D-Cache, TCM, TCFlash, EEFlash, TPU, BootROM, HS-SPI, MLB, IRIS-SDL PD4 RetRAM Controlgroup (1 ch) I2C USART (1 ch) I2C0_SCLi I2C0_SDAi I2C0_SCLo I2C0_SDAo SMC (6 ch) SMCn_M1 SMCn_P1 SMCn_M2 SMCn_P2 16−bit PPG (16 ch) I/O Timer (4 ch) OCU 0/1 ICU 2/3 FRT 0/1/2/3 FRTn_FRCK ICUn_IN0, ICUn_IN1 OTDn,OTDn_I,OTDn_G,OTDn_GI USART0_SCKi USART0_SIN USART0_SCKo USART0_SOT PERI0_RBUS Peripheral Bus Bridge 0 10−bit ADC (50 ch) PPGn_PPGA PPGn_PPGB PPG_ETRG0˘.. PPG_ETRG3 ADC0_EDGI AVRH AVDD5 AVSS5 Memory Map (1 ch) HS−SPI DMA0_DEOP_ACK0, DMA0_DEOP_ACK1 DMA0_DREQ_ACK0, DMA0_DREQ_ACK1 DMA0_DREQ0, DMA0_DREQ1 DMA0_DSTP0, DMA0_DSTP1 DMA0_DSTP_ACK0, DMA0_DSTP_ACK1 DMA0_DEOP0, DMA0_DEOP1 (8 ch) DMA RLTn_TOUT RLTn_TINRLT (10 ch) (1 ch) UDC Peripheral Bus Bridge 3 GPIOn_mi PERI3_eRBUS (117 pins) GPIO CLK_PERI3_PD2 UDC0_UDOT0 UDC0_UDOT1 PPU GPIOn_mo SPIn_CLKi SPIn_DATA0i˘. SPIn_DATA3i SPIn_SSi SPIn_SSO[1]˘. SPIn_SSO[3] SPIn_SSo SPIn_DATA[0]o˘. SPIn_DATA[3]o SPIn_CLKo SPI (3 ch) I2S I2Sn_ECLK I2Sn_SCKi I2Sn_SDi I2Sn_WSi I2Sn_SDo I2Sn_WSo (2 ch) I2Sn_SCKo FRTn_FRCK ICUn_IN0, ICUn_IN1 OTDn,OTDn_I,OTDn_G,OTDn_GI 16−bit PPG (8 ch) USART (1 ch) PPG_ETRG0˘.. PPG_ETRG3 PPGA PPGB ECC 16KRetRAM CSV/CLK−out PLL’s Oscillators Clock group RSTX X1A X0A MODE High Performance Matrix (HPM) PERI5_AHB BUS CLK_SYS_PD3CLK_CFG_PD1 CLK_PERI1_PD2 CLK_PERI0_PD2 CLK_DMA_PD2 CLK_TRACE_PD2 CLK_DBG_PD2 CLK_HPM_PD2CLK_HPM_PD2CLK_HPM_PD2 UDC0_AIN0, UDC0_AIN1 UDC0_BIN0, UDC0_BIN1 UDC0_ZIN0, UDC0_ZIN1 Peripheral Bus Bridge 4 PERI1_RBUS SG (1 ch) CAN Peripheral Bus Bridge 1 CANn_TX CANn_RX SG_SGA SG_SGO USART6_SCKi USART6_SIN USART6_SCKo USART6_SOT I/O Timer (4 ch) FRT 16/17/18/19 ICU 18/19 OCU 16/17 Memories CLK_HPM_PD2 CLK_CFG_PD4 SRAM DBG0_TRACE0.... DBG0_TRACE7 DBG0_CTL DBG0_CLK Cortex R4Cortex R4 MPUTrace Debug On−chip D−Cache I−Cache 8 ch CRC SHE CLK_PERI4_PD2 PERI4_SLAVE AHB BUS TCFlash TCMRAMEEFlash EIC Watchdog Power Control NMI TPU IRQ Control SYSC_CKOT RTC_WOTRTC SYSC_CKOTX EIC0_INT00.... EIC0_INT31 SYSC BootROM EIC0_NMI (2 ch) 16K 128K CLK_HPM_PD2 48K option 64K
128 MHz
GFXSPI_CLKi GFX0_DCLKI GFXSPI_SSi GFXSPI_DATA0i.... GFXSPI_DATA3i GFX0_TSIG[0].... GFX0_TSIG[11] GFX0_DISP[0].... GFX0_DISP[25] Pixel CLK_GFX_PD5 Display Engine Command Controller Bus Matrix Seq HS−SPI Signature VRAM TCON SPI−MEM 512KB/1M Graphical Subsystem "IRIS−SDL " 256MB MLB MLBn_CLKi MLBn_SIGo MLBn_DATo (1 ch)
Table 1. Overview
Table 2. Device Features ■ One background and 3 alpha blended foreground layers. ■ One dedicated alpha layer.
Table 2. Device Features (Continued)
- Electronically Erasable and Programmable Read-Only Memory (EEPROM).
■ Implements Miyaguchi-Preneel compression function.
Table 3. Memory Map
90000000 Reserved
80000000 HSSPI0_MEMORY
60000000 Reserved
40000000 GFXMEM
06000000 Reserved
Table 4. HSSPI0 Memory Map Table 5. Memory and Config (MEMORY_CONFIG) AHB Bus
Table 6. MCU_CONFIG AHB Bus Memory Map Table 7. PERI0_RBUS Memory Map Table 7. PERI0_RBUS Memory Map (Continued)
Table 8. PERI1_RBUS Memory Map Table 9. PERI3_eRBUS Memory Map Table 10. PERI4_SLAVE AHB Bus Memory Map Table 8. PERI1_RBUS Memory Map (Continued)
non-modulated clock. Table 12 provides the distribution. be unlocked before configuring and can be locked for protection. Table 11. PERI5_AHB Bus Memory Map Table 12. Clock Modulation for Resources Table 10. PERI4_SLAVE AHB Bus Memory Map (Continued) Table 13. Lock/Unlock Values for FCR4 Protection Module
which contain information about the module number, the version and possible patches. Table 14. Module ID List
The same die will be used for two packages. QFP-176 and QFP-240 packages will be used for MB9EF226. The package code is FPT-176P-M07. Also an optional QFP-240 package with trace pins is shown in Figure 1. The package code is FPT-240P-M06. Figure 1. QFP-240 Pin Assignment
Table 15. QFP-240 Pin Assignment
4 VSS 44 VDP3
5 VSS 45 VDP3
10 VDP5 50 VSS
11 VSS 51 P2_08
12 VSS 52 P2_09
13 VDP3 53 VDP3
14 VDP3 54 VDP3
15 P1_30 55 P2_10
16 P1_31 56 P2_11
17 P1_32 57 VSS
18 P1_33 58 VSS
19 P1_34 59 P2_12
20 DBG0_TRACE0 60 P2_13
21 P1_35 61 VDD
22 P1_36 62 VDD
23 P1_37 63 DBG0_TRACE4
24 P1_38 64 P2_14
25 DBG0_TRACE1 65 P2_15
26 P1_61 66 VDP3
27 P1_62 67 VDP3
28 P1_60 68 DBG0_TRACE5
29 VSS 69 P2_16
30 VSS 70 P2_17
31 VDP3 71 VSS
32 VDP3 72 P2_18
33 P2_00 73 P2_19
34 P2_01 74 VDP3
35 VSS 75 VDP3
36 VSS 76 DBG0_TRACE6
37 DBG0_TRACE2 77 P2_20
38 P2_02 78 P2_21
39 P2_03 79 VDD
40 VDD 80 VDD
81 P2_22 122 P1_43
82 P2_23 123 DBG0_TRACE13
83 VSS 124 P1_44
84 VSS 125 P1_45
85 DBG0_TRACE7 126 DBG0_TRACE14
86 P2_24 127 P1_46
87 P2_25 128 P1_47
88 VDP3 129 DBG0_TRACE15
89 VSS 130 VDD
90 DBG0_TRACE8 131 VDD
91 P1_48 132 VDP3
92 P1_49 133 VDP3
93 P1_50 134 VSS
94 P1_51 135 VSS
95 DBG0_TRACECTL 136 DVSS
96 P1_52 137 DVSS
97 P1_53 138 DVCC
98 VDP3 139 DVCC
99 VSS 140 P1_00
100 DBG0_TRACECLK 141 P1_01
101 P1_54 142 P1_02
102 P1_55 143 P1_03
103 P1_56 144 P1_04
104 P1_57 145 P1_05
105 DBG0_TRACE9 146 P1_06
106 P1_58 147 P1_07
107 P1_59 148 DVSS
108 VDP3 149 DVSS
109 DBG0_TRACE10 150 DVCC
110 VSS 151 DVCC
111 P1_26 152 P1_08
112 P1_27 153 P1_09
113 DBG0_TRACE11 154 P1_10
114 P1_28 155 P1_11
115 P1_29 156 P1_12
116 P1_39 157 P1_13
117 P1_40 158 P1_14
118 DBG0_TRACE12 159 P1_15
119 P1_41 160 DVSS
120 P1_42 161 DVSS
121 VDP3 162 DVCC
Table 15. QFP-240 Pin Assignment (Continued)
163 DVCC 204 NB
164 P1_16 205 P2_33
165 P1_17 206 P2_34
166 P1_18 207 P2_35
167 P1_19 208 P2_36
168 P1_20 209 P2_37
169 P1_21 210 VSS
170 P1_22 211 VSS
171 P1_23 212 VDD
172 DVSS 213 VDD
173 DVCC 214 NB
174 NB 215 P2_38
175 AVSS5 216 P2_39
176 AVRL5 217 P2_40
177 AVRH5 218 P2_41
178 AVDD5 219 NB
179 NB 220 P2_42
180 VDP5 221 P2_43
181 VSS 222 P2_48
182 VSS 223 P2_49
183 P0_24 224 VSS
184 P0_25 225 VSS
185 P0_40 226 VDP5
186 P0_41 227 NB
187 VSS 228 VDP5
188 VSS 229 P2_50
189 VDD 230 NB
190 VDD 231 P2_51
191 P0_42 232 P0_62
192 P0_43 233 P0_63
193 NB 234 JTAG_TDO
194 P0_44 235 JTAG_TDI
195 P0_45 236 NB
196 P0_46 237 NB
197 P0_47 238 JTAG_TMS
198 VSS 239 JTAG_TCK
199 VSS 240 JTAG_NTRST
200 VDP5
201 P0_48
202 P0_49
203 P2_32
Figure 2. QFP-176 Pin Assignment
Table 16. QFP-176 Package Pinout
1 MODE 40 P2_10
3 X0 42 VSS
4 VSS 43 P2_12
5 X0A 44 P2_13
6 X1A 45 VDD
7 RSTX 46 P2_14
8 VDP5 47 P2_15
9 VSS 48 VDP3
10 VDP3 49 P2_16
11 P1_30 50 P2_17
12 P1_31 51 VSS
13 P1_32 52 P2_18
14 P1_33 53 P2_19
15 P1_34 54 VDP3
16 P1_35 55 P2_20
17 P1_36 56 P2_21
18 P1_37 57 VDD
19 P1_38 58 P2_22
20 P1_61 59 P2_23
21 P1_62 60 VSS
22 P1_60 61 P2_24
23 VSS 62 P2_25
24 VDP3 63 VDP3
25 P2_00 64 VSS
26 P2_01 65 P1_48
27 VSS 66 P1_49
28 P2_02 67 P1_50
29 P2_03 68 P1_51
30 VDD 69 P1_52
31 P2_04 70 P1_53
32 P2_05 71 VDP3
33 VDP3 72 VSS
34 P2_06 73 P1_54
35 P2_07 74 P1_55
36 VSS 75 P1_56
37 P2_08 76 P1_57
38 P2_09 77 P1_58
39 VDP3 78 P1_59
79 VDP3 118 DVCC
80 VSS 119 P1_16
81 P1_26 120 P1_17
82 P1_27 121 P1_18
83 P1_28 122 P1_19
84 P1_29 123 P1_20
85 P1_39 124 P1_21
86 P1_40 125 P1_22
87 P1_41 126 P1_23
88 P1_42 127 DVSS
89 P1_43 128 DVCC
90 P1_44 129 AVSS5
91 P1_45 130 AVRH5
92 P1_46 131 AVDD5
93 P1_47 132 VDP5
94 VDD 133 VSS
95 VDP3 134 P0_24
96 VSS 135 P0_25
97 DVSS 136 P0_40
98 DVCC 137 P0_41
99 P1_00 138 VSS
100 P1_01 139 VDD
101 P1_02 140 P0_42
102 P1_03 141 P0_43
103 P1_04 142 P0_44
104 P1_05 143 P0_45
105 P1_06 144 P0_46
106 P1_07 145 P0_47
107 DVSS 146 VSS
108 DVCC 147 VDP5
109 P1_08 148 P0_48
110 P1_09 149 P0_49
111 P1_10 150 P2_32
112 P1_11 151 P2_33
113 P1_12 152 P2_34
114 P1_13 153 P2_35
115 P1_14 154 P2_36
116 P1_15 155 P2_37
117 DVSS 156 VSS
157 VDD 173 JTAG_TDI
Table 16. QFP-176 Package Pinout (Continued)
158 P2_38 174 JTAG_TMS
159 P2_39 175 JTAG_TCK
160 P2_40 176 JTAG_NTRST
161 P2_41
162 P2_42
163 P2_43
164 P2_48
165 P2_49
166 VSS
167 VDP5
168 P2_50
169 P2_51
170 P0_62
171 P0_63
172 JTAG_TDO
configuration, since GPIO_PPERn enables corresponding pin of the device. Note Since writing GPIO PPERn registers are required for both Portmux & resource-mux registers. Table 17. Port Multiplexing
1 CAN1_TX PPG1_PP
Table 17. Port Multiplexing (Continued)
Table 18. RICFG0_ADC
- The ADC0ZPDEN register is write-only-once protected.
Table 18. RICFG0_ADC (Continued)
- The ADC0ZPDEN register is write-only-once protected.
- The ADC0ZPDEN register is write-only-once protected.
Table 19. RICFG0
Table 19. RICFG0 (Continued)
Table 20. RICFG1
Table 20. RICFG1 (Continued)
Table 21. RICFG3
Table 21. RICFG3 (Continued)
Table 22. RICFG4
Table 22. RICFG4 (Continued)
Table 23. RICFG7
Table 23. RICFG7 (Continued)
Table 24. RICFG8
Table 25. Pin Circuit Type QFP-240
4 VSS50
5 VSS50
9 VDD50
10 VDD50
11 VSS50O
12 VSS50
13 VDD33
14 VDD33
15 BIDI33
16 BIDI33
17 BIDI33
18 BIDI33
19 BIDI33
20 BIDI33
21 BIDI33
22 BIDI33
23 BIDI33
24 BIDI33
25 BIDI33
26 BIDI33
27 BIDI33
28 BIDI33
29 VSS33
30 VSS33
31 VDD33
32 VDD33
33 RSDS
34 RSDS
35 VSS33
36 VSS33
37 BIDI33
38 RSDS
39 RSDS
40 VDD12L
41 VDD12L
42 RSDS
43 RSDS
44 VDD33
45 VDD33
46 BIDI33
47 RSDS
48 RSDS
49 VSS33
50 VSS33
51 RSDS
52 RSDS
53 VDD33
54 VDD33
55 RSDS
56 RSDS
57 VSS33
58 VSS33
59 RSDS
60 RSDS
61 VDD12L
62 VDD12L
63 BIDI33
64 RSDS
65 RSDS
66 VDD33
67 VDD33
68 BIDI33
69 RSDS
70 RSDS
71 VSS33
72 RSDS
73 RSDS
74 VDD33
75 VDD33
76 BIDI33
77 RSDS
78 RSDS
79 VDD12L
80 VDD12L
81 RSDS
Table 25. Pin Circuit Type QFP-240 (Continued)
82 RSDS
83 VSS33
84 VSS33
85 BIDI33
86 RSDS
87 RSDS
88 VDD33
89 VSS33
90 BIDI33
91 TTL33
92 TTL33
93 TTL33
94 TTL33
95 BIDI33
96 TTL33
97 TTL33
98 VDD33
99 VSS33
100 BIDI33
101 TTL33
102 TTL33
103 TTL33
104 TTL33
105 BIDI33
106 TTL33
107 TTL33
108 VDD33
109 BIDI33
110 VSS33
111 BIDI33
112 BIDI33
113 BIDI33
114 BIDI33
115 BIDI33
116 BIDI33
117 BIDI33
118 BIDI33
119 BIDI33
120 BIDI33
122 BIDI33
123 BIDI33
124 BIDI33
125 BIDI33
126 BIDI33
127 BIDI33
128 BIDI33
129 BIDI33
130 VDD12L
131 VDD12L
132 VDD33
133 VDD33
134 VSS33
135 VSS33
136 HVSS
137 HVSS
138 HVDD
139 HVDD
140 SMC
141 SMC
142 SMC
143 SMC
144 SMC
145 SMC
146 SMC
147 SMC
148 HVSS
149 HVSS
150 HVDD
151 HVDD
152 SMC
153 SMC
154 SMC
155 SMC
156 SMC
157 SMC
158 SMC
159 SMC
160 HVSS
161 HVSS
162 HVDD
163 HVDD
164 SMC
165 SMC
166 SMC
167 SMC
168 SMC
169 SMC
170 SMC
171 SMC
172 HVSS
173 HVDD
175 AVSS5
176 AVRL5
177 AVRH5
178 AVCC5
179 BIDI50
180 VDD50
181 VSS50
182 VSS50
183 BIDI50
184 BIDI50
185 BIDI50
186 BIDI50
187 VSS50
188 VSS50
189 VDD12H
190 VDD12H
191 BIDI50
192 BIDI50
194 BIDI50
195 BIDI50
196 BIDI50
197 BIDI50
198 VSS50
199 VSS50
200 VDD50
201 BIDI50
202 BIDI50
203 BIDI50
205 BIDI50
206 BIDI50
207 BIDI50
208 BIDI50
209 BIDI50
210 VSS50
211 VSS50
212 VDD12H
213 VDD12H
215 BIDI50
216 BIDI50
217 BIDI50
218 BIDI50
220 BIDI50
221 BIDI50
222 BIDI50
223 BIDI50
224 VSS50
225 VSS50
226 VDD50
228 VDD50
229 BIDI50
231 BIDI50
232 I2C
233 I2C
234 JTAGO
235 JTAGIUP
238 JTAGIUP
239 JTAGIUP
240 JTAGIDN
Table 26. Pin Circuit Type of QFP-176
8 VDD50
9 VSS50
10 VDD33
11 BIDI33
12 BIDI33
13 BIDI33
14 BIDI33
23 VSS33
24 VDD33
25 RSDS
26 RSDS
27 VSS33
28 RSDS
29 RSDS
30 VDD12L
31 RSDS
32 RSDS
33 VDD33
35 RSDS
37 RSDS
39 VDD33
40 RSDS
41 RSDS
42 VSS33
44 RSDS
45 VDD12L
46 RSDS
48 VDD33
49 RSDS
50 RSDS
51 VSS33
53 RSDS
57 VDD12L
58 RSDS
60 VSS33
61 RSDS
62 RSDS
63 VDD33
64 VSS33
65 TTL33
66 TTL33
67 TTL33
68 TTL33
69 TTL33
70 TTL33
71 VDD33
72 VSS33
73 TTL33
74 TTL33
75 TTL33
76 TTL33
77 TTL33
78 TTL33
79 VDD33
Table 26. Pin Circuit Type of QFP-176 (Continued)
80 VSS33
81 BIDI33
82 BIDI33
83 BIDI33
84 BIDI33
86 BIDI33
87 BIDI33
88 BIDI33
89 BIDI33
91 BIDI33
92 BIDI33
93 BIDI33
94 VDD12L
95 VDD33
96 VSS33
97 HVSS
98 HVDD
99 SMC
100 SMC
101 SMC
102 SMC
103 SMC
104 SMC
105 SMC
106 SMC
107 HVSS
108 HVDD
109 SMC
110 SMC
111 SMC
112 SMC
113 SMC
114 SMC
115 SMC
116 SMC
117 HVSS
118 HVDD
119 SMC
120 SMC
121 SMC
122 SMC
123 SMC
124 SMC
125 SMC
126 SMC
127 HVSS
128 HVDD
129 AVSS5
130 AVRH5
131 AVCC5
132 VDD50
133 VSS50
134 BIDI50
135 BIDI50
136 BIDI50
137 BIDI50
138 VSS50
139 VDD12H
140 BIDI50
141 BIDI50
142 BIDI50
143 BIDI50
144 BIDI50
145 BIDI50
146 VSS50
147 VDD50
148 BIDI50
149 BIDI50
150 BIDI50
151 BIDI50
152 BIDI50
153 BIDI50
154 BIDI50
155 BIDI50
156 VSS50
157 VDD12H
158 BIDI50
159 BIDI50
160 BIDI50
161 BIDI50
162 BIDI50
163 BIDI50
164 BIDI50
165 BIDI50
166 VSS50
167 VDD50
168 BIDI50
169 BIDI50
170 I2C
171 I2C
172 JTAGO
173 JTAGIUP
174 JTAGIUP
175 JTAGIUP
176 JTAGIDN
Table 27. IO Circuit Type
00 Hysteresis 20% / 80%
Table 27. IO Circuit Type (Continued)
01 Automotive 50% / 80%
11 CMOS 20% / 80%
pull-down resistor: 50k approx.
Figure 3. QFP-240 Package Dimension
Figure 4. QFP-176 Package Dimension
This section shows the allocation of interrupt and interrupt vector/interrupt register. Table 28. Interrupt Table
0 SYSCIRQ Status Interrupt from System Controller (SYSC_SYSSTSR:RUNDN is set
1 WDGIRQ
15 MLB0CINT
16 MLB0SINT
22 GFXIRQ0
23 GFXIRQ1
30 ADC0IRQ
31 ADC0IRQ2
32 ADC0IRQR
33 ADC0IRQP
34 RRCFGIRQERR
35 SRCFGIRQERR
36 TCFCFGIRQ
37 EECFGIRQERR
38 IRQ0IRQERR
41 EECFGIRQ
42 EICU0IRQ
43 HSSPI0IRQRX HSSPI0 Receive Interrupt
44 HSSPI0IRQTX HSSPI0 Transmit Interrupt
45 SHE
48 SHE
49 SPI0IRQRX SPI0 Receive Interrupt
50 SPI0IRQTX SPI0 Transmit Interrupt
52 SPI1IRQRX SPI1 Receive Interrupt
53 SPI1IRQTX SPI1 Transmit Interrupt
55 SPI2IRQRX SPI2 Receive Interrupt (check SPI2_RXF:[6:0] for detailed RX interrupt
56 SPI2IRQTX SSPI2 Transmit Interrupt (check SPI2_TXF:[6:0] for detailed TX interrupt
61 CAN0IRQ
62 CAN1IRQ
69 EIC0IRQ0
Table 28. Interrupt Table (Continued)
70 EIC0IRQ1
71 EIC0IRQ2
72 EIC0IRQ3
73 EIC0IRQ4
74 EIC0IRQ5
75 EIC0IRQ6
76 EIC0IRQ7
77 EIC0IRQ8
78 EIC0IRQ9
79 EIC0IRQ10
80 EIC0IRQ11
81 EIC0IRQ12
82 EIC0IRQ13
83 EIC0IRQ14
84 EIC0IRQ15
85 EIC0IRQ16
86 EIC0IRQ17
87 EIC0IRQ18
88 EIC0IRQ19
89 EIC0IRQ20
90 EIC0IRQ21
91 EIC0IRQ22
92 EIC0IRQ23
93 EIC0IRQ24
94 EIC0IRQ25
95 EIC0IRQ26
96 EIC0IRQ27
97 EIC0IRQ28
98 EIC0IRQ29
99 EIC0IRQ30
100 EIC0IRQ31
101 RTCIRQ Real Time Clock Interrupt
102 SG0IRQ
104 FRT0IRQ
105 FRT1IRQ
106 FRT2IRQ
107 FRT3IRQ
112 FRT16IRQ
113 FRT17IRQ
114 FRT18IRQ
115 FRT19IRQ
124 ICU2IRQ0 Input Capture Unit 2 c hannel 0 Interrupt (ICU2_ICEICS01:IDSE0)
125 ICU2IRQ1 Input Capture Unit 2 c hannel 1 Interrupt (ICU2_ICEICS01:IDSE1)
126 ICU3IRQ0 Input Capture Unit 3 c hannel 0 Interrupt (ICU3_ICEICS01:IDSE0)
127 ICU3IRQ1 Input Capture Unit 3 c hannel 1 Interrupt (ICU3_ICEICS01:IDSE1)
132 ICU18IRQ0 Input Capture Unit 18 c hannel 0 Interrupt (ICU18_ICEICS01:IDSE0)
133 ICU18IRQ1 Input Capture Unit 18 c hannel 1 Interrupt (ICU18_ICEICS01:IDSE1)
134 ICU19IRQ0 Input Capture Unit 19 ch annel 0 Interrupt (ICU19_ICEICS01:IDSE0)
135 ICU19IRQ1 Input Capture Unit 19 ch annel 1 Interrupt (ICU19_ICEICS01:IDSE1)
136 OCU0IRQ0 Output Compare Unit 1 channel 0 Interrupt (OCU0_OSR01:ICP0)
137 OCU0IRQ1 Output Compare Unit 0 channel 1 Interrupt (OCU0_OSR01:ICP1)
138 OCU1IRQ0 Output Compare Unit 1 channel 0 Interrupt (OCU1_OSR01:ICP0)
139 OCU1IRQ1 Output Compare Unit 1 channel 1 Interrupt (OCU1_OSR01:ICP1)
144 OCU16IRQ0 Output Compare Unit 16 channel 0 Interrupt (OCU16_OSR01:ICP0)
145 OCU16IRQ1 Output Compare Unit 16 channel 1 Interrupt (OCU16_OSR01:ICP1)
146 OCU17IRQ0 Output Compare Unit 17 channel 0 Interrupt (OCU17_OSR01:ICP0)
147 OCU17IRQ1 Output Compare Unit 17 channel 1 Interrupt (OCU17_OSR01:ICP1)
152 USART0IRQRX
153 USART0IRQTX
154 USART0IRQERR
158 USART6IRQRX
159 USART6IRQTX
160 USART6IRQERR
164 DMA0IRQD0 DMA0 Completion Interrupt for channels 0 + 8*n (DMACDIRQ1:DIRQ[24,
165 DMA0IRQD1 DMA0 Completion Interrupt for channels 1 + 8*n (DMACDIRQ1:DIRQ[25,
166 DMA0IRQD2 DMA0 Completion Interrupt for channels 2 + 8*n (DMACDIRQ1:DIRQ[26,
167 DMA0IRQD3 DMA0 Completion Interrupt for channels 3 + 8*n (DMACDIRQ1:DIRQ[27,
168 DMA0IRQD4 DMA0 Completion Interrupt for channels 4 + 8*n (DMACDIRQ1:DIRQ[28,
169 DMA0IRQD5 DMA0 Completion Interrupt for channels 5 + 8*n (DMACDIRQ1:DIRQ[29,
170 DMA0IRQD6 DMA0 Completion Interrupt for channels 6 + 8*n (DMACDIRQ1:DIRQ[30,
171 DMA0IRQD7 DMA0 Completion Interrupt for channels 7 + 8*n (DMACDIRQ1:DIRQ[31,
172 DMA0IRQERR DMA0 Error Interrupt
173 MSCTIRQ
174 SSCTIRQ
175 RCSCTIRQ RC Source Clock Timer Interrupt (SYSC_RCSCTSTATR:INTF is set when
176 SRCSCTIRQ
177 CORE0IRQ CORTEX R4 Perf ormance Monitor Interrupt
178 RLT0IRQ Reload Timer 0 Interrupt
179 RLT1IRQ Reload Timer 1 Interrupt
180 RLT2IRQ Reload Timer 2 Interrupt
181 RLT3IRQ Reload Timer 3 Interrupt
182 RLT4IRQ Reload Timer 4 Interrupt
183 RLT5IRQ Reload Timer 5 Interrupt
184 RLT6IRQ Reload Timer 6 Interrupt
185 RLT7IRQ Reload Timer 7 Interrupt
186 RLT8IRQ Reload Timer 8 Interrupt
187 RLT9IRQ Reload Timer 9 Interrupt
194 UDC0IRQ0 Up/Down Counter 0 channel 0 Interrupt
195 UDC0IRQ1 Up/Down Counter 0 channel 1 Interrupt
198 I2S0IRQ I2S0 Interrupt
199 I2S1IRQ I2S1 Interrupt
202 I2C0IRQ
203 I2C0IRQERR
206 CRC0IRQ
208 PPG0IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
209 PPG1IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
210 PPG2IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
211 PPG3IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
212 PPG4IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
213 PPG5IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
214 PPG6IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
215 PPG7IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
216 PPG8IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
217 PPG9IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
218 PPG10IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
219 PPG11IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
220 PPG12IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
221 PPG13IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
222 PPG14IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
223 PPG15IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
232 PPG64IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
233 PPG65IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
234 PPG66IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
235 PPG67IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
236 PPG68IRQ
237 PPG69IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
238 PPG70IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
239 PPG71IRQ
Microcontroller FCR4 Cluster Series Hardware Manual (002-09388).
Table 29. NMI List
0 EIC0NMI External Pin NMI (EIC0_NMIR:NMIINT)
1 SYSCNMILVD Low Voltage Detect NMI (check SYSC_SYSERRR:LVD12IF,
2 SYSCNMIERR
3 WDGNMI Watchdog NMI (WDG_INT:NMI_FLAG is set on Watchdog error condition if
7 MPUXGFXNMI MPU IRIS-SDL Access Violation NMI(MPUXGFX_CTRL0:NMI is set when a memory
8 MPUHMLB0NMI MPU MLB0 Access Violation NMI(MPUHMLB0_CTRL0:NMI is set when a memory
11 BECU0NMI BECU0 Access Violation NMI (BECU0_CTRL:NMI bit is set when a bus error is detected
12 BECU1NMI BECU1 Access Violation NMI (BECU1_CTRL:NMI bit is set when a bus error is detected
13 BECU3NMI BECU3 Access Violation NMI (BECU3_CTRL:NMI bit is set when a bus error is detected
14 GFXNMI GFX Signature Unit NMI (GFXGCTR_NmiStatus:NmiStatus is set if the number of error
18 MPUSHE MPU SHE Access Violation NMI(MPUXSHE0_CTRL0:NMI is set when a memory
Table 30. Modules with DMA
0 EXTDMA0 External DMA Request 0 (external pin DMA0_DREQ0)
1 EXTDMA1 External DMA Request 1 (external pin DMA0_DREQ0)
8 EIC0DMA0 External Interrupt 0 DMA Request (EIC0_DRFR:DRF0)
9 EIC0DMA1 External Interrupt 1 DMA Request (EIC0_DRFR:DRF1)
10 EIC0DMA2 External Interru pt 2 DMA Request (EIC0_DRFR:DRF2)
11 EIC0DMA3 External Interru pt 3 DMA Request (EIC0_DRFR:DRF3)
12 EIC0DMA4 External Interru pt 4 DMA Request (EIC0_DRFR:DRF4)
13 EIC0DMA5 External Interru pt 5 DMA Request (EIC0_DRFR:DRF5)
14 EIC0DMA6 External Interru pt 6 DMA Request (EIC0_DRFR:DRF6)
15 EIC0DMA7 External Interru pt 7 DMA Request (EIC0_DRFR:DRF7)
16 EIC0DMA8 External Interru pt 8 DMA Request (EIC0_DRFR:DRF8)
17 EIC0DMA9 External Interru pt 9 DMA Request (EIC0_DRFR:DRF9)
18 EIC0DMA10 External Interrupt 10 DMA Request (EIC0_DRFR:DRF10)
19 EIC0DMA11 External Interrupt 11 DMA Request (EIC0_DRFR:DRF11)
20 EIC0DMA12 External Interrupt 12 DMA Request (EIC0_DRFR:DRF12)
21 EIC0DMA13 External Interrupt 13 DMA Request (EIC0_DRFR:DRF13)
22 EIC0DMA14 External Interrupt 14 DMA Request (EIC0_DRFR:DRF14)
23 EIC0DMA15 External Interrupt 15 DMA Request (EIC0_DRFR:DRF15)
24 EIC0DMA16 External Interrupt 16 DMA Request(EIC0_DRFR:DRF16)
25 EIC0DMA17 External Interrupt 17 DMA Request (EIC0_DRFR:DRF17)
26 EIC0DMA18 External Interrupt 18 DMA Request (EIC0_DRFR:DRF18)
27 EIC0DMA19 External Interrupt 19 DMA Request (EIC0_DRFR:DRF19)
28 EIC0DMA20 External Interrupt 20 DMA Request (EIC0_DRFR:DRF20)
29 EIC0DMA21 External Interrupt 21 DMA Request (EIC0_DRFR:DRF21)
30 EIC0DMA22 External Interrupt 22 DMA Request (EIC0_DRFR:DRF22)
31 EIC0DMA23 External Interrupt 23 DMA Request (EIC0_DRFR:DRF23)
32 EIC0DMA24 External Interrupt 24 DMA Request (EIC0_DRFR:DRF24)
33 EIC0DMA25 External Interrupt 25 DMA Request (EIC0_DRFR:DRF25)
34 EIC0DMA26 External Interrupt 26 DMA Request (EIC0_DRFR:DRF26)
35 EIC0DMA27 External Interrupt 27 DMA Request (EIC0_DRFR:DRF27)
36 EIC0DMA28 External Interrupt 28 DMA Request (EIC0_DRFR:DRF28)
37 EIC0DMA29 External Interrupt 29 DMA Request (EIC0_DRFR:DRF29)
38 EIC0DMA30 External Interrupt 30 DMA Request (EIC0_DRFR:DRF30)
39 EIC0DMA31 External Interrupt 31 DMA Request (EIC0_DRFR:DRF31)
40 SG0DMA
44 HSSPI0DMARX
45 HSSPI0DMATX
48 FRT0DMA
49 FRT1DMA
50 FRT2DMA
51 FRT3DMA
64 FRT16DMA
65 FRT17DMA
66 FRT18DMA
67 FRT19DMA
84 ICU2DMA0 Input Capture Unit 2 chan nel 0 DMA Request (ICU2_ICEICS01:ICP0*)
85 ICU2DMA1 Input Capture Unit 2 chan nel 1 DMA Request (ICU2_ICEICS01:ICP1*)
86 ICU3DMA0 Input Capture Unit 3 chan nel 0 DMA Request (ICU2_ICEICS01:ICP0*)
87 ICU3DMA1 Input Capture Unit 3 chan nel 1 DMA Request (ICU2_ICEICS01:ICP1*)
116 ICU18DMA0 Input Capture Unit 18 ch annel 0 DMA Request (ICU18_ICEICS01:ICP0*)
117 ICU18DMA1 Input Capture Unit 18 chan nel 1 DMA Request (ICU18_ICEICS01:ICP1*)
118 ICU19DMA0 Input Capture Unit 19 ch annel 0 DMA Request (ICU19_ICEICS01:ICP0*)
119 ICU19DMA1 Input Capture Unit 19 ch annel 1 DMA Request (ICU19_ICEICS01:ICP1*)
144 OCU0DMA0 Output Compare Unit 0 channel 0 DMA Request (OCU0_OSR01:ICP0*)
145 OCU0DMA1 Output Compare Unit 0 channel 1 DMA Request (OCU0_OSR01:ICP1*)
146 OCU1DMA0 Output Compare Unit 1 channel 0 DMA Request (OCU1_OSR01:ICP0*)
147 OCU1DMA1 Output Compare Unit 1 channel 1 DMA Request (OCU1_OSR01:ICP1*)
176 OCU16DMA0 Output Compare Unit 16 c hannel 0 DMA Request (OCU16_OSR01:ICP0*)
177 OCU16DMA1 Output Compare Unit 16 c hannel 1 DMA Request (OCU16_OSR01:ICP1*)
178 OCU17DMA0 Output Compare Unit 17 channel 0 DMA Request (OCU17_OSR01:ICP0*)
179 OCU17DMA1 Output Compare Unit 17 c hannel 1 DMA Request (OCU17_OSR01:ICP1*)
Table 30. Modules with DMA (Continued)
208 USART0DMARX LIN USART 0 Receive DMA Request
209 USART0DMATX LIN USART 0 Transmit DMA Request
220 USART6DMARX LIN USART 6 Receive DMA Request
221 USART6DMATX LIN USART 6 Transmit DMA Request
232 I2C0DMARX I2C0 Receive DMA Request (I2C0_IBCSR:INT*)
233 I2C0DMATX I2C0 Transmit DMA Request (I2C0_IBCSR:INT*)
244 PPG0DMA Programmable Pulse Gene rator 0 DMA Request (PPG0_PCN:IRQF*)
245 PPG1DMA Programmable Pulse Generat or 1 DMA Request (PPG1_PCN:IRQF*)
246 PPG2DMA Programmable Pulse Generat or 2 DMA Request (PPG2_PCN:IRQF*)
247 PPG3DMA Programmable Pulse Generat or 3 DMA Request (PPG3_PCN:IRQF*)
248 PPG4DMA Programmable Pulse Generat or 4 DMA Request (PPG4_PCN:IRQF*)
249 PPG5DMA Programmable Pulse Generat or 5 DMA Request (PPG5_PCN:IRQF*)
250 PPG6DMA Programmable Pulse Generat or 6 DMA Request (PPG6_PCN:IRQF*)
251 PPG7DMA Programmable Pulse Generat or 7 DMA Request (PPG7_PCN:IRQF*)
252 PPG8DMA Programmable Pulse Generat or 8 DMA Request (PPG8_PCN:IRQF*)
253 PPG9DMA Programmable Pulse Generat or 9 DMA Request (PPG9_PCN:IRQF*)
254 PPG10DMA Programmable Pulse Generator 10 DMA Request (PPG10_PCN:IRQF*)
255 PPG11DMA Programmable Pulse Generat or 11 DMA Request (PPG11_PCN:IRQF*)
256 PPG12DMA Programmable Pulse Generator 12 DMA Request (PPG12_PCN:IRQF*)
257 PPG13DMA Programmable Pulse Generator 13 DMA Request (PPG13_PCN:IRQF*)
258 PPG14DMA Programmable Pulse Generator 14 DMA Request (PPG14_PCN:IRQF*)
259 PPG15DMA Programmable Pulse Generator 15 DMA Request (PPG15_PCN:IRQF*)
308 PPG64DMA Programmable Pulse Generator 64 DMA Request (PPG64_PCN:IRQF*)
309 PPG65DMA Programmable Pulse Generator 65 DMA Request (PPG65_PCN:IRQF*)
310 PPG66DMA Programmable Pulse Generator 66 DMA Request (PPG66_PCN:IRQF*)
311 PPG67DMA Programmable Pulse Generator 67 DMA Request (PPG67_PCN:IRQF*)
312 PPG68DMA Programmable Pulse Gener ator68 DMA Request (PPG68_PCN:IRQF*)
313 PPG69DMA Programmable Pulse Generator 69 DMA Request (PPG69_PCN:IRQF*)
314 PPG70DMA Programmable Pulse Generator 70 DMA Request (PPG70_PCN:IRQF*)
315 PPG71DMA Programmable Pulse Generator 71 DMA Request (PPG71_PCN:IRQF*)
372 ADC0DMA ADC0 Conversion End DMA Request
373 ADC0DMA2 ADC0 Scan End DMA Request
376 RLT0DMA Reload Timer 0 DMA Request
377 RLT1DMA Reload Timer 1 DMA Request
378 RLT2DMA Reload Timer 2 DMA Request
379 RLT3DMA Reload Timer 3 DMA Request
380 RLT4DMA Reload Timer 4 DMA Request
381 RLT5DMA Reload Timer 5 DMA Request
382 RLT6DMA Reload Timer 6 DMA Request
383 RLT7DMA Reload Timer 7 DMA Request
384 RLT8DMA Reload Timer 8 DMA Request
385 RLT9DMA Reload Timer 9 DMA Request
408 I2S0DMARX I2S0 Receive DMA Request
409 I2S0DMATX I2S0 Transmit DMA Request
410 I2S1DMARX I2S0 Receive DMA Request
411 I2S1DMATX I2S0 Transmit DMA Request
424 CRC0DMA CRC0 DMA Request (CRC0_CFG:CIRQ* (CRC calculated flag))
426 SPI0DMARX SPI0 Receive DMA Request
427 SPI0DMATX SPI0 Transmit DMA Request
428 SPI1DMARX SPI1 Receive DMA Request
429 SPI1DMATX SPI1 Transmit DMA Request
430 SPI2DMARX SPI2 Receive DMA Request
431 SPI2DMATX SPI2 Transmit DMA Request
450 EEFLASHDMA EE Flash DMA R equest (EEFCFG_WSR:ST[1:0])
467 PPUDMA
- In general, a PPU channel controls the access in user mode to the corresponding peripheral. However, there are a few exceptio ns:
- PPCPRIV controls the access to PPC in privileged mode.
- PPCUSER controls the access to PPC in user mode.
- MSCT, SSCT, RCSCT and SRCSCT control the access to the source clock timers within the System Controller, i.e. the registers SYSC_MSCT*, SYSC_SSCT*, SYSC_RCSCT* and SYSC_SRCSCT, after the corresponding source clock stabilization time has elapsed
- WDG controls the write access in user mode to the Watchdog trigger registers, so WDG has no read attribute
- Read attribute for DBG0 is always enabled. Even privilege mode access for DBG0 needs PPU to be enabled.
Table 31. List of PPU Channels
Table 32. List of Master IDs used on MB9EF226 Device
Table 33. Memory Layout of HSSPI0 Registers with Default Values
Table 33. Memory Layout of HSSPI0 Registers with Default Values (Continued)
Table 34. Memory Layout of MEMORY_CONFIG Registers with Default Values
Table 34. Memory Layout of MEMORY_CONFIG Registers with Default Values (Continued)
Table 35. Memory Layout of DEBUG_BUS Registers with Default Values
Table 35. Memory Layout of DEBUG_BUS Registers with Default Values (Continued)
Table 36. Memory Layout of MCU_CONFIG Registers with Default Values
Table 36. Memory Layout of MCU_CONFIG Registers with Default Values (Continued)
Table 37. Memory Layout of PERI0_RBUS Registers with Default Values
Table 37. Memory Layout of PERI0_RBUS Registers with Default Values (Continued)
00000000 XXXXXXXX
Table 38. Memory Layout of PERI1_RBUS Registers with Default Values
Table 38. Memory Layout of PERI1_RBUS Registers with Default Values (Continued)
Table 39. Memory Layout of PERI3_ERBUS Registers with Default Values
Table 39. Memory Layout of PERI3_ERBUS Registers with Default Values (Continued)
Table 40. Memory Layout of PERI4_SLAVE Registers with Default Values
Table 40. Memory Layout of PERI4_SLAVE Registers with Default Values (Continued)
Table 41. Memory Layout of PERI5_AHB Registers with Default Values
00000000 XXXXXXXX 00000000 XXXXXXXX
Table 41. Memory Layout of PERI5_AHB Registers with Default Values (Continued)
01000000 XXXXXXXX XXXXXXXX 00000001
00000000 XXXXXXXX XXXXXXXX XXXXXXXX
Table 42. Memory Layout for SYSTEM_RAM_CONFIG Registers with Default Values
- SYSC_SPCCFGR:FASTON register bit is reserved and should be a lways written as ’0’, since this device does not support "Fast Power domain control" feature.
- SCCFG_STAT1:EEFCEEN and SCCFG_STAT1:TCFCEEN register bits are re ad-1 (write has no impact and read always returns ’1’) in this device.
- SCCFG_STAT1:FPPEN and SCCFG_STAT1:SCMEN register bits are read-0 (write has no impact and read always returns ’0’) in this device.
Table 43. Memory Layout of EXCFG Registers with Default Values
Document Number: 002-05678 Rev. *A Page 336 of 418 MB9EF226 - Titan
Electrical Characteristics
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Table 44. Absolute Maximum Ratings
Table 44. Absolute Maximum Ratings (Continued)
- AV DD5 and VDP5 must be set to the same voltage. It is required that AVDD5 does not exceed VDP5 and that the voltage at the analog inputs does not exceed AVDD5
neither when the power is switched on.
- V I and VO should not exceed VDP5 + 0.3 V. VI should also not exceed the specified ratings. However if the maximum current to/from a input is limited by some means
with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of standard ports depend on VDP5.
- Clamping current limitation:
- Applicable to all general purpose I/O pins (Pi_jj)
- Use within recommended operating conditions.
- Use at DC voltage (current)
- The +B signal should always be applied a limiting resist ance placed between the +B signal and the microcontroller.
- The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
- Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass th rough the protective diode and increase the potential at the V DP5 pin, and this may affect other devices.
- Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result.
- Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage reset in internal vector mode). 10. Sample recommended circuits is shown in Figure 5.
Figure 5. ESD Protection Structure for GPIO Pins
- DVCC, AVDD5 and VDP5 must be set to the same voltage during zero point detection (ZPD) on any of the SMC ports. If zero point detection is not requ ired on any of
conversion time will be more and accuracy of measurement will be low.
Warning: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the devices electrical characteristics are guaranteed when the device is operated within these ranges. adversely affect reliability and could result in device failure. application outside the listed conditions are advised to contact their representatives beforehand. Table 45. Recommended Operating Conditions
Table 46. DC Characteristics
Table 46. DC Characteristics (Continued)
32 KHz oscil-
4 MHz oscil-
4 MHz
Table 47. Source Clock Timing Input frequency of PLL after PLLDIVL divider.
Figure 6. Source Clock Timing
- If MediaLB is used, a minimum CLK_PERI4_PD2 value of 50 MHz is required.
higher CLK_PERI4_PD2 values are required. Table 48. Internal Clock Timing
Figure 7. External Reset Timing Table 49. External Reset Timing
Figure 8. External Input Timing Table 50. External Input Timing
- tCLK_PER is the period of the corresponding peripheral clock.
- tNF is 200ns, if noise filter is enabled and 0ns, if noise filter is bypassed.
Figure 9. Slew Rate High Current Output Timing Table 51. Slew Rate High Current Outputs
in the different tables must be increased by 10ns. Table 52. USART Timing
- AC characteristic in CLK synchronized mode.
- CL is the load capacity value of pins when testing.
- Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters.
- Parameter N depends on tSCYCI and can be calculated as follows:
- i f tSCYCI = 2*k*tCLK_PERI0_PD2, then N = k, where k is an integer > 2
- i f tSCYCI = (2*k+1)*tCLK_PERI0_PD2, then N = k+1, where k is an integer > 1. Examples tSCYCI N 4 * tCLK_PERI0_PD2 2 5 * tCLK_PERI0_PD2, 6 * tCLK_PERI0_PD2 7 * tCLK_PERI0_PD2, 8 * tCLK_PERI0_PD2 …. ….
Figure 10. USART Timing
Figure 11. I2C Timing Table 53. I2C Timing
- For use at over 100 kHz, set the CLK_PERI0_PD2 to at least 6 MHz.
- Cb = capacitance of one bus line in pF.
- tCLK_PERI0_PD2 is the cycle time of the peripheral clock CLK_PERI0_PD2
- I2C spec only guaranteed at VDP5 = 4.5V to 5.5V.
Table 54. HSSPI Interface Timing (Master Mode)
Figure 12. HSSPI Interface Timing Table 55. HSSPI Interface Timing (Slave Mode)
worst case table, called “OVERALL SPI Interface timing” must be used. In Master Mode, using the clock retiming function improves the setup and hold times for input data. not). An example for calculation is given below each table. Table 56. OVERALL SPI Interface Timing
- A negative hold time implies that the clock edge output is delayed with respect to data output. In any case, an external device that will receive data, must use a
sampling point that is outside the time interval given by Output hold time and Output delay time.
Table 57. SPI Interface Timing for All Cells of Type RSDS
- A negative hold time implies that the clock edge output is delayed with respect to data output. In any case, an external device that will receive data, must use a
sampling point that is outside the time interval given by Output hold time and Output delay time. Table 58. SPI Interface Timing for All Cells of Type BIDI50
- A negative hold time implies that the clock edge output is delayed with respect to data output. In any case, an external device that will receive data, must use a
sampling point that is outside the time interval given by Output hold time and Output delay time.
Table 59. SPI Interface Timing for All Cells of Type SMC
- A negative hold time implies that the clock edge output is delayed with respect to data output. In any case, an external device that will receive data, must use a
sampling point that is outside the time interval given by Output hold time and Output delay time.
- A negative hold time implies that the clock edge output is delayed with respect to data output. In any case, an external device that will receive data, must use a
sampling point that is outside the time interval given by Output hold time and Output delay time.
Figure 13. SPI Interface Timing
Table 60. Analog Digital Converter
- The accuracy gets worse as |AVRH5 | becomes smaller.
Document Number: 002-05678 Rev. *A Page 365 of 418 MB9EF226 - Titan Minimum Sampling Time The minimum sampling time can be calculated from the following formula: For pins ADC0_AN0..25: T samp = 7.63 x [ Rext x ( Cext + 16pF ) + ( Rext + 1.78kOhm ) x 18.7pF ] For Pins ADC0_AN26..31: Definition of A/D Converter Terms ■ Resolution: Analog variation that is recognized by an A/D converter. ■ Total error: Difference between the actual value and the ideal value. The total error includes zero transition error, full-scale transition error and nonlinearity error. ■ Nonlinearity error: Deviation between a line across zero-transition line (00 0000 0000 <--> 00 0000 0001) and full-scale transition line (11 1111 1110 <--> 11 1111 1111) and actual conversion characteristics. ■ Differential linearity error: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. ■ Zero reading voltage: Input voltage which results in the minimum conversion value. ■ Full scale reading voltage: Input voltage which results in the maximum conversion value.
Figure 14. Total Error of Digital Output
1.5 LSB
0.5 LSB
1 LSB
VNT : A voltage at which digital output transition from (N−1) to N.
1 LSB = (Ideal value)
Table 61. Program/Erase Time for TCFLASH and EEFLASH procedure starts is included.
- Typical definition: TA=25°C / VDD=1.2V / Program/Erase cycle = Immediately after shipment.
Table 62. Program/Erase Cycle and Data Retention Time[29]
- These values were converted from the technology qualification using Arrhenius equation to translate high temperature measurements into normalized values at +85°C.
Table 63. Execution Time Limit
- This is the time it takes for the macro to detect a Hang up 1 error when 1 is to be programmed to a memory cell whose memory value is either 0 or X.
- See the Hardware Manual for an explanation about Flash Timing Limit Exceeded Flags. The time during Sector Erase Suspend (period from Suspend Command
Write Cycle to Resume Command Write Cycle) is not included.
SYSC_RCCFGR:SFREQ bit set to “1”. When the SYSC_RCCFGR:SFREQ bit is set to “0”, the central setting corresponds to about 8 MHz. frequency setting is 16.9 MHz (typical value). Figure 15. RC Oscillator Frequency at SYSC_RCCFGR:SFREQ = 0
- The provided function values are not guaranteed and can serve for reference, only. Guaranteed values are listed in Table 47 on page 349.
Figure 16. RC Oscillator Frequency at SYSC_RCCFGR:SFREQ = 1
- The provided function values are not guaranteed and can serve for reference, only. Guaranteed values are listed in Table 47 on page 349.
reserved values can result in indeterminate operation. Boundary scan mode may be entered by setting pins MODE = “1” and MD[0] = “0”. Table 64. Standard Instructions Table 65. IO Control (IO_CNTRL) Register
- MODE clipped to ’1’ and MD[0] clipped to ’0’.
- Release JTAG_NRST and RSTX.
- JTAG-Instruction IO_CNTRL (010001).
- Set IO_CNTRL-reg 10th bit: (For example, 0000010000000000).
- JTAG-Instruction SAMPLE > Port Input.
Table 66. IO Control (IO_CNTRL) Register Bits [15:11] reserved Reserved. Always write 0 to these bits. "0": IO_CNTRL[5:0] are disabled. Input buffers are disabled. [8:6] reserved Reserved. Always write 0 to these bits.
- When Bit[10] = “0”, all input buffers are disabled in Boundary Scan mode. Then, input of data via external pins to the BSR (Boundary Scan Register) is impossible.
Therefore, the minimum setting to allow input to the BSR is 0x0400.
HWM for details of Flash program/erase command sequence. higher order bits used for flash macro selection. sectoring are shown in Table 67. Table 67. Flash Sector Information Table 68. Flash Pin Mapping to External Pins additional details regarding use of DFSEL. 11 15 P1_30 SMD[0] Set to ‘1’ when entering FPP mode. 12 16 P1_31 SMD[1] Set to ‘1’ when entering FPP mode. 13 17 P1_32 MD[0] Set to ‘1’ when entering FPP mode. 14 18 P1_33 MD[1] Set to ‘1’ when entering FPP mode. 15 19 P1_34 MD[2] Set to ‘1’ when entering FPP mode.
additional details regarding use of FA[21]. Table 68. Flash Pin Mapping to External Pins (Continued)
support programming multiple devices at once.
Timing requirements for flash signals are provided in Figure 23 and Table 69. Figure 23. Flash Timing Parameters
Table 69. Flash Timing Requirements
- Input Data should change at falling edge of X0 clock.
- Output data should be sampled at next rising edge of X0 clock
sector) and 8 sectors of 8k byte (small sector). in the large sector and that in the small sector differ. determined according to the values of FA[15:0]. Table 70. Large Sector (0x100000 ~ 0x1FFFFF) data input pins, see Output Data Table and Input Data Table. input 8bit selected in FA[20:0]. ❐ FPP mode can only output 8 or 16 bit. ❐ RD64 should always be kept 0. **Table 71. Small Sector (0x0*0000 ~ 0x0*FFFF)** (except an indeterminate value). data input pins, see Output Data Table and Input Data Table. input 8bit selected in FA[20,15:0]. 16bit program mode (BYTEX=1): Ignore FA[0] and input 16bit. ❐ FPP mode can only output 8 or 16 bit. ❐ RD64 should always be kept 0. Table 72. Data Output Correspondence Table in Read Bit Modes
❐ FA[#] indicates the lowest bit of sector-selected address, i.e. FA[13] when the small sector is selected (FA[n]=0). Sector No. values shown in Memory Map. on the FA[0] values is programmed as shown in Table 73. both Regular bit and ECC parity bit are erased together. Table 73. Correspondence Table of Data Input and Memory Cell Bit in Program Bit Modes
■ "Any" a value of either 1 or 0. ■ FA[#] indicates the lowest bit of sector-selected address, i.e. of a program command in the Unlock-bypass state. which program data is input. ing scheme as mentioned in Table 74. differs based on whether small or large sectors are accessed. Table 74. Flash Macro Selection Table 75. TCFlash Small Sectors Address Translation
- Small sectors are interleaved (even and odd sectors). Even numbered sec-
- Apply following constant pin setting: MODE = 1 and MD[2:0]
= 111. The pins for MD[2:0] have pull-up, thus can be left open.
- Assert RSTX = 0 and JTAG_nTRST = 0. The pin
0 is optional. This is done internally at device startup.
- Ramp up the power supply (please refer to device specific
- Wait for at least 500ns after all power supplies are stable.
- De-assert RSTX= 1, also deassert FRSTX = 1 and FRSTRX
= 1 if those were asserted before.
- Wait until Flash Parallel Programming mode is entered by the
because RDY pin is High-Z before FPP mode is entered. mis-interpretation before that time is elapsed.
- Flash access is possible after RDY pin goes to “1”. Clock
supply is needed for monitoring RDY . RDY pin is pseudo open drain and thus needs a pull-up resistor. programming mode may be entered. Entering FPP by releasing RSTX while keeping.
- Setting MCFG_TSR:MD= ’XXX111’, and MCFG_TSR:SMD=
SYSC_MCR:FPPEN is set, which enables entry to FPP mode. in Security Description Record (SDR) (see HWM). ECC checking for erased flash. Table 76. TCFlash Large Sectors Address Translation
- Large sectors of TCFLASH are 4-times interleaved for best read performance
- Large sectors are interleaved (even and odd numbered sectors). Even num-
4 byte of a 64 bit FLASH line.
- Address space is interleaved between TCFLASH0 and TCFLASH1.
bit FLASH line (2 FLASHs are read in parallel).
Figure 24. Power On Sequence trace debug (core not halted and non-invasive) are supported. ■ QFP-176: 4-bit and 8-bit trace data shared with resources. Table 77. Timing Parameters Related to Power ON Sequence Table 78. Trace Port to External Pin Mapping
relevant pins and the corresponding settings for their activation. regain access is through application of external reset.
- Embedded Trace Macro (ETM) and Instrumentation Trace
- Independent AHB bus trace macro (HTM) for up to 8 busses
support cross triggering among all the above macros. mapped address 0xB0509404 (see Table 81). Table 79. HTM Trace Sources Table 78. Trace Port to External Pin Mapping (Continued) Table 80. Power Domain Status Information for Debugger Table 81. Trace Width Setting on QFP-240 Package
Document Number: 002-05678 Rev. *A Page 385 of 418 MB9EF226 - Titan Handling Devices Preventing Latch-up Latch-up may occur in a CMOS IC if a voltage higher than (VDD, VDP3 or VDP5) or less than (VSS) is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings. Handling of Unused Input Pins If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected to pull-up or pull-down resistor (2K to 10K) or enable internal pullup or pulldown resistors (PUE/PDE) before the input enable (PIE) is activated by software. The pins of circuit type MODE can be connected to V SS or VDP5 directly. Power Supply Pins In FCR4 series, devices including multiple power supply pins and ground pins are designed as follows: pins necessary to be at the same potential are interconnected internally to prevent malfunc- tions such as latch-up. All of the power supply pins and ground pins must be externally connected to the power supply and ground respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of the FCR4 series must be connected to the current supply source via a low impedance. It is also recommended to connect a ceramic capacitor of approximately 0.1 F as a bypass capacitor between power supply pin and ground pin near this device. If DV CC is not set to the same voltage level as AVDD5, the ZPD functionality of SMC pins cannot be used. Power on Sequence At any time, the difference between the power supply pins belonging to the same voltage level must not exceed 0.5V. This especially applies to the power on sequence. Otherwise, the risk of latchup will increase. Figure 25 shows the power on sequence and the groups of power supply that might be used, depending on the actual application. Furthermore, VDP5 supply must be switched on before any other power supply or at least at the same time. The following condi- tions must be fulfilled at any moment: 1. The voltage of VDP5 must be higher or equal than the voltage on AVDD5 and AVRH5. 2. The voltage of VDP3 must be higher or equal than the voltage on VDD. In particular, VDP3 must not be switched off for saving power. 3. The supply voltage for MODE and RSTX pins must reach the minimum operational value before switching on core voltage supply.
Figure 25. Power on Sequence must pay attention to the listed behavior. located near the device and ground. by ground plane for the stable operation. related characteristics of the crystal and this device. because the X1/X1A pin stops at “H” output in STOP mode). Table 82. Pin State During Active External Reset
Document Number: 002-05678 Rev. *A Page 388 of 418 MB9EF226 - Titan Reference Documents Notes 41. Refer all documents for the system development. 42. Primary user" is a most likely engineer for whom the document is the most useful. 43. FCR4 Hardware manual is expected to be used as dictionary of platform specification. 44. The IRIS-SDL manual describes the implemented graphics IP. 45. The ARM Technical Reference manual describes the Cortex™- R4 architecture of core, bus, trace and debug interface. Document Type Definition Primary User Document Code MB9EF226 Datasheet The function and its characteristics are specified quantitatively. Investigator and hardware engineer 002-05678 FCR4 Cluster Hardware manual The function and its operation of FCR4 cluster series are described. Software engineer 002-09388 Iris-SDL Hardware manual The function and its operation of GPU core platform are described. Software engineer 002-09380 ARM Cortex™-R4 Technical Reference manual ARM documentation set for the ARM Cortex-R4 processor core platform Software engineer Revision: r1p4 Application note The reference software, sample application, the reference board design and so on are explained. Software and hardware engineer Under consideration
Document Number: 002-05678 Rev. *A Page 389 of 418 MB9EF226 - Titan Errata This section describes the errata for the Titan, MB9EF226. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Product Status: In Production The following table defines the errata applicability to available [product name] family devices. An "X" indicates that the errata pertains to the selected device. 1. TCFlash Programming ■Problem Definition TCFlash programming problem was found in the logic of the TCFlas h Interface in the MB9EF226 series. Because of this problem, the behavior of the TCFlash programming is not working as specified. ■Parameters Affected All part numbers of the MB9EF226 series are affected. ■Trigger Condition Programming the TCFlash with ECC is not possible with 16 bit access sequences. ■Rootcause Data abort of 16 bit programming sequence. ■Workaround To handle ECC calculation and Flash writes, Flash write in CPU mode is restricted to 32-bit mode. ■Fix Status No fixes planned. 2. Port Pin Output Function Select Problem ■Problem Definition Port Pin Output Function Select problem was found in the logic of the port pin multiplexing on MB9EF226 series. Because of this problem, the behavior of the port pin multiplexing is not working as specified. ■Parameters Affected All part numbers of the MB9EF226 series are affected. ■Trigger Condition The problem occurs if the port pin output function select value '010' is programmed for port pin P2_40, P2_41, P2_42 or P2_43. Items Part Number Fix Status [1.]. TCFlash Programming MB9EF226PMC-GSE2 MB9EF226EPMC-GSE2 MB9EF226LPMC-GSE2 MB9EF226BPMC-GSE2 MB9EF226BEPMC-GSE2 MB9EF226BLPMC-GSE2 No silicon fix planned. Use workaround. [2]. Port Pin Output Function Select Problem No silicon fix planned. Use workaround. [3]. 3V IO Domain ESD Diode No silicon fix planned. Use workaround. [4]. IRQ Unit Register Read Timing Issue No silicon fix planned. Use workaround. [5]. Flash Erase Suspend Internal No silicon fix planned. Use workaround. [6]. IUNIT Interrupt Handling Problem No silicon fix planned. Use workaround. [7]. IUNIT Nesting Level Status Problem No silicon fix planned. Use workaround. [8]. 1.2V LVD VDP3 Supply Problem No silicon fix planned. Use workaround. [9]. SHE AXI Master Address Mask Problem No silicon fix planned. Use workaround. [10]. SCT Compare Value Update Limitation No silicon fix planned. Use workaround. [11]. Flash Execution Limitation No silicon fix planned. Use workaround. [12]. Automatic ADC Input Disable Problem No silicon fix planned. Use workaround. [13]. RTC Configuration Synchronization Problem No silicon fix planned. Use workaround. [14]. PSS Wakeup Problem No silicon fix planned. Use workaround. [15]. Undefined Data under Certain Conditions when Reading the Flash Memory No silicon fix planned. Use workaround. [16]. Undefined Port Pin State while Core Supply (VDD) is Unavailable MB9EF226PMC-GSE2 MB9EF226EPMC-GSE2 MB9EF226LPMC-GSE2 Redesign planned.
Document Number: 002-05678 Rev. *A Page 390 of 418 MB9EF226 - Titan ■Rootcause The port pin output function select value '010' for port pin P2_40, P2_41, P2_42, P2_43 does not select the specified output function. ■Workaround Do not program pin output function select value '010' for port pin P2_40, P2_41, P2_42, P2_43. To use the resources specified for port pin output function select value '010' on port pin P2_40, P2_41, P2_42, P2_43 select another specified port pin location for the corresponding resource functional output. Note The pin output function RTC_WOT, SYSC_CKOT, SYSC_CKOTX, WDG_OBSERVE specified on port pin P0_40, P0_41, P0_42, P0_43 are only supported when power domain PD2 is active. ■Fix Status No fixes planned. 3. 3V IO Domain ESD Diode ■Problem Definition The 3V IO domain ESD diode problem was found in the specific use-case of switching off the VDP3 supply (3V IO domain) in the MB9EF226 series. Due to an ESD diode between VDD (core supply) and VDP3 (3V IO domain supply), the voltage on VDP3 does not reach 0V even if not supplied. External components connected to same supply as VDP3 will be supplied with a voltage around 0.55V from VDD supply. Therefore, power saving target in standby modes may not be achieved. ■Parameters Affected All part numbers of the MB9EF226 series are affected. ■Trigger Condition The problem occurs if the supply of the 3V IO domain (VDP3) is switched off. ■Rootcause There is an ESD diode between VDD and VDP3 in the core supply cell to protect VDD against ESD overvoltage. In case VDP3 supply is switched off, then VDP3 is supplied by VDD - Uth (threshold voltage of diode) which is around ■Workaround Choose any one of the following workaround:
- Keep 3V power on in standby modes, or
- Switch 3V power off in standby modes, and use separated supplies of MCU and external components to avoid external components being supplied via ESD diode, or
- Switch 3V power off in standby modes, and use same supply of MCU and external components, but do not exceed the maximum current limit of forward-biased diode which is 4mA, i.e. current on VDP3 must not exceed 4mA in that case. ■Fix Status No fixes planned. VDD (1.2V typ) VDP3 (3.3V typ when supply is on) VSS(0V) Uth (~0.65V) VDP3 (0.55V when supply is off)
Document Number: 002-05678 Rev. *A Page 391 of 418 MB9EF226 - Titan 4. IRQ Unit Register Read Timing Issue ■Problem Definition The IRQ Unit register read timing issue was found in the Interrupt Unit (i.e., IRQ-Unit or I-Unit) on the MB9EF226 series. Due to this problem, data from I-Unit registers may be invali d when read at CLK_MEM_I_PD3 frequencies higher than 64 MHz (even though CLK_MEM_I_PD3 maximum frequency is specified up to 128MHz). The following are not affected by the timing issue: Write accesses to Interrupt Unit IRQ vector address transfer to CPU via ARM VIC port (if enabled) ■Parameters Affected All part numbers of the MB9EF226 series are affected. ■Trigger Condition The problem may occur at the following conditions:
- CLK_MEM_I_PD3 is set to more than 64MHz, and
- Data is read from I-Unit addresses (0xB0400000 - 0xB0400D57) or IRQ0_NMIVAS mirror register at address 0xFFFEFBFC Since occurrence of this timing issue is depending on logic path delays, the probability of reading invalid data is increasing with:
- Higher temperature conditions than room temperature
- Lower voltage conditions on VDD supply than nominal 1.2V
- Wafer process slow conditions ■Rootcause The root cause for this problem is a misinterpretation of the internal specification document, which states that one wait cycle is inserted in AHB read transactions while reading of all registers of the interrupt controller module. In the RTL design, there is one additional wait cycle added on the AHB bus, but internally, there was just one pipeline register added to the register read paths. With this, the valid read data is captured after one clock cycle, and then simply delayed by another clock cycle. For creating the timing constraining of the interrupt controller module, it was incorrectly assumed that the register read data actually has two clock cycles 'time' until it is being captured (and then output to the AHB bus). This assumption then led to the incorrect introduction of a multicycle_path definition in the timing cons traints file, which effectively causes a frequency relaxation of a factor of 2 for all register read accesses to interrupt controller registers. ■Workaround For workaround details, refer to “Workaround for IRQ Unit Register Read Timing Issue” on page 406. ■Fix Status Cypress is proposing software workaround specified in “Workaround for IRQ Unit Register Read Timing Issue” on page 406. Hardware redesigns are not planned. 5. Flash Erase Suspend Internal ■ Problem Definition The functional limitation was found with Flash memory implem ented in the MB9EF226 series. Data may not be read correctly irrespective on the state of erase suspend after the sector erase suspend command is issued to the Flash memory during sector erase. ■ Parameters Affected All part numbers of the MB9EF226 series are affected. ■ Trigger Condition(s) The limitation may occur under the all of following conditions are met: ❐ The sector erase suspend command is issued during sector erase. ❐ After it is shifted to the sector erase suspend state, the read operation from the same Flash memory is performed. ■ Details of the Limitation Data may not be read correctly irrespective of the large sectors or small sectors if the following operations are executed in sequence: ❐ The sector erase suspend command is issued to the flash memory during sector erase. ❐ After the state of the sector erase suspend is completed, the reading operation for the flash memory (instruction read or data read) is performed. In this case, the read data are undefined. After this read, data will remain undefined until the sector erase resume command is issued. Table 95 provides the combination of operating conditions for flash memories.
❐ The circuit to control automatic algorithm execution for sector erase operation. execution and to switch to the state where the read operation is enabled. receiving the sector erase suspend command. Refer to Workaround for Flash Erase Suspend Internal on page 412.
- IUNIT Interrupt Handling Problem
is not working as specified. CPU to read the interrupt vector address, the interrupt hold status for IRQ[n] in IRQ0_IRQHSn is not set.
- If IRQ[n] is active and IRQ0_IRQPLM is set to IRQ0_IRQPLM > IRQ0_IRQPL[n] before the interrupt flag at the peripheral is cleared and no enabled interrupt with high priority was asserted then IRQ[n] will be selected again for interrupt service.
- If IRQ[n]/IRQ[m] is active and IRQ0_IRQPLM is set to IRQ0_IRQPLM > IRQ0_IRQPL[m] > IRQ0_IRQPL[n] after the interrupt flag at the peripheral asserting IRQ[n] is cleared and no enabled interrupt with higher priority was asserted then IRQ[n] will be nested by IRQ[m]. ❐ IRQ/NMI Priority Level: IRQ0_IRQPL0~127, IRQ0_NMIPL0~7 are changed during interrupt priority evaluation.
- Wrong IRQ/NMI interrupt number and vector (even the number and vector of a non-existing IRQ/NMI interrupt) can be handed over to the CPU.
- One IRQ/NMI interrupt is executed, but the hold status bit of another IRQ/NMI interrupt (or no hold status bit or several hold status bits) may get set. ❐ IRQ/NMI Hold clear: IRQ0_IRQHC, IRQ0_NMIHC are written during interrupt priority evaluation.
- Wrong IRQ/NMI interrupt number and vector (even the number and vector of a non-existing IRQ/NMI interrupt) can be handed over to the CPU. ❐ IRQ0_IRQHC byte write access: 8-bit (byte) width write access to IRQ0_IRQHC register triggers the hold clear of partly specified IRQ number.
Table 95. Combination of Operating Conditions for Flash Memories
1 TC Flash-A TC Flash-A Undefined
2 TC Flash-B TC Flash-B Undefined
3 EE Flash EE Flash Undefined
4 TC Flash-A TC Flash-B / EE Flash Normal
5 TC Flash-B TC Flash-A / EE Normal
6 EE Flash TC Flash-A / TC Flash-B Normal
Document Number: 002-05678 Rev. *A Page 393 of 418 MB9EF226 - Titan ■ Parameters Affected All part numbers of the MBEF226 series are affected. ■ Trigger Conditions 1. Enabled IRQ[n] is selected for interrupt service (no other interrupt with higher priority pending and IRQ0_IRQPLn < IRQPLM) and IRQ0_IRQPLM is changed to equal or lower value than IRQ0_IRQPLn before IRQ0_IRQHS is set (point in time when CPU reads the interrupt vector address). 2. Priorities of active IRQ/NMI are changed during interrupt priority evaluation. 3. IRQ/NMI Hold Bit is cleared during interrupt priority evaluation. 4. IRQ0_IRQHC write access with 8-bit access width. ■ Root Cause 1. Not all inputs of priority encoder are latched during interrupt processing (period from start of priority evaluation until handover to CPU), in this case priority level mask IRQ0_IRQPLM. 2. Not all inputs of priority encoder are latched during interrupt processing (period from start of priority evaluation until handover to CPU), in this case priority level IRQ0_IRQPL0~127, resp. IRQ0_NMIPL0~7. 3. Not all inputs of priority encoder are latched during interrupt processing (period from start of priority evaluation until handover to CPU), in this case hold status IRQ0_IRQHS0~15 cleared by IRQ0_IRQHC, resp. IRQ0_NMIHS cleared by IRQ0_NMIHC. 4. Write strobes for the relevant 2 Bytes of IRQ0_IRQHC are evaluated by OR instead of AND which causes byte write access effects change on full 16 Bit. ■ Workaround Refer to Workaround for IUNIT Interrupt Handling Problem on page 413. ■ Fix Status Cypress is proposing software workaround specified in Workaround for IUNIT Interrupt Handling Problem on page 413. Hardware redesigns are not planned. 7. IUNIT Nesting Level Status Problem ■ Description The IUNIT Nesting Level Status Register problem was found in the logic of the IUNIT on MBEF226 series. Because of this problem the IUNIT Nesting Level Status Register (IRQ0_NESTL) is not working as specified. ■ Problem Conditions At least one of the following conditions must occur: ❐ Handover of IRQ vector address to CPU (by VIC protocol) and clearing of IRQ Hold status (by CPU executing ISR) occurs in the same clock cycle ❐ Handover of NMI vector address to CPU (by CPU reading the IRQ0_NMIVAS register) occurs one clock cycle before clearing of NMI Hold status (by CPU executing NMI handler). ■ Affected Devices All part numbers of the MBEF226 series are affected. ■ Root Cause IRQ0_NESTL:IRQNL: If handover of IRQ vector address to CPU (by VIC protocol) and clearing of IRQ Hold status (by CPU executing ISR) occurs in the same clock cycle, then IRQ0_NESTL:IRQNL is in cremented (if it is =0) or decremented (i f it is !=0), but it s value should not be changed. IRQ0_NESTL:NMINL: If handover of NMI vector address to CPU (by CPU reading the IRQ0_NMIVAS register) occurs one clock cycle before clearing of NMI Hold status (by CPU executing NMI handler) then IRQ0_NESTL:NMINL is incremented (if it is =0) or decremented (if it is !=0), but its value should not be changed. ■ Workaround Do not evaluate the value returned by reading IUNIT Nesting Level Status Register (IRQ0_NESTL). If software needs information about the current nesting level, a variable counter can be implemented which is incremented/decre- mented in the interrupt handler entry/exit code.
Document Number: 002-05678 Rev. *A Page 394 of 418 MB9EF226 - Titan ■ Fix Status Cypress is proposing above software workaround. Hardware redesigns are not planned. 8. 1.2V LVD VDP3 Supply Problem ■ Description The 1.2V Low Voltage Detection – VDP3 Supply problem was found in the MBEF226 series in the behavior of the 1.2V Low Voltage Detection (1.2V LVD, which is supervising the 1.2V core supply VDD) which is linked to the VDP3 supply voltage. Because of this problem, the 1.2V LVD may not output power-good even if VDD supply is above set limit of LVD. This may cause prevention of system startup after power-on and reset release and/or wrong 1.2V LVD behavior (Reset/Interrupt) at RUN and PSS mode. ■ Problem Conditions The problem may occur at the following conditions: ❐ VDD is above set limits of 1.2V LVD (set by default to 0.8V lower limit at reset) ❐ 1.2V LVD is enabled (enabled by default at reset) ❐ VDP3 supply is smaller than 2.2V ■ Affected Devices All part numbers of the MBEF226 series are affected. ■ Root Cause The band-gap reference (BGR) of 1.2V LVD (supervising 1.2V core supply VDD) is connected to VDP3 supply. If VDP3 supply is <2.2V then 1.2V LVD may not output power-good even if VDD supply is above set limit of LVD. ■ Workaround Keep VDP3 supply ≥ 2.2V for correct operation of 1.2V LVD (at device startup and in RUN/PSS modes). If 1.2V LVD is disabled at: ❐ RUN mode SYSC_RUNLVDCFGR. LVDE12 := 0, and ❐ PSS mode: SYSC_PSSLVDCFGR.LVDE12 := 0, then VDP3 can be lower than 2.2V, but consider behavior as described in 3V IO Domain ESD Diode on page 390. ■ Fix Status No fixes planned. 9. SHE AXI Master Address Mask Problem ■Problem Definition The SHE AXI Master Address Mask problem was found in the AXI Master Interface on the MB9EF226 series. In case Input Channel Master is configured in a way the transfer will start in the address ranges:
- 0x00900000 - 0x009FFFFF
- 0x00FE0000 - 0x00FEFFFF the first burst will be executed starting at the configured address. The transfer will continue after the completion of the first burst at address 0x00FF0000. In case Input Channel Master is configured in a way the transfer will start in the address ranges
- 0x01100000 - 0x011FFFFF
- 0x017E0000 - 0x017EFFFF the first burst will be executed starting at the configured address. The transfer will continue after the completion of the first burst at address 0x017F0000. In case Input Channel Master is configured in a way the transfer will start outside the address ranges
- 0x00900000 - 0x009FFFFF
- 0x00FE0000 - 0x00FEFFFF
Document Number: 002-05678 Rev. *A Page 395 of 418 MB9EF226 - Titan But crossing these address ranges, the transfer will be perf ormed till address 0x010FFFFF and continue with next burst at address 0x00FF0000. In case Input Channel Master is configured in a way the transfer will start outside the address ranges
- 0x01100000 - 0x011FFFFF
- 0x017E0000 - 0x017EFFFF but crossing these address ranges, the transfer will be performed till address 0x010FFFFF and continue with next burst at address 0x017F0000. ■Parameters Affected All part numbers of the MB9EF226 series are affected. ■Trigger Condition ❐ Problem may occur if all of the following conditions are met: Secure boot for TCFlash or any SHE AXI Master read operation is used. Note Secure boot uses SHE AXI Master implicitly. ❐ Above operation includes access to any of the following address ranges:
- 0x00900000 - 0x009FFFFF
- 0x00FE0000 - 0x00FEFFFF
- 0x01100000 - 0x011FFFFF
- 0x017E0000 - 0x017EFFFF ■Rootcause The current implementation of the SHE AXI Interface masks the address range between large and small sectors. The size of the masking window overlaps with Flash address range 0x00900000 - 0x009FFFFF, 0x00FE0000 - 0x00FEFFFF, 0x01100000 - 0x011FFFFF and 0x017E0000 - 0x017EFFFF. ■Workaround
- Store code protected by Secure Boot either in address range 0x01000000 - 0x010FFFFF or 0x017F0000 - 0x017FFFFF.
- Do not access 0x00900000 - 0x009FFFFF, 0x00FE0000 - 0x00FEFFFF, 0x01000000 - 0x010FFFFF or 0x017F0000 - 0x017FFFFF via SHE AXI Master IF ■Fix Status No fixes planned. 10.SCT Compare Value Update Limitation ■Problem Definition The SCT compare value update limitation problem was found in the Slow RC, RC, Main and Sub Source Clock Timer in the MB9EF226 series. In case a new compare value SYSC_SRCSCTCPR_CMP R is captured triggered by writing '1' to SYSC_SRCSCTTRG_CGCPT it could happen that the Slow RC Source Clock Timer Counter is set to an arbitrary value. In case a new compare value SYSC_RCSCTCPR_CMPR is captured triggered by writing '1' to SYSC_RCSCTTRG_CGCPT it could happen that the RC Source Clock Timer Counter is set to an arbitrary value. In case a new compare value SYSC_MAINSCTCPR_CM PR is captured trigger ed by writing '1' to SYSC_MAINSCTTRG_CGCPT it could happen that the Main Source Clock Timer Counter is set to an arbitrary value. In case a new compare value SYSC_SUBSCTCPR_CMPR is captured triggered by writing '1' to SYSC_SUBSCTTRG_CGCPT it could happen that the Sub Source Clock Timer Counter is set to an arbitrary value. ■Parameters Affected All part numbers of the MB9EF226 series are affected. ■Trigger Conditions Problem may occur for Slow RC Source Clock Timer if all of the following conditions are met:
- SRC source clock timer runs with compare value "old value"
- SYSC_SRCSCTCPR_CMPR is set to "new value"
- SYSC_SRCSCTTRG_CGCPT set to '1' trigger compare value update
- Bitwise AND of "new value" and "old value" is equal to 0 and neither "new value" nor "old value" equal to 0. By hard reset "old value" is initialized to 0x0001.
Document Number: 002-05678 Rev. *A Page 396 of 418 MB9EF226 - Titan Problem may occur for RC Source Clock Timer if all of the following conditions are met:
- RC Source Clock Timer runs with compare value "old value"
- SYSC_RCSCTCPR_CMPR is set to "new value"
- SYSC_RCSCTTRG_CGCPT set to '1' trigger compare value update
- Bitwise AND of "new value" and "old value" is equal to 0 and neither "new value" nor "old value" equal to 0. By hard reset "old value" is initialized to 0x001E. Problem may occur for Main Source Clock Timer if all of the following conditions are met:
- Main Source Clock Timer runs with compare value "old value"
- SYSC_MAINSCTCPR_CMPR is set to "new value"
- SYSC_MAINSCTTRG_CGCPT set to '1' trigger compare value update
- Bitwise AND of "new value" and "old value" is equal to 0 and neither "new value" nor "old value" equal to 0. By hard reset "old value" is initialized to 0x1000. Problem may occur for Sub Source Clock Timer if all of the following conditions are met:
- Sub Source Clock Timer runs with compare value "old value"
- SYSC_SUBSCTCPR_CMPR is set to "new value"
- SYSC_SUBSCTTRG_CGCPT set to '1' trigger compare value update
- Bitwise AND of "new value" and "old value" is equal to 0 and neither "new value" nor "old value" equal to 0. By hard reset "old value" is initialized to 0x0400. ■Rootcause The current implementation of the Source Clock Timer generates an asynchronous reset for the Source Clock Timer Counter in case the updated compare value is 0. This condition could be met for a short period of time when the compare value register in the Source Clock Timer capture the new compare value and generate a glitch at the reset of the counter registers. The width of this glitch does not guarantee a valid reset. As a result of this glitch, it is unpredictable which of the counter register bits is reset and which is not. ■Workaround For changing the compare value of a Source Clock timer from effective "old value" to a "new value", ensure the following conditions is true: "old value" & "new value" != 0 ■Fix Status No fixes planned. 11.Flash Execution Limitation ■ Description The Flash Code Execution Limitation problem was found in Flash Interface in MBEF226 series. In case device is secured and code execution is done from following address areas in TCFlash: SA0/SA1: 0x00FF0000 - 0x00FF3FFF (TCM)/ 0x017F0000 - 0x017F3FFF (AXI), a pre-fetch abort exception occurs. ■ Parameters Affected All part numbers of the MBEF226 series are affected. ■ Problem Conditions The problem occurs when device is secured and a code fetch is done from following addresses in TC Flash 0x00FF0000 - 0x00FF3FFF (TCM)/ 0x017F0000 - 0x017F3FFF (AXI)
Document Number: 002-05678 Rev. *A Page 397 of 418 MB9EF226 - Titan ■ Cause of Failure The current implementation of the flash security for protecti ng code execution from address space reserved for Main SDR and TCFlash SDR uses for comparison of the access area the CPU address translated into flash address. As limits there are used the lowest and highest CPU address without reflecting the interleaved arrangement of the flash sectors. So data access for code fetch within in the address range FA=0x0000 to 0x20DF for TCFlash A and range FA=0x0000 to 0x209F for TCFlash B is rejected and leads to pre-fetch abort exception. Code fetch is done 64-Bit aligned therefore always a Flash address from sector 0 is used for comparison. Due to the interleaved arrangement of sector 0, sector 1 in the CPU address space this prevents to use sector 1 for code execution too. Example TCFlash macro A: 0x017F0000 - 0x017F01BF (AXI) shall be non-executable if device is secured. The address comparison is done after translation to sequential flash addresses: 0x017F0000 --> 0x0000 0x017F01BF --> 0x20DF Any code fetch (after translation) from flash address 0x0000 - 0x20DF will be prohibited, which effectively covers 0x0000 - 0x3FFF area since code fetches are always done with 64-bit width. A correct implementation would need to compare the access with two areas: 0x0000 - 0x00DF and 0x2000 - 0x20DF ■ Workaround None, but read accesses are not prohibited, hence the affected regions can be used for constants. ■ Fix Status No fixes planned. Interleaved arrangement of Flash sectors in CPU Address Map Sequential arrangement of the sectors in the flash TCM Address AXI Address Fla sh Sectors FA TCFlash A 0x00FF3FFF 0x00FF01C0 0x017F3FFF 0x017F01C0 SA1 SA0 0x3FFF 0x20E0 SA1 0x00FF01BF 0x00FF0000 0x017F01BF 0x017F0000 SDR SDR 0x20DF 0x2000 SDR … 0x1FFF 0x00E0 SA0 0x00DF 0x0000 SDR
Document Number: 002-05678 Rev. *A Page 398 of 418 MB9EF226 - Titan 12.Automatic ADC Input Disable Problem ■ Description The Automatic ADC Input Disable problem was found in port pin multiplexing in MBEF226 series. Intended function: For pins with an ADC input, the digital input buffer is disabled irrespective of the PPC_PCFGRijj:PIE value if the corresponding ADC channel is enabled, i.e., if the corresponding bit of the ADCn_ER32/ADCn_ER10 register is set to ’1’. Problem: On MBEF226 series: Using ADC input of pin P0_40 de-activates the digital inputs of pin P0_15 and P0_40. Using ADC input of pin P2_41 de-activates the digital inputs of pin P0_08 and P2_41. Using ADC input of pin P2_42 de-activates the digital inputs of pin P0_09 and P2_42. Using ADC input of pin P2_43 de-activates the digital inputs of pin P0_10 and P2_43. Using ADC input of pin P2_44 de-activates the digital inputs of pin P0_11 and P2_44. Using ADC input of pin P2_45 de-activates the digital inputs of pin P0_12 and P2_45. Using ADC input of pin P2_46 de-activates the digital inputs of pin P0_13 and P2_46. Using ADC input of pin P2_47 de-activates the digital inputs of pin P0_14 and P2_47. ■ Affected Devices All part numbers of the MBEF226 series are affected. ■ Problem Conditions The problem occurs if the following conditions are met On MBEF226 series:
- Pin P0_40 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE15 to ‘1’) and
- Pin P0_15 is used as GPIO INPUT function or Peripheral INPUT function or
- Pin P2_41 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE08 to ‘1’) and
- Pin P0_08 is used as GPIO INPUT function or Peripheral INPUT function or
- Pin P2_42 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE09 to ‘1’) and
- Pin P0_09 is used as GPIO INPUT function or Peripheral INPUT function or
- Pin P2_43 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE10 to ‘1’) and
- Pin P0_10 is used as GPIO INPUT function or Peripheral INPUT function or
- Pin P2_44 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE11 to ‘1’) and
- Pin P0_11 is used as GPIO INPUT function or Peripheral INPUT function or
- Pin P2_45 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE12 to ‘1’) and
- Pin P0_12 is used as GPIO INPUT function or Peripheral INPUT function or
- Pin P2_46 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE13 to ‘1’) and
- Pin P0_13 is used as GPIO INPUT function or Peripheral INPUT function or
- Pin P2_47 is used as ADC input function (configuring the corresponding pin as ADC input with setting ADC0_ER32.ADE14 to ‘1’) and
- Pin P0_14 is used as GPIO INPUT function or Peripheral INPUT function ■ Rootcause Misconnection of the ADC channel enable and the digital input disable of affected pins. ■ Workaround None, don’t use affected pin pairs as ADC input and as GPIO INPUT or Peripheral INPUT at same time. ■ Fix Status No fixes planned. 13.RTC Configuration Synchronization Problem ■ Description The RTC Configuration Synchronization problem was found in synchronization architecture of the RTC in MB9EF226 series. In the case of two consecutive write accesses to RTC_WTCR register, it could happen that the values UPCAL, SCAL[2:0], ENUP, ACAL are synchronized as random values into the CLK_MAIN clock domain or cannot be changed inside CLK_MAIN clock domain until next hard reset occurrence. In the case of two consecutive write accesses to RTC_WTCR register it could happen that the values RCKSEL[1:0], CSM are synchronized as random value into the RTC clock domain or cannot be changed inside RTC clock domain until next hard reset occurrence. That UPCAL, SCAL[2:0], ENUP , ACAL, RCKSEL[1:0], CSM cannot be changed in CLK_MAIN or RTC clock domain cannot be identified by reading back RTC_WTCR. ■ Parameters Affected All part numbers of the MB9EF226 series are affected. ■ Problem Conditions The problem could occur if the following conditions are met: Two write accesses to RTC_WTCR are performed within less than 10 times the period of slowest clock out of CLK_MAIN, previous and new CLK_S_RTC and CLK_CFG_PD1 in between.
Figure 28. RTC Timer Module Diagram
data sampled in CLK_CFG_PD1 domain changes at sampling by CLK_MAIN. CLK_CFG_PD1 domain changes at sampling by CLK_S_RTC. write access occurs during handshake of synchronization flag. during handshake of synchronization flag. The waveform in Figure 29 shows the principle of handshake interference which causes a deadlock. Figure 29. Handshake Synchronization of CLK_MAIN, previous and new CLK_S_RTC and CLK_CFG_PD1.
- Read RTC_WTCR to ensure that first write has arrived at RTC due to CPU store buffer.
- Wait 10 times the period of slowest clock out of CLK_MAIN, previous and new CLK_S_RTC and CLK_CFG_PD1 before next
The PSS Wakeup problem was found at wakeup from Power Saving State (PSS) in MB9EF226 series. At wakeup from PSS, an unexpected Non-Maskable Interrupt (NMI) will appear if the PSS profile settings meet certain conditions. All part numbers of the MB9EF226 series are affected. SYSC_SYSSTSR:IPPAPSS would be set and a transition to PSS would not be possible. Figure 30. PSS to RUN State Switching
SYSC_SYSERRR:PSSERRIF is set and NMI is triggered. ❐ Do not use the combination of settings mentioned in the above Condition. Flash interface or at concurrent TCM port and AXI port accesses to the Flash memory of MB9EF226 series microcontrollers. All part numbers of the MB9EF226 series are affected. Figure 31. The TCM port of this interface is the direct connection to the TCM port of the CPU and th e AXI port is the connection
- The wait state setting of the Flash interface can be changed by writing to register TCFCFG_FCFGR:FAWC[1:0]. If the Wait state setting is changed while the Flash is read via the TCM interface, then invalid data may be read from the TCM port of the Flash interface.
- If the Flash is read via the TCM port while there is a concurrent access via the AXI port, then invalid data may be read from the TCM port of the Flash interface.
Figure 31. Connection of Flash Memory For issue no. 1, avoid changing the wait state setting of the Flash interface while reading from the Flash interface via the TCM port. CPU with the maximum specified clock. In case it is unavoidable to change wait state settings, make sure there are no accesses to the Flash memory via the TCM port. For example, execute code from a routine previously copied to RAM. a. Access the Flash memory only via the AXI interface. b. Access the Flash memory only via the TCM interface. for details how to use the MPU.
Refer to Limitation Details Undefined Port Pin State while Core Supply (VDD) is Unavailable on page 414. phase, i.e. in the time between VDP3/VDP5 is powered until VDD is powered. In case the application allows that VDP3/VDP5 is powered and VDD is not powered for a longer time, this must also be analyzed. Use the new die version available. Table 97 provides the new part numbers. Cypress intends to release new die versions of the affected devices that prevent these issues. Contact Cypress sales representative for more information.
- In all situations, in which VDD is out of the recommended operating conditions, the MODE pin must be tied to 'L'.
Hardware Manual (002-09388)). Table 96. Affected Part Numbers
1 MB9EF226PSC-ESE2 (Trace variant)
2 MB9EF226PMC-ESE2 (Engineering Samples)
3 MB9EF226EPMC-ESE2 (Engineering Samples)
4 MB9EF226LPMC-ESE2 (Engineering Samples)
5 MB9EF226PMC-GSE2
6 MB9EF226EPMC-GSE2
7 MB9EF226LPMC-GSE2
Table 97. New Part Numbers
1 MB9EF226BPMC-GSE2
2 MB9EF226EBPMC-GSE2
3 MB9EF226LBPMC-GSE2
Document Number: 002-05678 Rev. *A Page 405 of 418 MB9EF226 - Titan
Ordering Information
Table 98 lists the MB9EF226 series key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress Note 46. These devices are subject to the limitation shown in Limitation Details Undefined Port Pin State while Core Supply (VDD) is Unavailable on page 414. Table 98. Ordering Information
4 SMC variant
6 SMC variant
Document Number: 002-05678 Rev. *A Page 406 of 418 MB9EF226 - Titan Appendix Workaround for IRQ Unit Register Read Timing Issue General Considerations It is assumed that for normal operation of the MCU and most use cases it is not necessary to read back any I-Unit registers, i.e. the application software e.g. knows which vector addresses are configured, which priorities are set and which IRQ channels are enabled. Furthermore, it is assumed that for IRQ handling the application enables the ARM VIC port which is not affected by the read timing issue. It is not necessary to poll the I-Unit lock status bit (IRQ0_CSR_LST) after unlocking/locking the I-Unit. This bit does not indicate any I-Unit internal time consuming operations. Its purpose is to inform the application about the current lock state so that exceptions caused by double unlocking or locking can be avoided. This can also be implemented with software means (e.g. semaphore). For debugging during development or error logging purposes it may be useful to read certain status registers from the I-Unit (e.g. IRQ0_IRQST, IRQ0_EAN) which still can be done but it must be regarded that the gathered information may not be reliable. Considering above mentioned assumptions the only functionality that is affected by the read timing issue is the NMI handling. FCR4 MCUs by default use the ARM "high exception vectors" option with exception vector table located at address 0xFFFF0000. This area is implemented as ROM and its contents are not changeable. The instruction placed at the FIQ exception vector (Note FIQ and NMI are used synonymously throughout the document) will read from the NMIVAS mirror register at address 0xFFFEFBFC to retrieve the branch target. Due to the read timing issue the target address is not reliable and the read must be prevented. Following two workarounds exist to overcome this situation and still provide NMI functionality: ■ Workaround #1: Using Memory Protection Unit ' preventing the read from NMIVAS mirror ■ Workaround #2: Using ARM "low exception vector" option ' allowing to replace the instruction at FIQ exception vector All described preparatory steps in these workarounds (e.g. MPU configuration) must be completed before application enables NMIs (clearing of 'F'-bit in CPU Current Program Status Register). If these workarounds are used, it is also not necessary to initialize the NMI specific I-Unit registers (NMI priorities, NMI vectors) Software samples are provided to demonstrate both workarounds: ■ Workaround #1: fcr4_nmi_mpu_mbxxxxx-vxx ■ Workaround #2: fcr4_nmi_low_exception_mbxxxxx-vxx Workaround #1 (MPU) Overview This workaround aims to detect the read access to the IRQ0_NMIVAS mirror register from the instruction at the FIQ exception vector. The NMIVAS mirror register is located at address 0xFFFEFBFC which will be secured by a memory protection region supported by the ARM core MPU. The flowchart below introduces the process of the workaround when the application code is interrupted by an NMI event.
Document Number: 002-05678 Rev. *A Page 407 of 418 MB9EF226 - Titan Figure 32. Workaround #1 Software Flow
Description
- Each non-maskable interrupt will cause an FIQ exception and t he instruction at address 0xFFFF001C is executed. The instruc- tion reads the vector for the NMI exception handler. This vector is determined by the I-Unit and made available via NMIVAS reg- ister and because of the specified hardware fault in the I-Unit cannot be read reliably. To prevent a branch to a corrupted NMI vector address, the access to NMIVAS mirror register at address 0xFFFEFBFC must be protected by an ARM MPU region. 2. When the FIQ exception instruction accesses the NMIVAS mirror register, a Data Abort exception will occur because of the MPU protection. 3. After the Data Abort handler is entered, the Data Fault Status Register (DFSR) and Data Fault Address Register (DFAR) which are located in System Control coprocessor and the CPU Link Register (R14) are evaluated to determine whether the Data Abort was caused by the occurrence of an NMI. Conditions for NMI cause:
- Data Fault Status Register DFSR[10,3:0] = 0b01101 (Permission Fault) DFSR[11] = 0 (read access)
- Data Fault Address Register DFAR = 0xFFFEFBFC (NMIVAS mirror register)
- Link Register R14_abt = 0xFFFF0024 shows that an NMI caused the abort (0xFFFF001C + 0x8) Before evaluation starts all CPU registers modified by the code are pushed on Data Abort stack (R13_abt). 4. There are two cases depending on this evaluation result: a. In case not all conditions are true, the Data Abort was not caused by the occurrence of an NMI. The modified registers are restored from the stack and the Da ta Abort handler branches to the user's Data Abort handler ("branch without link" -> Link Register is not modified). This behavior is transparent for the user's Data Abort handler which can be written assuming that the handler is directly executed from a Data Abort exception. Application code NMI event Exception table 0xFFFF0010 Data Abort Exception 0xFFFF001C FIQ Exception 0xFFFEFBFC NMIVAS mirror Protected area with no access permission Read address of NMI Exception Handler Permission fault leads to Data Abort exception Data Abort Exception Handler Evaluation of Data Abort cause: NMI exception in case of access to NMIVAS mirror register (0xFFFEFBFC) ... Regular data abort exception handling NMI Dispatcher Dummy read (non-mirrored) NMIVAS Evaluation of NMI cause by checking all NMI flags in relevant ressources. Branch to corresponding User NMI Handler User NMI Handler <user specific implementation> Clear corresponding NMI flag Clear all NMI Hold bits Return to application code User Data Abort Exception Handler <user specific implementation>
Document Number: 002-05678 Rev. *A Page 408 of 418 MB9EF226 - Titan b. In case all conditions are true, the Data Abort was caused by the occurrence of an NMI. Data Fault Status and Data Fault Address register are explicit ly cleared to prevent a repetitive NMI handling in case an NMI occurred shortly after a "normal" Data Abort. After that, the modified registers are restored from the stack and the CPU mode is changed from "Abort" to "FIQ". The program continues at NMI Dispatcher function where a dummy read to the NMIV AS register is done, because this read has the I-Unit internal effect of deasserting the nFIQ CPU signal and setting the NMI Hold bit of the NMI which has won I-Unit priority decision. Finally, the NMI cause must be evaluated. This is done by c hecking all NMI flags in the corresponding peripheral resources (availability may vary for different FCR4 de rivates). As it is not possible to reliably read the I-Unit ECC Double Bit Error NM I flag (IRQ0_EEI_EENS), the software must assume that this is the NMI cause in case no other NMI is present. Once the NMI cause has been detected, the software can branch to the user's NMI handler. Before doing the "branch without link", the stack and registers should be restored (if used by NMI Dispatcher), as the user handler will directly return to the program location where the NMI occurred. 5. The user NMI handler must be changed as described in “Changes to User NMI Handler” on page 411. It will directly return to the application code. ARM MPU Configuration The MPU is a part of Cortex-R4 MCU and can be configured via System Control Coprocessor. It controls the accesses to defined memory regions with the configuration of permission rights. For protection of NMIVAS mirror register, this function will be used in following way: The setup of MPU is done by defining the following: ■ Region number ■ Region access permissions ■ Region size and enable setting ■ Region base address The region number with the highest priority ('11') must be chosen. The access permission must be set to 'No Access' in User and in Privileged Mode. The region size (bit 5..1) is set to minimum size (32 byte) which will not influence any other used memory area. Bit 0 enables the configured MPU setup. It must be ensured that the region base address is 32 byte aligned and the NMIVAS mirror address is within the given region size. In addition, two more settings in the System Control Register (also located in System Control Coprocessor) must be done for activating the MPU function: ■ M (bit 0) = 1: MPU enable ■ BR (bit 17) = 1: MPU background region enable Refer to the ARM Cortex-R4 Technical Reference Manual and the provided software sample for information on how to configure and enable the MPU. Configuration Sequence The following configuration sequence for this workaround is recommended: 1. Reset (High Exception Vectors ac tive, FIQ/NMI masked, IRQ masked). 2. Configure MPU to prohibit access to NMIVAS mirror register. 3. Enable NMI processing in CPU (clear 'F'-bit in CPSR register). 4. Configure IRQ vector table, priority levels and channel enable status in I-Unit. 5. Enable VIC port (to enable IRQ processing via not-affected VIC port). 6. Enable IRQ processing in I-Unit (IRQ0_CSR_IRQEN). 7. Enable IRQ processing in CPU (clear 'I'-bit in CPSR register).
Document Number: 002-05678 Rev. *A Page 409 of 418 MB9EF226 - Titan Workaround Limitations The following limitations need to be considered, if this workaround is used: ■ NMI dispatcher and all called NMI handlers must not allow NMI nesting. If NMIs would be re-enabled (clearing of 'F'-bit in CPU Current Program Status Regi ster), another NMI exception could occur. In case the NMI flag of the already handled NMI is evaluated again by the new/nested NMI Dispatcher function, the same handler will be called again. Further error scenarios are imaginable which can also result in some inconsistent state. ■ Return from a "normal" Data or Prefetch Abort may not be possible. It can happen that while a “normal” Data or Prefetch Abort handle r is currently executed, an NM I occurs because they are not masked on Abort exception entry. As a consequence, this NMI will lead to another Data Abort exception that overwrites the original SPSR_abt and R14_abt CPU register values, an d the Fault Status Registers in the Syst em Control Coprocessor. This makes it impossible for the user's Data or Prefetch Abort handler to return to application or correctly evaluate the circumstances (for example, program location and processor state) of the original Abort. Basically, a similar behavior can occur on any ARMv7-R architectu re if another precise Abort occurs while an Abort handler is executed. Workaround #2 (Low Exception) Overview The application needs to set up an exception table at the “low exception table” location at address 0x0 (inside TCMRAM) and afterwards make this the active table. With this solution, the instruction at the FIQ exception vector can be chosen arbitrarily and the read to NMIVAS register is avoided. For the implementation shown in the software samples, the linker settings of the application must ensure that 64 bytes starting from address 0x0 are reserved for the low exception table and corresponding handler addresses (address area 0x00 - 0x3F). Exception Table Setup The exception table in ARMv7-R architecture is defined as provided in Table 99. Typically, a LDR PC, [PC, #+/-<imm>] instruction is placed at each of these exception vectors which will do a 32-bit read at a PC-relative location and move this value to the PC (= branch to this address). In ARM terminology, the data that is read are called "literals". These literals are the addresses of the corresponding exception handler functions. In the sample software, the exception table and literals are setup as provided in Table 100. Table 99. ARMv7-R Exception Table Table 100. Exception Table Setup in Sample Software
address of the currently executed instruction + 0x8 0x18 + 0x8 = 0x20 offset between instruction and corresponding literal. low exception table and related literals against accidental write accesses by setting up a read-only MPU region for that address area. The same NMI Dispatcher as for Workaround #1 is also used for workaround #2. CPU signal and setting the NMI Hold bit of the NMI which has won I-Unit priority decision.Finally, the NMI cause must be evaluated. This is done by checking all NMI flags in the corresponding peripheral resources (availability may vary for different FCR4 derivates). handler will directly return to the program location where the NMI occurred. The user NMI handler must be changed as described in “Changes to User NMI Handler” on page 411.
- Reset (High Exception Vectors ac tive, FIQ/NMI masked, IRQ masked).
- Create Low Exception Vector table at 0x00000000.
- Configure MPU to protect exception vector table in TCMRAM.
- Switch to Low Exception Vector table.
- Enable NMI processing in CPU (clear 'F'-bit in CPSR register).
- Configure IRQ vector table, priority levels and channel enable status in I-Unit.
- Enable VIC port (to enable IRQ processing via not-affected VIC port).
- Enable IRQ processing in I-Unit (IRQ0_CSR_IRQEN).
- Enable IRQ processing in CPU (clear 'I'-bit in CPSR register).
Table 100. Exception Table Setup in Sample Software (Continued)
Document Number: 002-05678 Rev. *A Page 411 of 418 MB9EF226 - Titan Workaround Limitations Following limitations need to be considered, if this workaround is used: ■ NMI dispatcher and all called NMI handlers must not allow NMI nesting. If NMIs would be re-enabled (clearing of 'F'-bit in CPU Current Program Status Regi ster), another NMI exception could occur. In case the NMI flag of the already handled NMI is evaluated again by the new/nested NMI Dispatcher function, the same handler will be called again. Further error scenarios are imaginable which can also result in some inconsistent state. Changes to User NMI Handler The limitation and workarounds covered by this document result in necessary changes to the user NMI handlers. A different NMI handler exit code is required for correct operation. Instead of only clearing the corresponding NMI Hold bit, all NMI Hold bits must be cleared (as currently set Hold Bit cannot be read back from I-Unit). If this is not done a problem can occur in case of multiple pending NMIs. The software NMI dispatcher may have evaluated a different “winning” NMI than the I-Unit hardware logic (in case of multiple pending NMIs), because it uses the resource NMI flags to determine pending NMIs. Consequently, the NMI Hold bit would not be cleared by the user NMI handler and this prevents the I-Unit from asserting the nFIQ signal to CPU again for this still pending and not yet handled NMI. Ordering of NMI Flag Evaluation In the event of an NMI, no information can be read from the I-Unit, hence the NMI flag(s) of all resources that can generate NMIs need to be evaluated. Following order of NMI flag evaluation is used in the provided software samples: 1. Low voltage detection NMI 2. System controller error NMI 3. External NMI pin 4. Watchdog NMI 5. Timing Protection Unit NMI 6. MPU DMA Access Violation NMI 7. MPU IRIS Access Violation NMI (if available) 8. MPU MLB0 Access Violation NMI (if available) 9. Bus Error Collection Unit BECU0 Access Violation (Peripheral group 0) 10.Bus Error Collection Unit BECU1 Access Violation (Peripheral group 1) 11.Bus Error Collection Unit BECU3 Access Violation (Peripheral group 3) 12.Iris Signature Unit NMI (if available) 13.MPU SHE Access violation (if available) 14.IRQ Double Error NMI The order may be re-arranged to decrease NMI latency for certain use cases, except "IRQ Double Error NMI", which must remain on last position as it must be determined by exclusion principle. Writing I-Unit Registers Care must be taken when writing code for the initialization of I-Unit registers. Any code that would result in RMW (Read-Modify-Write) accesses must be avoided. RMW accesses may be generated if register bit field types are used for assigning values. Example: If priority level for IRQ channel 2 shall be set to 19: C-Code: IRQ0_IRQPL0_IRQPL2 = 19; (wrong!) Compiler Output: 32-bit read of IRQ0_IRQPL0 register Modify bits belonging to IRQPL2 bit field 32-bit write of IRQ0_IRQPL0 register Because the read of this RMW access is affected by the limitation, a possibility that other priority levels in the same register are getting corrupted exists.
To avoid this limitation, the following workaround by software is recommended. the hardware sequence flag DQ4 bit indicating the specific internal state which can read flash or not (see Figure 33). Figure 33. Workaround by Software ■ Approximately a maximum of 10 ms would be required for DQ4 to become "0" after the suspend command is issued first. Table 101. Bit Assignment of Hardware Sequence Flags (Cypress Cortex R4 Family) Table 102. 4 Bit Assignment of Hardware Sequence Flags (FR5 Family)
Document Number: 002-05678 Rev. *A Page 413 of 418 MB9EF226 - Titan Workaround for IUNIT Interrupt Handling Problem 1. To change the IRQ Priority Level Mask Regist er (IRQ0_IRQPLM), use the following workaround: a. Safe sequence to change IRQ0_PLM (temporarily disable interrupt processing and perform wait until IUNIT idle) SuspendAllInterrupts(); // globally disable all IRQs with // 'I'-bit in CPU CPSR IRQ0_UNLOCK = <unlock-key>; IRQ0_CSR = 0; // setting IRQEN bit to '0' IRQ0_CSR; // dummy read to generate wait cycles // until state machine has returned to // idle state IRQ0_IRQPLM = <new PLM value>; IRQ0_CSR = 1; // setting IRQEN bit to '1' IRQ0_UNLOCK = <lock-key>; ResumeAllInterrupts(); // restore previous state of 'I'- // bit in CPU CPSR b. Extension for each ISR entry code (check if corresponding IRQ0_IRQPL[n] < current IRQ0_IRQPLM) Pseudocode: __interrupt void Interrupt_1_Handler(void) // Check if priority of current IRQ is higher (means lower value) // than the currently active priority level mask if (Interrupt_1_Prio < Current_PLM_Value) // The interrupt is "valid" and corresponding code // shall be executed // Call user callback function, which is also responsible // for clearing the interrupt flag in the peripheral .... // Clear Hold-Bit of Interrupt_1 ... IMPORTANT: 'Interrupt_1_Prio' must be determined indire ctly by the called ISR and OS/application in ternal interrupt priority configuration variable(s). IRQ0_IRQPL0~127 and IRQ0_IRQST:IRQSN must not be read. (see CI707-00026-E_FCR4_IRQ_Unit_register_read_timing_issue) Current_PLM_value must be read from OS/application internal buffer variable IRQ0_IRQPLM must not be read. (see CI707-00026-E_FCR4_IRQ_Unit_register_read_timing_issue) 2. To avoid changing the priority level of an active IRQ inte rrupt, configure IRQ0_IRQPL0~127 only in initial phase before enabling interrupts by setting IRQ0_CSR.IRQEN=1. 3. With the software workaround explained in CI707-00026-E_FCR4_I RQ_Unit_register_read_timing_issue, it is not necessary to change IRQ0_NMIPL0~7.
Document Number: 002-05678 Rev. *A Page 414 of 418 MB9EF226 - Titan 4. IRQ Hold Clear - use following sequence to clear the bit: IRQ0_UNLOCK = <unlock-key> IRQ0_CSR = 0; // setting IRQEN bit to '0' IRQ0_CSR; // dummy read to generate wait cycles // until IRQ is latched in IUNIT, resp. // state machine returned to idle state IRQ0_IRQHC = <IRQ-Nr> // clear Hold-bit of IRQ IRQ0_CSR = 1; // setting IRQEN bit to '1' IRQ0_UNLOCK = <lock-key> NMI Hold Clear - use following workaround: NMI handling shall be implemented according to workarounds in CI707-00026-E_FCR4_IRQ_Unit_register_read_timing_issue (will not use any potential wrong NMI register values, as reading is prohibited anyway). 5. Perform write access to IR Q0_IRQHC only with 16-bit or 32-bit access width. Limitation Details Undefined Port Pin State while Core Supply (VDD) is Unavailable When the port pins (Pi_jj) are powered (i.e. depending on the IO Pin type, VDP3 or VDP5 is applied) and the core supply voltage VDD is out of the recommended operating conditions, then two issues occur: 1. the port pins (Pi_jj) may drive any state, i.e. they may show any of the following states high/low, pull-up, pull-down or high-Z instead of the intended state high-Z. 2. the states of the analog switches to connect the Stepper Moto r Controller (SMC) port pins to the A/D converter may be unde- fined. Several switches may be in the conducting state at once and create connections between the SMC port pins. Depending on the voltage levels on the SMC port pins internal currents may flow. This is described in more detail in the next two sections. Undefined Port Pin State As can be seen in Figure 34, port pins Pi_jj in VDP3 and VDP5 power domain may enter undefined state while the 1.2V core supply VDD is below the recommended operating conditions. As an example, the figure shows a system in which a VDP5 power drop is starting at T0. At T1 an external supply voltage monitor asserts RSTX. This switches the port pins Pi_jj to high-Z state. At T2, VDP3, which was also decreasing, is out of recommended operating conditions. The port pins Pi_jj should stay in the high-Z state down to a lower VDP3 voltage. However, as they are operated outside recommended operating conditions, this is shown as X. At T3 VDP5 is out of recommended operating conditions. The port pins Pi_jj should stay in the high-Z state down to a lower VDP5 voltage. However, as they are operated outside recommended operating conditions, this is shown as X.
Figure 34. Undefined Port Pin Pi_jj State while VDP3/VDP5 is Powered, but VDD is not Pi_jj show the undefined state instead of the intended high-Z state. This failure case is indicated by the red rectangles. switched back to high-Z state caused by the still asserted RSTX. state. This also applies to the JTAG_TDO pin. Previously no output pin state change would have occurred. Behavior of the boundary scan test if enabled through the board test mode (MODE pin = ‘1’) is not affected by the fix. internal connections between the SMC port pins. Depending on the voltage levels on the SMC port pins, internal currents may flow.
Figure 35. Current Flowing Between SMC Pins of Different State because Multiple Analog Switches are in Conducting State The minimum resistance of the internal switches when closed is RON = 270Ω. Depending on the state of the connected pins, a current I may flow. The maximum number of SMC output drivers is 6 channels x 4 output drivers / SMC channel = 24. are driving ‘L’ or vice versa and all analog switches are in conducting state. longer time as it is exceeding the allowable sustained current of 1mA. for longer time as the current flowing through a single switch (10mA) is exceeding the allowable sustained current of 1mA. total power consumption PTOT. Make sure the total power consumption PTOT(max) = 2000mW at TA = 105°C is not exceeded. the microcontroller is expected to be low.
Document Number: 002-05678 Rev. *A Page 417 of 418 MB9EF226 - Titan Document History Page Document Title: MB9EF226 - Titan, MB9EF226 Series Document Number: 002-05678 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 09/01/2015 Initial draft Corrected pinout for 176pin and 240pin variant Updated electrical characteristics, procedures, io map. added device handling, order information New IO Map tables included; Corrections to RICFG tables Updated part numbers, removed preliminary Added MB9EF226L part number for non graphics variant Updated IO Map tables: corrected addresses 0xb0400aa8 0xb070005c-0xb0707ffe 0xb07fa46a-0xb07ffffe 0xb0c02900-0xb0cffffc 0xfffef000-0xfffefff8 corrected default values of IRQ0_NMIPL0, IRQ0_IRQPL0, IRQ0_IRQPL12, IRQ0_IRQPL13, EECFG_EMENR *A 5300963 GESC 07/01/2016 Updated to Cypress template. Updated CY Logo and Sales Disclaimer. Added Features. Incorporated all customer information documents into the Errata. Updated references to “Pin State while Power-On-Reset” in section title, section text, and table title for Table 82, in Pin State During Active External Reset. Updated Table 2: Removed “Power on Reset (PoR)” from the list of Resets. Removed PT_TESTPAD in Figure 1. Updated Figure 2. Added ESD Structure between Power Domains. Updated Ordering Information. Added Document Definition in Reference Documents.
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