MB9BF128TABGL-GK7E1

MB9B120TA CYPRESS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 137

Technical content

Datasheet sections

• 6.1 Precautions for Product Design
• 6.2 Precautions for Package Mounting
• 6.3 Precautions for Use Environment
• 12.1 Absolute Maximum Ratings
• 12.2 Recommended Operating Conditions
• 12.3 DC Characteristics
• 12.3.1 Current Rating
• 12.3.2 Pin Characteristics
• 12.4 AC Characteristics
• 12.4.1 Main Clock Input Characteristics
• 12.4.2 Sub Clock Input Characteristics
• 12.4.3 Built-in CR Oscillation Characteristics
• 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
• 12.4.6 Reset Input Characteristics
• 12.4.7 Power-on Reset Timing
• 12.4.8 External Bus Timing
• 12.4.9 Base Timer Input Timing
• 12.4.10 CSIO/UART Timing
• 12.4.11 External Input Timing
• 12.4.12 Quadrature Position/Revolution Counter timing
• 12.4.13 I2C Timing
• 12.4.14 ETM Timing
• 12.4.15 JTAG Timing
• 12.7 Low-Voltage Detection Characteristics
• 12.7.1 Low-Voltage Detection Reset
• 12.7.2 Interrupt of Low-Voltage Detection
• 12.8 Flash Memory Write/Erase Characteristics
• 12.8.1 Write / Erase time
• 12.8.2 Write cycles and data hold time
• 12.9 Return Time from Low-Power Consumption Mode
• 12.9.1 Return Factor: Interrupt/WKUP

The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix “CY”. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrup t markets by creating new product categories in record time. To learn more, go to www.cypress.com.

32-bit A rm® Cortex®-M3 FM3 Microcontroller Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-05667 Rev. *D Revised January 12, 2018 The MB9B120T A Series are highly integrated 32 -bit microcontrollers dedicated for embedded controllers with low -power consumption mode and competitive cost. These series are based on the Arm® Cortex®-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (UART, CSIO, I2C, LIN). The products which are described in this data sheet are placed into TYPE12 product categories in "FM3 Family PERIPHERAL MANUAL".

Features

32-bit Arm® Cortex®-M3 Core  Processor version: r2p1  Up to 60 MHz Frequency Operation  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory]  Dual operation Flash memory  Main area:

• Up to 1.5 Mbytes (1008 Kbytes(ROM0) + 512 Kbytes (ROM1) of Upper bank and 16 Kbytes (ROM0) of Lower bank.)  Work area
• 64 Kbytes(ROM1) of Lower bank  Read cycle: 0 wait-cycle  Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  SRAM0: Up to 96 Kbytes  SRAM1: Up to 96 Kbytes External Bus Interface  Supports SRAM, NOR NAND Flash memory device  Up to 8 chip selects  8-/16-bit Data width  Up to 25-bit Address bit  Maximum area size: Up to 256 Mbytes  Supports Address/Data multiplex  Supports external RDY function Multi-function Serial Interface (Max 16channels)  16 channels with 16 steps×9-bit FIFO  Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2C [UART]  Full duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4)  Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO]  Full duplex double buffer  Built-in dedicated baud rate generator  Overrun error detection function available

Document Number: 002-05667 Rev. *D Page 2 of 136 MB9B120TA Series [LIN]  LIN protocol Rev.2.1 supported  Full duplex double buffer  Master/Slave mode supported  LIN break field generation (can be changed to 13 to 16-bit length)  LIN break delimiter generation (can be changed to 1 to 4-bit length)  Various error detection functions available (parity errors, framing errors, and overrun errors) [I2C] Standard - mode (Max 100 kbps) / Fast - mode (Max 400 kbps) supported DMA Controller (8channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.  8 independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  Transfer address area: 32-bit (4 Gbytes)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: byte/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536 A/D Converter (Max 24channels) [12-bit A/D Converter]  Successive Approximation type  Built-in 2units  Conversion time: 1.0μs @ 2.7V to 5.5V  Priority conversion available (priority at 2 levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) D/A Converter (Max 2 channels)  R-2R type  10-bit resolution Base Timer (Max 16channels) Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up to 154 high-speed general-purpose I/O Ports@176 pin Package  Some ports are 5V tolerant. See "List of Pin Functions" and "I/O Circuit Type" to confirm the corresponding pins. Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot Quadrature Position/Revolution Counter (QPRC) (Max 2channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use as the up/down counter.  The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers

Document Number: 002-05667 Rev. *D Page 3 of 136 MB9B120TA Series HDMI-CEC/Remote Control Reception (Up to 2channels)  HDMI-CEC transmission  Header block automatic transmission by judging Signal free  Generating status interrupt by detecting Arbitration lost  Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data  Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)  HDMI-CEC reception  Automatic ACK reply function available  Line error detection function available  Remote control reception  4 bytes reception buffer  Repeat code detection function available Multi-function Timer The Multi-function timer is composed of the following blocks.  16-bit free-run timer × 3 ch./unit  Input capture × 4 ch./unit  Output compare × 6 ch./unit  A/D activation compare × 2 ch./unit  Waveform generator × 3 ch./unit  16-bit PPG timer × 3 ch./unit The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D convertor activate function  DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.  The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute.) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. Watch Counter The Watch counter is used for wake up from sleep and timer mode. Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz External Interrupt Controller Unit  Up to 32 external interrupt input pins @ 176 pin Package  Include one non-maskable interrupt (NMI) input pin Watchdog Timer (2channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. The "Hardware" watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the "Hardware" watchdog is active in any low-power consumption modes except RTC, STOP , Deep standby RTC, Deep standby STOP modes. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).  Main Clock: 4 MHz to 48 MHz  Sub Clock: 32.768 kHz  Built-in high-speed CR Clock: 4 MHz  Built-in low-speed CR Clock: 100 kHz  Main PLL Clock [Resets]  Reset requests from INITX pin  Power-on reset  Software reset  Watchdog timers reset  Low-voltage detection reset  Clock Super Visor reset

Document Number: 002-05667 Rev. *D Page 4 of 136 MB9B120TA Series Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.  If external clock failure (clock stop) is detected, reset is asserted.  If external frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation Low-Power Consumption Mode Six low-power consumption modes supported.  SLEEP  TIMER  RTC  STOP  Deep standby RTC (selectable between keeping the value of RAM and not)  Deep standby STOP (selectable between keeping the value of RAM and not) Debug  Serial Wire JTAG Debug Port (SWJ-DP)  Embedded Trace Macrocell (ETM) Unique ID Unique value of the device (41-bit) is set. Power Supply Wide range voltage: VCC = 2.7 V to 5.5 V

Document Number: 002-05667 Rev. *D Page 6 of 136 MB9B120TA Series

Document Number: 002-05667 Rev. *D Page 7 of 136 MB9B120TA Series 1. Product Lineup Memory size Product name MB9BF128SA/TA MB9BF129SA/TA On-chip Flash memory Main area 1 Mbytes 1.5 Mbytes Work area 64 Kbytes 64 Kbytes On-chip SRAM SRAM0 80 Kbytes 96 Kbytes SRAM1 80 Kbytes 96 Kbytes Total 160 Kbytes 192 Kbytes Function Product name MB9BF128SA MB9BF129SA MB9BF128TA MB9BF129TA Pin count 144 176/192 CPU Cortex-M3 Freq. 60 MHz Power supply voltage range 2.7 V to 5.5 V DMAC 8 ch. External Bus Interface Addr: 25-bit (Max) R/Wdata : 8-/16-bit (Max) CS: 8 (Max) SRAM , NOR Flash memory , NAND Flash memory Multi-function Serial Interface (UART/CSIO/LIN/I2C) 16 ch. (Max) with 16steps×9-bit FIFO Base Timer (PWC/Reload timer/PWM/PPG) 16 ch. (Max) MF- Timer A/D activation compare 2 ch. 1 unit Input capture 4 ch. Free-run timer 3 ch. Output compare 6 ch. Waveform generator 3 ch. PPG 3 ch. QPRC 1 ch.(Max) 2 ch. (Max) Dual Timer 1 unit HDMI-CEC/ Remote Control Reception 2 ch. (Max) Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog timer 1 ch. (SW) + 1 ch. (HW) External Interrupts 32 pins (Max) + NMI × 1 I/O ports 122 pins (Max) 154 pins (Max) 12-bit A/D converter 24 ch. (2 units) 10-bit D/A converter 2 ch. (Max) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2 ch. Built-in CR High-speed 4 MHz Low-speed 100 kHz Debug Function SWJ-DP / ETM Unique ID Yes Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See "Electrical Characteristics 12.4 AC Characteristics (12.4.3) Built-in CR Oscillation Characteristics" for accuracy of built-in CR.

Document Number: 002-05667 Rev. *D Page 8 of 136 MB9B120TA Series 2. Packages Product name Package MB9BF128SA MB9BF129SA MB9BF128TA MB9BF129TA LQFP: LQS144 (0.5 mm pitch)  - LQFP: LQP176 (0.5 mm pitch) -  BGA: LBE192 (0.8 mm pitch) -  : Supported Note: − See "Package Dimensions" for detailed information on each package.

Document Number: 002-05667 Rev. *D Page 9 of 136 MB9B120TA Series 3. Pin Assignment LQP176 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81 P80 VCC PF5/SCK6_2/IGTRG0_1/INT08_0/WKUP3/CEC1_0 PF4/SOT6_2/TIOB06_0/INT07_0 PF3/SIN6_2/TIOA06_0/INT06_0 P60/SIN5_0/TIOA02_2/INT15_1/WKUP5/MAD20_0 P61/SOT5_0/TIOB02_2/MAD19_0 P62/ADTG_3/SCK5_0/MAD18_0 PD3/TIOB03_2/MAD17_0 PD2/SIN4_0/TIOA03_2/INT00_2/MAD16_0 PD1/SOT4_0/TIOB14_0/INT31_1/MAD15_0 PD0/SCK4_0/TIOB10_2/INT30_1/MAD14_0 PCF/CTS4_0/TIOB08_2/MAD13_0 PCE/RTS4_0/TIOB06_1/MAD12_0 PCD/MAD11_0 PCC/MAD10_0 PCB/MAD09_0 VSS VCC PCA/SCK15_0/MAD08_0 PC9/SOT15_0/MAD07_0 PC8/SIN15_0/MAD06_0 PC7/CROUT_1/RTCCO_0/SUBOUT_0/MAD05_0 PC6/SCK14_0/TIOA14_0/MAD04_0 PC5/SOT14_0/TIOA10_2/MAD03_0 PC4/SIN14_0/TIOA08_2/CEC0_1/MAD02_0 PC3/TIOA06_1/MAD01_0 PC2/SCK13_0/MAD00_0 PC1/DA1_0/SOT13_0/MCSX4_0 PC0/DA0_0/SIN13_0/MCSX5_0 P95/TIOB13_0/INT27_0 P94/SCK5_1/TIOB12_0/INT26_0 P93/SOT5_1/TIOB11_0 P92/SIN5_1/TIOB10_0 P91/TIOB09_0/INT31_0 P90/TIOB08_0/INT30_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VCC 1 132 VSS PA0/SIN8_0/TIOA08_0/MAD21_0 2 131 VCC PA1/SOT8_0/TIOA09_0/MAD22_0 3 130 P83/MCSX6_0 PA2/SCK8_0/TIOA10_0/MAD23_0 4 129 P82/MCSX7_0 PA3/SIN9_0/TIOA11_0/MAD24_0 5 128 PF6/NMIX/WKUP0 PA4/SOT9_0/TIOA12_0/INT03_0 6 127 P20/AIN1_1/INT05_0/CROUT_0 PA5/SCK9_0/TIOA13_0/INT10_2 7 126 P21/SIN0_0/BIN1_1/INT06_1 P05/TRACED0/SIN4_2/TIOA05_2/INT00_1 8 125 P22/AN23/SOT0_0/ZIN1_1/TIOB07_1 P06/TRACED1/SOT4_2/TIOB05_2/INT01_1 9 124 P23/AN22/SCK0_0/RTO00_1/TIOA07_1 P07/TRACED2/ADTG_0/SCK4_2 10 123 P24/AN21/SIN2_1/RTO01_1/INT01_2 P08/TRACED3/CTS4_2/TIOA00_2 11 122 P25/AN20/SOT2_1/RTO02_1 P09/TRACECLK/RTS4_2/TIOB00_2 12 121 P26/AN19/SCK2_1/RTO03_1 P50/SIN3_1/AIN0_2/INT00_0/MOEX_0 13 120 P27/AN18/SCK12_0/RTO04_1/INT02_2 P51/SOT3_1/BIN0_2/INT01_0/MWEX_0 14 119 P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0 P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_0 15 118 P29/AN16/SIN12_0 P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_0 16 117 AVRH P54/SOT6_0/TIOB01_2/MALE_0 17 116 AVRL P55/ADTG_1/SCK6_0/MRDY_0 18 115 AVSS P56/SIN1_0/TIOA09_2/INT08_2/CEC1_1/MNALE_0 19 114 AVCC P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0 20 113 PB7/TIOB12_1/INT23_0 P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0 21 112 PB6/SCK0_2/TIOA12_1/INT22_0 P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0 22 111 PB5/SOT0_2/TIOB11_1/INT21_0 P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0 23 110 PB4/SIN0_2/TIOA11_1/INT20_0 P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0 24 109 PB3/TIOB10_1/INT19_0 P5C/TIOA06_2/INT28_0 25 108 PB2/SCK7_2/TIOA10_1/INT18_0 P5D/TIOB06_2/INT29_0 26 107 PB1/SOT7_2/TIOB09_1/INT17_0 VSS 27 106 PB0/SIN7_2/TIOA09_1/INT16_0 P30/AIN0_0/TIOB00_1/INT03_2/WKUP4 28 105 P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1 P31/SCK6_1/BIN0_0/TIOB01_1/INT04_2 29 104 P1E/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1 P32/SOT6_1/ZIN0_0/TIOB02_1/INT05_2 30 103 P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1 P33/ADTG_6/SIN6_1/TIOB03_1/INT04_0 31 102 P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1 P34/FRCK0_0/TIOB04_1 32 101 P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1 P35/IC03_0/TIOB05_1/INT08_1 33 100 P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1 P36/SIN5_2/IC02_0/TIOA12_2/INT09_1 34 99 P19/AN09/SCK2_2/INT22_1 P37/SOT5_2/IC01_0/TIOB12_2/INT10_1 35 98 P18/AN08/SOT2_2/INT21_1 P38/SCK5_2/IC00_0/INT11_1 36 97 P17/AN07/SIN2_2/INT04_1 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2 37 96 P16/AN06/SCK0_1/INT20_1 P3A/RTO00_0/TIOA00_1 38 95 P15/AN05/SOT0_1/IC03_2 P3B/RTO01_0/TIOA01_1 39 94 P14/AN04/SIN0_1/IC02_2/INT03_1 P3C/RTO02_0/TIOA02_1 40 93 P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3D/RTO03_0/TIOA03_1 41 92 P12/AN02/SOT1_1/IC00_2 P3E/RTO04_0/TIOA04_1 42 91 P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1 P3F/RTO05_0/TIOA05_1 43 90 P10/AN00 VSS 44 89 VCC VCC P40/SIN10_0/TIOA00_0/INT12_1/MCSX2_0 P41/SOT10_0/TIOA01_0/INT13_1/MCSX3_0 P42/SCK10_0/TIOA02_0/MCLKOUT_0 P43/ADTG_7/SIN11_0/TIOA03_0 P44/SOT11_0/TIOA04_0 P45/SCK11_0/TIOA05_0 C VSS VCC P46/X0A P47/X1A INITX P48/SIN3_2/INT14_1 P49/SOT3_2/AIN0_1/TIOB00_0 P4A/SCK3_2/BIN0_1/TIOB01_0/MADATA00_0 P4B/IGTRG0_0/ZIN0_1/TIOB02_0/MADATA01_0 P4C/SCK7_1/AIN1_2/TIOB03_0/MADATA02_0 P4D/SOT7_1/BIN1_2/TIOB04_0/MADATA03_0 P4E/SIN7_1/ZIN1_2/TIOB05_0/INT06_2/MADATA04_0 P70/TIOA04_2/MADATA05_0 P71/TIOB04_2/INT13_2/MADATA06_0 P72/SIN2_0/INT14_2/WKUP2/MADATA07_0 P73/SOT2_0/INT15_2/MADATA08_0 P74/SCK2_0/MADATA09_0 P75/ADTG_8/SIN3_0/INT07_1/MADATA10_0 P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0 P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0 P78/AIN1_0/TIOA15_0/MADATA13_0 P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0 P7A/ZIN1_0/INT24_1/MADATA15_0 P7B/TIOB07_0/INT10_0 P7C/TIOA07_0/INT11_0 P7D/TIOA14_1/INT12_0 P7E/TIOB14_1/INT24_0 P7F/TIOA15_1/INT25_0 PF0/SIN1_2/TIOB15_1/INT13_0/CEC0_0 PF1/SOT1_2/TIOA08_1/INT14_0 PF2/SCK1_2/TIOB08_1/INT15_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 176

Document Number: 002-05667 Rev. *D Page 10 of 136 MB9B120TA Series LQS144 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81 P80 VCC PF5/IGTRG0_1/INT08_0/WKUP3/CEC1_0 P60/SIN5_0/TIOA02_2/INT15_1/WKUP5/MAD20_0 P61/SOT5_0/TIOB02_2/MAD19_0 P62/ADTG_3/SCK5_0/MAD18_0 PD3/TIOB03_2/MAD17_0 PD2/SIN4_0/TIOA03_2/INT00_2/MAD16_0 PD1/SOT4_0/TIOB14_0/INT31_1/MAD15_0 PD0/SCK4_0/TIOB10_2/INT30_1/MAD14_0 PCF/CTS4_0/TIOB08_2/MAD13_0 PCE/RTS4_0/TIOB06_1/MAD12_0 PCD/MAD11_0 PCC/MAD10_0 PCB/MAD09_0 VSS VCC PCA/SCK15_0/MAD08_0 PC9/SOT15_0/MAD07_0 PC8/SIN15_0/MAD06_0 PC7/CROUT_1/RTCCO_0/SUBOUT_0/MAD05_0 PC6/SCK14_0/TIOA14_0/MAD04_0 PC5/SOT14_0/TIOA10_2/MAD03_0 PC4/SIN14_0/TIOA08_2/CEC0_1/MAD02_0 PC3/TIOA06_1/MAD01_0 PC2/SCK13_0/MAD00_0 PC1/DA1_0/SOT13_0/MCSX4_0 PC0/DA0_0/SIN13_0/MCSX5_0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VCC 1 108 VSS PA0/SIN8_0/TIOA08_0/MAD21_0 2 107 VCC PA1/SOT8_0/TIOA09_0/MAD22_0 3 106 P83/MCSX6_0 PA2/SCK8_0/TIOA10_0/MAD23_0 4 105 P82/MCSX7_0 PA3/SIN9_0/TIOA11_0/MAD24_0 5 104 PF6/NMIX/WKUP0 PA4/SOT9_0/TIOA12_0/INT03_0 6 103 P20/AIN1_1/INT05_0/CROUT_0 PA5/SCK9_0/TIOA13_0/INT10_2 7 102 P21/SIN0_0/BIN1_1/INT06_1 P05/TRACED0/SIN4_2/TIOA05_2/INT00_1 8 101 P22/AN23/SOT0_0/ZIN1_1/TIOB07_1 P06/TRACED1/SOT4_2/TIOB05_2/INT01_1 9 100 P23/AN22/SCK0_0/RTO00_1/TIOA07_1 P07/TRACED2/ADTG_0/SCK4_2 10 99 P24/AN21/SIN2_1/RTO01_1/INT01_2 P08/TRACED3/CTS4_2/TIOA00_2 11 98 P25/AN20/SOT2_1/RTO02_1 P09/TRACECLK/RTS4_2/TIOB00_2 12 97 P26/AN19/SCK2_1/RTO03_1 P50/SIN3_1/AIN0_2/INT00_0/MOEX_0 13 96 P27/AN18/SCK12_0/RTO04_1/INT02_2 P51/SOT3_1/BIN0_2/INT01_0/MWEX_0 14 95 P28/AN17/ADTG_4/SOT12_0/RTO05_1/INT09_0 P52/SCK3_1/ZIN0_2/INT02_0/MDQM0_0 15 94 P29/AN16/SIN12_0 P53/SIN6_0/TIOA01_2/INT07_2/MDQM1_0 16 93 AVRH P54/SOT6_0/TIOB01_2/MALE_0 17 92 AVRL P55/ADTG_1/SCK6_0/MRDY_0 18 91 AVSS P56/SIN1_0/TIOA09_2/INT08_2/CEC1_1/MNALE_0 19 90 AVCC P57/SOT1_0/TIOB09_2/INT16_1/MNCLE_0 20 89 P1F/AN15/ADTG_5/FRCK0_1/TIOB15_2/INT29_1 P58/SCK1_0/TIOA11_2/INT17_1/MNWEX_0 21 88 P1E/AN14/RTS4_1/DTTI0X_1/TIOA15_2/INT28_1 P59/SIN7_0/TIOB11_2/INT09_2/MNREX_0 22 87 P1D/AN13/CTS4_1/IC03_1/TIOB14_2/INT27_1 P5A/SOT7_0/TIOA13_1/INT18_1/MCSX0_0 23 86 P1C/AN12/SCK4_1/IC02_1/TIOA14_2/INT26_1 P5B/SCK7_0/TIOB13_1/INT19_1/MCSX1_0 24 85 P1B/AN11/SOT4_1/IC01_1/TIOB13_2/INT25_1 VSS 25 84 P1A/AN10/SIN4_1/IC00_1/TIOA13_2/INT05_1 P36/SIN5_2/IC02_0/TIOA12_2/INT09_1 26 83 P19/AN09/SCK2_2/INT22_1 P37/SOT5_2/IC01_0/TIOB12_2/INT10_1 27 82 P18/AN08/SOT2_2/INT21_1 P38/SCK5_2/IC00_0/INT11_1 28 81 P17/AN07/SIN2_2/INT04_1 P39/ADTG_2/DTTI0X_0/RTCCO_2/SUBOUT_2 29 80 P16/AN06/SCK0_1/INT20_1 P3A/RTO00_0/TIOA00_1 30 79 P15/AN05/SOT0_1/IC03_2 P3B/RTO01_0/TIOA01_1 31 78 P14/AN04/SIN0_1/IC02_2/INT03_1 P3C/RTO02_0/TIOA02_1 32 77 P13/AN03/SCK1_1/IC01_2/RTCCO_1/SUBOUT_1 P3D/RTO03_0/TIOA03_1 33 76 P12/AN02/SOT1_1/IC00_2 P3E/RTO04_0/TIOA04_1 34 75 P11/AN01/SIN1_1/FRCK0_2/INT02_1/WKUP1 P3F/RTO05_0/TIOA05_1 35 74 P10/AN00 VSS 36 73 VCC VCC P40/SIN10_0/TIOA00_0/INT12_1/MCSX2_0 P41/SOT10_0/TIOA01_0/INT13_1/MCSX3_0 P42/SCK10_0/TIOA02_0/MCLKOUT_0 P43/ADTG_7/SIN11_0/TIOA03_0 P44/SOT11_0/TIOA04_0 P45/SCK11_0/TIOA05_0 C VSS VCC P46/X0A P47/X1A INITX P48/SIN3_2/INT14_1 P49/SOT3_2/AIN0_1/TIOB00_0 P4A/SCK3_2/BIN0_1/TIOB01_0/MADATA00_0 P4B/IGTRG0_0/ZIN0_1/TIOB02_0/MADATA01_0 P4C/SCK7_1/AIN1_2/TIOB03_0/MADATA02_0 P4D/SOT7_1/BIN1_2/TIOB04_0/MADATA03_0 P4E/SIN7_1/ZIN1_2/TIOB05_0/INT06_2/MADATA04_0 P70/TIOA04_2/MADATA05_0 P71/TIOB04_2/INT13_2/MADATA06_0 P72/SIN2_0/INT14_2/WKUP2/MADATA07_0 P73/SOT2_0/INT15_2/MADATA08_0 P74/SCK2_0/MADATA09_0 P75/ADTG_8/SIN3_0/INT07_1/MADATA10_0 P76/SOT3_0/TIOA07_2/INT11_2/MADATA11_0 P77/SCK3_0/TIOB07_2/INT12_2/MADATA12_0 P78/AIN1_0/TIOA15_0/MADATA13_0 P79/BIN1_0/TIOB15_0/INT23_1/MADATA14_0 P7A/ZIN1_0/INT24_1/MADATA15_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 144

Document Number: 002-05667 Rev. *D Page 11 of 136 MB9B120TA Series LBE192 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A P81 P80 VCC VSS PCD PCB VSS VCC PC8 VSS TCK VCC B VSS PA0 PF5 PF3 P61 PD1 PCA PC1 P95 P92 TDO TMS TRSTX VSS C VCC PA1 PA2 PF4 P60 PD2 PCC PC5 PC0 P93 P90 TDI PF6 VCC D PA5 PA4 P05 P06 PA3 PD3 PCE PC6 PC2 P94 P91 P21 P20 P83 E VSS P07 P08 P09 P50 P62 PCF PC7 PC3 P25 P24 P23 P22 P82 F P51 P52 P53 P54 P55 P56 PD0 PC9 PC4 P29 P28 P27 P26 AVRH G VSS P57 P58 P59 P5A P5B VSS VSS PB7 PB6 PB5 PB4 PB3 AVRL H P5C P5D P30 P31 P32 P33 VSS VSS P1F P1E PB2 PB1 PB0 AVSS J VSS P37 P36 P35 P34 P70 VSS P76 P1D P1C P1B P1A P19 AVCC K P38 P39 P3A P3B P4A P4E VSS P74 P7B P7F P18 P16 P15 P17 L P3C P3D P3E P43 P49 P4D VSS P73 P7A P7E P14 P13 P12 VSS M VSS P3F P42 P44 P48 P4C VSS P72 P79 PF0 PF2 P11 P10 VCC N VCC P40 P41 P45 INITX P4B VSS P71 P78 P7D PF1 MD0 MD1 VSS P C VSS VCC X0A X1A VSS P75 P77 P7C VSS X0 X1

Document Number: 002-05667 Rev. *D Page 12 of 136 MB9B120TA Series 4. List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Pin Name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 1 1 C1 VCC - 2 2 B2 PA0 I* J SIN8_0 TIOA08_0 MAD21_0 3 3 C2 PA1 I* J SOT8_0 TIOA09_0 MAD22_0 4 4 C3 PA2 I* J SCK8_0 TIOA10_0 MAD23_0 5 5 D5 PA3 I* J SIN9_0 TIOA11_0 MAD24_0 6 6 D2 PA4 I* K SOT9_0 TIOA12_0 INT03_0 7 7 D1 PA5 I* K SCK9_0 TIOA13_0 INT10_2 8 8 D3 P05 E Q TRACED0 SIN4_2 TIOA05_2 INT00_1 9 9 D4 P06 E Q TRACED1 SOT4_2 TIOB05_2 INT01_1

Document Number: 002-05667 Rev. *D Page 13 of 136 MB9B120TA Series Pin No Pin Name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 10 10 E2 P07 E P TRACED2 ADTG_0 SCK4_2 11 11 E3 P08 E P TRACED3 CTS4_2 TIOA00_2 12 12 E4 P09 E P TRACECLK RTS4_2 TIOB00_2 13 13 E5 P50 E K SIN3_1 AIN0_2 INT00_0 MOEX_0 14 14 F1 P51 E K SOT3_1 BIN0_2 INT01_0 MWEX_0 15 15 F2 P52 E K SCK3_1 ZIN0_2 INT02_0 MDQM0_0

Document Number: 002-05667 Rev. *D Page 14 of 136 MB9B120TA Series Pin No Pin Name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 16 16 F3 P53 E K SIN6_0 TIOA01_2 INT07_2 MDQM1_0 17 17 F4 P54 E J SOT6_0 TIOB01_2 MALE_0 18 18 F5 P55 E J ADTG_1 SCK6_0 MRDY_0 19 19 F6 P56 I* S SIN1_0 TIOA09_2 INT08_2 CEC1_1 MNALE_0 20 20 G2 P57 I* K SOT1_0 TIOB09_2 INT16_1 MNCLE_0 21 21 G3 P58 I* K SCK1_0 TIOA11_2 INT17_1 MNWEX_0 22 22 G4 P59 E K SIN7_0 TIOB11_2 INT09_2 MNREX_0

Document Number: 002-05667 Rev. *D Page 15 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 23 23 G5 P5A E K SOT7_0 TIOA13_1 INT18_1 MCSX0_0 24 24 G6 P5B E K SCK7_0 TIOB13_1 INT19_1 MCSX1_0 25 - H1 P5C E K TIOA06_2 INT28_0 26 - H2 P5D E K TIOB06_2 INT29_0 27 25 A5 VSS - 28 - H3 P30 E U AIN0_0 TIOB00_1 INT03_2 WKUP4 29 - H4 P31 E K SCK6_1 BIN0_0 TIOB01_1 INT04_2 30 - H5 P32 E K SOT6_1 ZIN0_0 TIOB02_1 INT05_2 31 - H6 P33 E K ADTG_6 SIN6_1 TIOB03_1 INT04_0

Document Number: 002-05667 Rev. *D Page 16 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 32 - J5 P34 E J FRCK0_0 TIOB04_1 33 - J4 P35 E K IC03_0 TIOB05_1 INT08_1 34 26 J3 P36 E K SIN5_2 IC02_0 TIOA12_2 INT09_1 35 27 J2 P37 E K SOT5_2 IC01_0 TIOB12_2 INT10_1 36 28 K1 P38 E K SCK5_2 IC00_0 INT11_1 37 29 K2 P39 E J ADTG_2 DTTI0X_0 RTCCO_2 SUBOUT_2 38 30 K3 P3A F J RTO00_0 TIOA00_1 39 31 K4 P3B F J RTO01_0 TIOA01_1 40 32 L1 P3C F J RTO02_0 TIOA02_1 41 33 L2 P3D F J RTO03_0 TIOA03_1 42 34 L3 P3E F J RTO04_0 TIOA04_1

Document Number: 002-05667 Rev. *D Page 17 of 136 MB9B120TA Series in No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 43 35 M2 P3F F J RTO05_0 TIOA05_1 44 36 A8 VSS - 45 37 N1 VCC - 46 38 N2 P40 E K SIN10_0 TIOA00_0 INT12_1 MCSX2_0 47 39 N3 P41 E K SOT10_0 TIOA01_0 INT13_1 MCSX3_0 48 40 M3 P42 E J SCK10_0 TIOA02_0 MCLKOUT_0 49 41 L4 P43 I* J ADTG_7 SIN11_0 TIOA03_0 50 42 M4 P44 I* J SOT11_0 TIOA04_0 51 43 N4 P45 I* J SCK11_0 TIOA05_0 52 44 P2 C - 53 45 A11 VSS - 54 46 P4 VCC - 55 47 P5 P46 D F X0A 56 48 P6 P47 D G X1A 57 49 N5 INITX B C 58 50 M5 P48 E K SIN3_2 INT14_1

Document Number: 002-05667 Rev. *D Page 18 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 59 51 L5 P49 E J SOT3_2 AIN0_1 TIOB00_0 60 52 K5 P4A E J SCK3_2 BIN0_1 TIOB01_0 MADATA00_0 61 53 N6 P4B E J IGTRG0_0 ZIN0_1 TIOB02_0 MADATA01_0 62 54 M6 P4C E J SCK7_1 AIN1_2 TIOB03_0 MADATA02_0 63 55 L6 P4D E J SOT7_1 BIN1_2 TIOB04_0 MADATA03_0 64 56 K6 P4E E K SIN7_1 ZIN1_2 TIOB05_0 INT06_2 MADATA04_0 65 57 J6 P70 E J TIOA04_2 MADATA05_0 66 58 N8 P71 E K TIOB04_2 INT13_2 MADATA06_0

Document Number: 002-05667 Rev. *D Page 19 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 67 59 M8 P72 E U SIN2_0 INT14_2 WKUP2 MADATA07_0 68 60 L8 P73 E K SOT2_0 INT15_2 MADATA08_0 69 61 K8 P74 E J SCK2_0 MADATA09_0 70 62 P8 P75 E K ADTG_8 SIN3_0 INT07_1 MADATA10_0 71 63 J8 P76 E K SOT3_0 TIOA07_2 INT11_2 MADATA11_0 72 64 P9 P77 E K SCK3_0 TIOB07_2 INT12_2 MADATA12_0 73 65 N9 P78 E J AIN1_0 TIOA15_0 MADATA13_0 74 66 M9 P79 E K BIN1_0 TIOB15_0 INT23_1 MADATA14_0 - - M1 VSS - - - P3 VSS -

Document Number: 002-05667 Rev. *D Page 20 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 75 67 L9 P7A E K ZIN1_0 INT24_1 MADATA15_0 76 - K9 P7B E K TIOB07_0 INT10_0 77 - P10 P7C E K TIOA07_0 INT11_0 78 - N10 P7D E K TIOA14_1 INT12_0 79 - L10 P7E E K TIOB14_1 INT24_0 80 - K10 P7F E K TIOA15_1 INT25_0 81 - M10 PF0 I* S SIN1_2 TIOB15_1 INT13_0 CEC0_0 82 - N11 PF1 I* K SOT1_2 TIOA08_1 INT14_0 83 - M11 PF2 I* K SCK1_2 TIOB08_1 INT15_0 84 68 N13 PE0 C E MD1 85 69 N12 MD0 J D 86 70 P12 PE2 A A X0 87 71 P13 PE3 A B X1 88 72 E1 VSS - 89 73 M14 VCC - - - P7 VSS - - - N7 VSS -

Document Number: 002-05667 Rev. *D Page 21 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 90 74 M13 P10 G L AN00 91 75 M12 P11 G N AN01 SIN1_1 FRCK0_2 INT02_1 WKUP1 92 76 L13 P12 G L AN02 SOT1_1 IC00_2 93 77 L12 P13 G L AN03 SCK1_1 IC01_2 RTCCO_1 SUBOUT_1 94 78 L11 P14 G M AN04 SIN0_1 IC02_2 INT03_1 95 79 K13 P15 G L AN05 SOT0_1 IC03_2 96 80 K12 P16 G M AN06 SCK0_1 INT20_1 97 81 K14 P17 G M AN07 SIN2_2 INT04_1 - - M7 VSS - - - L7 VSS - - - K7 VSS -

Document Number: 002-05667 Rev. *D Page 22 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 98 82 K11 P18 G M AN08 SOT2_2 INT21_1 99 83 J13 P19 G M AN09 SCK2_2 INT22_1 100 84 J12 P1A G M AN10 SIN4_1 IC00_1 TIOA13_2 INT05_1 101 85 J11 P1B G M AN11 SOT4_1 IC01_1 TIOB13_2 INT25_1 102 86 J10 P1C G M AN12 SCK4_1 IC02_1 TIOA14_2 INT26_1 103 87 J9 P1D G M AN13 CTS4_1 IC03_1 TIOB14_2 INT27_1 104 88 H10 P1E G M AN14 RTS4_1 DTTI0X_1 TIOA15_2 INT28_1

Document Number: 002-05667 Rev. *D Page 23 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 105 89 H9 P1F G M AN15 ADTG_5 FRCK0_1 TIOB15_2 INT29_1 106 - H13 PB0 E K SIN7_2 TIOA09_1 INT16_0 107 - H12 PB1 E K SOT7_2 TIOB09_1 INT17_0 108 - H11 PB2 E K SCK7_2 TIOA10_1 INT18_0 109 - G13 PB3 E K TIOB10_1 INT19_0 110 - G12 PB4 E K SIN0_2 TIOA11_1 INT20_0 111 - G11 PB5 E K SOT0_2 TIOB11_1 INT21_0 112 - G10 PB6 E K SCK0_2 TIOA12_1 INT22_0 113 - G9 PB7 E K TIOB12_1 INT23_0 114 90 J14 AVCC - 115 91 H14 AVSS - - - J7 VSS - - - P11 VSS -

Document Number: 002-05667 Rev. *D Page 24 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 116 92 G14 AVRL - 117 93 F14 AVRH - 118 94 F10 P29 G L AN16 SIN12_0 119 95 F11 P28 G M AN17 ADTG_4 SOT12_0 RTO05_1 INT09_0 120 96 F12 P27 G M AN18 SCK12_0 RTO04_1 INT02_2 121 97 F13 P26 G L AN19 SCK2_1 RTO03_1 122 98 E10 P25 G L AN20 SOT2_1 RTO02_1 123 99 E11 P24 G M AN21 SIN2_1 RTO01_1 INT01_2

Document Number: 002-05667 Rev. *D Page 25 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 124 100 E12 P23 G L AN22 SCK0_0 RTO00_1 TIOA07_1 125 101 E13 P22 G L AN23 SOT0_0 ZIN1_1 TIOB07_1 126 102 D12 P21 E K SIN0_0 BIN1_1 INT06_1 127 103 D13 P20 E K AIN1_1 INT05_0 CROUT_0 128 104 C13 PF6 I* H NMIX WKUP0 129 105 E14 P82 E J MCSX7_0 130 106 D14 P83 E J MCSX6_0 131 107 C14 VCC - 132 108 G7 VSS - 133 109 A13 VCC - 134 110 B13 P00 E I TRSTX 135 111 A12 P01 E I TCK SWCLK 136 112 C12 P02 E I TDI 137 113 B12 P03 E I TMS SWDIO 138 114 B11 P04 E I TDO SWO 139 - C11 P90 E K TIOB08_0 INT30_0 - - N14 VSS -

Document Number: 002-05667 Rev. *D Page 26 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 140 - D11 P91 E K TIOB09_0 INT31_0 141 - B10 P92 E J SIN5_1 TIOB10_0 142 - C10 P93 E J SOT5_1 TIOB11_0 143 - D10 P94 E K SCK5_1 TIOB12_0 INT26_0 144 - B9 P95 E K TIOB13_0 INT27_0 145 115 C9 PC0 H O DA0_0 SIN13_0 MCSX5_0 146 116 B8 PC1 H O DA1_0 SOT13_0 MCSX4_0 147 117 D9 PC2 E J SCK13_0 MAD00_0 148 118 E9 PC3 E J TIOA06_1 MAD01_0 149 119 F9 PC4 I* R SIN14_0 TIOA08_2 CEC0_1 MAD02_0 150 120 C8 PC5 I* J SOT14_0 TIOA10_2 MAD03_0 - - L14 VSS -

Document Number: 002-05667 Rev. *D Page 27 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 151 121 D8 PC6 I* J SCK14_0 TIOA14_0 MAD04_0 152 122 E8 PC7 E J CROUT_1 RTCCO_0 SUBOUT_0 MAD05_0 153 123 A10 PC8 E J SIN15_0 MAD06_0 154 124 F8 PC9 E J SOT15_0 MAD07_0 155 125 B7 PCA E J SCK15_0 MAD08_0 156 126 A9 VCC - 157 127 G8 VSS - 158 128 A7 PCB E J MAD09_0 159 129 C7 PCC E J MAD10_0 160 130 A6 PCD E J MAD11_0 161 131 D7 PCE E J RTS4_0 TIOB06_1 MAD12_0 162 132 E7 PCF E J CTS4_0 TIOB08_2 MAD13_0 163 133 F7 PD0 E K SCK4_0 TIOB10_2 INT30_1 MAD14_0 164 134 B6 PD1 E K SOT4_0 TIOB14_0 INT31_1 MAD15_0 - - B14 VSS - - - H7 VSS - - - B1 VSS - - - G1 VSS -

Document Number: 002-05667 Rev. *D Page 28 of 136 MB9B120TA Series Pin No Pin name I/O circuit type Pin state type LQFP-176 LQFP-144 BGA-192 165 135 C6 PD2 E K SIN4_0 TIOA03_2 INT00_2 MAD16_0 166 136 D6 PD3 E J TIOB03_2 MAD17_0 167 137 E6 P62 E J ADTG_3 SCK5_0 MAD18_0 168 138 B5 P61 E J SOT5_0 TIOB02_2 MAD19_0 169 139 C5 P60 E U SIN5_0 TIOA02_2 INT15_1 WKUP5 MAD20_0 170 - B4 PF3 I* K SIN6_2 TIOA06_0 INT06_0 171 - C4 PF4 I* K SOT6_2 TIOB06_0 INT07_0 172 140 B3 PF5 I* T IGTRG0_1 INT08_0 WKUP3 CEC1_0 - SCK6_2 173 141 A4 VCC - 174 142 A3 P80 K V 175 143 A2 P81 K V 176 144 H8 VSS - - - J1 VSS - *: 5V tolerant I/O

Document Number: 002-05667 Rev. *D Page 29 of 136 MB9B120TA Series List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 ADC ADTG_0 A/D converter external trigger input pin 10 10 E2 ADTG_1 18 18 F5 ADTG_2 37 29 K2 ADTG_3 167 137 E6 ADTG_4 119 95 F11 ADTG_5 105 89 H9 ADTG_6 31 - H6 ADTG_7 49 41 L4 ADTG_8 70 62 P8 AN00 A/D converter analog input pin. ANxx describes ADC ch.xx. 90 74 M13 AN01 91 75 M12 AN02 92 76 L13 AN03 93 77 L12 AN04 94 78 L11 AN05 95 79 K13 AN06 96 80 K12 AN07 97 81 K14 AN08 98 82 K11 AN09 99 83 J13 AN10 100 84 J12 AN11 101 85 J11 AN12 102 86 J10 AN13 103 87 J9 AN14 104 88 H10 AN15 105 89 H9 AN16 118 94 F10 AN17 119 95 F11 AN18 120 96 F12 AN19 121 97 F13 AN20 122 98 E10 AN21 123 99 E11 AN22 124 100 E12 AN23 125 101 E13

Document Number: 002-05667 Rev. *D Page 30 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 Base Timer TIOA00_0 Base timer ch.0 TIOA pin 46 38 N2 TIOA00_1 38 30 K3 TIOA00_2 11 11 E3 TIOB00_0 Base timer ch.0 TIOB pin 59 51 L5 TIOB00_1 28 - H3 TIOB00_2 12 12 E4 Base Timer TIOA01_0 Base timer ch.1 TIOA pin 47 39 N3 TIOA01_1 39 31 K4 TIOA01_2 16 16 F3 TIOB01_0 Base timer ch.1 TIOB pin 60 52 K5 TIOB01_1 29 - H4 TIOB01_2 17 17 F4 Base Timer TIOA02_0 Base timer ch.2 TIOA pin 48 40 M3 TIOA02_1 40 32 L1 TIOA02_2 169 139 C5 TIOB02_0 Base timer ch.2 TIOB pin 61 53 N6 TIOB02_1 30 - H5 TIOB02_2 168 138 B5 Base Timer TIOA03_0 Base timer ch.3 TIOA pin 49 41 L4 TIOA03_1 41 33 L2 TIOA03_2 165 135 C6 TIOB03_0 Base timer ch.3 TIOB pin 62 54 M6 TIOB03_1 31 - H6 TIOB03_2 166 136 D6 Base Timer TIOA04_0 Base timer ch.4 TIOA pin 50 42 M4 TIOA04_1 42 34 L3 TIOA04_2 65 57 J6 TIOB04_0 Base timer ch.4 TIOB pin 63 55 L6 TIOB04_1 32 - J5 TIOB04_2 66 58 N8 Base Timer TIOA05_0 Base timer ch.5 TIOA pin 51 43 N4 TIOA05_1 43 35 M2 TIOA05_2 8 8 D3 TIOB05_0 Base timer ch.5 TIOB pin 64 56 K6 TIOB05_1 33 - J4 TIOB05_2 9 9 D4 Base Timer TIOA06_0 Base timer ch.6 TIOA pin 170 - B4 TIOA06_1 148 118 E9 TIOA06_2 25 - H1 TIOB06_0 Base timer ch.6 TIOB pin 171 - C4 TIOB06_1 161 131 D7 TIOB06_2 26 - H2

Document Number: 002-05667 Rev. *D Page 31 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 Base Timer TIOA07_0 Base timer ch.7 TIOA pin 77 - P10 TIOA07_1 124 100 E12 TIOA07_2 71 63 J8 TIOB07_0 Base timer ch.7 TIOB pin 76 - K9 TIOB07_1 125 101 E13 TIOB07_2 72 64 P9 Base Timer TIOA08_0 Base timer ch.8 TIOA pin 2 2 B2 TIOA08_1 82 - N11 TIOA08_2 149 119 F9 TIOB08_0 Base timer ch.8 TIOB pin 139 - C11 TIOB08_1 83 - M11 TIOB08_2 162 132 E7 Base Timer TIOA09_0 Base timer ch.9 TIOA pin 3 3 C2 TIOA09_1 106 - H13 TIOA09_2 19 19 F6 TIOB09_0 Base timer ch.9 TIOB pin 140 - D11 TIOB09_1 107 - H12 TIOB09_2 20 20 G2 Base Timer TIOA10_0 Base timer ch.10 TIOA pin 4 4 C3 TIOA10_1 108 - H11 TIOA10_2 150 120 C8 TIOB10_0 Base timer ch.10 TIOB pin 141 - B10 TIOB10_1 109 - G13 TIOB10_2 163 133 F7 Base Timer TIOA11_0 Base timer ch.11 TIOA pin 5 5 D5 TIOA11_1 110 - G12 TIOA11_2 21 21 G3 TIOB11_0 Base timer ch.11 TIOB pin 142 - C10 TIOB11_1 111 - G11 TIOB11_2 22 22 G4 Base Timer TIOA12_0 Base timer ch.12 TIOA pin 6 6 D2 TIOA12_1 112 - G10 TIOA12_2 34 26 J3 TIOB12_0 Base timer ch.12 TIOB pin 143 - D10 TIOB12_1 113 - G9 TIOB12_2 35 27 J2 Base Timer TIOA13_0 Base timer ch.13 TIOA pin 7 7 D1 TIOA13_1 23 23 G5 TIOA13_2 100 84 J12 TIOB13_0 Base timer ch.13 TIOB pin 144 - B9 TIOB13_1 24 24 G6 TIOB13_2 101 85 J11

Document Number: 002-05667 Rev. *D Page 32 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 Base Timer TIOA14_0 Base timer ch.14 TIOA pin 151 121 D8 TIOA14_1 78 - N10 TIOA14_2 102 86 J10 TIOB14_0 Base timer ch.14 TIOB pin 164 134 B6 TIOB14_1 79 - L10 TIOB14_2 103 87 J9 Base Timer TIOA15_0 Base timer ch.15 TIOA pin 73 65 N9 TIOA15_1 80 - K10 TIOA15_2 104 88 H10 TIOB15_0 Base timer ch.15 TIOB pin 74 66 M9 TIOB15_1 81 - M10 TIOB15_2 105 89 H9 Debugger SWCLK Serial wire debug interface clock input 135 111 A12 SWDIO Serial wire debug interface data input / output 137 113 B12 SWO Serial wire viewer output 138 114 B11 TCK JTAG test clock input 135 111 A12 TDI JTAG test data input 136 112 C12 TDO JTAG debug data output 138 114 B11 TMS JTAG test mode state input/output 137 113 B12 TRACECLK Trace CLK output of ETM 12 12 E4 TRACED0 Trace data output of ETM 8 8 D3 TRACED1 9 9 D4 TRACED2 10 10 E2 TRACED3 11 11 E3 TRSTX JTAG test reset Input 134 110 B13

Document Number: 002-05667 Rev. *D Page 33 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 External Bus MAD00_0 External bus interface address bus 147 117 D9 MAD01_0 148 118 E9 MAD02_0 149 119 F9 MAD03_0 150 120 C8 MAD04_0 151 121 D8 MAD05_0 152 122 E8 MAD06_0 153 123 A10 MAD07_0 154 124 F8 MAD08_0 155 125 B7 MAD09_0 158 128 A7 MAD10_0 159 129 C7 MAD11_0 160 130 A6 MAD12_0 161 131 D7 MAD13_0 162 132 E7 MAD14_0 163 133 F7 MAD15_0 164 134 B6 MAD16_0 165 135 C6 MAD17_0 166 136 D6 MAD18_0 167 137 E6 MAD19_0 168 138 B5 MAD20_0 169 139 C5 MAD21_0 2 2 B2 MAD22_0 3 3 C2 MAD23_0 4 4 C3 MAD24_0 5 5 D5 MCSX0_0 External bus interface chip select output pin 23 23 G5 MCSX1_0 24 24 G6 MCSX2_0 46 38 N2 MCSX3_0 47 39 N3 MCSX4_0 146 116 B8 MCSX5_0 145 115 C9 MCSX6_0 130 106 D14 MCSX7_0 129 105 E14 MDQM0_0 External bus interface byte mask signal output 15 15 F2 MDQM1_0 16 16 F3 MOEX_0 External bus interface read enable signal for SRAM 13 13 E5 MWEX_0 External bus interface write enable signal for SRAM 14 14 F1

Document Number: 002-05667 Rev. *D Page 34 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 External Bus MNALE_0 External bus interface ALE signal to control NAND Flash output pin 19 19 F6 MNCLE_0 External bus interface CLE signal to control NAND Flash output pin 20 20 G2 MNREX_0 External bus interface read enable signal to control NAND Flash 22 22 G4 MNWEX_0 External bus interface write enable signal to control NAND Flash 21 21 G3 MADATA00_0 External bus interface data bus (Address / data multiplex bus) 60 52 K5 MADATA01_0 61 53 N6 MADATA02_0 62 54 M6 MADATA03_0 63 55 L6 MADATA04_0 64 56 K6 MADATA05_0 65 57 J6 MADATA06_0 66 58 N8 MADATA07_0 67 59 M8 MADATA08_0 68 60 L8 MADATA09_0 69 61 K8 MADATA10_0 70 62 P8 MADATA11_0 71 63 J8 MADATA12_0 72 64 P9 MADATA13_0 73 65 N9 MADATA14_0 74 66 M9 MADATA15_0 75 67 L9 MALE_0 External bus interface Address Latch enable output signal for multiplex 17 17 F4 MRDY_0 External bus interface external RDY input signal 18 18 F5 MCLKOUT_0 External bus interface external clock output 48 40 M3

Document Number: 002-05667 Rev. *D Page 35 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 External Interrupt INT00_0 External interrupt request 00 input pin 13 13 E5 INT00_1 8 8 D3 INT00_2 165 135 C6 INT01_0 External interrupt request 01 input pin 14 14 F1 INT01_1 9 9 D4 INT01_2 123 99 E11 INT02_0 External interrupt request 02 input pin 15 15 F2 INT02_1 91 75 M12 INT02_2 120 96 F12 INT03_0 External interrupt request 03 input pin 6 6 D2 INT03_1 94 78 L11 INT03_2 28 - H3 INT04_0 External interrupt request 04 input pin 31 - H6 INT04_1 97 81 K14 INT04_2 29 - H4 INT05_0 External interrupt request 05 input pin 127 103 D13 INT05_1 100 84 J12 INT05_2 30 - H5 INT06_0 External interrupt request 06 input pin 170 - B4 INT06_1 126 102 D12 INT06_2 64 56 K6 INT07_0 External interrupt request 07 input pin 171 - C4 INT07_1 70 62 P8 INT07_2 16 16 F3 INT08_0 External interrupt request 08 input pin 172 140 B3 INT08_1 33 - J4 INT08_2 19 19 F6 INT09_0 External interrupt request 09 input pin 119 95 F11 INT09_1 34 26 J3 INT09_2 22 22 G4 INT10_0 External interrupt request 10 input pin 76 - K9 INT10_1 35 27 J2 INT10_2 7 7 D1 INT11_0 External interrupt request 11 input pin 77 - P10 INT11_1 36 28 K1 INT11_2 71 63 J8 INT12_0 External interrupt request 12 input pin 78 - N10 INT12_1 46 38 N2 INT12_2 72 64 P9 INT13_0 External interrupt request 13 input pin 81 - M10 INT13_1 47 39 N3 INT13_2 66 58 N8 INT14_0 External interrupt request 14 input pin 82 - N11 INT14_1 58 50 M5 INT14_2 67 59 M8

Document Number: 002-05667 Rev. *D Page 36 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 External Interrupt INT15_0 External interrupt request 15 input pin 83 - M11 INT15_1 169 139 C5 INT15_2 68 60 L8 INT16_0 External interrupt request 16 input pin 106 - H13 INT16_1 20 20 G2 INT17_0 External interrupt request 17 input pin 107 - H12 INT17_1 21 21 G3 INT18_0 External interrupt request 18 input pin 108 - H11 INT18_1 23 23 G5 INT19_0 External interrupt request 19 input pin 109 - G13 INT19_1 24 24 G6 INT20_0 External interrupt request 20 input pin 110 - G12 INT20_1 96 80 K12 INT21_0 External interrupt request 21 input pin 111 - G11 INT21_1 98 82 K11 INT22_0 External interrupt request 22 input pin 112 - G10 INT22_1 99 83 J13 INT23_0 External interrupt request 23 input pin 113 - G9 INT23_1 74 66 M9 INT24_0 External interrupt request 24 input pin 79 - L10 INT24_1 75 67 L9 INT25_0 External interrupt request 25 input pin 80 - K10 INT25_1 101 85 J11 INT26_0 External interrupt request 26 input pin 143 - D10 INT26_1 102 86 J10 INT27_0 External interrupt request 27 input pin 144 - B9 INT27_1 103 87 J9 INT28_0 External interrupt request 28 input pin 25 - H1 INT28_1 104 88 H10 INT29_0 External interrupt request 29 input pin 26 - H2 INT29_1 105 89 H9 INT30_0 External interrupt request 30 input pin 139 - C11 INT30_1 163 133 F7 INT31_0 External interrupt request 31 input pin 140 - D11 INT31_1 164 134 B6 NMIX Non-Maskable Interrupt input 128 104 C13

Document Number: 002-05667 Rev. *D Page 37 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 GPIO P00 General-purpose I/O port 0 134 110 B13 P01 135 111 A12 P02 136 112 C12 P03 137 113 B12 P04 138 114 B11 P05 8 8 D3 P06 9 9 D4 P07 10 10 E2 P08 11 11 E3 P09 12 12 E4 P10 General-purpose I/O port 1 90 74 M13 P11 91 75 M12 P12 92 76 L13 P13 93 77 L12 P14 94 78 L11 P15 95 79 K13 P16 96 80 K12 P17 97 81 K14 P18 98 82 K11 P19 99 83 J13 P1A 100 84 J12 P1B 101 85 J11 P1C 102 86 J10 P1D 103 87 J9 P1E 104 88 H10 P1F 105 89 H9 P20 General-purpose I/O port 2 127 103 D13 P21 126 102 D12 P22 125 101 E13 P23 124 100 E12 P24 123 99 E11 P25 122 98 E10 P26 121 97 F13 P27 120 96 F12 P28 119 95 F11 P29 118 94 F10

Document Number: 002-05667 Rev. *D Page 38 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 GPIO P30 General-purpose I/O port 3 28 - H3 P31 29 - H4 P32 30 - H5 P33 31 - H6 P34 32 - J5 P35 33 - J4 P36 34 26 J3 P37 35 27 J2 P38 36 28 K1 P39 37 29 K2 P3A 38 30 K3 P3B 39 31 K4 P3C 40 32 L1 P3D 41 33 L2 P3E 42 34 L3 P3F 43 35 M2 P40 General-purpose I/O port 4 46 38 N2 P41 47 39 N3 P42 48 40 M3 P43 49 41 L4 P44 50 42 M4 P45 51 43 N4 P46 55 47 P5 P47 56 48 P6 P48 58 50 M5 P49 59 51 L5 P4A 60 52 K5 P4B 61 53 N6 P4C 62 54 M6 P4D 63 55 L6 P4E 64 56 K6 P50 General-purpose I/O port 5 13 13 E5 P51 14 14 F1 P52 15 15 F2 P53 16 16 F3 P54 17 17 F4 P55 18 18 F5 P56 19 19 F6 P57 20 20 G2 P58 21 21 G3 P59 22 22 G4 P5A 23 23 G5 P5B 24 24 G6 P5C 25 - H1 P5D 26 - H2

Document Number: 002-05667 Rev. *D Page 39 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 GPIO P60 General-purpose I/O port 6 169 139 C5 P61 168 138 B5 P62 167 137 E6 P70 General-purpose I/O port 7 65 57 J6 P71 66 58 N8 P72 67 59 M8 P73 68 60 L8 P74 69 61 K8 P75 70 62 P8 P76 71 63 J8 P77 72 64 P9 P78 73 65 N9 P79 74 66 M9 P7A 75 67 L9 P7B 76 - K9 P7C 77 - P10 P7D 78 - N10 P7E 79 - L10 P7F 80 - K10 P80 General-purpose I/O port 8 174 142 A3 P81 175 143 A2 P82 129 105 E14 P83 130 106 D14 P90 General-purpose I/O port 9 139 - C11 P91 140 - D11 P92 141 - B10 P93 142 - C10 P94 143 - D10 P95 144 - B9 PA0 General-purpose I/O port A 2 2 B2 PA1 3 3 C2 PA2 4 4 C3 PA3 5 5 D5 PA4 6 6 D2 PA5 7 7 D1 PB0 General-purpose I/O port B 106 - H13 PB1 107 - H12 PB2 108 - H11 PB3 109 - G13 PB4 110 - G12 PB5 111 - G11 PB6 112 - G10 PB7 113 - G9

Document Number: 002-05667 Rev. *D Page 40 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 GPIO PC0 General-purpose I/O port C 145 115 C9 PC1 146 116 B8 PC2 147 117 D9 PC3 148 118 E9 PC4 149 119 F9 PC5 150 120 C8 PC6 151 121 D8 PC7 152 122 E8 PC8 153 123 A10 PC9 154 124 F8 PCA 155 125 B7 PCB 158 128 A7 PCC 159 129 C7 PCD 160 130 A6 PCE 161 131 D7 PCF 162 132 E7 PD0 General-purpose I/O port D 163 133 F7 PD1 164 134 B6 PD2 165 135 C6 PD3 166 136 D6 PE0 General-purpose I/O port E 84 68 N13 PE2 86 70 P12 PE3 87 71 P13 PF0 General-purpose I/O port F* 81 - M10 PF1 82 - N11 PF2 83 - M11 PF3 170 - B4 PF4 171 - C4 PF5 172 140 B3 PF6 128 104 C13

Document Number: 002-05667 Rev. *D Page 41 of 136 MB9B120TA Series Pin function Pin name Function description Pin No. LQFP-176 LQFP-144 BGA-192 Multi Function Serial SIN0_0 Multifunction serial interface ch.0 input pin 126 102 D12 SIN0_1 94 78 L11 SIN0_2 110 - G12 SOT0_0 (SDA0_0) Multifunction serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). 125 101 E13 SOT0_1 (SDA0_1) 95 79 K13 SOT0_2 (SDA0_2) 111 - G11 SCK0_0 (SCL0_0) Multifunction serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 4). 124 100 E12 SCK0_1 (SCL0_1) 96 80 K12 SCK0_2 (SCL0_2) 112 - G10 Multi Function Serial SIN1_0 Multifunction serial interface ch.1 input pin 19 19 F6 SIN1_1 91 75 M12 SIN1_2 81 - M10 SOT1_0 (SDA1_0) Multifunction serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). 20 20 G2 SOT1_1 (SDA1_1) 92 76 L13 SOT1_2 (SDA1_2) 82 - N11 SCK1_0 (SCL1_0) Multifunction serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). 21 21 G3 SCK1_1 (SCL1_1) 93 77 L12 SCK1_2 (SCL1_2) 83 - M11

Document Number: 002-05667 Rev. *D Page 42 of 136 MB9B120TA Series Pin function Pin name Function description Pin No. LQFP-176 LQFP-144 BGA-192 Multi Function Serial SIN2_0 Multifunction serial interface ch.2 input pin 67 59 M8 SIN2_1 123 99 E11 SIN2_2 97 81 K14 SOT2_0 (SDA2_0) Multifunction serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). 68 60 L8 SOT2_1 (SDA2_1) 122 98 E10 SOT2_2 (SDA2_2) 98 82 K11 SCK2_0 (SCL2_0) Multifunction serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). 69 61 K8 SCK2_1 (SCL2_1) 121 97 F13 SCK2_2 (SCL2_2) 99 83 J13 Multi Function Serial SIN3_0 Multifunction serial interface ch.3 input pin 70 62 P8 SIN3_1 13 13 E5 SIN3_2 58 50 M5 SOT3_0 (SDA3_0) Multifunction serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). 71 63 J8 SOT3_1 (SDA3_1) 14 14 F1 SOT3_2 (SDA3_2) 59 51 L5 SCK3_0 (SCL3_0) Multifunction serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). 72 64 P9 SCK3_1 (SCL3_1) 15 15 F2 SCK3_2 (SCL3_2) 60 52 K5

Document Number: 002-05667 Rev. *D Page 43 of 136 MB9B120TA Series Pin function Pin name Function description Pin No. LQFP-176 LQFP-144 BGA-192 Multi Function Serial SIN4_0 Multifunction serial interface ch.4 input pin 165 135 C6 SIN4_1 100 84 J12 SIN4_2 8 8 D3 SOT4_0 (SDA4_0) Multifunction serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). 164 134 B6 SOT4_1 (SDA4_1) 101 85 J11 SOT4_2 (SDA4_2) 9 9 D4 SCK4_0 (SCL4_0) Multifunction serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). 163 133 F7 SCK4_1 (SCL4_1) 102 86 J10 SCK4_2 (SCL4_2) 10 10 E2 RTS4_0 Multifunction serial interface ch.4 RTS output pin 161 131 D7 RTS4_1 104 88 H10 RTS4_2 12 12 E4 CTS4_0 Multifunction serial interface ch.4 CTS input pin 162 132 E7 CTS4_1 103 87 J9 CTS4_2 11 11 E3 Multi Function Serial SIN5_0 Multifunction serial interface ch.5 input pin 169 139 C5 SIN5_1 141 - B10 SIN5_2 34 26 J3 SOT5_0 (SDA5_0) Multifunction serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). 168 138 B5 SOT5_1 (SDA5_1) 142 - C10 SOT5_2 (SDA5_2) 35 27 J2 SCK5_0 (SCL5_0) Multifunction serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). 167 137 E6 SCK5_1 (SCL5_1) 143 - D10 SCK5_2 (SCL5_2) 36 28 K1

Document Number: 002-05667 Rev. *D Page 44 of 136 MB9B120TA Series Pin function Pin name Function description Pin No. LQFP-176 LQFP-144 BGA-192 Multi Function Serial SIN6_0 Multifunction serial interface ch.6 input pin 16 16 F3 SIN6_1 31 - H6 SIN6_2 170 - B4 SOT6_0 (SDA6_0) Multifunction serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). 17 17 F4 SOT6_1 (SDA6_1) 30 - H5 SOT6_2 (SDA6_2) 171 - C4 SCK6_0 (SCL6_0) Multifunction serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). 18 18 F5 SCK6_1 (SCL6_1) 29 - H4 SCK6_2 (SCL6_2) 172 - B3 Multi Function Serial SIN7_0 Multifunction serial interface ch.7 input pin 22 22 G4 SIN7_1 64 56 K6 SIN7_2 106 - H13 SOT7_0 (SDA7_0) Multifunction serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). 23 23 G5 SOT7_1 (SDA7_1) 63 55 L6 SOT7_2 (SDA7_2) 107 - H12 SCK7_0 (SCL7_0) Multifunction serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). 24 24 G6 SCK7_1 (SCL7_1) 62 54 M6 SCK7_2 (SCL7_2) 108 - H11

Document Number: 002-05667 Rev. *D Page 45 of 136 MB9B120TA Series Pin function Pin name Function description Pin No. LQFP-176 LQFP-144 BGA-192 Multi Function Serial SIN8_0 Multifunction serial interface ch.8 input pin 2 2 B2 SOT8_0 (SDA8_0) Multifunction serial interface ch.6 output pin. This pin operates as SOT8 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA8 when it is used in an I2C (operation mode 4). 3 3 C2 SCK8_0 (SCL8_0) Multifunction serial interface ch.7 clock I/O pin. This pin operates as SCK8 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL8 when it is used in an I2C (operation mode 4). 4 4 C3 Multi Function Serial SIN9_0 Multifunction serial interface ch.9 input pin 5 5 D5 SOT9_0 (SDA9_0) Multifunction serial interface ch.9 output pin. This pin operates as SOT9 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA9 when it is used in an I2C (operation mode 4). 6 6 D2 SCK9_0 (SCL9_0) Multifunction serial interface ch.9 clock I/O pin. This pin operates as SCK9 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL9 when it is used in an I2C (operation mode 4). 7 7 D1

Document Number: 002-05667 Rev. *D Page 46 of 136 MB9B120TA Series Pin function Pin name Function description Pin No. LQFP-176 LQFP-144 BGA-192 Multi Function Serial SIN10_0 Multifunction serial interface ch.10 input pin 46 38 N2 SOT10_0 (SDA10_0) Multifunction serial interface ch.10 output pin. This pin operates as SOT10 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA10 when it is used in an I2C (operation mode 4). 47 39 N3 SCK10_0 (SCL10_0) Multifunction serial interface ch.10 clock I/O pin. This pin operates as SCK10 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL10 when it is used in an I2C (operation mode 4). 48 40 M3 Multi Function Serial SIN11_0 Multifunction serial interface ch.11 input pin 49 41 L4 SOT11_0 (SDA11_0) Multifunction serial interface ch.11 output pin. This pin operates as SOT11 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA11 when it is used in an I2C (operation mode 4). 50 42 M4 SCK11_0 (SCL11_0) Multifunction serial interface ch.11 clock I/O pin. This pin operates as SCK11 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL11 when it is used in an I2C (operation mode 4). 51 43 N4

Document Number: 002-05667 Rev. *D Page 47 of 136 MB9B120TA Series Pin function Pin name Function description Pin No. LQFP-176 LQFP-144 BGA-192 Multi Function Serial SIN12_0 Multifunction serial interface ch.12 input pin 118 94 F10 SOT12_0 (SDA12_0) Multifunction serial interface ch.12 output pin. This pin operates as SOT12 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA12 when it is used in an I2C (operation mode 4). 119 95 F11 SCK12_0 (SCL12_0) Multifunction serial interface ch.12 clock I/O pin. This pin operates as SCK12 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL12 when it is used in an I2C (operation mode 4). 120 96 F12 Multi Function Serial SIN13_0 Multifunction serial interface ch.13 input pin 145 115 C9 SOT13_0 (SDA13_0) Multifunction serial interface ch.13 output pin. This pin operates as SOT13 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA13 when it is used in an I2C (operation mode 4). 146 116 B8 SCK13_0 (SCL13_0) Multifunction serial interface ch.13 clock I/O pin. This pin operates as SCK13 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL13 when it is used in an I2C (operation mode 4). 147 117 D9

Document Number: 002-05667 Rev. *D Page 48 of 136 MB9B120TA Series Pin function Pin name Function description Pin No. LQFP-176 LQFP-144 BGA-192 Multi Function Serial SIN14_0 Multifunction serial interface ch.14 input pin 149 119 F9 SOT14_0 (SDA14_0) Multifunction serial interface ch.14 output pin. This pin operates as SOT14 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA14 when it is used in an I2C (operation mode 4). 150 120 C8 SCK14_0 (SCL14_0) Multifunction serial interface ch.14 clock I/O pin. This pin operates as SCK14 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL14 when it is used in an I2C (operation mode 4). 151 121 D8 Multi Function Serial SIN15_0 Multifunction serial interface ch.15 input pin 153 123 A10 SOT15_0 (SDA15_0) Multifunction serial interface ch.15 output pin. This pin operates as SOT15 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA15 when it is used in an I2C (operation mode 4). 154 124 F8 SCK15_0 (SCL15_0) Multifunction serial interface ch.15 clock I/O pin. This pin operates as SCK15 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL15 when it is used in an I2C (operation mode 4). 155 125 B7

Document Number: 002-05667 Rev. *D Page 49 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 Multi Function Timer DTTI0X_0 Input signal controlling wave form generator outputs RTO00 to RTO05 of multi-function timer 0. 37 29 K2 DTTI0X_1 104 88 H10 FRCK0_0 16-bit free-run timer ch.0 external clock input pin 32 - J5 FRCK0_1 105 89 H9 FRCK0_2 91 75 M12 IC00_0 16-bit input capture ch.0 input pin of multi-function timer 0. ICxx describes channel number. 36 28 K1 IC00_1 100 84 J12 IC00_2 92 76 L13 IC01_0 35 27 J2 IC01_1 101 85 J11 IC01_2 93 77 L12 IC02_0 34 26 J3 IC02_1 102 86 J10 IC02_2 94 78 L11 IC03_0 33 - J4 IC03_1 103 87 J9 IC03_2 95 79 K13 RTO00_0 (PPG00_0) Wave form generator output of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 38 30 K3 RTO00_1 (PPG00_1) 124 100 E12 RTO01_0 (PPG00_0) Wave form generator output of multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 39 31 K4 RTO01_1 (PPG00_1) 123 99 E11 RTO02_0 (PPG02_0) Wave form generator output of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 40 32 L1 RTO02_1 (PPG02_1) 122 98 E10 RTO03_0 (PPG02_0) Wave form generator output of multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 41 33 L2 RTO03_1 (PPG02_1) 121 97 F13 RTO04_0 (PPG04_0) Wave form generator output of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 42 34 L3 RTO04_1 (PPG04_1) 120 96 F12 RTO05_0 (PPG04_0) Wave form generator output of multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 43 35 M2 RTO05_1 (PPG04_1) 119 95 F11 IGTRG0_0 PPG IGBT mode external trigger input pin 61 53 N6 IGTRG0_1 172 140 B3

Document Number: 002-05667 Rev. *D Page 50 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 Quadrature Position/ Revolution Counter AIN0_0 QPRC ch.0 AIN input pin 28 - H3 AIN0_1 59 51 L5 AIN0_2 13 13 E5 BIN0_0 QPRC ch.0 BIN input pin 29 - H4 BIN0_1 60 52 K5 BIN0_2 14 14 F1 ZIN0_0 QPRC ch.0 ZIN input pin 30 - H5 ZIN0_1 61 53 N6 ZIN0_2 15 15 F2 Quadrature Position/ Revolution Counter AIN1_0 QPRC ch.1 AIN input pin 73 65 N9 AIN1_1 127 103 D13 AIN1_2 62 54 M6 BIN1_0 QPRC ch.1 BIN input pin 74 66 M9 BIN1_1 126 102 D12 BIN1_2 63 55 L6 ZIN1_0 QPRC ch.1 ZIN input pin 75 67 L9 ZIN1_1 125 101 E13 ZIN1_2 64 56 K6 Real-time clock RTCCO_0 0.5 seconds pulse output pin of Real-time clock 152 122 E8 RTCCO_1 93 77 L12 RTCCO_2 37 29 K2 SUBOUT_0 Sub clock output pin 152 122 E8 SUBOUT_1 93 77 L12 SUBOUT_2 37 29 K2

Document Number: 002-05667 Rev. *D Page 51 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 Reset INITX External Reset Input. A reset is valid when INITX="L". 57 49 N5 Mode MD0 Mode 0 Pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. 85 69 N12 MD1 Mode 1 Pin. During serial programming to Flash memory, MD1="L" must be input. 84 68 N13 Power VCC Power supply Pin 1 1 C1 45 37 N1 54 46 P4 89 73 M14 131 107 C14 133 109 A13 156 126 A9 Low-Power Consumption Mode WKUP0 Deep standby mode return signal input pin 0 128 104 C13 WKUP1 Deep standby mode return signal input pin 1 91 75 M12 WKUP2 Deep standby mode return signal input pin 2 67 59 M8 WKUP3 Deep standby mode return signal input pin 3 172 140 B3 WKUP4 Deep standby mode return signal input pin 4 28 - H3 WKUP5 Deep standby mode return signal input pin 5 169 139 C5 HDMI- CEC/ Remote Control Reception CEC0_0 HDMI-CEC/Remote Control Reception ch.0 input/output pin 81 - M10 CEC0_1 149 119 F9 CEC1_0 HDMI-CEC/Remote Control Reception ch.1 input/output pin 172 140 B3 CEC1_1 19 19 F6 DAC DA0_0 D/A converter ch.0 analog output pin 145 115 C9 DA1_0 D/A converter ch.1 analog output pin 146 116 B8

Document Number: 002-05667 Rev. *D Page 52 of 136 MB9B120TA Series Pin function Pin name Function description Pin No LQFP-176 LQFP-144 BGA-192 GND VSS GND Pin 27 25 A5 44 36 A8 53 45 A11 88 72 E1 132 108 G7 157 127 G8 176 144 H8 - - M1 - - P3 - - P7 - - N7 - - M7 - - L7 - - K7 - - J7 - - P11 - - N14 - - L14 - - B14 - - H7 - - B1 - - G1 - - J1 Clock X0 Main clock (oscillation) input pin 86 70 P12 X0A Sub clock (oscillation) input pin 55 47 P5 X1 Main clock (oscillation) I/O pin 87 71 P13 X1A Sub clock (oscillation) I/O pin 56 48 P6 CROUT_0 Built-in high-speed CR-osc clock output port 127 103 D13 CROUT_1 152 122 E8 Analog Power AVCC A/D converter, D/A converter analog power pin 114 90 J14 AVRH A/D converter analog reference voltage input pin 117 93 F14 Analog GND AVSS A/D converter, D/A converter GND pin 115 91 H14 AVRL A/D converter analog reference voltage input pin 116 92 G14 C pin C Power supply stabilization capacity pin 52 44 P2 *: 5V tolerant I/O Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller.

Document Number: 002-05667 Rev. *D Page 53 of 136 MB9B120TA Series 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected.

• Oscillation feedback resistor : Approximately 1 MΩ
• With Standby mode control When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA B
• CMOS level hysteresis input
• Pull-up resistor : Approximately 50 kΩ P-ch P-ch N-ch R R P-ch P-ch N-ch Pull-up resistor Feedback resistor Pull-up resistor Pull-up resistor Digital input Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control

Document Number: 002-05667 Rev. *D Page 54 of 136 MB9B120TA Series Type Circuit Remarks C

• Open drain output
• CMOS level hysteresis input D It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected.
• Oscillation feedback resistor : Approximately 5 MΩ
• With Standby mode control When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA N-ch P-ch P-ch N-ch R R P-ch P-ch N-ch X0A X1A Pull-up resistor Feedback resistor Pull-up resistor Digital input Digital output Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control

Document Number: 002-05667 Rev. *D Page 55 of 136 MB9B120TA Series Type Circuit Remarks E

• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off
• +B input available F
• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -12 mA, IOL= 12 mA
• +B input available P-chP-ch N-ch R P-chP-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control

Document Number: 002-05667 Rev. *D Page 56 of 136 MB9B120TA Series Type Circuit Remarks G

• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off
• +B input available H P-chP-ch N-ch Analog output R Digital output Digital output Digital input Standby mode Control Pull-up resistor control
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog output
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA P-chP-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control

Document Number: 002-05667 Rev. *D Page 57 of 136 MB9B120TA Series Type Circuit Remarks I

• CMOS level output
• CMOS level hysteresis input
• 5 V tolerant
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• Available to control PZR registers.
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off J CMOS level hysteresis input K
• CMOS level output
• CMOS level hysteresis input
• With standby mode control
• IOH= -18.0 mA, IOL= 16.5 mA P-chP-ch N-ch R P-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Mode input Digital output Digital output Digital input Standby mode Control

Document Number: 002-05667 Rev. *D Page 58 of 136 MB9B120TA Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

6.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

Document Number: 002-05667 Rev. *D Page 59 of 136 MB9B120TA Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

6.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h

Document Number: 002-05667 Rev. *D Page 60 of 136 MB9B120TA Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

6.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives.

Document Number: 002-05667 Rev. *D Page 61 of 136 MB9B120TA Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.  Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: Approximately 6 pF to 7 pF  Lead type Load capacitance: Approximately 6 pF to 7 pF Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Example of Using an External Clock Device X0(X0A) X1(PE3), X1A (P47) Can be used as general-purpose I/O ports. Set as External clock input

Document Number: 002-05667 Rev. *D Page 62 of 136 MB9B120TA Series Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series. Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on : VCC → AVCC → AVRH Turning off : AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up function of 5V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5V tolerant I/O. Adjoining wiring on circuit board If wiring of the crystal oscillation circuit (X0/X1 and X0A/X1A) adjoins and also runs in parallel with the wiring of GPIO, there is a possibility that the oscillation erroneously counts because oscillation wave has noise with the change of GPIO. Keep as much distance as possible between both wirings and insert the ground pattern between them in order to avoid this possibility. Device C VSS CS GND

Document Number: 002-05667 Rev. *D Page 63 of 136 MB9B120TA Series 8. Block Diagram 9. Memory Size See “Memory size" in "Product Lineup" to confirm the memory size. Cortex-M3 Core @60 MHz(Max) Flash I/F Clock Reset Generator Dual-Timer WatchDog Timer (Hardware) DMAC 8ch. Watch Counter Unit 0 CSV External Interrupt Controller 32pin + NMI Power-On Reset SRAM0 80/96 Kbytes SRAM1 80/96 Kbytes I D Sys CLK NVIC WatchDog Timer (Software) Security Unit 1 TRSTX,TCK, TDI,TMS TRACEDx, TRACECLK AVCC, AVSS, AVRH ANxx TIOAx TIOBx C TDO X0A X1A SCKx SINx SOTx INTx NMIX P0x, P1x, PFx INITX MODE-Ctrl IRQ-Monitor MD0, MD1 Regulator CRC Accelerator ADTGx RTS4 CTS4 MADx MADATAx On-Chip Flash

1 Mbytes+64 Kbytes/

1.5 Mbytes+64 Kbytes

16ch. HW flow control(ch.4) External Bus I/F GPIO PIN-Function-Ctrl LVD TPIU ROM Table ETMSWJ-DP Main Osc PLL Sub Osc CR

4 MHz

CEC0_x, CEC1_x LVD CtrlBase Timer 16-bit 16ch./ 32-bit 8ch. HDMI-CEC/ Remote Reciver Control Real-Time Clock RTCCO, SUBOUT Deep Standby Ctrl WKUPx 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. A/D Activation Compare 2ch. 16-bit PPG 3ch. DTTI0X FRCK0 QPRC 2ch.BINx ZINx IC0x RTO0x AINx 12-bit A/D Converter Multi-function Timer × 1 MCSXx,MDQMx, MOEX,MWEX, MALE,MRDY, MNALE,MNCLE, MNWEX,MNREX, MCLKOUT IGTRGx Waveform Generator 3ch. CROUT Source Clock 10-bit D/Aconverter

2 UnitsDAx

AHB-APB Bridge: APB0(Max 32 MHz) Multi-layer AHB (Max 60 MHz) AHB-AHB Bridge AHB-APB Bridge : APB1 (Max 32 MHz) AHB-APB Bridge : APB2 (Max 32 MHz)

Document Number: 002-05667 Rev. *D Page 64 of 136 MB9B120TA Series 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF 0xE010_0000 0xE000_0000 0x4006_1000 0x4006_0000 DMAC 0x4004_0000 0x4003_F000 EXT-bus I/F 0x4003_C000 Reserved 0x7000_0000 0x4003_B000 RTC 0x4003_A000 Watch Counter 0x6000_0000 0x4003_9000 CRC 0x4003_8000 MFS 0x4400_0000 0x4003_6000 0x4003_5000 LVD/DS mode 0x4200_0000 0x4003_4000 HDMI-CEC/ Remote Control Receiver 0x4003_3000 GPIO 0x4000_0000 0x4003_2000 Reserved 0x4003_1000 Int-Req.Read 0x2400_0000 0x4003_0000 EXTI 0x4002_F000 Reserved 0x2200_0000 0x4002_E000 CR Trim 0x4002_9000 Reserved 0x2001_8000 0x4002_8000 D/AC 0x2000_0000 SRAM1 0x4002_7000 A/DC 0x1FFE_8000 SRAM0 0x4002_6000 QPRC 0x4002_5000 Base Timer 0x0051_8000 0x4002_4000 PPG 0x0050_8000 Flash(Work area) 0x0040_4000 Reserved 0x0040_0000 Security/CR Trim 0x4002_1000 0x4002_0000 MFT unit0 0x4001_6000 0x4001_5000 Dual Timer 0x0000_0000 0x4001_3000 0x4001_2000 SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 Flash I/F Reserved Cortex-M3 Private Peripherals Reserved Reserved Reserved Reserved Reserved External Device Area 32Mbytes Bit band alias See "lMemory map(2)" for the memory size details. Reserved Peripherals Reserved 32Mbytes Bit band alias Reserved Reserved Flash(Main area) Reserved Reserved Reserved

Document Number: 002-05667 Rev. *D Page 65 of 136 MB9B120TA Series Memory Map (2) The content of SRAM can be retained at the deep standby modes by the setting of Deep Standby RAM Retention Register (DSRAMR). See "MB9B520T/420T/320T/120T Series Flash Programming Manual" for sector structure of Flash. MB9BF129SA/TA MB9BF128SA/TA 0x2008_0000 0x2008_0000 0x2001_8000 0x2001_4000 0x2000_4000 0x2000_4000 0x2000_0000 SRAM1 16Kbytes* 0x2000_0000 SRAM1 16Kbytes* 0x1FFF_C000 SRAM0 16Kbytes* 0x1FFF_C000 SRAM0 16Kbytes* 0x1FFE_C000 0x1FFE_8000 0x0051_8000 0x0051_8000 0x0050_8000 0x0050_8000 0x0040_4000 0x0040_4000 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_0000 Security 0x0040_0000 Security 0x0018_0000 Reserved 0x0010_0000 0x0010_0000 ROM0_SA8(48KB) ROM0_SA8(48KB) 0x0000_0000 ROM0_SA2-3(8KBx2) 0x0000_0000 ROM0_SA2-3(8KBx2) Reserved ROM1_SA8-15(8KBx8) Flash (Main area, ROM1) 512Kbytes ROM0_SA9-23(64KBx15) Flash (Main area, ROM0) 1Mbytes Reserved Reserved Reserved ROM1_SA0-7(8KBx8) SRAM1 80Kbytes SRAM0 80Kbytes Reserved Reserved SRAM1 64Kbytes SRAM0 64Kbytes Reserved Flash (Work area, ROM1) 64Kbytes ROM0_SA9-23(64KBx15) Flash (Main area, ROM0) 1Mbytes Flash (Work area, ROM1) 64Kbytes ROM1_SA0-7(8KBx8) ROM1_SA8_15(64KBx8)

Document Number: 002-05667 Rev. *D Page 66 of 136 MB9B120TA Series Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB Flash Memory I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF APB1 Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter (QPRC) 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_8FFF D/A Converter 0x4002_9000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Resister 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF HDMI-CEC/Remote control Reception 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF External bus interface 0x4004_0000 0x4005_FFFF AHB Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x41FF_FFFF Reserved

Document Number: 002-05667 Rev. *D Page 67 of 136 MB9B120TA Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the "L" level.  INITX=1 This is the period when the INITX pin is the "H" level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".  Input enabled Indicates that the input function can be used.  Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L".  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port.

Document Number: 002-05667 Rev. *D Page 68 of 136 MB9B120TA Series List of Pin Status Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Main crystal oscillator output pin Hi-Z / Internal input fixed at "0"/ or Input enable Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state/Wh en oscillatio n stops*1, Hi-Z / Internal input fixed at "0" Maintain previous state/Wh en oscillatio n stops*1, Hi-Z / Internal input fixed at "0" Maintain previous state/Wh en oscillatio n stops*1, Hi-Z / Internal input fixed at "0" Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at "0" Maintain previous state/Wh en oscillatio n stops*1, Hi-Z / Internal input fixed at "0" Maintain previous state/When oscillation stops*1, Hi-Z / Internal input fixed at "0" C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled

Document Number: 002-05667 Rev. *D Page 69 of 136 MB9B120TA Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - E Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled GPIO selected F GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled G GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Hi-Z/ Internal input fixed at "0" Maintain previous state Sub crystal oscillator output pin Hi-Z / Internal input fixed at "0"/ or Input enable Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state Maintain previous state/Wh en oscillatio n stops*2, Hi-Z / Internal input fixed at "0" Maintain previous state/Wh en oscillatio n stops*2, Hi-Z / Internal input fixed at "0" Maintain previous state/When oscillation stops*2, Hi-Z/ Internal input fixed at "0" Maintain previous state/Wh en oscillatio n stops*2, Hi-Z/ Internal input fixed at "0" Maintain previous state/When oscillation stops*2, Hi-Z/ Internal input fixed at "0"

Document Number: 002-05667 Rev. *D Page 70 of 136 MB9B120TA Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - H NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at "0" I JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected J Resource selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected GPIO selected K External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at "0" GPIO selected L Analog input selected Hi-Z Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected GPIO selected

Document Number: 002-05667 Rev. *D Page 71 of 136 MB9B120TA Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - M Analog input selected Hi-Z Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected Resource other than above selected Hi-Z / Internal input fixed at "0" GPIO selected N Analog input selected Hi-Z Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Resource other than above selected Hi-Z / Internal input fixed at "0" GPIO selected

Document Number: 002-05667 Rev. *D Page 72 of 136 MB9B120TA Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - O Analog output selected Setting disabled Setting disabled Setting disabled Maintain previous state *3 *4 GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected P Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at "0" GPIO selected Q Trace selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Trace output GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected External interrupt enabled selected Maintain previous state Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at "0" GPIO selected R CEC enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected GPIO selected

Document Number: 002-05667 Rev. *D Page 73 of 136 MB9B120TA Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - S CEC enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state External interrupt enabled selected GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at "0" GPIO selected T CEC enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state WKUP enabled WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at "0" GPIO selected U WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at "0" GPIO selected

Document Number: 002-05667 Rev. *D Page 74 of 136 MB9B120TA Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - V GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected *1: Oscillation is stopped at Sub timer mode, Low-speed CR timer mode, RTC mode, STOP mode, Deep standby RTC mode, and Deep standby STOP mode. *2: Oscillation is stopped at STOP mode and Deep standby STOP mode. *3: Maintain previous state at timer mode. GPIO selected Internal input fixed at "0" at RTC mode, STOP mode. *4: Maintain previous state at timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, STOP mode.

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12.1 Absolute Maximum Ratings

Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*1, *2 VCC VSS - 0.5 VSS + 6.5 V Analog power supply voltage*1, *3 AVCC VSS - 0.5 VSS + 6.5 V Analog reference voltage*1, *3 AVRH VSS - 0.5 VSS + 6.5 V Input voltage*1 VI VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V VSS - 0.5 VSS + 6.5 V 5V tolerant VSS - 0.5 VSS + 3.63 V 5V tolerant*8 Analog pin input voltage*1 VIA VSS - 0.5 AVCC + 0.5 (≤ 6.5 V) V Output voltage*1 VO VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V Clamp maximum current ICLAMP -2 +2 mA *8 Clamp total maximum current Σ[ICLAMP] +20 mA *8 "L" level maximum output current*4 IOL - 10 mA 4mA type 20 mA 12mA type 39 mA P80/P81 "L" level average output current*5 IOLAV - 4 mA 4mA type 12 mA 12mA type 16.5 mA P80/P81 "L" level total maximum output current ∑IOL - 100 mA "L" level total average output current*6 ∑IOLAV - 50 mA "H" level maximum output current*4 IOH - - 10 mA 4mA type - 20 mA 12mA type - 39 mA P80/P81 "H" level average output current*5 IOHAV - - 4 mA 4mA type - 12 mA 12mA type - 18 mA P80/P81 "H" level total maximum output current ∑IOH - - 100 mA "H" level total average output current*6 ∑IOHAV - - 50 mA Power consumption PD - 390 mW Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that VSS = AVSS = 0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. *7: VCC = AVCC = AVRH = VSS = AVSS = AVRL = 0.0 V

Document Number: 002-05667 Rev. *D Page 76 of 136 MB9B120TA Series *8:

• See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.
• Use within recommended operating conditions.
• Use at DC voltage (current) the +B input.
• The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit). WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. R Protection Diode P-ch VCC VCC Limiting resistor N-ch AVCC Analog input Digital input Digital output +B input (0V to 16V)

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12.2 Recommended Operating Conditions

(VSS = AVSS = 0.0V) Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage VCC - 2.7*2 5.5 V Analog power supply voltage AVCC - 2.7 5.5 V AVCC = VCC Analog reference voltage AVRH - 2.7 AVCC V AVRL - AVSS AVSS V Smoothing capacitor CS - 1 10 μF For built-in Regulator*1 Operating temperature TA - - 40 + 105 °C *1: See "C Pin" in "Handling Devices" for the connection of the smoothing capacitor. *2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR(including Main PLL is used) or built-in Low-speed CR is possible to operate only. WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

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12.3 DC Characteristics

12.3.1 Current Rating

(Pin name) Conditions Value Unit Remarks Typ*1 Max*2 Power supply current ICC PLL RUN mode CPU: 60 MHz, Peripheral: 30 MHz *3,*5 29 37 mA CPU: 60 MHz, Peripheral clock stops *3,*5 19 26 mA High-speed CR RUN mode CPU/ Peripheral: 4 MHz *4,*3 3.1 6.4 mA Sub RUN mode CPU/ Peripheral: 32 kHz *3,*6 170 2300 µA Low-speed CR RUN mode CPU/ Peripheral: 100 kHz *3 210 2300 µA ICCS PLL SLEEP mode Peripheral: 30 MHz *3,*5 19 26 mA High-speed CR SLEEP mode Peripheral: 4 MHz*4 *3 2.1 5.1 mA Sub SLEEP mode Peripheral: 32 kHz *3,*6 160 2200 µA Low-speed CR SLEEP mode Peripheral: 100 kHz *3 190 2200 µA ICCH STOP mode TA = + 25°C *3 20 75 μA TA = + 105°C *3 - 1.3 mA ICCT Main TIMER mode TA = + 25°C *3,*6 2.8 5.5 mA TA = + 105°C *3,*6 - 6.5 mA Sub TIMER mode TA = + 25°C *3,*6 24 95 μA TA = + 105°C *3,*6 - 1.7 mA ICCR RTC mode TA = + 25°C *3,*6 21 89 μA TA = + 105°C *3,*6 - 1.7 mA *1: TA=+25℃,VCC= 3.3 V *2: TA=+105℃,VCC=5.5 V *3: When all ports are fixed. *4: When setting it to 4 MHz by trimming. *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

Document Number: 002-05667 Rev. *D Page 79 of 136 MB9B120TA Series Parameter Symbol (Pin name) Conditions Value Unit Remarks Typ*1 Max*2 Power supply current ICCHD Deep Standby STOP mode TA = + 25°C, When RAM is off 1.9 13 μA TA = + 25°C, When RAM is on(16 KB) *4,*3 4.8 17 μA TA = + 25°C, When RAM is on(32 KB) *4,*3 5.5 20 μA TA = + 105°C, When RAM is off 300 μA TA = + 105°C, When RAM is on(16 KB) *4,*3 320 μA TA = + 105°C, When RAM is on(32 KB) *4,*3 330 μA ICCRD Deep Standby RTC mode TA = + 25°C, When RAM is off *3,*5 2.5 14 μA TA = + 25°C, When RAM is on(16 KB) *4,*3,*5 5.4 18 μA TA = + 25°C, When RAM is on(32 KB) *4,*3,*5 6.1 21 μA TA = + 105°C, When RAM is off *3,*5 305 μA TA = + 105°C, When RAM is on(16 KB) *4,*3,*5 325 μA TA = + 105°C, When RAM is on(32 KB) *4,*3,*5 335 μA *1: VCC=3.3 V *2: VCC=5.5 V *3: When all ports are fixed and LVD off. *4: For more information about RAM retention area, see "Memory Map (2)" in "Memory Map". *5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

Document Number: 002-05667 Rev. *D Page 80 of 136 MB9B120TA Series Low-Voltage Detection Current (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol (Pin name) Conditions Value Unit Remarks Min Typ Max Low-Voltage detection circuit (LVD) power supply current ICCLVD (VCC) At operation - 0.13 0.3 μA For occurrence of reset - 0.13 0.3 μA For occurrence of interrupt Flash Memory Current (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Flash memory write/erase current ICCFLASH (VCC) VCC At ROM0 Write/Erase - 9.9 11.8 mA *1 At ROM1 Write/Erase - 9.5 11.2 mA *1 *1: When programming or erase in flash memory, Flash Memory Write/Erase current (ICCFLASH) is added to the Power supply current (ICC). In addition, When programming or erase in flash memory ROM0 and ROM1 at the same time, Flash Memory Write/Erase current (ICCFLASH) of both ROM0 and ROM1 are added to the Power supply current (ICC). A/D Converter Current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Power supply current ICCAD (VCC) AVCC At 1unit operation - 0.69 0.9 mA At stop - 0.6 35 μA Reference power supply current (AVRH) ICCAVRH (VCC) AVRH At 1unit operation AVRH=5.5 V - 1.1 1.97 mA At stop - 0.2 3.4 μA

Document Number: 002-05667 Rev. *D Page 81 of 136 MB9B120TA Series D/A Converter Current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Power supply current*1 IDDA*2 (VCC) AVCC At 1unit operation AVCC=3.3 V 250 315 380 μA At 1unit operation AVCC=5.0 V 380 475 580 μA IDSA (VCC) At stop - - 30 μA *1: No-load *2: Generates the max current by the CODE about 0x200

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12.3.2 Pin Characteristics

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max "H" level input voltage (hysteresis input) VIHS CMOS hysteresis input pin, MD0, MD1 - VCC × 0.8 - VCC + 0.3 V 5V tolerant input pin - VCC × 0.8 - VSS + 5.5 V "L" level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0, MD1 - VSS - 0.3 - VCC × 0.2 V 5V tolerant input pin - VSS - 0.3 - VCC × 0.2 V "H" level output voltage VOH 4mA type VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 2 mA 12mA type VCC ≥ 4.5 V, IOH = - 12 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 8 mA P80/P81 VCC ≥ 4.5 V, IOH = - 18.0 mA VCC - 0.4 - VCC V VCC < 4.5 V, IOH = - 12.0 mA "L" level output voltage VOL 4mA type VCC ≥ 4.5 V, IOL = 4 mA VSS - 0.4 V VCC < 4.5 V, IOL = 2 mA 12mA type VCC ≥ 4.5 V, IOL = 12 mA VSS - 0.4 V VCC < 4.5 V, IOL = 8 mA P80/P81 VCC ≥ 4.5 V, IOL = 16.5 mA VSS - 0.4 V VCC < 4.5 V, IOL = 10.5 mA Input leak current IIL - - - 5 - + 5 μA CEC0_0, CEC0_1, CEC1_0, CEC1_1 VCC = AVCC = AVRH = VSS = AVSS = AVRL = 0.0 V - - +1.8 μA Pull-up resistance value RPU Pull-up pin VCC ≥ 4.5 V 33 50 90 kΩ VCC < 4.5 V - - 180

Document Number: 002-05667 Rev. *D Page 83 of 136 MB9B120TA Series Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Input capacitance CIN Other than VCC, VSS, AVCC, AVSS, AVRH, AVRL - - 5 15 pF

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12.4 AC Characteristics

12.4.1 Main Clock Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input frequency FCH X0, VCC ≥ 4.5 V 4 48 MHz When crystal oscillator is connected VCC < 4.5 V 4 20 - 4 48 MHz When using external clock Input clock cycle tCYLH - 20.83 250 ns When using external clock Input clock pulse width - PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock Input clock rising time and falling time tCF, tCR - - 5 ns When using external clock Internal operating clock*1 frequency FCM - - - 60 MHz Master clock FCC - - - 60 MHz Base clock (HCLK/FCLK) FCP0 - - - 32 MHz APB0 bus clock*2 FCP1 - - - 32 MHz APB1 bus clock*2 FCP2 - - - 32 MHz APB2 bus clock*2 Internal operating clock*1 cycle time tCYCC - - 16.7 - ns Base clock (HCLK/FCLK) tCYCP0 - - 31.25 - ns APB0 bus clock*2 tCYCP1 - - 31.25 - ns APB1 bus clock*2 tCYCP2 - - 31.25 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". *2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this data sheet.

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12.4.2 Sub Clock Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Input frequency 1/ tCYLL X0A, X1A - - 32.768 - kHz When crystal oscillator is connected* - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock *: For more information about crystal oscillator, see "Sub crystal oscillator" in "Handling Devices". X0A

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12.4.3 Built-in CR Oscillation Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency FCRH TA = + 25°C, 3.6 V < VCC ≤ 5.5 V 3.92 4 4.08 MHz When trimming*1 TA = 0°C to + 85°C, 3.6 V < VCC ≤ 5.5 V 3.9 4 4.1 TA = -40°C to + 105°C, 3.6 V < VCC ≤ 5.5 V 3.88 4 4.12 TA = + 25°C, 2.7 V ≤ VCC ≤ 3.6 V 3.94 4 4.06 TA = - 20°C to + 85°C, 2.7 V ≤ VCC ≤ 3.6 V 3.92 4 4.08 TA = - 20°C to + 105°C, 2.7 V ≤ VCC ≤ 3.6 V 3.9 4 4.1 TA = -40°C to + 105°C, 2.7 V ≤ VCC ≤ 3.6 V 3.88 4 4.12 TA = - 40°C to + 105°C 2.8 4 5.2 When not trimming Frequency stability time tCRWT - - - 30 μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: Frequency stable time is time to stable of the frequency of the High-speed CR clock after the trim value is set. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency FCRL - 50 100 150 kHz

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12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency FPLLI 4 - 16 MHz PLL multiplication rate - 5 - 37 multiplier PLL macro oscillation clock frequency FPLLO 75 - 150 MHz Main PLL clock frequency*2 FCLKPLL - - 60 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". 12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of main PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency FPLLI 3.8 4 4.2 MHz PLL multiplication rate - 19 - 35 multiplier PLL macro oscillation clock frequency FPLLO 72 - 150 MHz Main PLL clock frequency*2 FCLKPLL - - 60 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "CHAPTER 2-1: Clock" in "FM3 Family PERIPHERAL MANUAL". Note: − Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency/temperature has been trimmed. K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Main PLL connection High-speed CR clock (CLKHC) Main clock (CLKMO)

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12.4.6 Reset Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns

12.4.7 Power-on Reset Timing

(VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Power supply shut down time tOFF VCC - 1 - ms *1 Power ramp rate dV/dt VCC: 0.2 V to 2.70 V 0.9 1000 mV/ /µs *2 Time until releasing power-on reset tPRT - 0.46 0.76 ms *1: Vcc must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF > 1ms). Note: − If tOFF cannot be satisfied designs must assert external reset (INTX) at power-up and at any brownout event per 12.4.6. Glossary VDH : detection voltage of Low Voltage detection reset. See “12.7. Low-Voltage Detection Characteristics” VDH tPRT Internal RST VCC CPU Operation start RST Active release 0.2V 0.2V tOFF dV/dt0.2V 2.7V

Document Number: 002-05667 Rev. *D Page 89 of 136 MB9B120TA Series

12.4.8 External Bus Timing

External bus clock output characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max Output frequency tCYCLE MCLKOUT* VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz *: The external bus clock (MCLKOUT) is a divided clock of HCLK. For more information about setting of clock divider, see "CHAPTER 12: External Bus Interface" in "FM3 Family PERIPHERAL MANUAL". When external bus clock is not output, this characteristics does not give any effect on external bus operation. External bus signal input/output characteristics (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Signal input characteristics VIH 0.8 × VCC V VIL 0.2 × VCC V Signal output characteristics VOH 0.8 × VCC V VOL 0.2 × VCC V VIH VIL VIL VIH VOH VOL VOL VOH Input signal Output signal MCLKOUT

Document Number: 002-05667 Rev. *D Page 90 of 136 MB9B120TA Series Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max MOEX Min pulse width tOEW MOEX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V MCSX ↓ → Address output delay time tCSL – AV MCSX[7:0], MAD[24:0] VCC ≥ 4.5 V -9 +9 ns VCC < 4.5 V -12 +12 MOEX ↑ → Address hold time tOEH - AX MOEX, MAD[24:0] VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX ↓ → MOEX ↓ delay time tCSL - OEL MOEX, MCSX[7:0] VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MOEX ↑ → MCSX ↑ time tOEH - CSH VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX ↓ → MDQM ↓ delay time tCSL - RDQML MCSX, MDQM[1:0] VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 Data set up → MOEX ↑ time tDS - OE MOEX, MADATA[15:0] VCC ≥ 4.5 V 20 - ns VCC < 4.5 V 38 - MOEX ↑ → Data hold time tDH - OE MOEX, MADATA[15:0] VCC ≥ 4.5 V 0 - ns VCC < 4.5 V MWEX Min pulse width tWEW MWEX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V MWEX ↑ → Address output delay time tWEH - AX MWEX, MAD[24:0] VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX ↓ → MWEX ↓ delay time tCSL - WEL MWEX, MCSX[7:0] VCC ≥ 4.5 V MCLK×n-9 MCLK×n+9 ns VCC < 4.5 V MCLK×n-12 MCLK×n+12 MWEX ↑ → MCSX ↑ delay time tWEH - CSH VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX ↓→ MDQM ↓ delay time tCSL-WDQML MCSX, MDQM[1:0] VCC ≥ 4.5 V MCLK×n-9 MCLK×n+9 ns VCC < 4.5 V MCLK×n-12 MCLK×n+12 MCSX ↓→ Data output time tCSL-DV MCSX, MADATA[15:0] VCC ≥ 4.5 V MCLK-9 MCLK+9 ns VCC < 4.5 V MCLK-12 MCLK+12 MWEX ↑ → Data hold time tWEH - DX MWEX, MADATA[15:0] VCC ≥ 4.5 V 0 MCLK×m+12 ns VCC < 4.5 V Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).

Document Number: 002-05667 Rev. *D Page 91 of 136 MB9B120TA Series Invalid Address tCSL-OEL tCSL-AV RD Address WD tDH-OEtDS-OE tWEH-DX tOEW tOEH-AX tOEH-CSH tWEW tCYCLE tCSL-WEL tCSL-AV tWEH-CSH tWEH-AX tCSL-WDQMLtCSL-RDQML tCSL-DV MCLK MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

Document Number: 002-05667 Rev. *D Page 92 of 136 MB9B120TA Series Separate Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max Address delay time tAV MCLK, MAD[24:0] VCC ≥ 4.5 V 1 12 ns VCC < 4.5 V MCSX delay time tCSL MCLK, MCSX[7:0] VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 tCSH VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 MOEX delay time tREL MCLK, MOEX VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 tREH VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 Data set up → MCLK ↑ time tDS MCLK, MADATA[15:0] VCC ≥ 4.5 V 19 - ns VCC < 4.5 V 37 MCLK ↑ → Data hold time tDH MCLK, MADATA[15:0] VCC ≥ 4.5 V 0 - ns VCC < 4.5 V MWEX delay time tWEL MCLK, MWEX VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 tWEH VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 MDQM[1:0] delay time tDQML MCLK, MDQM[1:0] VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 tDQMH VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 MCLK ↑ → Data output time tODS MCLK, MADATA[15:0] VCC ≥ 4.5 V MCLK+1 MCLK+18 ns VCC < 4.5 V MCLK+24 MCLK ↑ → Data hold time tOD MCLK, MADATA[15:0] VCC ≥ 4.5 V 1 18 ns VCC < 4.5 V 24 Note: − When the external load capacitance CL = 30 pF.

Document Number: 002-05667 Rev. *D Page 93 of 136 MB9B120TA Series Invalid tDQML tREH Address tCSL tAV tREL RD Address WD tDQMH tWEHtWEL tDHtDS tOD tAV tCSH tCYCLE tDQML tDQMH tODS MCLK MCSX[7:0] MAD[24:0] MDQM[1:0] MWEX MADATA[15:0] MOEX

Document Number: 002-05667 Rev. *D Page 94 of 136 MB9B120TA Series Multiplexed Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max Multiplexed address delay time tALE-CHMADV MALE, MADATA[15:0] VCC ≥ 4.5 V 0 +10 ns VCC < 4.5 V +20 Multiplexed address hold time tCHMADH VCC ≥ 4.5 V MCLK×n+0 MCLK×n+12 ns VCC < 4.5 V MCLK×n+0 MCLK×n+20 Note: − When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16). MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

Document Number: 002-05667 Rev. *D Page 95 of 136 MB9B120TA Series Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MALE delay time tCHAL MCLK, ALE VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 ns tCHAH VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 ns MCLK ↑ → Multiplexed Address delay time tCHMADV MCLK, MADATA[15:0] VCC ≥ 4.5 V 1 tOD ns VCC < 4.5 V MCLK ↑ → Multiplexed Data output time tCHMADX VCC ≥ 4.5 V 1 tOD ns VCC < 4.5 V Note: − When the external load capacitance CL = 30 pF. MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0]

Document Number: 002-05667 Rev. *D Page 96 of 136 MB9B120TA Series NAND Flash Memory Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Min Max MNREX Min pulse width tNREW MNREX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V Data setup → MNREX↑time tDS – NRE MNREX, MADATA[15:0] VCC ≥ 4.5 V 20 - ns VCC < 4.5 V 38 - MNREX↑→ Data hold time tDH – NRE MNREX, MADATA[15:0] VCC ≥ 4.5 V 0 - ns VCC < 4.5 V MNALE↑→ MNWEX delay time tALEH - NWEL MNALE, MNWEX VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MNALE↓→ MNWEX delay time tALEL - NWEL MNALE, MNWEX VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MNCLE↑→ MNWEX delay time tCLEH - NWEL MNCLE, MNWEX VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MNWEX↑→ MNCLE delay time tNWEH - CLEL MNCLE, MNWEX VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MNWEX Min pulse width tNWEW MNWEX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V MNWEX↓→ Data output time tNWEL – DV MNWEX, MADATA[15:0] VCC ≥ 4.5 V - 9 + 9 ns VCC < 4.5 V -12 +12 MNWEX↑→ Data hold time tNWEH – DX MNWEX, MADATA[15:0] VCC ≥ 4.5 V 0 MCLK×m+11 ns VCC < 4.5 V MCLK×m+12 Note: − When the external load capacitance CL = 30 pF (m=0 to 15, n=1 to 16).

Document Number: 002-05667 Rev. *D Page 97 of 136 MB9B120TA Series NAND Flash Memory Read NAND Flash Memory Address Write MCLK MNREX MADATA[15:0] Read MCLK MNALE MNCLE MADATA[15:0] MNWEX Write

Document Number: 002-05667 Rev. *D Page 98 of 136 MB9B120TA Series NAND Flash Memory Command Write MCLK MNALE MNCLE MADATA[15:0] MNWEX Write

Document Number: 002-05667 Rev. *D Page 99 of 136 MB9B120TA Series External Ready Input Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MCLK ↑ MRDY input setup time tRDYI MCLK, MRDY VCC ≥ 4.5 V 19 - ns VCC < 4.5 V 37 When RDY is input When RDY is released

• · · Over 2cycles tRDYI 2 cycles t RDYI 0.5×VCC MCLK Original MOEX MWEX MRDY MCLK Extended MOEX MWEX MRDY

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12.4.9 Base Timer Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - 2tCYCP - ns Trigger input timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see "Block Diagram" in this data sheet. tTIWH VIHS VIHS VILS VILS tTIWL tTRGH VIHS VIHS VILS VILS tTRGL ECK TIN TGIN

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12.4.10 CSIO/UART Timing

CSIO (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud Rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 33 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. − About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05667 Rev. *D Page 102 of 136 MB9B120TA Series Master mode Slave mode tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI tSLSH tSHSL VIH tF tR VIH VOH VIH VIL VIL VOL VIH VIL VIH VIL tSLOVE tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-05667 Rev. *D Page 103 of 136 MB9B120TA Series CSIO (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud Rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 33 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. − About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05667 Rev. *D Page 104 of 136 MB9B120TA Series Master mode Slave mode tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI tSHSL tSLSH VIH tFtR VIH VOH VILVIL VIL VOL VIH VIL VIH VIL tSHOVE tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-05667 Rev. *D Page 105 of 136 MB9B120TA Series CSIO (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud Rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK ↓→ SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 33 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓→ SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. − About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05667 Rev. *D Page 106 of 136 MB9B120TA Series Master mode Slave mode *: Changes when writing to TDR register tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-05667 Rev. *D Page 107 of 136 MB9B120TA Series CSIO (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud Rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock "L" pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 33 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. − About the APB bus number which Multi-function Serial is connected to, see "Block Diagram" in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05667 Rev. *D Page 108 of 136 MB9B120TA Series Master mode Slave mode UART external clock input (EXT = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Max Serial clock "L" pulse width tSLSH CL = 30 pF tCYCP + 10 - ns Serial clock "H" pulse width tSHSL tCYCP + 10 - ns SCK falling time tF - 5 ns SCK rising time tR - 5 ns tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI t SHSL tR t SLSH t SLOVE V IL V IL V IL V IH V IH V IH V OH V OL V OH V OL V IH V IL V IH V IL t IVSHE t SHIXE tF t SHSL V I L V I L V I L V IH V IH V IH tR tF t SLSH SCK SOT SIN SCK SOT SIN SCK

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12.4.11 External Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tINH, tINL ADTG - 2tCYCP*1 - ns A/D converter trigger input FRCKx Free-run timer input clock ICxx Input capture DTTIxX - 2tCYCP*1 - ns Waveform generator INTxx *2 2tCYCP + 100*1 - ns External interrupt, NMI *3 500 - ns WKUPx *4 500 - ns Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see "Block Diagram" in this data sheet. *2: When in RUN mode, in SLEEP mode. *3: When in STOP mode, in TIMER mode. *4: When in Deep standby RTC mode, in Deep standby STOP mode.

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12.4.12 Quadrature Position/Revolution Counter timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Min Max AIN pin "H" width tAHL - 2tCYCP* - ns AIN pin "L" width tALL - BIN pin "H" width tBHL - BIN pin "L" width tBLL - Time from AIN pin "H" level to BIN rise tAUBU PC_Mode2 or PC_Mode3 Time from BIN pin "H" level to AIN fall tBUAD PC_Mode2 or PC_Mode3 Time from AIN pin "L" level to BIN fall tADBD PC_Mode2 or PC_Mode3 Time from BIN pin "L" level to AIN rise tBDAU PC_Mode2 or PC_Mode3 Time from BIN pin "H" level to AIN rise tBUAU PC_Mode2 or PC_Mode3 Time from AIN pin "H" level to BIN fall tAUBD PC_Mode2 or PC_Mode3 Time from BIN pin "L" level to AIN fall tBDAD PC_Mode2 or PC_Mode3 Time from AIN pin "L" level to BIN rise tADBU PC_Mode2 or PC_Mode3 ZIN pin "H" width tZHL QCR:CGSC="0" ZIN pin "L" width tZLL QCR:CGSC="0" Time from determined ZIN level to AIN/BIN rise and fall tZABE QCR:CGSC="1" Time from AIN/BIN rise and fall time to determined ZIN level tABEZ QCR:CGSC="1" *: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see "Block Diagram" in this data sheet. AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL

Document Number: 002-05667 Rev. *D Page 111 of 136 MB9B120TA Series BIN tBUAU tAUBD tBDAD tADBU tBHL tBLL tAHL tALL AIN ZIN ZIN AIN/BIN

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12.4.13 I2C Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency FSCL CL = 30 pF, R = (Vp/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCLclock "L" width tLOW 4.7 - 1.3 - μs SCLclock "H" width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between "STOP condition" and "START condition" tBUF 4.7 - 1.3 - μs Noise filter tSP - 2 tCYCP*4 - 2 tCYCP*4 - ns *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal. *3: Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see "Block Diagram" in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL

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12.4.14 ETM Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Data hold tETMH TRACECLK, TRACED[3:0] VCC ≥ 4.5 V 2 10 ns VCC < 4.5 V 2 15 TRACECLK frequency 1/ tTRACE TRACECLK VCC ≥ 4.5 V - 40 MHz VCC < 4.5 V - 20 MHz TRACECLK clock cycle tTRACE VCC ≥ 4.5 V 25 - ns VCC < 4.5 V 50 - ns Note: − When the external load capacitance CL = 30 pF. HCLK TRACECLK TRACED[3:0]

Document Number: 002-05667 Rev. *D Page 114 of 136 MB9B120TA Series

12.4.15 JTAG Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max TMS, TDI setup time tJTAGS TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TMS, TDI hold time tJTAGH TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TDO delay time tJTAGD TCK, TDO VCC ≥ 4.5 V - 25 ns VCC < 4.5 V - 45 Note: − When the external load capacitance CL = 30 pF. TCK TMS/TDI TDO

Document Number: 002-05667 Rev. *D Page 115 of 136 MB9B120TA Series 12.5 12-bit A/D Converter Electrical characteristics for the A/D converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - - ± 1.5 ± 4.5 LSB AVRH = 2.7 V to 5.5 V Differential Nonlinearity - - - ± 2.2 ± 2.5 LSB Zero transition voltage VZT ANxx - ± 6 ± 15 mV Full-scale transition voltage VFST ANxx - AVRH ±

5 AVRH ± 15 mV

Conversion time - - 1.0*1 - - μs Sampling time*2 Ts - 0.3 - 10 μs Compare clock cycle*3 Tcck - 50 - 1000 ns State transition time to operation permission Tstt - - - 1.0 μs Analog input capacity CAIN - - - 9.5 pF Analog input resistor RAIN - - - 1.62 kΩ AVCC ≥ 4.5 V 2.35 AVCC < 4.5 V Interchannel disparity - - - - 4 LSB Analog port input leak current - ANxx - - 5 μA Analog input voltage - ANxx AVRL - AVRH V Reference voltage - AVRH 2.7 - AVCC V - AVRL AVSS - AVSS V *1: The conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is when the value of sampling time: 300 ns, the value of compare time: 700 ns (AVCC ≥ 4.5 V). Ensure that it satisfies the value of the sampling time (Ts) and compare clock cycle (Tcck). For setting of the sampling time and compare clock cycle, see "CHAPTER 1-1: A/D Converter" in "FM3 Family PERIPHERAL MANUAL Analog Macro Part". The register setting of the A/D Converter are reflected in the operation according to the APB bus clock timing. The sampling clock and compare clock is generated from the Base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see "Block Diagram" in this data sheet. *2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1). *3: The compare time (Tc) is the value of (Equation 2).

Document Number: 002-05667 Rev. *D Page 116 of 136 MB9B120TA Series (Equation 1) Ts ≥ ( RAIN + Rext ) × CAIN × 9 Ts: Sampling time CAIN: Input capacity of A/D = 9.5 pF at 2.7 V < AVCC < 5.5 V Rext: Output impedance of external circuit (Equation 2) Tc = Tcck × 14 Tc: Compare time Tcck: Compare clock cycle Rext CAIN Analog signal source ANxx Analog input pin Comparator RAIN

Document Number: 002-05667 Rev. *D Page 117 of 136 MB9B120TA Series Definition of 12-bit A/D Converter Terms

• Resolution: Analog variation that is recognized by an A/D converter.
• Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
• Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST – VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVRL AVRH AVRL AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T

Document Number: 002-05667 Rev. *D Page 118 of 136 MB9B120TA Series 12.6 10-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - DAx - - 10 bit Conversion time tc20 0.47 0.58 0.69 μs Load 20 pF tc100 2.37 2.90 3.43 μs Load 100 pF Integral Nonlinearity*1 INL - 4.0 - + 4.0 LSB Differential Nonlinearity*1,*2 DNL - 0.9 - + 0.9 LSB Output Voltage offset VOFF - - 10.0 mV Code is 0x000 - 20.0 - + 5.4 mV Code is 0x3FF Analog output impedance RO 3.10 3.80 4.50 kΩ D/A operation 2.0 - - MΩ D/A stop Output undefined period tR - - 70 ns *1: No-load *2: Generates the max current by the CODE about 0x200

Document Number: 002-05667 Rev. *D Page 119 of 136 MB9B120TA Series

12.7 Low-Voltage Detection Characteristics

12.7.1 Low-Voltage Detection Reset

(TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHR*1 = 00000 2.25 2.45 2.65 V When voltage drops Released voltage VDH 2.30 2.50 2.70 V When voltage rises Detected voltage VDL SVHR*1 = 00001 2.39 2.60 2.81 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00010 2.48 2.70 2.92 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00011 2.58 2.80 3.02 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00100 2.76 3.00 3.24 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00101 2.94 3.20 3.46 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00110 3.31 3.60 3.89 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00111 3.40 3.70 4.00 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 01000 3.68 4.00 4.32 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 01001 3.77 4.10 4.43 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 01010 3.86 4.20 4.54 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises LVD stabilization wait time TLVDW - - - 6432 × tCYCP*2 μs LVD detection delay time TLVDDL - - - 200 μs *1: The SVHR bit of Low-voltage Detection Voltage Control Register (LVD_CTL) is initialized to “0000” by low-voltage detection reset. *2: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-05667 Rev. *D Page 120 of 136 MB9B120TA Series

12.7.2 Interrupt of Low-Voltage Detection

(TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHI = 00011 2.58 2.80 3.02 V When voltage drops Released voltage VDH 2.67 2.90 3.13 V When voltage rises Detected voltage VDL SVHI = 00100 2.76 3.00 3.24 V When voltage drops Released voltage VDH 2.85 3.10 3.35 V When voltage rises Detected voltage VDL SVHI = 00101 2.94 3.20 3.46 V When voltage drops Released voltage VDH 3.04 3.30 3.56 V When voltage rises Detected voltage VDL SVHI = 00110 3.31 3.60 3.89 V When voltage drops Released voltage VDH 3.40 3.70 4.00 V When voltage rises Detected voltage VDL SVHI = 00111 3.40 3.70 4.00 V When voltage drops Released voltage VDH 3.50 3.80 4.10 V When voltage rises Detected voltage VDL SVHI = 01000 3.68 4.00 4.32 V When voltage drops Released voltage VDH 3.77 4.10 4.43 V When voltage rises Detected voltage VDL SVHI = 01001 3.77 4.10 4.43 V When voltage drops Released voltage VDH 3.86 4.20 4.54 V When voltage rises Detected voltage VDL SVHI = 01010 3.86 4.20 4.54 V When voltage drops Released voltage VDH 3.96 4.30 4.64 V When voltage rises LVD stabilization wait time TLVDW - - - 6432 × tCYCP* μs LVD detection delay time TLVDDL - - - 200 μs *: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-05667 Rev. *D Page 121 of 136 MB9B120TA Series

12.8 Flash Memory Write/Erase Characteristics

12.8.1 Write / Erase time

(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Value Unit Remarks Typ Max Sector erase time Large Sector 1.1 2.7 s Includes write time prior to internal erase Small Sector 0.3 0.9 Half word (16-bit) write time 20 317 μs Not including system-level overhead time Chip erase time 31 79 s Includes write time prior to internal erase *: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.

12.8.2 Write cycles and data hold time

Erase/write cycles (cycle) Data hold time (year) Remarks 1,000 20* 10,000 10* *: At average + 85C

Document Number: 002-05667 Rev. *D Page 122 of 136 MB9B120TA Series

12.9 Return Time from Low-Power Consumption Mode

12.9.1 Return Factor: Interrupt/WKUP

The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Typ Max* SLEEP mode Ticnt tCYCC ns High-speed CR TIMER mode, Main TIMER mode, PLL TIMER mode 43 83 μs Low-speed CR TIMER mode 310 620 μs Sub TIMER mode 534 724 μs RTC mode, STOP mode 278 479 μs Deep Standby RTC mode, Deep Standby STOP mode 298 543 μs When RAM is off 288 523 μs When RAM is on *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by external interrupt*) Ext.INT Ticnt Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.

Document Number: 002-05667 Rev. *D Page 123 of 136 MB9B120TA Series Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal Resource INT Ticnt Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family PERIPHERAL MANUAL about the return factor from Low-Power consumption mode. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL".

Document Number: 002-05667 Rev. *D Page 124 of 136 MB9B120TA Series

12.9.2 Return Factor: Reset

The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Typ Max* SLEEP mode Trcnt 149 264 μs High-speed CR TIMER mode, Main TIMER mode, PLL TIMER mode 149 264 μs Low-speed CR TIMER mode 318 603 μs Sub TIMER mode 308 583 μs RTC/STOP mode 248 443 μs Deep Standby RTC mode, Deep Standby STOP mode 298 543 μs When RAM is off 288 523 μs When RAM is on *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by INITX) INITX Trcnt Internal RST CPU Operation Start RST Active Release

Document Number: 002-05667 Rev. *D Page 125 of 136 MB9B120TA Series Operation example of return from low power consumption mode (by internal resource reset*) Internal Resource RST Trcnt Internal RST CPU Operation Start RST Active Release *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See "CHAPTER 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family PERIPHERAL MANUAL. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "CHAPTER 6: Low Power Consumption Mode" in "FM3 Family PERIPHERAL MANUAL". − The time during the power-on reset/low-voltage detection reset is excluded. See "(6) Power-on Reset Timing in 4. AC Characteristics in Electrical Characteristics" for the detail on the time during the power-on reset/low -voltage detection reset. − When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset.

Document Number: 002-05667 Rev. *D Page 126 of 136 MB9B120TA Series 13. Ordering Information Part number On-chip Flash memory On-chip MB9BF128SAPMC-GK7E2 Main: 1 Mbyte Work: 64 Kbyte 160 Kbyte Plastic・LQFP, 144-pin (0.5 mm pitch) (LQS144) Tray MB9BF129SAPMC-GK7E2 Main: 1.5 Mbyte Work: 64 Kbyte 192 Kbyte MB9BF128TAPMC-GK7E2 Main: 1 Mbyte Work: 64 Kbyte 160 Kbyte Plastic・LQFP, 176-pin (0.5 mm pitch) (LQP176) MB9BF129TAPMC-GK7E2 Main: 1.5 Mbyte Work: 64 Kbyte 192 Kbyte MB9BF128TABGL-GK7E1 Main: 1 Mbyte Work: 64 Kbyte 160 Kbyte Plastic・FBGA, 192-pin (0.8 mm pitch) (LBE192) MB9BF129TABGL-GK7E1 Main: 1.5 Mbyte Work: 64 Kbyte 192 Kbyte

Document Number: 002-05667 Rev. *D Page 127 of 136 MB9B120TA Series 14. Package Dimensions Package Type Package Code LQFP 176 LQP176 DIMENSIONS SYMBOL MIN. NOM. MAX. A 1.70 A1 0.05 0.15 b 0.17 0.22 0.27 c 0.09 0.20 D 26.00 BSC D1 24.00 BSC e 0.50 BSC E L 0.45 0.60 0.75

26.00 BSC

24.00 BSC

0.30 0.50 0.70 176 e D EE1

0.08 C A-B Db

0.10 C A-B D

0.08 C A SEATING PLANE 5 7 A A10.25 10L1 L b SECTION A-A'

0.20 C A-B D

PACKAGE OUTLINE, 176 LEAD LQFP 24.0X24.0X1.7 MM LQP176 REV002-15150

Document Number: 002-05667 Rev. *D Page 128 of 136 MB9B120TA Series Package Type Package Code LQFP 144 LQS144 DIMENSIONS SYMBOL MIN. NOM. MAX. A 1.70 A1 0.05 0.15 b 0.17 0.27 c 0.09 0.20 D 22.00 BSC D1 20.00 BSC e 0.50 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70

22.00 BSC

20.00 BSC

0.22 144 D e EE1

0.08 C A-B D

b A SEATING PLANE 0.08 C A 0.25 10L1 L b SECTION A-A' 5 7 752 144 D E E1 4 5 73108 109 72 109 36 1 80137 SIDE VIEW TOP VIEW BOTTOM VIEW PACKAGE OUTLINE, 144 LEAD LQFP 20.0X20.0X1.7 MM LQS144 REV*A 002-13015 *A

Document Number: 002-05667 Rev. *D Page 129 of 136 MB9B120TA Series Package Type Package Code BGA 192 LBE192 002-13493 *A

Document Number: 002-05667 Rev. *D Page 130 of 136 MB9B120TA Series 15. Errata This chapter describes the errata for MB9B120T series. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.

15.1 Part Numbers Affected

MB9BF128TPMC-GE2, MB9BF129TPMC-GE2, MB9BF128TBGL-GE1, MB9BF129TBGL-GE1, MB9BF128SPMC-GE2, MB9BF129SPMC-GE2, MB9BF128TPMC-GK7E2, MB9BF129TPMC-GK7E2, MB9BF128TBGL-GK7E1, MB9BF129TBGL-GK7E1, MB9BF128SPMC-GK7E2, MB9BF129SPMC-GK7E2

15.2 Qualification Status

Product Status: In Production − Qual.

15.3 Errata Summary

This table defines the errata applicability to available devices. Items Part Number Silicon Revision Fix Status [1] HDMI-CEC polling message issue Refer to 15.1 Initial rev. Fixed in Rev. A

15.4 Errata Detail

15.4.1 HDMI-CEC polling message issue

 PROBLEM DEFINITION Error#1) While MCU sends a Polling Message, it always returns a NACK to a message coming to the MCU from another node. Error#2) MCU always waits for 7-bit signal free on CEC line before it drives the line even when the last line initiator was another node.  PARAMETERS AFFECTED N/A  TRIGGER CONDITION(S) This error always happens.  SCOPE OF IMPACT MCU does not reply properly to another node.  WORKAROUND The software workaround is applied to Error #1. 1. Store 0x0 to SFREE register. 2. Monitor CEC line with GPIO and wait until 1 lasts for the signal free time. 3. Store frame data to TXDATA register and store 0x0F to RCADR1 or RCADR2 register. It sends a message after 3~4 clocks of 32.768 kHz clock when TXDATA is stored 0x0F. If the device receives a frame from another node within 2~3 clocks after storing TXDATA, the bus error occurs and if the device receives a frame from another node within 3~4 clocks after storing TXDATA, the arbitration lost occurs. In these cases:

Document Number: 002-05667 Rev. *D Page 131 of 136 MB9B120TA Series 4-A-1. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK 4-A-2. Return back to step 2 above If the device receives a frame from another node within 1~2 clocks after storing TXDATA, take these steps. 4-B-1. Monitor CEC line with GPIO after 50us from storing TXDATA 4-B-2. Set TXEN to 1 -> 0 -> 1 immediately when GPIO finds state low on the CEC line 4-B-3. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK 4-B-4. Return back to step 2 above For Error #2, there is no software workaround, but signal free time of fixed 7-bit does not violate HDMI-CEC specification. The specification says signal free time must be more than and equals to 5-bit.  FIX STATUS This issue was fixed in Rev. A.

Document Number: 002-05667 Rev. *D Page 132 of 136 MB9B120TA Series 16. Major Changes Spansion Publication Number: DS706-00063 Page Section Change Results Revision 0.1 - - Initial release Revision 0.2 - - Company name and layout design change Revision 1.0 - - Preliminary → Full Production

2 FEATURES

Added the descriptions as follows  Maximum area size : Up to 256 Mbytes

3 FEATURES

A/D Converter Corrected conversion time

5 FEATURES

Multi-function Timer Corrected the channel count of "A/D activation compare"

7 PRODUCT LINEUP

Function Added the footnote

63 HANDLING DEVICES

 Power supply pins Added the description

65 BLOCK DIAGRAM Corrected the figure

66 MEMORY MAP

Memory Map(1) Corrected the Address of “External Device Area”

76 ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings Added the Item of “Input Voltage” 78 2. Recommended Operating Conditions Added the footnote 79 - 81 3.DC Characteristics (1) Current Rating  Corrected the Condition  Corrected the Value  Corrected the Remarks  Added the footnote 83 (2) Pin Characteristics Added the Item of “Input leak current” 88 4. AC Characteristics (6) Power-on Reset Timing  Revised the values of “Time until releasing Power-on reset”  Corrected the figure  Corrected the Glossary 107 (9) CSIO Timing  Synchronous serial (SPI=1, SCINV=1) Corrected the figure of “MS bit=1”  External clock (EXT=1):asynchronous only Corrected the figure 114 5.12-bit A/D Converter ・Electrical characteristics for the A/D converter  Corrected the Pins name AN00 - AN23 → ANxx  Corrected the Min Vale of “Conversion time”  Corrected the Min Vale of “Sampling time”  Corrected the Min Value of “Compare clock cycle”  Corrected the “State Transition time to operation permission”  Corrected the footnote 119 9. Electrical characteristics for the A/D converter (1) Write / Erase time Revised the values of “TBD”

Document Number: 002-05667 Rev. *D Page 133 of 136 MB9B120TA Series Page Section Change Results 120 10. Return Time from Low-Power Consumption Mode (1) Return Factor: Interrupt/WKUP  Return Count Time Revised the values of “TBD” 122 (2) Return Factor: Reset  Return Count Time Revised the values of “TBD” Revision 2.0 - - Changed the series name. MB9B120T Series -> MB9B120TA Series - - Changed the product name as follows. MB9BF128SA, MB9BF129SA, MB9BF128TA, MB9BF129TA 41 to 48 List of Pin Functions

• List of pin functions Added LIN to the description of SOTxx 55, 56 I/O Circuit Type Added about +B input

67 Memory Map

• Memory map(2) Added the summary of Flash memory sector 1. Absolute Maximum Ratings
• Added the Clamp maximum current
• Added about +B input 79, 80

Electrical Characteristics

1. DC Characteristics (1) Current rating

• Changed the expression of condition
• Added Main TIMER mode current

1. AC Characteristics (4-1) Operating Conditions of Main PLL (4-2) Operating Conditions of Main PLL

• Added the figure of Main PLL connection 100 to 107

1. AC Characteristics (7) CSIO/UART Timing

• Modified from UART Timing to CSIO/UART Timing
• Changed from Internal shift clock operation to Master mode
• Changed from External shift clock operation to Slave mode 5. 12bit A/D Converter
• Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage NOTE: Please see “Document History” about later revised information.

Document Number: 002-05667 Rev. *D Page 134 of 136 MB9B120TA Series Document History Document Title: MB9B120TA Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller Document Number: 002-05667 Revision ECN Orig. of Change Submission Date Description of Change ** - TOYO 01/30/2015 Migrated to Cypress and assigned document number 002-05667. No change to document contents or format. *A 5201323 TOYO 04/05/2016 Updated to Cypress format. *B 5653479 NOSU 03/10/2017 Updated Cypress Logo Corrected the package codes the following chapters as the table below. 2. Packages 3. Pin Assignment 13. Ordering Information 14. Package Dimensions Before After FPT-144P-M08 LQS144 FPT-176P-M07 LQP176 BGA-192P-M06 LBE192 Modified RTC description in chapter Features Before The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of the week.) is available. After The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute.) is available. Corrected a word “J-TAG” to “JTAG” in 4. List of Pin Functions (Page 32) Added a note of “TAP Controller” in 4. List of Pin Functions (Page 52) Corrected sector size of Memory Map (2) in 10. Memory Map ROM1_SA8_15(8KBx8)  ROM1_SA8_15(64KBx8) Replaced a word “Ta” to “TA” in the following chapters. 12.2. Recommended Operating Conditions 12.3. DC Characteristics 12.4. AC Characteristics 12.5. 12-bit A/D Converter 12.6. 10-bit D/A Converter 12.7. Low-Voltage Detection Characteristics 12.8. Flash Memory Write/Erase Characteristics 12.9. Return Time from Low-Power Consumption Mode Added the Baud rate spec in 12.4.10 CSIO Timing (Page 101, 103, 105, 107) Updated 12.4.7. Power-on Reset Timing Corrected the following statement in chapter 12.5. 12-bit A/D Converter Analog port input current  Analog port input leak current Corrected the Part numbers in chapter 13. Ordering Information MB9BF128SAPMC-GE1  MB9BF128SAPMC-GK7E2 MB9BF129SAPMC-GE1  MB9BF129SAPMC-GK7E2 MB9BF128TAPMC-GE1  MB9BF128TAPMC-GK7E2 MB9BF129TAPMC-GE1  MB9BF129TAPMC-GK7E2 MB9BF128TABGL-GE1  MB9BF128TABGL-GK7E1 MB9BF129TABGL-GE1  MB9BF129TABGL-GK7E1 Updated 14. Package Dimensions Added 15. Errata

Document Number: 002-05667 Rev. *D Page 135 of 136 MB9B120TA Series Revision ECN Orig. of Change Submission Date Description of Change *C 5790538 YSAT 07/04/2017 Adapted new Cypress logo *D 6013729 YSAT 01/12/2018 Updated Arm trademark and the last page Updated the figure of LBE192 in 14. Package Dimensions

Document Number: 002-05667 Rev. *D January 12, 2018 Page 136 of 136 MB9B120TA Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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