MB9BF124LPMC-G-JNE2

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Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 101

Technical content

Datasheet sections

• 6.1 Precautions for Product Design
• 6.2 Precautions for Package Mounting
• 6.3 Precautions for Use Environment
• 12.1 Absolute Maximum Ratings
• 12.2 Recommended Operating Conditions
• 12.3 DC Characteristics
• 12.3.1 Current Rating
• 12.3.2 Pin Characteristics
• 12.4 AC Characteristics
• 12.4.1 Main Clock Input Characteristics
• 12.4.2 Sub Clock Input Characteristics
• 12.4.3 Built-in CR Oscillation Characteristics
• 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
• 12.4.6 Reset Input Characteristics
• 12.4.7 Power-on Reset Timing
• 12.4.8 Base Timer Input Timing
• 12.4.9 CSIO/UART Timing
• 12.4.10 External Input Timing
• 12.4.11 Quadrature Position/Revolution Counter timing
• 12.4.12 I2C Timing
• 12.4.13 JTAG Timing
• 12.7 Low-Voltage Detection Characteristics
• 12.7.1 Low-Voltage Detection Reset
• 12.7.2 Interrupt of Low-Voltage Detection
• 12.8 Flash Memory Write/Erase Characteristics
• 12.8.1 Write / Erase time
• 12.8.2 Write cycles and data hold time
• 12.9 Return Time from Low-Power Consumption Mode
• 12.9.1 Return Factor: Interrupt/WKUP
• 12.9.2 Return Factor: Reset

Features

32-bit Arm® Cortex®-M3 Core  Processor version: r2p1  Up to 72 MHz Frequency Operation  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory]  Dual operation Flash memory  Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously.  Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)  Work area: 32 Kbytes (lower bank)  Read cycle: 0 wait-cycle  Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  SRAM0: Up to 16 Kbytes  SRAM1: Up to 16 Kbytes Multi-function Serial Interface (Max eight channels)  4 channels with 16 stepsx9-bit FIFO (ch.0/1/3/4), 4 channels without FIFO (ch.2/5/6/7)  Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2C [UART]  Full duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control: Automatically control the transmission/reception by CTS/RTS (only ch.4)  Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO]  Full duplex double buffer  Built-in dedicated baud rate generator  Overrun error detection function available [LIN]  LIN protocol Rev.2.1 supported  Full duplex double buffer  Master/Slave mode supported  LIN break field generation (can be changed to 13 to 16-bit length)  LIN break delimiter generation (can be changed to 1 to 4-bit length)  Various error detection functions available (parity errors, framing errors, and overrun errors) [I2C]  Standard mode (Max 100 kbps)/Fast mode (Max 400 kbps) supported

Document Number: 002-05655 Rev. *D Page 2 of 101 MB9B120M Series DMA Controller (Eight channels) The DMA controller has an independent bus from the CPU, so the CPU and the DMA controller can process simultaneously.  8 independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  Transfer address area: 32-bit (4 Gbytes)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: bytes/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536 A/D Converter (Max 26 channels) [12-bit A/D Converter]  Successive Approximation type  Built-in 2 units  Conversion time: 0.8 μs @ 5V  Priority conversion available (priority at 2 levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) D/A Converter (Max two channels)  R-2R type  10-bit resolution Base Timer (Max eight channels) Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in port relocate function  Up to 65 high-speed general-purpose I/O ports @ 80 pin package  Some ports are 5V tolerant. See "List of Pin Functions" and "I/O Circuit Type" to confirm the corresponding pins. Dual Timer (32-/16-bit Down Counter) The dual timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot Quadrature Position/Revolution Counter (QPRC) (Max two channels) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use as the up/down counter.  The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers

Document Number: 002-05655 Rev. *D Page 3 of 101 MB9B120M Series Multi-Function Timer The multi-function timer is composed of the following blocks.  16-bit free-run timer × 3ch./unit  Input capture × 4ch./unit  Output compare × 6ch./unit  A/D activation compare × 2ch./unit  Waveform generator × 3ch./unit  16-bit PPG timer × 3ch./unit The following functions can be used to achieve motor control.  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D converter activate function  DTIF (motor emergency stop) interrupt function Real-Time Clock (RTC) The real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.  The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. Watch Counter The watch counter is used for wake up from the Sleep and Timer mode. Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz External Interrupt Controller Unit  Up to 23 external interrupt input pins @ 80 pin Package  Include one non-maskable interrupt (NMI) input pin Watchdog Timer (Two channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a “Hardware” watchdog and a “Software” watchdog. The “Hardware” watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the “Hardware” watchdog is active in any low-power consumption modes except RTC, Stop, Deep Standby RTC, Deep Standby Stop modes. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillator, and Main PLL).  Main Clock: 4 MHz to 48 MHz  Sub Clock: 32.768 kHz  Built-in High-speed CR Clock: 4 MHz  Built-in Low-speed CR Clock: 100 kHz  Main PLL Clock [Resets]  Reset requests from INITX pin  Power-on reset  Software reset  Watchdog timers reset  Low-voltage detection reset  Clock Super Visor reset Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.  If external clock failure (clock stop) is detected, reset is asserted.  If external frequency anomaly is detected, interrupt or reset is asserted.

Document Number: 002-05655 Rev. *D Page 4 of 101 MB9B120M Series Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation Low-Power Consumption Mode Six low-power consumption modes are supported.  Sleep  Timer  RTC  Stop  Deep Standby RTC (selectable between keeping the value of RAM and not)  Deep Standby Stop (selectable between keeping the value of RAM and not) Debug Serial Wire JTAG Debug Port (SWJ-DP) Unique ID Unique value of the device (41-bit) is set. Power Supply  Wide range voltage: VCC = 2.7 V to 5.5 V

Document Number: 002-05655 Rev. *D Page 6 of 101 MB9B120M Series

Document Number: 002-05655 Rev. *D Page 7 of 101 MB9B120M Series 1. Product Lineup Memory Size Product Name MB9BF121K/L/M MB9BF122K/L/M MB9BF124K/L/M On-chip Flash memory Main area 64 Kbytes 128 Kbytes 256 Kbytes Work area 32 Kbytes 32 Kbytes 32 Kbytes On-chip SRAM SRAM0 8 Kbytes 8 Kbytes 16 Kbytes SRAM1 8 Kbytes 8 Kbytes 16 Kbytes Total 16 Kbytes 16 Kbytes 32 Kbytes Function Product Name MB9BF121K MB9BF122K MB9BF124K MB9BF121L MB9BF122L MB9BF124L MB9BF121M MB9BF122M MB9BF124M Pin count 48 64 80/96 CPU Cortex-M3 Freq. 72 MHz Power supply voltage range 2.7 V to 5.5 V DMAC 8ch. Multi-function Serial Interface (UART/CSIO/LIN/I2C) 4 ch. (Max) ch.0/1/3: FIFO ch.5: No FIFO (In ch.1/5, only UART and LIN are available.) 8 ch. (Max) ch.0/1/3/4 FIFO ch.2/5/6/7: No FIFO (In ch.1, only UART and LIN are available.) Base Timer (PWC/Reload timer/PWM/PPG) 8ch. (Max) MF Timer A/D activation compare 2 ch. 1 unit Input capture 4 ch.* Free-run timer 3 ch. Output compare 6 ch. Waveform generator 3 ch. PPG 3 ch. QPRC 1 ch. 2 ch. (Max) Dual Timer 1 unit Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog Timer 1 ch. (SW) + 1 ch. (HW) External Interrupts 14 pins (Max) + NMI × 1 19 pins (Max) + NMI x 1 23 pins (Max) + NMI x 1 I/O ports 35 pins (Max) 50 pins (Max) 60 pins (Max) 12-bit A/D converter 14 ch. (2 units) 23 ch. (2 units) 26 ch. (2 units) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2 ch. Built-in CR High-speed 4 MHz Low-speed 100 kHz Debug Function SWJ-DP Unique ID Yes *: The external input channel which can be used is shown as follows.

• ch.0 to ch.3: MB9BF121M/F122M/F124M
• ch.0, ch.2, ch.3: MB9BF121K/F122K/F124K, MB9BF121L/F122L/F124L Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See “12 Electrical Characteristics 12.4 AC Characteristics 12.4.3 Built-in CR Oscillation Characteristics” for the accuracy of the built-in CR.

Document Number: 002-05655 Rev. *D Page 8 of 101 MB9B120M Series 2. Packages Product name Package MB9BF121K MB9BF122K MB9BF124K MB9BF121L MB9BF122L MB9BF124L MB9BF121M MB9BF122M MB9BF124M LQFP: LQA048 (0.5 mm pitch)  - - QFN: VNA048 (0.5 mm pitch)  - - LQFP: LQD064 (0.5 mm pitch) -  - LQFP: LQG064 (0.65 mm pitch) -  - QFP: VNC064 (0.5 mm pitch) -  - LQFP: LQH080 (0.5 mm pitch) - -  LQFP: LQJ080 (0.65 mm pitch) - -  BGA: FDG096 (0.5 mm pitch) - -  : Supported Note: − See "Package Dimensions" for detailed information on each package

Document Number: 002-05655 Rev. *D Page 9 of 101 MB9B120M Series 3. Pin Assignment LQH080/LQJ080 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81/INT17_1 P80/INT16_1 VCC P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1 P61/AN20/SOT5_0/TIOB2_2/DTTI0X_2 P62/AN19/SCK5_0/ADTG_3 P63/INT03_0 P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0 P0E/CTS4_0/TIOB3_2/INT21_0 P0D/RTS4_0/TIOA3_2/INT20_0 P0C/AN17/SCK4_0/TIOA6_1/INT19_0 P0B/AN16/SOT4_0/TIOB6_1/INT18_0 P0A/AN15/SIN4_0/INT00_2 P07/ADTG_0/INT23_1 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 1 60 P20/INT05_0/CROUT_0/AIN1_1 P50/AN22/INT00_0/AIN0_2/SIN3_1 2 59 P21/AN14/SIN0_0/INT06_1/BIN1_1/WKUP2 P51/AN23/INT01_0/BIN0_2/SOT3_1 3 58 P22/AN13/SOT0_0/TIOB7_1/ZIN1_1 P52/AN24/INT02_0/ZIN0_2/SCK3_1 4 57 P23/AN12/SCK0_0/TIOA7_1 P53/SIN6_0/TIOA1_2/INT07_2 5 56 P1B/AN11/SOT4_1/INT20_2/IC01_1 P54/SOT6_0/TIOB1_2/INT18_1 6 55 P1A/AN10/SIN4_1/INT05_1/IC00_1 P55/SCK6_0/ADTG_1/INT19_1 7 54 P19/AN09/SCK2_2 P56/INT08_2 8 53 P18/AN08/SOT2_2 P30/AN25/AIN0_0/TIOB0_1/INT03_2 9 52 AVRL P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2 10 51 AVRH P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2 11 50 AVCC P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 12 49 P17/AN07/SIN2_2/INT04_1 P39/DTTI0X_0/INT06_0/ADTG_2 13 48 P16/AN06/SCK0_1/INT15_0 P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 14 47 P15/AN05/SOT0_1/INT14_0/IC03_2 P3B/RTO01_0/TIOA1_1 15 46 P14/AN04/SIN0_1/INT03_1/IC02_2 P3C/RTO02_0/TIOA2_1/INT18_2 16 45 AVSS P3D/RTO03_0/TIOA3_1 17 44 P12/AN02/SOT1_1/IC00_2 P3E/RTO04_0/TIOA4_1/INT19_2 18 43 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1 P3F/RTO05_0/TIOA5_1 19 42 P10/AN00 VSS 20 41 VCC P44/TIOA4_0/INT10_0 P45/TIOA5_0/INT11_0 C VSS VCC P46/X0A P47/X1A INITX P48/SIN3_2/INT14_1 P49/TIOB0_0/SOT3_2/INT20_1/AIN0_1/DA0_0 P4A/TIOB1_0/SCK3_2/INT21_1/BIN0_1/DA1_0 P4B/TIOB2_0/INT22_1/ZIN0_1/IGTRG_0 P4C/TIOB3_0/SCK7_1/INT12_0/AIN1_2 P4D/TIOB4_0/SOT7_1/INT13_0/BIN1_2 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 80

Document Number: 002-05655 Rev. *D Page 10 of 101 MB9B120M Series LQD064/LQG064 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81/INT17_1 P80/INT16_1 VCC P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1 P61/AN20/SOT5_0/TIOB2_2/DTTI0X_2 P62/AN19/SCK5_0/ADTG_3 P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0 P0C/AN17/SCK4_0/TIOA6_1/INT19_0 P0B/AN16/SOT4_0/TIOB6_1/INT18_0 P0A/AN15/SIN4_0/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 1 48 P21/AN14/SIN0_0/INT06_1/WKUP2 P50/AN22/INT00_0/AIN0_2/SIN3_1 2 47 P22/AN13/SOT0_0/TIOB7_1 P51/AN23/INT01_0/BIN0_2/SOT3_1 3 46 P23/AN12/SCK0_0/TIOA7_1 P52/AN24/INT02_0/ZIN0_2/SCK3_1 4 45 P19/AN09/SCK2_2 P30/AN25/AIN0_0/TIOB0_1/INT03_2 5 44 P18/AN08/SOT2_2 P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2 6 43 AVRL P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2 7 42 AVRH P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 8 41 AVCC P39/DTTI0X_0/INT06_0/ADTG_2 9 40 P17/AN07/SIN2_2/INT04_1 P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 10 39 P15/AN05/SOT0_1/INT14_0/IC03_2 P3B/RTO01_0/TIOA1_1 11 38 P14/AN04/SIN0_1/INT03_1/IC02_2 P3C/RTO02_0/TIOA2_1/INT18_2 12 37 AVSS P3D/RTO03_0/TIOA3_1 13 36 P12/AN02/SOT1_1/IC00_2 P3E/RTO04_0/TIOA4_1/INT19_2 14 35 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1 P3F/RTO05_0/TIOA5_1 15 34 P10/AN00 VSS 16 33 VCC C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/SOT3_2/INT20_1/AIN0_1/DA0_0 P4A/TIOB1_0/SCK3_2/INT21_1/BIN0_1/DA1_0 P4B/TIOB2_0/INT22_1/ZIN0_1/IGTRG_0 P4C/TIOB3_0/SCK7_1/INT12_0/AIN1_2 P4D/TIOB4_0/SOT7_1/INT13_0/BIN1_2 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 64

Document Number: 002-05655 Rev. *D Page 11 of 101 MB9B120M Series VNC064 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81/INT17_1 P80/INT16_1 VCC P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1 P61/AN20/SOT5_0/TIOB2_2/DTTI0X_2 P62/AN19/SCK5_0/ADTG_3 P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0 P0C/AN17/SCK4_0/TIOA6_1/INT19_0 P0B/AN16/SOT4_0/TIOB6_1/INT18_0 P0A/AN15/SIN4_0/INT00_2 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 1 48 P21/AN14/SIN0_0/INT06_1/WKUP2 P50/AN22/INT00_0/AIN0_2/SIN3_1 2 47 P22/AN13/SOT0_0/TIOB7_1 P51/AN23/INT01_0/BIN0_2/SOT3_1 3 46 P23/AN12/SCK0_0/TIOA7_1 P52/AN24/INT02_0/ZIN0_2/SCK3_1 4 45 P19/AN09/SCK2_2 P30/AN25/AIN0_0/TIOB0_1/INT03_2 5 44 P18/AN08/SOT2_2 P31/AN26/BIN0_0/TIOB1_1/SCK6_1/INT04_2 6 43 AVRL P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2 7 42 AVRH P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6 8 41 AVCC P39/DTTI0X_0/INT06_0/ADTG_2 9 40 P17/AN07/SIN2_2/INT04_1 P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 10 39 P15/AN05/SOT0_1/INT14_0/IC03_2 P3B/RTO01_0/TIOA1_1 11 38 P14/AN04/SIN0_1/INT03_1/IC02_2 P3C/RTO02_0/TIOA2_1/INT18_2 12 37 AVSS P3D/RTO03_0/TIOA3_1 13 36 P12/AN02/SOT1_1/IC00_2 P3E/RTO04_0/TIOA4_1/INT19_2 14 35 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1 P3F/RTO05_0/TIOA5_1 15 34 P10/AN00 VSS 16 33 VCC C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/SOT3_2/INT20_1/AIN0_1/DA0_0 P4A/TIOB1_0/SCK3_2/INT21_1/BIN0_1/DA1_0 P4B/TIOB2_0/INT22_1/ZIN0_1/IGTRG_0 P4C/TIOB3_0/SCK7_1/INT12_0/AIN1_2 P4D/TIOB4_0/SOT7_1/INT13_0/BIN1_2 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN - 64

Document Number: 002-05655 Rev. *D Page 12 of 101 MB9B120M Series LQA048 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81/INT17_1 P80/INT16_1 VCC P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1 P61/AN20/SOT5_0/TIOB2_2/DTTI0X_2 P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 1 36 P21/AN14/SIN0_0/INT06_1/WKUP2 P50/AN22/INT00_0/AIN0_2/SIN3_1 2 35 P22/AN13/SOT0_0/TIOB7_1 P51/AN23/INT01_0/BIN0_2/SOT3_1 3 34 P23/AN12/SCK0_0/TIOA7_1 P52/AN24/INT02_0/ZIN0_2/SCK3_1 4 33 AVRL P39/DTTI0X_0/INT06_0/ADTG_2 5 32 AVRH P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 6 31 AVCC P3B/RTO01_0/TIOA1_1 7 30 P15/AN05/SOT0_1/INT14_0/IC03_2 P3C/RTO02_0/TIOA2_1/INT18_2 8 29 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 9 28 AVSS P3E/RTO04_0/TIOA4_1/INT19_2 10 27 P12/AN02/SOT1_1/IC00_2 P3F/RTO05_0/TIOA5_1 11 26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1 VSS 12 25 P10/AN00 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/INT20_1/DA0_0 P4A/TIOB1_0/INT21_1/DA1_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 48

Document Number: 002-05655 Rev. *D Page 13 of 101 MB9B120M Series VNA048 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81/INT17_1 P80/INT16_1 VCC P60/AN21/SIN5_0/TIOA2_2/INT15_1/WKUP3/IGTRG_1 P61/AN20/SOT5_0/TIOB2_2/DTTI0X_2 P0F/AN18/NMIX/SUBOUT_0/CROUT_1/RTCCO_0/WKUP0 P04/TDO/SWO P03/TMS/SWDIO P02/TDI P01/TCK/SWCLK P00/TRSTX VCC 1 36 P21/AN14/SIN0_0/INT06_1/WKUP2 P50/AN22/INT00_0/AIN0_2/SIN3_1 2 35 P22/AN13/SOT0_0/TIOB7_1 P51/AN23/INT01_0/BIN0_2/SOT3_1 3 34 P23/AN12/SCK0_0/TIOA7_1 P52/AN24/INT02_0/ZIN0_2/SCK3_1 4 33 AVRL P39/DTTI0X_0/INT06_0/ADTG_2 5 32 AVRH P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2 6 31 AVCC P3B/RTO01_0/TIOA1_1 7 30 P15/AN05/SOT0_1/INT14_0/IC03_2 P3C/RTO02_0/TIOA2_1/INT18_2 8 29 P14/AN04/SIN0_1/INT03_1/IC02_2 P3D/RTO03_0/TIOA3_1 9 28 AVSS P3E/RTO04_0/TIOA4_1/INT19_2 10 27 P12/AN02/SOT1_1/IC00_2 P3F/RTO05_0/TIOA5_1 11 26 P11/AN01/SIN1_1/INT02_1/FRCK0_2/WKUP1 VSS 12 25 P10/AN00 C VCC P46/X0A P47/X1A INITX P49/TIOB0_0/INT20_1/DA0_0 P4A/TIOB1_0/INT21_1/DA1_0 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN - 48

Document Number: 002-05655 Rev. *D Page 14 of 101 MB9B120M Series FDG096 (TOP VIEW) H J A B C 6 7 K L D E F G 8 9 103 4 5 VCC P3D 1 2 VSS VCC AN22 P53 P3E VSS AN05 AVSS MD1VSS X1A INITX P4CP45 P49 P39 AN25 AN01 VSS TRSTX VSS P20 AN12 AN10 AN07 VSS P3F P56 VSS P32 P3A VSS P3B VSS AN11 AN08 AN06 AN04 AN02 AN18 TCK/ SWCLK VSS P07 AN16 TDO/ SWOAN17 AN13 AN15AN19 P81 P80 VCC VSS TMS/ SWDIO AN24 AN20 P63 P0D VSS AN26 VSS AN21 P0E P4E P48 P4A P4D MD0 P55 X0 X1VSS Index P33 P3C AVCC AN00 VCC VSS C X0A VSS P44 VSS P4B AN23 VSS P54 VSS TDI AN14 VSS AN09 AVRH AVRL Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin.

Document Number: 002-05655 Rev. *D Page 15 of 101 MB9B120M Series 4. List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Pin Name I/O circuit type Pin state type LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48

1 B1 1 1 VCC -

2 C1 2 2

INT00_0 AIN0_2 SIN3_1 AN22

3 C2 3 3

INT01_0 BIN0_2 SOT3_1 (SDA3_1) AN23

4 B3 4 4

INT02_0 ZIN0_2 SCK3_1 (SCL3_1) AN24

5 D1 - -

E L SIN6_0 TIOA1_2 INT07_2

6 D2 - -

SOT6_0 (SDA6_0) TIOB1_2 INT18_1

7 D3 - -

SCK6_0 (SCL6_0) ADTG_1 INT19_1

8 E1 - - P56 E L INT08_2

9 E2 5 -

AIN0_0 TIOB0_1 INT03_2 AN25

10 E3 6 -

BIN0_0 TIOB1_1 SCK6_1 (SCL6_1) INT04_2 AN26

Document Number: 002-05655 Rev. *D Page 16 of 101 MB9B120M Series Pin No Pin Name I/O circuit type Pin state type LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48

11 G1 7 -

ZIN0_0 TIOB2_1 SOT6_1 (SDA6_1) INT05_2

12 G2 8 -

INT04_0 TIOB3_1 SIN6_1 ADTG_6

13 G3 9 5

E L DTTI0X_0 INT06_0 ADTG_2

14 H1 10 6

RTO00_0 (PPG00_0) TIOA0_1 INT07_0 SUBOUT_2 RTCCO_2

15 H2 11 7

G K RTO01_0 (PPG00_0) TIOA1_1

16 H3 12 8

RTO02_0 (PPG02_0) TIOA2_1 INT18_2

17 J1 13 9

G K RTO03_0 (PPG02_0) TIOA3_1

18 J2 14 10

RTO04_0 (PPG04_0) TIOA4_1 INT19_2

19 J4 15 11

G K RTO05_0 (PPG04_0) TIOA5_1

20 L1 16 12 VSS -

21 L5 - -

G L TIOA4_0 INT10_0

22 K5 - -

G L TIOA5_0 INT11_0

Document Number: 002-05655 Rev. *D Page 17 of 101 MB9B120M Series Pin No Pin Name I/O circuit type Pin state type LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48

23 L2 17 13 C -

24 L4 - - VSS -

25 K1 18 14 VCC -

26 L3 19 15 P46 D F X0A

27 K3 20 16 P47 D G X1A

28 K4 21 17 INITX B C

29 J5 - -

E L INT14_1 SIN3_2

30 K6 22

TIOB0_0 INT20_1 DA0_0 SOT3_2 (SDA3_2) AIN0_1

31 J6 23

TIOB1_0 INT21_1 DA1_0 SCK3_2 (SCL3_2) BIN0_1

32 L7 24 -

TIOB2_0 INT22_1 IGTRG_0 ZIN0_1

33 K7 25 -

I* L TIOB3_0 SCK7_1 (SCL7_1) INT12_0 AIN1_2

34 J7 26 -

I* L TIOB4_0 SOT7_1 (SDA7_1) INT13_0 BIN1_2

35 K8 27 -

I* L TIOB5_0 INT06_2 SIN7_1 ZIN1_2

36 K9 28 20 MD1 C E PE0

37 L8 29 21 MD0 K D

Document Number: 002-05655 Rev. *D Page 18 of 101 MB9B120M Series Pin No Pin Name I/O circuit type Pin state type LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48

38 L9 30 22 X0 A A PE2

39 L10 31 23 X1 A B PE3

40 L11 32 24 VSS -

41 K11 33 - VCC -

42 J11 34 25 P10 F M AN00

43 J10 35 26

SIN1_1 INT02_1 FRCK0_2 WKUP1

44 J8 36 27

SOT1_1 (SDA1_1) IC00_2

45 H10 37 28 AVSS -

46 H9 38 29

INT03_1 IC02_2 SIN0_1

47 G10 39 30

IC03_2 SOT0_1 (SDA0_1) INT14_0

48 G9 - -

SCK0_1 (SCL0_1) INT15_0

49 F10 40 -

SIN2_2 INT04_1

50 H11 41 31 AVCC -

51 F11 42 32 AVRH -

52 G11 43 33 AVRL -

53 F9 44 -

SOT2_2 (SDA2_2)

54 E11 45 -

SCK2_2 (SCL2_2)

Document Number: 002-05655 Rev. *D Page 19 of 101 MB9B120M Series Pin No Pin Name I/O circuit type Pin state type LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48

55 E10 - -

SIN4_1 INT05_1 IC00_1

56 E9 - -

SOT4_1 (SDA4_1) IC01_1 INT20_2

57 D10 46 34

SCK0_0 (SCL0_0) TIOA7_1 AN12

58 D9 47 35

SOT0_0 (SDA0_0) TIOB7_1 AN13 - - ZIN1_1

59 C11 48 36

SIN0_0 INT06_1 WKUP2 BIN1_1 AN14

60 C10 - -

E N INT05_0 CROUT_0 AIN1_1

61 A10 49 37 P00 E J TRSTX

62 B9 50 38

63 B11 51 39 P02 E J TDI

64 A9 52 40

65 B8 53 41

66 A8 - -

E L ADTG_0 INT23_1

67 C8 54 -

J* N SIN4_0 INT00_2 AN15

Document Number: 002-05655 Rev. *D Page 20 of 101 MB9B120M Series Pin No Pin Name I/O circuit type Pin state type LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48

68 C7 55 -

J* N SOT4_0 (SDA4_0) TIOB6_1 AN16 INT18_0

69 B7 56 -

J* N SCK4_0 (SCL4_0) TIOA6_1 INT19_0 AN17

70 B6 - -

E L RTS4_0 TIOA3_2 INT20_0

71 C6 - -

E L CTS4_0 TIOB3_2 INT21_0

72 A6 57 42

SUBOUT_0 CROUT_1 RTCCO_0 WKUP0 AN18

73 B5 - - P63 E L INT03_0

74 C5 58 -

SCK5_0 (SCL5_0) ADTG_3 AN19

75 B4 59 43

SOT5_0 (SDA5_0) TIOB2_2 DTTI0X_2 AN20

76 C4 60 44

J* N SIN5_0 TIOA2_2 INT15_1 WKUP3 IGTRG_1 AN21

Document Number: 002-05655 Rev. *D Page 21 of 101 MB9B120M Series Pin No Pin Name I/O circuit type Pin state type LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48

77 A4 61 45 VCC -

78 A3 62 46 P80 H H INT16_1

79 A2 63 47 P81 H H INT17_1

80 A1 64 48 VSS -

A5, A7, A11, B2, B10, C3, C9, D11, F1, F2, F3, J3, J9, K2, K10, L6 - - VSS - *: 5 V tolerant I/O

Document Number: 002-05655 Rev. *D Page 22 of 101 MB9B120M Series List of functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function Pin name Function description Pin No LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48 ADC ADTG_0 A/D converter external trigger input pin ADTG_1 7 D3 - - ADTG_2 13 G3 9 5 ADTG_3 74 C5 58 - ADTG_6 12 G2 8 - AN00 A/D converter analog input pin. ANxx describes ADC ch.xx.

42 J11 34 25

TIOA0_1 Base timer ch.0 TIOA pin 14 H1 10 6 TIOB0_0 Base timer ch.0 TIOB pin 30 K6 22 18 TIOB0_1 9 E2 5 - Base Timer TIOA1_1 Base timer ch.1 TIOA pin 15 H2 11 7 TIOA1_2 5 D1 - - TIOB1_0 Base timer ch.1 TIOB pin

31 J6 23 19

TIOB1_1 10 E3 6 - TIOB1_2 6 D2 - - Base Timer TIOA2_1 Base timer ch.2 TIOA pin 16 H3 12 8 TIOA2_2 76 C4 60 44 TIOB2_0 Base timer ch.2 TIOB pin TIOB2_1 11 G1 7 - TIOB2_2 75 B4 59 43 Base Timer TIOA3_1 Base timer ch.3 TIOA pin 17 J1 13 9 TIOA3_2 70 B6 - - TIOB3_0 Base timer ch.3 TIOB pin TIOB3_1 12 G2 8 - TIOB3_2 71 C6 - - Base Timer TIOA4_0 Base timer ch.4 TIOA pin 21 L5 - - TIOA4_1 18 J2 14 10 TIOB4_0 Base timer ch.4 TIOB pin 34 J7 26 -

Document Number: 002-05655 Rev. *D Page 23 of 101 MB9B120M Series Pin function Pin name Function description Pin No LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48 Base Timer TIOA5_0 Base timer ch.5 TIOA pin 22 K5 - - TIOA5_1 19 J4 15 11 TIOB5_0 Base timer ch.5 TIOB pin 35 K8 27 - Base Timer TIOA6_1 Base timer ch.6 TIOA pin 69 B7 56 - TIOB6_1 Base timer ch.6 TIOB pin 68 C7 55 - Base Timer TIOA7_1 Base timer ch.7 TIOA pin 57 D10 46 34 TIOB7_1 Base timer ch.7 TIOB pin 58 D9 47 35 Debugger SWCLK Serial wire debug interface clock input pin 62 B9 50 38 SWDIO Serial wire debug interface data input / output pin 64 A9 52 40 SWO Serial wire viewer output pin 65 B8 53 41 TCK JTAG test clock input pin 62 B9 50 38 TDI JTAG test data input pin 63 B11 51 39 TDO JTAG debug data output pin 65 B8 53 41 TMS JTAG test mode state input/output pin 64 A9 52 40 TRSTX JTAG test reset input pin 61 A10 49 37

Document Number: 002-05655 Rev. *D Page 24 of 101 MB9B120M Series Pin function Pin name Function description Pin No LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48 External Interrupt INT00_0 External interrupt request 00 input pin 2 C1 2 2 INT00_2 67 C8 54 - INT01_0 External interrupt request 01 input pin 3 C2 3 3 INT02_0 External interrupt request 02 input pin 4 B3 4 4 INT02_1 43 J10 35 26 INT03_0 External interrupt request 03 input pin

73 B5 - -

INT03_1 46 H9 38 29 INT03_2 9 E2 5 - INT04_0 External interrupt request 04 input pin INT04_1 49 F10 40 - INT04_2 10 E3 6 - INT05_0 External interrupt request 05 input pin

60 P20 - -

INT05_1 55 E10 - - INT05_2 11 G1 7 - INT06_0 External interrupt request 06 input pin INT06_1 59 C11 48 36 INT06_2 35 K8 27 - INT07_0 External interrupt request 07 input pin 14 H1 10 6 INT07_2 5 D1 - - INT08_2 External interrupt request 08 input pin 8 E1 - - INT10_0 External interrupt request 10 input pin 21 L5 - - INT11_0 External interrupt request 11 input pin 22 K5 - - INT12_0 External interrupt request 12 input pin 33 K7 25 - INT13_0 External interrupt request 13 input pin 34 J7 26 - INT14_0 External interrupt request 14 input pin 47 G10 39 30 INT14_1 29 J5 - - INT15_0 External interrupt request 15 input pin 48 G9 - - INT15_1 76 C4 60 44 INT16_1 External interrupt request 16 input pin 78 A3 62 46 INT17_1 External interrupt request 17 input pin 79 A2 63 47 INT18_0 External interrupt request 18 input pin INT18_1 6 D2 - - INT18_2 16 H3 12 8 INT19_0 External interrupt request 19 input pin

59 C11 56 -

INT19_1 7 D3 - - INT19_2 18 J2 14 10 INT20_0 External interrupt request 20 input pin INT20_1 30 K6 22 18 INT20_2 56 E9 - - INT21_0 External interrupt request 21 input pin 71 C6 - - INT21_1 31 J6 23 19 INT22_1 External interrupt request 22 input pin 32 L7 24 - INT23_1 External interrupt request 23 input pin 66 A8 - - NMIX Non-Maskable Interrupt input pin 72 A6 57 42

Document Number: 002-05655 Rev. *D Page 25 of 101 MB9B120M Series Pin function Pin name Function description Pin No LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48 GPIO P00 General-purpose I/O port 0

61 A10 49 37

General-purpose I/O port 1 General-purpose I/O port 2 General-purpose I/O port 3

Document Number: 002-05655 Rev. *D Page 26 of 101 MB9B120M Series Pin function Pin name Function description Pin No LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48 GPIO P44 General-purpose I/O port 4 General-purpose I/O port 5 General-purpose I/O port 6 P80 General-purpose I/O port 8 78 A3 62 46 P81 79 A2 63 47 PE0 General-purpose I/O port E

36 K9 28 20

SIN0_0 Multi-function serial interface ch.0 input pin 59 C11 48 36 SIN0_1 46 H9 38 29 SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). SOT0_1 (SDA0_1) 47 G10 39 30 SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I2C (operation mode 4). SCK0_1 (SCL0_1) 48 G9 - - Multi- function Serial SIN1_1 Multi-function serial interface ch.1 input pin 43 J10 35 26 SOT1_1 (SDA1_1) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/LIN (operation modes 0,1,3) . SIN2_2 Multi-function serial interface ch.2 input pin 49 F10 40 - SOT2_2 (SDA2_2) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). SCK2_2 (SCL2_2) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a CSIO (operation mode 2) and as SCL2 when it is used in an I2C (operation mode 4).

Document Number: 002-05655 Rev. *D Page 27 of 101 MB9B120M Series Pin function Pin name Function description Pin No LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48 Multi- function Serial SIN3_1 Multi-function serial interface ch.3 input pin 2 C1 2 2 SIN3_2 29 J5 - - SOT3_1 (SDA3_1) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I2C (operation mode 4). SOT3_2 (SDA3_2) 30 K6 - - SCK3_1 (SCL3_1) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation mode 2) and as SCL3 when it is used in an I2C (operation mode 4). SCK3_2 (SCL3_2) 31 J6 - - Multi- function Serial SIN4_0 Multi-function serial interface ch.4 input pin SIN4_1 55 E10 - - SOT4_0 (SDA4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I2C (operation mode 4). SOT4_1 (SDA4_1) 56 E9 - - SCK4_0 (SCL4_0) Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation mode 2) and as SCL4 when it is used in an I2C (operation mode 4). RTS4_0 Multi-function serial interface ch.4 RTS output pin 70 B6 - - CTS4_0 Multi-function serial interface ch.4 CTS input pin 71 C6 - - Multi- function Serial SIN5_0 Multi-function serial interface ch.5 input pin 76 C4 60 44 SOT5_0 (SDA5_0) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation mode 2) and as SCL5 when it is used in an I2C (operation mode 4).

Document Number: 002-05655 Rev. *D Page 28 of 101 MB9B120M Series Pin function Pin name Function description Pin No LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48 Multi- function Serial SIN6_0 Multi-function serial interface ch.6 input pin 5 D1 - - SIN6_1 12 G2 8 - SOT6_0 (SDA6_0) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I2C (operation mode 4). SOT6_1 (SDA6_1) 11 G1 7 - SCK6_0 (SCL6_0) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation mode 2) and as SCL6 when it is used in an I2C (operation mode 4). SCK6_1 (SCL6_1) 10 E3 6 - Multi- function Serial SIN7_1 Multi-function serial interface ch.7 input pin 35 K8 27 - SOT7_1 (SDA7_1) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA7 when it is used in an I2C (operation mode 4). SCK7_1 (SCL7_1) Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a CSIO (operation mode 2) and as SCL7 when it is used in an I2C (operation mode 4).

Document Number: 002-05655 Rev. *D Page 29 of 101 MB9B120M Series Pin function Pin name Function description Pin No LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48 Multi- function Timer DTTI0X_0 Input signal of waveform generator to control outputs RTO00 to RTO05 of Multi-function timer 0. DTTI0X_2 75 B4 59 43 FRCK0_2 16-bit free-run timer ch.0 external clock input pin 43 J10 35 26 IC00_1 16-bit input capture input pin of Multi-function timer 0. ICxx describes channel number. IC00_2 44 J8 36 27 IC01_1 56 E9 - - IC02_2 46 H9 38 29 IC03_2 47 G10 39 30 RTO00_0 (PPG00_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. RTO01_0 (PPG00_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. RTO02_0 (PPG02_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. RTO03_0 (PPG02_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. RTO04_0 (PPG04_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. RTO05_0 (PPG04_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. IGTRG_0 PPG IGBT mode external trigger input pin 32 L7 24 - IGTRG_1 76 C4 60 44 Quadrature Position/ Revolution Counter 0 AIN0_0 QPRC ch.0 AIN input pin AIN0_1 30 K6 22 - AIN0_2 2 C1 2 2 BIN0_0 QPRC ch.0 BIN input pin BIN0_1 31 J6 23 - BIN0_2 3 C2 3 3 ZIN0_0 QPRC ch.0 ZIN input pin ZIN0_1 32 L7 24 - ZIN0_2 4 B3 4 4 Quadrature Position/ Revolution Counter 1 AIN1_1 QPRC ch.1 AIN input pin 60 C10 - - AIN1_2 33 K7 25 - BIN1_1 QPRC ch.1 BIN input pin 59 C11 - - BIN1_2 34 J7 26 - ZIN1_1 QPRC ch.1 ZIN input pin 58 D9 - - ZIN1_2 35 K8 27 - Real-time clock RTCCO_0 0.5 seconds pulse output pin of Real-time clock 72 A6 57 42 RTCCO_2 14 H1 10 6 SUBOUT_0 Sub clock output pin 72 A6 57 42 SUBOUT_2 14 H1 10 6

Document Number: 002-05655 Rev. *D Page 30 of 101 MB9B120M Series Pin function Pin name Function description Pin No LQFP-80 BGA-96 LQFP-64 QFN-64 LQFP-48 QFN-48 Low-Power Consumption Mode WKUP0 Deep standby mode return signal input pin 0 72 A6 57 42 WKUP1 Deep standby mode return signal input pin 1 43 J10 35 26 WKUP2 Deep standby mode return signal input pin 2 59 C11 48 36 WKUP3 Deep standby mode return signal input pin 3 76 C4 60 44 DAC DA0 D/A converter ch.0 analog output pin 30 K6 22 18 DA1 D/A converter ch.1 analog output pin 31 J6 23 19 Reset INITX External Reset Input pin. A reset is valid when INITX="L". 28 K4 21 17 Mode MD0 Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input.

37 L8 29 21

Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. Power VCC Power supply Pin 1 B1 1 1 VCC Power supply Pin 25 K1 18 14 VCC Power supply Pin 41 K11 33 - VCC Power supply Pin 77 A4 61 45 GND VSS GND Pin - F1 - - VSS GND Pin - F2 - - VSS GND Pin - F3 - - VSS GND Pin - B2 - - VSS GND Pin 20 L1 16 12 VSS GND Pin - K2 - - VSS GND Pin - J3 - - VSS GND Pin - L6 - - VSS GND Pin 24 L4 - - VSS GND Pin 40 L11 32 24 VSS GND Pin - K10 - - VSS GND Pin - J9 - - VSS GND Pin - B10 - - VSS GND Pin - C9 - - VSS GND Pin - D11 - - VSS GND Pin - A11 - - VSS GND Pin - A7 - - VSS GND Pin - C3 - - VSS GND Pin - A5 - - VSS GND Pin 80 A1 64 48 Clock X0 Main clock (oscillation) input pin 38 L9 30 22 X0A Sub clock (oscillation) input pin 26 L3 19 15 X1 Main clock (oscillation) I/O pin 39 L10 31 23 X1A Sub clock (oscillation) I/O pin 27 K3 20 16 CROUT_0 Built-in high-speed CR-osc clock output port 60 C10 - - CROUT_1 72 A6 57 42 Analog Power AVCC A/D converter and D/A converter analog power supply pin 50 H11 41 31 AVRH A/D converter analog reference voltage input pin 51 F11 42 32 Analog GND AVSS A/D converter and D/A converter GND pin 45 H10 37 28 AVRL A/D converter analog reference voltage input pin 52 G11 43 33 C pin C Power supply stabilization capacity pin 23 L2 17 13 Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller.

Document Number: 002-05655 Rev. *D Page 31 of 101 MB9B120M Series 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected.

• Oscillation feedback resistor : Approximately 1 MΩ
• With Standby mode control When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA P-ch P-ch N-ch R R P-ch P-ch N-ch X0A X1A Pull-up resistor Feedback resistor Pull-up resistor Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control

Document Number: 002-05655 Rev. *D Page 32 of 101 MB9B120M Series Type Circuit Remarks B

• CMOS level hysteresis input
• Pull-up resistor : Approximately 50 kΩ C
• Open drain output
• CMOS level hysteresis input N-ch Pull-up resistor Digital input Digital input Digital output

Document Number: 002-05655 Rev. *D Page 33 of 101 MB9B120M Series Type Circuit Remarks D It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected.

• Oscillation feedback resistor : Approximately 5 MΩ
• With Standby mode control When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA P-ch P-ch N-ch R R P-ch P-ch N-ch X0A X1A Pull-up resistor Feedback resistor Pull-up resistor Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control

Document Number: 002-05655 Rev. *D Page 34 of 101 MB9B120M Series Type Circuit Remarks E

• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off
• +B input is available F
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off
• +B input is available P-chP-ch N-ch R P-chP-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control

Document Number: 002-05655 Rev. *D Page 35 of 101 MB9B120M Series Type Circuit Remarks G

• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -12 mA, IOL= 12 mA
• +B input is available H
• CMOS level output
• CMOS level hysteresis input
• With standby mode control
• IOH = -18 mA, IOL = 16.5 mA P-chP-ch N-ch R P-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Digital input Standby mode control

Document Number: 002-05655 Rev. *D Page 36 of 101 MB9B120M Series Type Circuit Remarks I

• CMOS level output
• CMOS level hysteresis input
• 5 V tolerant
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• Available to control PZR registers.
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off J
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• 5 V tolerant
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH= -4 mA, IOL= 4 mA
• Available to control PZR registers.
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off K
• CMOS level hysteresis input P-chP-ch N-ch R P-chP-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control Mode input

Document Number: 002-05655 Rev. *D Page 37 of 101 MB9B120M Series Type Circuit Remarks L P-chP-ch N-ch Analog output R Digital output Digital output Digital input Standby mode Control Pull-up resistor control

• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog output
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA

Document Number: 002-05655 Rev. *D Page 38 of 101 MB9B120M Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

6.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

Document Number: 002-05655 Rev. *D Page 39 of 101 MB9B120M Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

6.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress’ recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h

Document Number: 002-05655 Rev. *D Page 40 of 101 MB9B120M Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies.

6.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives.

Document Number: 002-05655 Rev. *D Page 41 of 101 MB9B120M Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin, between AVRH pin and AVRL pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.  Surface mount type Size : More than 3.2 mm × 1.5 mm Load capacitance : Approximately 6 pF to 7 pF  Lead type Load capacitance : Approximately 6 pF to 7 pF Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.

• Example of Using an External Clock Device X0(X0A) X1(PE3), X1A (P47) Can be used as general-purpose I/O ports. Set as External clock input

Document Number: 002-05655 Rev. *D Page 42 of 101 MB9B120M Series Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on: VCC →AVCC → AVRH Turning off: AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up function of 5 V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. Device C VSS CS GND

Document Number: 002-05655 Rev. *D Page 43 of 101 MB9B120M Series 8. Block Diagram MB9BF121K/L/M, F122K/L/M, F124K/L/M Cortex-M3 Core @72MHz(Max) Flash I/F Clock Reset Generator Dual-Timer WatchDog Timer (Hardware) DMAC 8ch. Watch Counter CSV External Interrupt Controller 16-pin + NMI Power-On Reset SRAM0 8/16 Kbytes SRAM1 8/16 Kbytes I D SysNVIC WatchDog Timer (Software) Security 12-bit A/D Converter TRSTX,TCK, TDI,TMS AVCC, AVSS, AVRH, AVRL ANxx TIOAx TIOBx C TDO SCKx SINx SOTx INTx NMIX P0x, P1x, PFx INITX MODE-Ctrl IRQ-Monitor MD0, MD1 Regulator CRC Accelerator ADTGx RTS4 CTS4 On-Chip Flash 64+32 Kbytes/ 128+32 Kbytes/ 256+32 Kbytes Multi-Function Serial I/F 8ch. (with FIFO ch.0/1/3/4) HW flow control(ch.4) GPIO PIN-Function-Ctrl LVD ROM Table SWJ-DP LVD Ctrl Base Timer 16-bit 8ch./ 32-bit 4ch. Real-Time Colck RTCCO_x, SUBOUT_x Deep Standby Ctrl WKUPx Unit 0 Unit 1 10-bit D/A Converter 2unitsDAx QPRC 2ch. AINx BINx ZINx Multi-function Timer 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. Waveform Generator 3ch. A/D Activation Compare 2ch. 16-bit PPG 3ch. IC0x DTTI0X RTO0x FRCKx IGTRG_x AHB-APB Bridge: APB0(Max 40MHz) AHB-AHB Bridge Multi-layer AHB (Max 72MHz) AHB-APB Bridge : APB1 (Max 40MHz) AHB-APB Bridge : APB2 (Max 40MHz) X0A PLL CLK CR 100kHz Source Clock CROUT Main Osc Sub Osc CR 4MHzX1A

Document Number: 002-05655 Rev. *D Page 44 of 101 MB9B120M Series 9. Memory Size See "Memory Size" in "Product Lineup" to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF 0xE010_0000 0xE000_0000 0x4006_1000 0x4006_0000 DMAC 0x4003_C000 0x4003_B000 RTC 0x7000_0000 0x4003_A000 Watch Counter 0x4003_9000 CRC 0x6000_0000 0x4003_8000 MFS 0x4003_6000 0x4400_0000 0x4003_5000 LVD/DS mode 0x4003_4000 Reserved 0x4200_0000 0x4003_3000 GPIO 0x4003_2000 Reserved 0x4000_0000 0x4003_1000 Int-Req.Read 0x4003_0000 EXTI 0x2400_0000 0x4002_F000 Reserved 0x4002_E000 CR Trim 0x2200_0000 0x4002_9000 Reserved 0x4002_8000 D/AC 0x2008_0000 0x4002_7000 A/DC 0x2000_0000 SRAM1 0x4002_6000 QPRC 0x1FF8_0000 SRAM0 0x4002_5000 Base Timer 0x4002_4000 PPG 0x0020_8000 0x0020_0000 Flash(Work area) 0x0010_4000 Reserved 0x4002_1000 0x0010_0000 Security/CR Trim 0x4002_0000 MFT unit0 0x4001_6000 0x4001_5000 Dual Timer 0x4001_3000 0x0000_0000 0x4001_2000 SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 Flash I/F See " Memory Map (2)" for the memory size details. 32Mbytes Bit band alias Reserved Reserved Reserved Reserved Cortex-M3 Private Peripherals 32Mbytes Bit band alias Reserved Reserved ReservedReserved Peripherals Reserved Reserved Reserved Reserved Reserved External Device Area Flash(Main area)

Document Number: 002-05655 Rev. *D Page 45 of 101 MB9B120M Series Memory Map (2) Refer to the programming manual for the detail of Flash main area.  MB9AB40N/A40N/340N/140N/150R,MB9B520M/320M/120M Series Flash Programming Manual MB9BF124K/L/M MB9BF122K/L/M MB9BF121K/L/M 0x2008_0000 0x2008_0000 0x2008_0000 0x2000_4000 0x2000_2000 0x2000_2000 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFF_E000 0x1FFF_E000 0x1FFF_C000 0x0020_8000 0x0020_8000 0x0020_8000 SA7(8KB) SA7(8KB) SA7(8KB) SA6(8KB) SA6(8KB) SA6(8KB) SA5(8KB) SA5(8KB) SA5(8KB) 0x0020_0000 SA4(8KB) 0x0020_0000 SA4(8KB) 0x0020_0000 SA4(8KB) 0x0010_4000 0x0010_4000 0x0010_4000 0x0010_2000 CR trimming 0x0010_2000 CR trimming 0x0010_2000 CR trimming 0x0010_0000 Security 0x0010_0000 Security 0x0010_0000 Security 0x0004_0000 0x0002_0000 0x0001_0000 SA3(8KB) SA3(8KB) SA3(8KB) 0x0000_0000 SA2(8KB) 0x0000_0000 SA2(8KB) 0x0000_0000 SA2(8KB) Flash(Main area) 64Kbytes SA8(48KB) SA8(48KB) SA8(48KB) Reserved ReservedSA11(64KB) Flash(Main area) 256KbytesSA10(64KB) SA9(64KB) SA9(64KB) Flash(Main area) 128Kbytes Flash(Work area) 32Kbytes Reserved Reserved Reserved Reserved SRAM1 8Kbytes SRAM1 8Kbytes SRAM0 8Kbytes SRAM0 8Kbytes Reserved Reserved Flash(Work area) 32Kbytes SRAM0 16Kbytes SRAM1 16Kbytes Reserved Reserved Reserved Flash(Work area) 32Kbytes Reserved

Document Number: 002-05655 Rev. *D Page 46 of 101 MB9B120M Series Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB Flash Memory I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF APB1 Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter (QPRC) 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_8FFF D/A Converter 0x4002_9000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Register 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4005_FFFF AHB Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x41FF_FFFF Reserved

Document Number: 002-05655 Rev. *D Page 47 of 101 MB9B120M Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the "L" level.  INITX=1 This is the period when the INITX pin is the "H" level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "0".  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to "1".  Input enabled Indicates that the input function can be used.  Internal input fixed at "0" This is the status that the input function cannot be used. Internal input is fixed at "L".  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port.

Document Number: 002-05655 Rev. *D Page 48 of 101 MB9B120M Series List of Pin Status Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Main crystal oscillator output pin Hi-Z / Internal input fixed at "0"/ or Input enable Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*1, Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*1, Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*1, Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*1, Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*1, Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*1, Hi-Z / Internal input fixed at "0" C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled

Document Number: 002-05655 Rev. *D Page 49 of 101 MB9B120M Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - E Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled GPIO selected F GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled G GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Hi-Z / Internal input fixed at "0" Maintain previous state Sub crystal oscillator output pin Hi-Z / Internal input fixed at "0"/ or Input enable Hi-Z / Internal input fixed at "0" Hi-Z / Internal input fixed at "0" Maintain previous state Maintain previous state/ When oscillation stops*2, Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*2, Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*2, Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*2, Hi-Z / Internal input fixed at "0" Maintain previous state/ When oscillation stops*2, Hi-Z / Internal input fixed at "0" H External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at "0"

Document Number: 002-05655 Rev. *D Page 50 of 101 MB9B120M Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable ‐ INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 ‐ ‐ ‐ ‐ SPL = 0 SPL = 1 SPL = 0 SPL = 1 - I Analog input selected Hi-Z Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input disabled Hi-Z / Internal input fixed at "0" / Analog input disabled Hi-Z / Internal input fixed at "0" / Analog input disabled NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at "0" GPIO selected Maintain previous state J JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected K Resource selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected GPIO selected L Analog output selected Setting disabled Setting disabled Setting disabled Maintain previous state *3 *4 GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected External interrupt enabled selected Maintain previous state Maintain previous state Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at "0" GPIO selected

Document Number: 002-05655 Rev. *D Page 51 of 101 MB9B120M Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state Timer mode, RTC mode, or STOP mode state Deep standby RTC mode or Deep standby STOP mode state Return from Deep standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable ‐ INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 ‐ ‐ ‐ ‐ SPL = 0 SPL = 1 SPL = 0 SPL = 1 - M Analog input selected Hi-Z Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected GPIO selected N Analog input selected Hi-Z Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled Hi-Z / Internal input fixed at "0" / Analog input enabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at "0" Hi-Z / Internal input fixed at "0" GPIO selected Resource other than above selected Hi-Z / Internal input fixed at "0" GPIO selected *1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Oscillation is stopped at Stop mode and Deep Standby Stop mode. *3: Maintain previous state at Timer mode. GPIO selected Internal input fixed at "0" at RTC mode, Stop mode. *4: Maintain previous state at Timer mode. Hi-Z/Internal input fixed at "0" at RTC mode, Stop mode.

Document Number: 002-05655 Rev. *D Page 52 of 101 MB9B120M Series 12. Electrical Characteristics

12.1 Absolute Maximum Ratings

Parameter Symbol Rating Unit Remarks Min Max Power supply voltage *1, *2 VCC VSS - 0.5 VSS + 6.5 V Analog power supply voltage *1, *3 AVCC VSS - 0.5 VSS + 6.5 V Analog reference voltage *1, *3 AVRH VSS - 0.5 VSS + 6.5 V Input voltage *1 VI VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V VSS - 0.5 VSS + 6.5 V 5V tolerant Analog pin input voltage *1 VIA VSS - 0.5 AVCC + 0.5 (≤ 6.5 V) V Output voltage *1 VO VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V Clamp maximum current ICLAMP -2 +2 mA *7 Clamp total maximum current ∑ [ICLAMP] +20 mA *7 "L" level maximum output current *4 IOL - 10 mA 4mA type 20 mA 12mA type 39 mA P80/P81 pin "L" level average output current *5 IOLAV - 4 mA 4mA type 12 mA 12mA type 16.5 mA P80/P81 pin "L" level total maximum output current ∑IOL - 100 mA "L" level total maximum output current *8 ∑IOLAV - 50 mA "H" level maximum output current *6 IOH - - 10 mA 4mA type - 20 mA 12mA type - 39 mA P80/P81 pin "H" level average output current *7 IOHAV - - 4 mA 4mA type - 12 mA 12mA type - 18 mA P80/P81 pin "H" level total maximum output current ∑IOH - - 100 mA "H" level total average output current *8 ∑IOHAV - - 50 mA Power consumption PD - 300 mW Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that VSS = AVSS = 0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms period.

Document Number: 002-05655 Rev. *D Page 53 of 101 MB9B120M Series *7:

• See "List of Pin Functions" and "I/O Circuit Type" about +B input available pin.
• Use within recommended operating conditions.
• Use at DC voltage (current) the +B input.
• The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass through the protective diode and increase the potential at the VCC and AVCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit). WARNING: − Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. R +B input (0V to 16V) P-ch VCC VCC Limiting resistor N-ch AVCC Analog input Digital input Digital output Protection Diode

Document Number: 002-05655 Rev. *D Page 54 of 101 MB9B120M Series

12.2 Recommended Operating Conditions

(VSS = AVSS = AVRL = 0.0V) Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage VCC - 2.7*2 5.5 V Analog power supply voltage AVCC - 2.7 5.5 V AVCC=VCC Analog reference voltage AVRH - 2.7 AVCC V AVRL AVSS AVSS V Smoothing capacitor CS - 1 10 μF For Regulator*1 Operating temperature TA - - 40 + 105 °C *1: See "C Pin" in "Handling Devices" for the connection of the smoothing capacitor. *2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate only. WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.

Document Number: 002-05655 Rev. *D Page 55 of 101 MB9B120M Series

12.3 DC Characteristics

12.3.1 Current Rating

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Run mode current ICC VCC PLL Run mode CPU: 72 MHz, Peripheral: 36 MHz 32.5 41 mA *1, *5 CPU:72 MHz, Peripheral clock stops NOP operation 18 23 mA *1, *5 High-speed CR Run mode CPU/ Peripheral: 4 MHz*2 2.5 3.4 mA *1 Sub Run mode CPU/ Peripheral: 32 kHz 110 980 µA *1, *6 Low-speed CR Run mode CPU/ Peripheral: 100 kHz 130 1030 µA *1 Sleep mode current ICCS PLL Sleep mode Peripheral: 36 MHz 22 28 mA *1, *5 High-speed CR Sleep mode Peripheral: 4 MHz*2 1.6 2.6 mA *1 Sub Sleep mode Peripheral: 32 kHz 96 955 µA *1, *6 Low-speed CR Sleep mode Peripheral: 100 kHz 115 975 µA *1 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=5.5 V *4: TA=+105°C, VCC=5.5 V *5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)

Document Number: 002-05655 Rev. *D Page 56 of 101 MB9B120M Series (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ*2 Max*2 Timer mode current ICCT VCC Main Timer mode TA = + 25°C, When LVD is off 4.1 4.8 mA *1, *4 TA = + 105°C, When LVD is off - 5.4 mA *1, *4 ICCT Sub Timer mode TA = + 25°C, When LVD is off 17 66 μA *1, *5 TA = + 105°C, When LVD is off - 835 μA *1, *5 RTC mode current ICCR RTC mode TA = + 25°C, When LVD is off 15 61 μA *1, *5 TA = + 105°C, When LVD is off - 680 μA *1, *5 Stop mode current ICCH Stop mode TA = + 25°C, When LVD is off 14 53 μA *1 TA = + 105°C, When LVD is off - 600 μA *1 Deep Standby mode current ICCRD Deep Standby RTC mode TA = + 25°C, When LVD is off, When RAM is off TA = + 25°C, When LVD is off, When RAM is on TA = + 105°C, When LVD is off, When RAM is off - 155 μA *1, *3, *5 TA = + 105°C, When LVD is off, When RAM is on 215 μA *1, *3, *5 ICCHD Deep Standby Stop mode TA = + 25°C, When LVD is off, When RAM is off 1.6 9.6 μA *1, *3 TA = + 25°C, When LVD is off, When RAM is on 5.6 22 μA *1, *3 TA = + 105°C, When LVD is off, When RAM is off - 150 μA *1, *3 TA = + 105°C, When LVD is off, When RAM is on 210 μA *1, *3 *1: When all ports are fixed. *2: VCC=5.5 V *3: RAM on/off setting is on-chip SRAM only. *4: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) *5: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)

Document Number: 002-05655 Rev. *D Page 57 of 101 MB9B120M Series Low-Voltage Detection Current (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Low-voltage detection circuit (LVD) power supply current ICCLVD VCC At operation for reset Vcc = 5.5 V 0.13 0.3 μA At not detect At operation for interrupt Vcc = 5.5 V 0.13 0.3 μA At not detect Flash Memory Current (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Flash memory write/erase current ICCFLASH VCC At Write/Erase 9.5 11.2 mA * *: The current at which to write or erase Flash memory, "ICCFLASH" is added to "ICC". A/D Converter Current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Power supply current ICCAD AVCC At 1unit operation 0.69 0.90 mA At stop 0.25 25.84 μA Reference power supply current ICCAVRH AVRH At 1unit operation AVRH=5.5 V 1.1 1.97 mA At stop 0.2 3.4 μA D/A Converter Current (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Power supply current*1 IDDA*2 AVCC At 1unit operation AVCC=3.3 V 250 315 380 μA At 1unit operation AVCC=5.0 V 380 475 580 μA IDSA At stop - - 16 μA *1: No-load *2: Generates the max current by the CODE about 0x200

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12.3.2 Pin Characteristics

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max H level input voltage (hysteresis input) VIHS CMOS hysteresis input pin, MD0, MD1 - VCC × 0.8 - VCC + 0.3 V 5V tolerant input pin - VCC × 0.8 - VSS + 5.5 V L level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0, MD1 - VSS - 0.3 - VCC × 0.2 V

5 V tolerant

input pin - VSS - 0.3 - VCC × 0.2 V H level output voltage VOH 4 mA type VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 2 mA 12 mA type VCC ≥ 4.5 V, IOH = - 12 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 8 mA P80, P81 VCC ≥ 4.5 V, IOH = - 18.0 mA VCC - 0.4 - VCC V VCC < 4.5 V, IOH = - 12.0 mA L level output voltage VOL 4 mA type VCC ≥ 4.5 V, IOL = 4 mA VSS - 0.4 V VCC < 4.5 V, IOL = 2 mA 12 mA type VCC ≥ 4.5 V, IOL = 12 mA VSS - 0.4 V VCC < 4.5 V, IOL = 8 mA P80, P81 VCC ≥ 4.5 V, IOL = 16.5 mA VSS - 0.4 V VCC < 4.5 V, IOL = 10.5 mA Input leak current IIL - - - 5 - + 5 μA Pull-up resistance value RPU Pull-up pin VCC ≥ 4.5 V 33 50 90 kΩ VCC < 4.5 V - - 180 Input capacitance CIN Other than VCC, VSS, AVCC, AVSS, AVRH, AVRL - - 5 15 pF

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12.4 AC Characteristics

12.4.1 Main Clock Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input frequency fCH X0, VCC ≥ 4.5 V 4 48 MHz When crystal oscillator is connected VCC < 4.5 V 4 20 VCC ≥ 4.5 V 4 48 MHz When using external clock VCC < 4.5 V 4 20 Input clock cycle tCYLH VCC ≥ 4.5 V 20.83 250 ns When using external clock VCC < 4.5 V 50 250 Input clock pulse width - PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock Input clock rising time and falling time tCF, tCR - - 5 ns When using external clock Internal operating clock frequency*1 fCM - - - 72 MHz Master clock fCC - - - 72 MHz Base clock (HCLK/FCLK) fCP0 - - - 40 MHz APB0 bus clock*2 fCP1 - - - 40 MHz APB1 bus clock*2 fCP2 - - - 40 MHz APB2 bus clock*2 Internal operating clock cycle time*1 tCYCC - - 13.8 - ns Base clock (HCLK/FCLK) tCYCP0 - - 25 - ns APB0 bus clock*2 tCYCP1 - - 25 - ns APB1 bus clock*2 tCYCP2 - - 25 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual". *2: For about each APB bus which each peripheral is connected to, see "Block Diagram" in this data sheet.

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12.4.2 Sub Clock Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Input frequency 1/ tCYLL X0A, X1A - - 32.768 - kHz When crystal oscillator is connected - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock *: See "Sub crystal oscillator" in "Handling Devices" for the crystal oscillator used.

12.4.3 Built-in CR Oscillation Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRH TA = + 25°C 3.92 4 4.08 MHz When trimming*1 TA = 0°C to + 85°C 3.9 4 4.1 TA = -40°C to + 105°C 3.88 4 4.12 TA = + 25°C VCC ≤ 3.6 V 3.94 4 4.06 TA = - 20°C to + 85°C VCC ≤ 3.6 V 3.92 4 4.08 TA = - 20°C to + 105°C VCC ≤ 3.6 V 3.9 4 4.1 TA = - 40°C to + 105°C 2.8 4 5.2 When not trimming Frequency stabilization time tCRWT - - - 30 μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value. This period is able to use high-speed CR clock as source clock. X0A

Document Number: 002-05655 Rev. *D Page 61 of 101 MB9B120M Series Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRL - 50 100 150 kHz

12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiplication rate - 5 - 37 multiplier PLL macro oscillation clock frequency fPLLO 75 - 150 MHz Main PLL clock frequency*2 fCLKPLL - - 72 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter: Clock" in "FM3 Family Peripheral Manual".

12.4.5 Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock

of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate - 19 - 35 multiplier PLL macro oscillation clock frequency fPLLO 72 - 150 MHz Main PLL clock frequency*2 fCLKPLL - - 72 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see "Chapter 2-1: Clock" in "FM3 Family Peripheral Manual". Note: − Make sure to input to the Main PLL source clock, the high-speed CR clock (CLKHC) that the frequency/temperature has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Main PLL connection

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12.4.6 Reset Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns

12.4.7 Power-on Reset Timing

(VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Power supply shut down time tOFF VCC - 1 - - ms *1 Power ramp rate dV/dt VCC: 0.2 V to 2.70 V 0.3 - 1000 mV/µs *2 Time until releasing Power-on reset tPRT - 1.34 - 18.6 ms *1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1 ms). Note: − If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12.4.6. Glossary

• VDH : detection voltage (when SVHR=00000) of Low-Voltage detection reset. See "12.8. Low-Voltage Detection Characteristics". VDH tPRT Internal RST VCC CPU Operation start RST Active release 0.2V 0.2V tOFF dV/dt0.2V 2.7V

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12.4.8 Base Timer Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - 2tCYCP - ns Trigger input timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see "Block Diagram" in this data sheet. tTIWH VIHS VIHS VILS VILS tTIWL tTRGH VIHS VIHS VILS VILS tTRGL ECK TIN TGIN

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12.4.9 CSIO/UART Timing

CSIO (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05655 Rev. *D Page 65 of 101 MB9B120M Series Master mode Slave mode tSLSH tSHSL VIH tF tR VIH VOH VIH VIL VIL VOL VIH VIL VIH VIL tSLOVE tIVSHE tSHIXE SCK SOT SIN tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI SCK SOT SIN

Document Number: 002-05655 Rev. *D Page 66 of 101 MB9B120M Series CSIO (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05655 Rev. *D Page 67 of 101 MB9B120M Series Master mode Slave mode tSHSL tSLSH VIH tF tR VIH VOH VIL VIL VIL VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSHOVE tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI SCK SOT SIN

Document Number: 002-05655 Rev. *D Page 68 of 101 MB9B120M Series CSIO (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK ↓→ SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓→ SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05655 Rev. *D Page 69 of 101 MB9B120M Series Master mode Slave mode *: Changes when writing to TDR register tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI SCK SOT SIN

Document Number: 002-05655 Rev. *D Page 70 of 101 MB9B120M Series CSIO (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see "Block Diagram" in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05655 Rev. *D Page 71 of 101 MB9B120M Series Master mode Slave mode UART external clock input (EXT = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Min Max Unit Remarks Serial clock L pulse width tSLSH CL = 30 pF tCYCP + 10 - ns Serial clock H pulse width tSHSL tCYCP + 10 - ns SCK falling time tF - 5 ns SCK rising time tR - 5 ns tSHSL VIL VIL VIL VIH VIH tR tF tSLSH SCK tSHSL tR tSLSH tF tSLOVE VIL VIL VIL VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI SCK SOT SIN

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12.4.10 External Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tINH, tINL ADTG - 2tCYCP*1 - ns A/D converter trigger input FRCKx Free-run timer input clock ICxx Input capture DTTIxX - 2tCYCP*1 - ns Waveform generator INTxx, NMIX *2 2tCYCP + 100*1 - ns External interrupt NMI *3 500 - ns WKUPx *4 500 - ns Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the A/D converter, Multi-function Timer, External interrupt are connected to, see "Block Diagram” in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in Stop mode, in RTL mode, in Timer mode. *4: When in Deep Standby RTC mode, in Deep Standby Stop mode.

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12.4.11 Quadrature Position/Revolution Counter timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Min Max AIN pin H width tAHL - 2tCYCP* - ns AIN pin L width tALL - BIN pin H width tBHL - BIN pin L width tBLL - BIN rising time from AIN pin H level tAUBU PC_Mode2 or PC_Mode3 AIN falling time from BIN pin H level tBUAD PC_Mode2 or PC_Mode3 BIN falling time from AIN pin L level tADBD PC_Mode2 or PC_Mode3 AIN rising time from BIN pin L level tBDAU PC_Mode2 or PC_Mode3 AIN rising time from BIN pin H level tBUAU PC_Mode2 or PC_Mode3 BIN falling time from AIN pin H level tAUBD PC_Mode2 or PC_Mode3 AIN falling time from BIN pin L level tBDAD PC_Mode2 or PC_Mode3 BIN rising time from AIN pin L level tADBU PC_Mode2 or PC_Mode3 ZIN pin H width tZHL QCR:CGSC=0 ZIN pin L width tZLL QCR:CGSC=0 AIN/BIN rise and falling time from determined ZIN level tZABE QCR:CGSC=1 Determined ZIN level from AIN/BIN rise and falling time tABEZ QCR:CGSC=1 *: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Quadrature Position/Revolution Counter is connected to, see "Block Diagram" in this data sheet. AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL

Document Number: 002-05655 Rev. *D Page 74 of 101 MB9B120M Series BIN tBUAU tAUBD tBDAD tADBU tBHL tBLL tAHL tALL AIN ZIN ZIN AIN/BIN

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12.4.12 I2C Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Standard- mode Fast- mode Unit Remarks Min Max Min Max SCL clock frequency fSCL CL = 30 pF, R = (VP/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCL clock L width tLOW 4.7 - 1.3 - μs SCL clock H width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between STOP condition and START condition tBUF 4.7 - 1.3 - μs Noise filter tSP - 2 tCYCP*4 - 2 tCYCP*4 - ns *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-speed mode I2C bus device can be used on a Standard mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see "Block Diagram" in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL

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12.4.13 JTAG Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max TMS, TDI setup time tJTAGS TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TMS, TDI hold time tJTAGH TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TDO delay time tJTAGD TCK, TDO VCC ≥ 4.5 V - 25 ns VCC < 4.5 V - 45 Note: − When the external load capacitance CL = 30 pF. TCK TMS/TDI TDO

Document Number: 002-05655 Rev. *D Page 77 of 101 MB9B120M Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - - ± 1.5 ± 4.5 LSB AVRH = 2.7 V to 5.5 V Differential Nonlinearity - - - ± 1.7 ± 2.5 LSB Zero transition voltage VZT ANxx - ± 10 ± 15 mV Full-scale transition voltage VFST ANxx - AVRH ± 5 AVRH ± 15 mV Conversion time - - 0.8*1 - - μs AVCC ≥ 4.5 V Sampling time*2 tS - 0.24 - 10 μs AVCC ≥ 4.5 V 0.3 - AVCC < 4.5 V Compare clock cycle*3 tCCK - 40 - 1000 ns AVCC ≥ 4.5 V 50 - AVCC < 4.5 V State transition time to operation permission tSTT - - - 1.0 μs Analog input capacity CAIN - - - 9.7 pF Analog input resistor RAIN - - - 1.7 kΩ AVCC ≥ 4.5 V 2.4 AVCC < 4.5 V Interchannel disparity - - - - 4 LSB Analog port input leak current - ANxx - - 5 μA Analog input voltage - ANxx AVRL - AVRH V Reference voltage - AVRH 2.7 - AVCC V - AVRL AVSS - AVSS V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 4.5 V, HCLK=50 MHz sampling time: 240 ns, compare time: 560 ns. AVCC < 4.5 V, HCLK=40 MHz sampling time: 300 ns, compare time: 700 ns Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting of the sampling time and compare clock cycle, see "Chapter 1-1: A/D Converter" in "FM3 Family Peripheral Manual Analog Macro Part". The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see "Block Diagram". The base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: A necessary sampling time changes by external impedance. Ensure that it sets the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2).

Document Number: 002-05655 Rev. *D Page 78 of 101 MB9B120M Series (Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: Sampling time CAIN: Input capacity of A/D = 9.7 pF at 2.7 V < AVCC < 5.5 V REXT: Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle CAIN Analog signal source ANxx Analog input pin Comparator REXT RAIN

Document Number: 002-05655 Rev. *D Page 79 of 101 MB9B120M Series Definition of 12-bit A/D Converter Terms  Resolution: Analog variation that is recognized by an A/D converter.  Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.  Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVRL AVRH AVRL AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T

Document Number: 002-05655 Rev. *D Page 80 of 101 MB9B120M Series 12.6 10-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - DAx - - 10 bit Conversion time tC20 0.47 0.58 0.69 μs Load 20 pF tC100 2.37 2.90 3.43 μs Load 100 pF Integral Nonlinearity*1 INL - 4.0 - + 4.0 LSB Differential Nonlinearity*1,*2 DNL - 0.9 - + 0.9 LSB Output Voltage offset VOFF - - 10.0 mV Code is 0x000 - 20.0 - + 5.4 mV Code is 0x3FF Analog output impedance RO 3.10 3.80 4.50 kΩ D/A operation 2.0 - - MΩ D/A stop Output undefined period tR - - 70 ns *1: No-load *2: Generates the max current by the CODE about 0x200

Document Number: 002-05655 Rev. *D Page 81 of 101 MB9B120M Series

12.7 Low-Voltage Detection Characteristics

12.7.1 Low-Voltage Detection Reset

(TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHR*1= 00000 2.25 2.45 2.65 V When voltage drops Released voltage VDH 2.30 2.50 2.70 V When voltage rises Detected voltage VDL SVHR*1= 00001 2.39 2.60 2.81 V When voltage drops Released voltage VDH 2.48 2.70 2.92 V When voltage rises Detected voltage VDL SVHR*1= 00010 2.48 2.70 2.92 V When voltage drops Released voltage VDH 2.58 2.80 3.02 V When voltage rises Detected voltage VDL SVHR*1= 00011 2.58 2.80 3.02 V When voltage drops Released voltage VDH 2.67 2.90 3.13 V When voltage rises Detected voltage VDL SVHR*1= 00100 2.76 3.00 3.24 V When voltage drops Released voltage VDH 2.85 3.10 3.35 V When voltage rises Detected voltage VDL SVHR*1= 00101 2.94 3.20 3.46 V When voltage drops Released voltage VDH 3.04 3.30 3.56 V When voltage rises Detected voltage VDL SVHR*1= 00110 3.31 3.60 3.89 V When voltage drops Released voltage VDH 3.40 3.70 4.00 V When voltage rises Detected voltage VDL SVHR*1= 00111 3.40 3.70 4.00 V When voltage drops Released voltage VDH 3.50 3.80 4.10 V When voltage rises Detected voltage VDL SVHR*1= 01000 3.68 4.00 4.32 V When voltage drops Released voltage VDH 3.77 4.10 4.43 V When voltage rises Detected voltage VDL SVHR*1= 01001 3.77 4.10 4.43 V When voltage drops Released voltage VDH 3.86 4.20 4.54 V When voltage rises Detected voltage VDL SVHR*1= 01010 3.86 4.20 4.54 V When voltage drops Released voltage VDH 3.96 4.30 4.64 V When voltage rises LVD stabilization wait time tLVDW - - - 8160 × tCYCP*2 μs LVD detection delay time tLVDDL - - - 200 μs *1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to "00000" by Low-Voltage Detection Reset. *2: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-05655 Rev. *D Page 82 of 101 MB9B120M Series

12.7.2 Interrupt of Low-Voltage Detection

(TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHI = 00011 2.58 2.80 3.02 V When voltage drops Released voltage VDH 2.67 2.90 3.13 V When voltage rises Detected voltage VDL SVHI = 00100 2.76 3.00 3.24 V When voltage drops Released voltage VDH 2.85 3.10 3.35 V When voltage rises Detected voltage VDL SVHI = 00101 2.94 3.20 3.46 V When voltage drops Released voltage VDH 3.04 3.30 3.56 V When voltage rises Detected voltage VDL SVHI = 00110 3.31 3.60 3.89 V When voltage drops Released voltage VDH 3.40 3.70 4.00 V When voltage rises Detected voltage VDL SVHI = 00111 3.40 3.70 4.00 V When voltage drops Released voltage VDH 3.50 3.80 4.10 V When voltage rises Detected voltage VDL SVHI = 01000 3.68 4.00 4.32 V When voltage drops Released voltage VDH 3.77 4.10 4.43 V When voltage rises Detected voltage VDL SVHI = 01001 3.77 4.10 4.43 V When voltage drops Released voltage VDH 3.86 4.20 4.54 V When voltage rises Detected voltage VDL SVHI = 01010 3.86 4.20 4.54 V When voltage drops Released voltage VDH 3.96 4.30 4.64 V When voltage rises LVD stabilization wait time tLVDW - - - 8160× tCYCP* μs LVD detection delay time tLVDDL - - - 200 μs *: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-05655 Rev. *D Page 83 of 101 MB9B120M Series

12.8 Flash Memory Write/Erase Characteristics

12.8.1 Write / Erase time

(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Value Unit Remarks Typ Max Sector erase time Large Sector 1.1 2.7 s Includes write time prior to internal erase Small Sector 0.3 0.9 Half word (16-bit) write time 16 310 μs Not including system-level overhead time Chip erase time 6.8 18 s Includes write time prior to internal erase *: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.

12.8.2 Write cycles and data hold time

Erase/write cycles (cycle) Data hold time (year) Remarks 1,000 20* 10,000 10* *: At average + 85C

Document Number: 002-05655 Rev. *D Page 84 of 101 MB9B120M Series

12.9 Return Time from Low-Power Consumption Mode

12.9.1 Return Factor: Interrupt/WKUP

The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tICNT tCYCC μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 40 80 μs Low-speed CR Timer mode 340 680 μs Sub Timer mode 680 860 μs RTC mode, Stop mode 268 503 μs Deep Standby RTC mode Deep Standby Stop mode 308 583 μs When RAM is off 268 503 μs When RAM is on *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.

Document Number: 002-05655 Rev. *D Page 85 of 101 MB9B120M Series Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual".

Document Number: 002-05655 Rev. *D Page 86 of 101 MB9B120M Series

12.9.2 Return Factor: Reset

The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tRCNT 148 263 μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 148 263 μs Low-speed CR Timer mode 248 463 μs Sub Timer mode 312 496 μs RTC mode, Stop mode 268 503 μs Deep Standby RTC mode Deep Standby Stop mode 308 583 μs When RAM is off 268 503 μs When RAM is on *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by INITX) INITX tRCNT Internal reset CPU Operation Start Reset active Release

Document Number: 002-05655 Rev. *D Page 87 of 101 MB9B120M Series Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset tRCNT Internal reset CPU Operation Start Reset active Release *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See "Chapter 6: Low Power Consumption Mode" and "Operations of Standby Modes" in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See "Chapter 6: Low Power Consumption Mode" in "FM3 Family Peripheral Manual". − The time during the power-on reset/low-voltage detection reset is excluded. See “12.4.7 Power-on Reset Timing in 12.4 AC Characteristics in 12. Electrical Characteristics” for the detail on the time during the power-on reset/low -voltage detection reset. − When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset.

Document Number: 002-05655 Rev. *D Page 88 of 101 MB9B120M Series 13. Ordering Information Part number On-chip Flash memory On-chip MB9BF121KQN-G-AVE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic・QFN (0.5 mm pitch), 48-pin (VNA048) Tray MB9BF122KQN-G-AVE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9BF124KQN-G-AVE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9BF121KPMC-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic・LQFP (0.5 mm pitch), 48-pin (LQA048) MB9BF122KPMC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9BF124KPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9BF121LQN-G-AVE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic・QFN (0.5 mm pitch), 64-pin (VNC064) MB9BF122LQN-G-AVE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9BF124LQN-G-AVE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9BF121LPMC1-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic・LQFP (0.5 mm pitch), 64-pin (LQD064) MB9BF122LPMC1-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9BF124LPMC1-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9BF121LPMC-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic・LQFP (0.65 mm pitch), 64-pin (LQG064) MB9BF122LPMC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9BF124LPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9BF121MPMC-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic・LQFP (0.5 mm pitch), 80-pin (LQH080) MB9BF122MPMC-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9BF124MPMC-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9BF121MPMC1-G-JNE2 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic・LQFP (0.65 mm pitch), 80-pin (LQJ080) MB9BF122MPMC1-G-JNE2 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9BF124MPMC1-G-JNE2 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte MB9BF121MBGL-GE1 Main: 64 Kbyte Work: 32 Kbyte 16 Kbyte Plastic・PFBGA (0.5 mm pitch), 96-pin (FDG096) Tray MB9BF122MBGL-GE1 Main: 128 Kbyte Work: 32 Kbyte 16 Kbyte MB9BF124MBGL-GE1 Main: 256 Kbyte Work: 32 Kbyte 32 Kbyte

Document Number: 002-05655 Rev. *D Page 89 of 101 MB9B120M Series 14. Package Dimensions Package Type Package Code LQFP 80 LQH080 DIMENSIONS MIN. NOM. MAX. 07.1A A1 0.05 0.15 b 0.15 0.27 c 0.09 0.20 D 14.00 BSC. D1 12.00 BSC. e 0.50 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70 14.00 BSC. 12.00 BSC. SYMBOL BOTTOM VIEW A A10.25 D e b D

0.20 C A-B D

0.10 C A-B D

0.08 C A-B D

E 5 7 752 10 b SECTION A-A' SEATING PLANE 0.08 C A L SIDE VIEW TOP VIEW 1406 0614 120 PACKAGE OUTLINE, 80 LEAD LQFP 12.0X12.0X1.7 MM LQH080 Rev 002-11501

Document Number: 002-05655 Rev. *D Page 90 of 101 MB9B120M Series Package Type Package Code LQFP 80 LQJ080 DIMENSIONS SYMBOL MIN. NOM. MAX. A 1.70 A1 0.00 0.20 b 0.16 0.38 c 0.09 0.20 D 16.00 BSC D1 14.00 BSC e 0.65 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70

16.00 BSC

14.00 BSC

0.32 D e 021 EE1 5 7 b A SEATING PLANE A A10.25 10 b SECTION A-A' c L 0.10 C ddd C A-B D 4160 0614 14.0X14.0X1.7 MM LQJ080 REV PACKAGE OUTLINE, 80 LEAD LQFP 002-14043

Document Number: 002-05655 Rev. *D Page 91 of 101 MB9B120M Series Package Type Package Code LQFP 64 LQD064 DIMENSIONS SYMBOL MIN. NOM. MAX. 07.1A A1 0.00 0.20 b 0.15 0.2 c 0.09 0.20 D 12.00 BSC. D1 10.00 BSC. e 0.50 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70 12.00 BSC. 10.00 BSC. D e 1 16 5 7 E b A A10.25 b SECTION A-A' L1 L A SEATING PLANE 0.08 C SIDE VIEW TOP VIEW BOTTOM VIEW 3348 116 33 48 PACKAGE OUTLINE, 64 LEAD LQFP 10.0X10.0X1.7 MM LQD064 Rev 002-11499

Document Number: 002-05655 Rev. *D Page 92 of 101 MB9B120M Series Package Type Package Code LQFP 64 LQG064 DIMENSION SYMBOL MIN. NOM. MAX. A 1.70 A1 0.00 0.20 b 0.27 0.32 0.37 c 0.09 0.20 D 14.00 BSC D1 12.00 BSC e 0.65 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70

12.00 BSC

D e 1 16 EE1 5 7 b

0.13 C A-B D 8

0.10 C A SEATI NG PLA NE b SECTION A -A' c A A10.25 10L1 L SIDE VIEW TOP VIEW BOTTOM VIEW 3348 116 8433 12.0X12.0X1.7 MM LQG064 REV PACKAGE OUTLINE, 64 LEAD LQFP 002-13881

Document Number: 002-05655 Rev. *D Page 93 of 101 MB9B120M Series Package Type Package Code QFN 64 VNC064 DIMENSIONS NOM.MIN. b E

6.00 BSC

9.00 BSC

D A 0.00 SYMBOL MAX. 0.90 0.05

0.50 BSC

L 0.35 0.450.40 0.20 0.25 0.30 E 2 6.00 BSC e N 64

0.20 REFR

BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE. MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED N IS THE TOTAL NUMBER OF TERMINALS. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. NOTES: MAX. PACKAGE WARPAGE IS 0.05mm. HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA. ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE OR E SIDE. SINK SLUG AS WELL AS THE TERMINALS. BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL SIDE VIEW BOTTOM VIEWTOP VIEW D A E B 0.10 C 0.10 C 0.10 CA 0.05 C C SEATINGPLANE

0.10 C A B

0.05 C (ND-1) e INDEXMARK L 8433 PACKAGE OUTLINE, 64 LEAD QFN 002-13234 **

Document Number: 002-05655 Rev. *D Page 94 of 101 MB9B120M Series Package Type Package Code LQFP 48 LQA048 DIMENSIONS SYMBOL MIN. NOM. MAX. A 1.70 A1 0.00 0.20 b 0.15 0.27 c 0.09 0.20 D 9.00 BSC D1 7.00 BSC e 0.50 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70

7.00 BSC

D e 1 12 EE1 5 7 b

0.80 C A-B D

A SEATING PLANE A A10.25 b SECTION A-A' c L 0.80 C 4813 36 25 25 36 7.0X7.0X1.7 MM LQA048 REV PACKAGE OUTLINE, 48 LEAD LQFP 002-13731

Document Number: 002-05655 Rev. *D Page 95 of 101 MB9B120M Series Package Type Package Code QFN 48 VNA048 DIMENSIONS NOM.MIN. b E

5.50 BSC

D A 0.00 SYMBOL MAX. 0.90 0.05 2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL.THE DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE. 6. MAX. PACKAGE WARPAGE IS 0.05mm. 1. ALL DIMENSIONS ARE IN MILLIMETERS. L 0.20 0.25 0.30 E 2 5.50 BSC e R 0.20 REF 7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS. 8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT SINK SLUG AS WELL AS THE TERMINALS. 0.400.35 0.45 NOTE 10. JEDEC SPEC IFICATIONNO . REF : N/A SIDE VIEW BOTTOM VIEW TOP VIEW D A E B 0.10 C 0.10 C 0.10 CA 0.05 C C SEATING PLANE e b 0.10 C A B 0.05 C R (ND-1) e INDEX MARK L 9 12 3625 PACKAGE OUTLINE, 48 LEAD QFN 002-15528 **

Document Number: 002-05655 Rev. *D Page 96 of 101 MB9B120M Series Package Type Package Code FBGA 96 FDG096 N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. "SD" AND "SE" ARE MEASUREDWITH RESPECT TO DATUMS A AND B AND SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. "e" REPRESENTSTHE SOLDER BALL GRID PITCH. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A SOLDER BALL POSITION DESIGNATIO N PER JEP95, SECTION 3, SPP-020. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. SD b eE eD ME N 0.20 0.00 0.30 0.40 DIMENSIONS MD E D A SYMBOL 0.15 MIN.

5.00 BSC

NOM. - 1.30 0.35 MAX. SE 0.00 0.25 METALIZED MARK, INDENTATION OR OTHER MEANS. "SD" = eD/2 AND "SE" = eE/2. PLANE PARALLEL TO DATUM C. "SD" OR "SE" = 0. SIZE MD X ME. BALLS. A 0.20 C B 0.20 C INDEX MARKPIN A1 CORNER 7 ABCDEFGHJKL 96xφb

0.05 C A B

0.20 C

0.08 C C

6.0X6.0X1.3 MM FDG096 REV PACKAGE OUTLINE, 96 BALL FBGA 002-13224

Document Number: 002-05655 Rev. *D Page 97 of 101 MB9B120M Series 15. Major Changes Spansion Publication Number: DS706-00050 Page Section Change Results Revision 1.0 - - Preliminary → Data Sheet

3 FEATURES

A/D Converter (Max 26channels) Revised the conversion time: 1.0μs → 0.8μs 5 Unique ID Added the "Unique ID".

6 PRODUCT LINEUP

Function Added the "Unique ID". 15 to 17 LIST OF PIN FUNCTIONS List of pin numbers Corrected the I/O circuit type. Corrected the Pin state type. 32 List of pin functions Corrected the Pin function. 38 I/O CIRCUIT TYPE Added the "Type: L". BLOCK DIAGRAM Corrected the figure. - TIOA: input → input/output - TIOB: output → input

54 ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings Revised the value of "TBD". 55 2. Recommended Operating Conditions Revised the Condition of "Operating temperature". 56, 57 3. DC Characteristics (1) Current Rating Revised the value of "TBD". Added "Flash memory write/erase current". 60 4. AC Characteristics (3) Built-in CR Oscillation Characteristics Revised the Condition. Revised the footnote. (4-2) Operating Conditions of Main PLL (In the case of using built-in high-speed CR for input clock of main PLL) Revised the value of "TBD". 5. 12-bit A/D Converter Electrical characteristics for the A/D converter Deleted "(Preliminary value)". Revised the conversion time. Min: 1.0μs → 0.8μs Revised the value of "Compare clock cycle (AVCC ≥ 4.5V)". Min: 50ns → 40ns Revised the footnote. 80 6. 10-bit D/A Converter Deleted "(Preliminary value)". 81 7. Low-Voltage Detection Characteristics Revised the value of "TBD". 8. MainFlash Memory Write/Erase Characteristics Revised the value of "TBD". Revised the value of "Sector erase time". - Large Sector Typ: 1.065s → 1.1s - Small Sector Typ: 0.606s → 0.3s Revised the value of "Chip erase time". Typ: 9.11s → 6.8s Deleted "(targeted value)". Revision 1.1 - - Company name and layout design change Revision 2.0

On-chip Memories [Flash memory] Revised the features of Dual operation Flash memory Multi-function Serial Interface [I2C] Corrected the mode. High speed mode → Fast mode 3 General-Purpose I/O Port Revised the features of 5V tolerant I/O. 4 Multi-function Timer Corrected the number of A/D activating compare channels. 3ch. → 2ch. Corrected the number of A/D activating compare channels. 3ch. → 2ch. Revised Built-in CR. High-speed: 4MHz(± 2%) → 4MHz Low-speed: 100kHz(Typ) → 100kHz 7 Revised the footnote.

Document Number: 002-05655 Rev. *D Page 98 of 101 MB9B120M Series Page Section Change Results

20 LIST OF PIN FUNCTIONS

List of pin numbers Corrected the pin number of ZIN1_1. List of pin functions Corrected the pin number of ADTG_2. 28 Corrected pin numbers of SIN0_1 and SOT0_1. 30 Corrected the pin number of DTTI0X_2.

36 I/O CIRCUIT TYPE TYPE H :

Revised the value of "TBD".

43 HANDLING DEVICES

Sub crystal oscillator Added the descriptions. 46 BLOCK DIAGRAM Corrected the figure. -A/D Activation Compare: 3ch → 2ch

48 MEMORY MAP

Memory Map (2) Added the explanatory note.

53 PIN STATUS IN EACH CPU STATE

List of Pin Status Added the pin function of selected Analog output about type L. 54 Corrected the footnote. Sub CR timer→ Low-speed CR timer

56 ELECTRICAL CHARACTERISTICS

1. Recommended Operating Conditions Added the note and footnote. Corrected the value of Analog reference voltage “AVRH”. Min.: AVss → 2.7 57 3. DC Characteristics (1) Current Rating Added notes and footnotes. Added the remarks of Icc. Added the frequency of main clock crystal oscillator in remarks. 61 4. AC Characteristics (2) Sub clock input Characteristics Added the footnote. 62 (3) Built-in CR Oscillation Characteristics

• Built-in High-speed CR Added "Frequency stabilization time" Added notes and footnotes. 64 (6) Power-on Reset Timing Added "Timing until releasing Power-on reset" Added the timing chart (8) CSIO Timing Corrected the title. UART Timing → CSIO Timing Corrected the footnote. UART → Multi-function serial 68,70,72 Corrected the footnote. UART → Multi-function serial 77 (11) I2C Timing Revised the Condition. Revised the footnote. 79 5. 12-bit A/D Converter Electrical characteristics for the A/D converter Changed the name of parameter.
• Non Linearity error → Integral Nonlinearity
• Differential linearity error → Differential Nonlinearity Changed the Symbol. Of Zero transition voltage. VoT → VZT Changed the pin name. AN00 to AN26 → ANxx Corrected the value of V0T, VFST , Ts, Tstt, and reference voltage. Revised footnotes. 80 Change the figure. AN00 to AN26 → ANxx

81 Definition of 12-bit A/D Converter Terms

• Linearity error → Integral Nonlinearity
• Differential linearity error → Differential Nonlinearity V0T → VZT 82 6. 10-bit D/A Converter Electrical characteristics for the D/A converter Revised the remark of IDDA. D/A operation → D/A 1unit operation Changed the name of parameter.
• Linearity error → Integral Nonlinearity
• Differential linearity error → Differential Nonlinearity 83 7. Low-Voltage Detection Characteristics (1) Low-Voltage Detection Reset Corrected the condition and the value. Added the note and the footnote. Added “LVD detection delay time”. 84 (2) Interrupt of Low-Voltage Detection Corrected the condition and the value. Added “LVD detection delay time”.

Document Number: 002-05655 Rev. *D Page 99 of 101 MB9B120M Series Page Section Change Results 85 8. Flash Memory Write/Erase Characteristics Changed the title of Chapter. Main Flash Memory Write/Erase Characteristics → Flash Memory Write/Erase Characteristics 86 9. Return Time Low-Power Consumption Mode Added the Chapter “Return Time from Low-Power Consumption Mode”. Revision 3.0

2 Features

USB Interface Added the description of PLL for USB 35, 36 I/O Circuit Type Added about +B input Memory map(2) Added the summary of Flash memory sector and the note

52 PIN STATUS IN EACH CPU STAE

List of Pin Status Changed the pin status of I-type 1. Absolute Maximum Ratings Added the Clamp maximum current Added about +B input 58-60

Electrical Characteristics

1. DC Characteristics (1) Current rating Changed the table format Added Main TIMER mode current Moved A/D Converter Current Moved D/A Converter Current
2. AC Characteristics (4-1) Operating Conditions of Main PLL (4-2) Operating Conditions of Main PLL

• Added the figure of Main PLL connection 68-75

1. AC Characteristics (7) CSIO/UART Timing

• Modified from UART Timing to CSIO/UART Timing
• Changed from Internal shift clock operation to Master mode
• Changed from External shift clock operation to Slave mode

1. AC Characteristics (9) External Input Timing Added input pulse width of WKUPx pin 5. 12bit A/D Converter

• Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage
• Added Conversion time at AVcc < 4.5V NOTE: Please see “Document History” about later revised information.

Document Number: 002-05655 Rev. *D Page 100 of 101 MB9B120M Series Document History Document Title: MB9B120M Series 32-bit Arm® Cortex®-M3 FM3 Microcontroller Document Number: 002-05655 Revision ECN Orig. of Change Submission Date Description of Change ** - TOYO 03/18/2015 Migrated to Cypress and assigned document number 002-05655. No change to document contents or format. *A 5171443 TOYO 03/18/2016 Updated to Cypress format. *B 5653470 HTER 03/09/2017 ・ Modified RTC description in “Features, Real-Time Clock(RTC)”. Changed starting count value from 01 to 00. Deleted “second , or day of the week” in the Interrupt function. (Page 3) ・ Updated Package code and dimensions as follows (Page 8-14, 88-96) - FPT-48P-M49 -> LQA048 - LCC-48P-M73 -> VNA048 - FPT-64P-M38 -> LQD064 - FPT-64P-M39 -> LQG064 - LCC-64P-M24 -> VNC064 - FPT-80P-M37 -> LQH080 - FPT-80P-M40 -> LQJ080 - BGA-96P-M07 -> FDG096 ・ Added Notes for JTAG. (Page 30) ・ Updated “12.4.7 Power-On Reset Timing”. Changed parameter from “Power Supply rise time(Tr) [ms]” to “Power ramp rate(dV/dt) [mV/μs]” and add some comments. (Page 62) ・ Added the Baud rate spec in “12.4.9 CSIO/UART Timing”.(Page 64-70) ・ Corrected the erroneous descriptions as follows. - “J-TAG” -> “JTAG” (Page 23) - “Analog port input current” -> “Analog port input leak current” (Page 77) *C 5787307 YSAT 06/29/2017 Adapted new Cypress logo *D HUAL 02/09/2018 Updated the Sales information and legal 6064687

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