MB9BF121JPMC

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Document overview

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• PDF pages: 77

Technical content

Datasheet sections

• 6.1 Precautions for Product Design
• 6.2 Precautions for Package Mounting
• 6.3 Precautions for Use Environment
• 12.1 Absolute Maximum Ratings
• 12.2 Recommended Operating Conditions
• 12.3 DC Characteristics
• 12.3.1 Current Rating
• 12.3.2 Pin Characteristics
• 12.4 AC Characteristics
• 12.4.1 Main Clock Input Characteristics
• 12.4.2 Sub Clock Input Characteristics
• 12.4.3 Built-in CR Oscillation Characteristics
• 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL)
• 12.4.6 Reset Input Characteristics
• 12.4.7 Power-on Reset Timing
• 12.4.8 Base Timer Input Timing
• 12.4.9 CSIO/UART Timing
• 12.4.10 External Input Timing
• 12.4.11 Quadrature Position/Revolution Counter Timing
• 12.4.12 I2C Timing
• 12.4.13 SWD Timing
• 12.6 Low-Voltage Detection Characteristics
• 12.6.1 Low-Voltage Detection Reset
• 12.6.2 Interrupt of Low-Voltage Detection
• 12.7 Flash Memory Write/Erase Characteristics
• 12.7.1 Write / Erase time
• 12.7.2 Write cycles and data hold time
• 12.8 Return Time from Low-Power Consumption Mode
• 12.8.1 Return Factor: Interrupt
• 12.8.2 Return Factor: Reset

Features

32-bit ARM® Cortex®-M3 Core  Processor version: r2p1  Up to 72 MHz Frequency Operation  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory]  64 Kbytes  Read cycle: 0 wait-cycle  Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.  SRAM0: 4 Kbytes  SRAM1: 4 Kbytes Multi-function Serial Interface (Max four channels)  2 channels with 16steps×9-bit FIFO (ch.0/ch.1), 2 channels without FIFO (ch.2/ ch.5)  Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2C [UART]  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO]  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detection function available [LIN]  LIN protocol Rev.2.1 supported  Full-duplex double buffer  Master/Slave mode supported  LIN break field generate (can be changed 13-bit to 16-bit length)  LIN break delimiter generate (can be changed 1-bit to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors) [I2C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400kbps) supported DMA Controller (Four channels) The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.  4 independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  Transfer address area: 32-bit (4 Gbytes)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: byte/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536

Document Number: 002-05657 Rev.*C Page 2 of 77 MB9B120J Series A/D Converter (Max 8channels) [12-bit A/D Converter]  Successive Approximation type  Conversion time: 1.0 μs @ 5 V  Priority conversion available (priority at 2 levels) Not included the function to activate A/D by external trigger input  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4steps) Base Timer (Max eight channels) Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built-in. It can set which I/O port the peripheral function can be allocated to.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up to 23 fast general-purpose I/O Ports@32pin Package  Some ports are 5V tolerant See List of Pin Functions and I/O Circuit Type to confirm the corresponding pins. Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot Quadrature Position/Revolution Counter (QPRC) (One channel) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use as the up/down counter.  The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers Multi-function Timer The Multi-function timer is composed of the following blocks.  16-bit free-run timer × 3ch.  Input capture × 4ch.  Output compare × 6ch.  A/D activation compare × 1ch.  Waveform generator × 3ch.  16-bit PPG timer × 3ch. The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D convertor activate function  DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.  The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. External Interrupt Controller Unit  Up to 7 external interrupt input pins@32 pin Package  Include one non-maskable interrupt (NMI) input pin

Document Number: 002-05657 Rev.*C Page 3 of 77 MB9B120J Series Watchdog Timer (Two channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog. The "Hardware" watchdog timer is clocked by the built-in Low-speed CR oscillator. Therefore, the "Hardware" watchdog is active in any low-power consumption modes except RTC, Stop modes. Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillator, and Main PLL).  Main Clock: 4 MHz to 48 MHz  Sub Clock: 32.768 kHz  Built-in High-speed CR Clock: 4 MHz  Built-in Low-speed CR Clock: 100 kHz  Main PLL Clock [Resets]  Reset requests from INITX pin  Power on reset  Software reset  Watchdog timers reset  Low-Voltage detection reset  Clock Super Visor reset Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.  If external clock failure (clock stop) is detected, reset is asserted.  If external frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Consumption Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation Low-Power Consumption Mode Four low-power consumption modes supported.  Sleep  Timer  RTC  Stop Debug Serial Wire Debug Port (SW-DP) Unique ID Unique value of the device (41-bit) is set. Power Supply Wide range voltage: VCC = 2.7 V to 5.5 V

Document Number: 002-05657 Rev.*C Page 5 of 77 MB9B120J Series

Document Number: 002-05657 Rev.*C Page 6 of 77 MB9B120J Series 1. Product Lineup Memory Size Product name MB9BF121J On-chip Flash memory 64 Kbytes On-chip SRAM SRAM0 4 Kbytes SRAM1 4 Kbytes Total 8 Kbytes Function Product name MB9BF121J Pin count 32 CPU Cortex-M3 Freq. 72 MHz Power supply voltage range 2.7 V to 5.5 V DMAC 4 ch. Multi-function Serial Interface (UART/CSIO/I2C) 4 ch. (Max) ch.0/ch.1: FIFO ch.2/ch.5: No FIFO Base Timer (PWC/Reload timer/PWM/PPG) 8ch. (Max) MF- Timer A/D activation compare 1 ch. 1 unit Input capture 4 ch. Free-run timer 3 ch. Output compare 6 ch. Waveform generator 3 ch. PPG 3 ch. QPRC 1 ch. Dual Timer 1 unit Real-Time Clock 1 unit Watchdog timer 1 ch. (SW) + 1 ch. (HW) External Interrupts 7 pins (Max) + NMI × 1 I/O ports 23 pins (Max) 12-bit A/D converter 8 ch. (1 unit) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2 ch. Built-in CR High-speed 4 MHz Low-speed 100 kHz Debug Function SW-DP Unique ID Yes Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. CR.

Document Number: 002-05657 Rev.*C Page 7 of 77 MB9B120J Series 2. Packages Product name LQFP: LQB032 (0.8 mm pitch)  QFN: WNU032 (0.5 mm pitch)  : Supported Note: − See Package Dimensions for detailed information on each package.

Document Number: 002-05657 Rev.*C Page 8 of 77 MB9B120J Series 3. Pin Assignment LQB032 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 P04/SWO P03/SWDIO P01/SWCLK AVRH AVRL VSS VCC P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2/FRCK0_0/SCK2_0 1 24 P21/AN14/SIN0_0/INT06_1/BIN1_1 P3B/RTO01_0/TIOA1_1/IC00_0/SOT2_0 2 23 P22/AN13/SOT0_0/TIOB7_1/ZIN1_1 P3C/RTO02_0/TIOA2_1/INT18_2/IC01_0/SIN2_0 3 22 P23/AN12/SCK0_0/TIOA7_1/AIN1_1/DTTI0X_1 P3D/RTO03_0/TIOA3_1/SCK5_1/AIN1_0/IC02_0 4 21 P15/AN05/SOT0_1/INT14_0/IC03_2 P3E/RTO04_0/TIOA4_1/INT19_2/SOT5_1/BIN1_0 5 20 P14/AN04/SIN0_1/INT03_1/IC02_2/SCK0_1 P3F/RTO05_0/TIOA5_1/SIN5_1/ZIN1_0 6 19 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/ZIN1_2/TIOB6_2 VCC 7 18 P12/AN02/SOT1_1/IC00_2/BIN1_2/TIOA6_2 C 8 17 P11/AN01/SIN1_1/INT02_1/FRCK0_2/AIN1_2 VSS PE2/X0 PE3/X1 INITX DTTI0X_0/INT07_1/P46/X0A INT14_2/P47/X1A MD0 PE0/MD1 LQFP - 32

Document Number: 002-05657 Rev.*C Page 9 of 77 MB9B120J Series WNU032 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. P0F/NMIX/SUBOUT_0/CROUT_1/RTCCO_0 P04/SWO P03/SWDIO P01/SWCLK AVRH AVRL VSS VCC P3A/RTO00_0/TIOA0_1/INT07_0/SUBOUT_2/RTCCO_2/FRCK0_0/SCK2_0 1 24 P21/AN14/SIN0_0/INT06_1/BIN1_1 P3B/RTO01_0/TIOA1_1/IC00_0/SOT2_0 2 23 P22/AN13/SOT0_0/TIOB7_1/ZIN1_1 P3C/RTO02_0/TIOA2_1/INT18_2/IC01_0/SIN2_0 3 22 P23/AN12/SCK0_0/TIOA7_1/AIN1_1/DTTI0X_1 P3D/RTO03_0/TIOA3_1/SCK5_1/AIN1_0/IC02_0 4 21 P15/AN05/SOT0_1/INT14_0/IC03_2 P3E/RTO04_0/TIOA4_1/INT19_2/SOT5_1/BIN1_0 5 20 P14/AN04/SIN0_1/INT03_1/IC02_2/SCK0_1 P3F/RTO05_0/TIOA5_1/SIN5_1/ZIN1_0 6 19 P13/AN03/SCK1_1/SUBOUT_1/IC01_2/RTCCO_1/ZIN1_2/TIOB6_2 VCC 7 18 P12/AN02/SOT1_1/IC00_2/BIN1_2/TIOA6_2 C 8 17 P11/AN01/SIN1_1/INT02_1/FRCK0_2/AIN1_2 VSS PE2/X0 PE3/X1 INITX DTTI0X_0/INT07_1/P46/X0A INT14_2/P47/X1A MD0 PE0/MD1 QFN - 32

Document Number: 002-05657 Rev.*C Page 10 of 77 MB9B120J Series 4. List of Pin Functions List of Pin Numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Pin name I/O circuit type Pin state type P3A F K RTO00_0 (PPG00_0) FRCK0_0 INT07_0 TIOA0_1 SCK2_0 (SCL2_0) SUBOUT_2 RTCCO_2 P3B F J RTO01_0 (PPG00_0) IC00_0 TIOA1_1 SOT2_0 (SDA2_0) P3C F K RTO02_0 (PPG02_0) IC01_0 INT18_2 TIOA2_1 SIN2_0 P3D F J RTO03_0 (PPG02_0) IC02_0 TIOA3_1 SCK5_1 (SCL5_1) AIN1_0 P3E F K RTO04_0 (PPG04_0) INT19_2 TIOA4_1 SOT5_1 (SDA5_1) BIN1_0

Document Number: 002-05657 Rev.*C Page 11 of 77 MB9B120J Series Pin No Pin name I/O circuit type Pin state type P3F F J RTO05_0 (PPG04_0) TIOA5_1 SIN5_1 ZIN1_0

7 VCC - -

8 C - -

9 VSS - -

12 INITX B C

DTTI0X_0 INT07_1 P47 D G X1A INT14_2

15 MD0 H D

G* M AN01 SIN1_1 INT02_1 FRCK0_2 AIN1_2 P12 G* L AN02 SOT1_1 (SDA1_1) TIOA6_2 IC00_2 BIN1_2

Document Number: 002-05657 Rev.*C Page 12 of 77 MB9B120J Series Pin No Pin name I/O circuit type Pin state type P13 G* L AN03 SCK1_1 (SCL1_1) SUBOUT_1 TIOB6_2 IC01_2 RTCCO_1 ZIN1_2 P14 G* M AN04 SIN0_1 INT03_1 SCK0_1 (SCL0_1) IC02_2 P15 G* M AN05 SOT0_1 (SDA0_1) INT14_0 IC03_2 P23 G* L AN12 SCK0_0 (SCL0_0) TIOA7_1 DTTI0X_1 AIN1_1 P22 G* L AN13 SOT0_0 (SDA0_0) TIOB7_1 ZIN1_1 P21 G* M AN14 SIN0_0 INT06_1 BIN1_1

25 VCC - -

26 VSS - -

Document Number: 002-05657 Rev.*C Page 13 of 77 MB9B120J Series Pin No Pin name I/O circuit type Pin state type

27 AVRL - -

28 AVRH - -

SUBOUT_0 CROUT_1 RTCCO_0 *: 5 V tolerant I/O

Document Number: 002-05657 Rev.*C Page 14 of 77 MB9B120J Series List of Pin Functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function Pin name Function description Pin No ADC AN01 A/D converter analog input pin. ANxx describes ADC ch.xx. AN02 18 AN03 19 AN04 20 AN05 21 AN12 22 AN13 23 AN14 24 Base Timer 0 TIOA0_1 Base timer ch.0 TIOA pin 1 Base Timer 1 TIOA1_1 Base timer ch.1 TIOA pin 2 Base Timer 2 TIOA2_1 Base timer ch.2 TIOA pin 3 Base Timer 3 TIOA3_1 Base timer ch.3 TIOA pin 4 Base Timer 4 TIOA4_1 Base timer ch.4 TIOA pin 5 Base Timer 5 TIOA5_1 Base timer ch.5 TIOA pin 6 Base Timer 6 TIOA6_2 Base timer ch.6 TIOA pin 18 TIOB6_2 Base timer ch.6 TIOB pin 19 Base Timer 7 TIOA7_1 Base timer ch.7 TIOA pin 22 TIOB7_1 Base timer ch.7 TIOB pin 23 Debugger SWCLK Serial wire debug interface clock input pin 29 SWDIO Serial wire debug interface data input / output pin 30 SWO Serial wire viewer output pin 31 External Interrupt INT02_1 External interrupt request 02 input pin 17 INT03_1 External interrupt request 03 input pin 20 INT06_1 External interrupt request 06 input pin 24 INT07_0 External interrupt request 07 input pin INT07_1 13 INT14_0 External interrupt request 14 input pin INT14-2 14 INT18_2 External interrupt request 18 input pin 3 INT19_2 External interrupt request 19 input pin 5 NMIX Non-Maskable Interrupt input pin 32

Document Number: 002-05657 Rev.*C Page 15 of 77 MB9B120J Series Pin function Pin name Function description Pin No GPIO P01 General-purpose I/O port 0 P03 30 P04 31 P0F 32 P11 General-purpose I/O port 1 P12 18 P13 19 P14 20 P15 21 P21 General-purpose I/O port 2 P22 23 P23 22 P3A General-purpose I/O port 3 P3B 2 P3C 3 P3D 4 P3E 5 P3F 6 P46 General-purpose I/O port 4 P47 14 PE0 General-purpose I/O port E PE2 10 PE3 11 Multi-function Serial 0 SIN0_0 Multi-function serial interface ch.0 input pin SIN0_1 20 SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I2C (operation mode 4). SOT0_1 (SDA0_1) 21 SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I2C (operation mode 4). SCK0_1 (SCL0_1) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation mode 2) and as SCL0 when it is used in an I2C (operation mode 4). Multi-function Serial 1 SIN1_1 Multi-function serial interface ch.1 input pin 17 SOT1_1 (SDA1_1) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I2C (operation mode 4). SCK1_1 (SCL1_1) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation mode 2) and as SCL1 when it is used in an I2C (operation mode 4).

Document Number: 002-05657 Rev.*C Page 16 of 77 MB9B120J Series Pin function Pin name Function description Pin No Multi-function Serial 2 SIN2_0 Multi-function serial interface ch.2 input pin 3 SOT2_0 (SDA2_0) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I2C (operation mode 4). SCK2_0 (SCL2_0) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a CSIO (operation mode 2) and as SCL2 when it is used in an I2C (operation mode 4). Multi-function Serial 5 SIN5_1 Multi-function serial interface ch.5 input pin 6 SOT5_1 (SDA5_1) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA5 when it is used in an I2C (operation mode 4). SCK5_1 (SCL5_1) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a CSIO (operation mode 2) and as SCL5 when it is used in an I2C (operation mode 4). Multi-function Timer 0 DTTI0X_0 Input signal of waveform generator to control outputs RTO00 to RTO05 of Multi-function timer 0. DTTI0X_1 22 FRCK0_0 16-bit free-run timer ch.0 external clock input pin FRCK0_2 17 IC00_0 16-bit input capture input pin of Multi-function timer 0. ICxx describes channel number. IC00_2 18 IC01_0 3 IC01_2 19 IC02_0 4 IC02_2 20 IC03_2 21 RTO00_0 (PPG00_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. 1 RTO01_0 (PPG00_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. 2 RTO02_0 (PPG02_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. 3 RTO03_0 (PPG02_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. 4 RTO04_0 (PPG04_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. 5 RTO05_0 (PPG04_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. 6

Document Number: 002-05657 Rev.*C Page 17 of 77 MB9B120J Series Pin function Pin name Function description Pin No Quadrature Position/ Revolution Counter AIN1_0 QPRC ch.1 AIN input pin AIN1_1 22 AIN1_2 17 BIN1_0 QPRC ch.1 BIN input pin BIN1_1 24 BIN1_2 18 ZIN1_0 QPRC ch.1 ZIN input pin ZIN1_1 23 ZIN1_2 19 Real-time clock RTCCO_0 0.5 seconds pulse output pin of Real-time clock RTCCO_1 19 RTCCO_2 1 SUBOUT_0 Sub clock output pin SUBOUT_1 19 SUBOUT_2 1 RESET INITX External Reset Input pin. A reset is valid when INITX="L". 12 Mode MD0 Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. MD1 Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. 16 POWER VCC Analog/Digital Power supply Pin 7 VCC Analog/Digital Power supply Pin 25 GND VSS Analog/Digital GND Pin 9 VSS Analog/Digital GND Pin 26 CLOCK X0 Main clock (oscillation) input pin 10 X0A Sub clock (oscillation) input pin 13 X1 Main clock (oscillation) I/O pin 11 X1A Sub clock (oscillation) I/O pin 14 CROUT_1 Built-in High-speed CR-osc clock output port 32 Analog POWER AVRH A/D converter analog reference voltage input pin 28 Analog GND AVRL A/D converter analog reference voltage input pin 27 C pin C Power supply stabilization capacity pin 8

Document Number: 002-05657 Rev.*C Page 18 of 77 MB9B120J Series 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected. − Oscillation feedback resistor : Approximately 1 MΩ − With standby mode control When the GPIO is selected. − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH= -4 mA, IOL= 4 mA B − CMOS level hysteresis input − Pull-up resistor : Approximately 50 kΩ P-ch P-ch N-ch R R P-ch P-ch N-ch X0A X1A Pull-up resistor Feedback resistor Pull-up resistor Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control Pull-up resistor Digital input

Document Number: 002-05657 Rev.*C Page 19 of 77 MB9B120J Series Type Circuit Remarks C − Open drain output − CMOS level hysteresis input D It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected. − Oscillation feedback resistor : Approximately 5 MΩ − With standby mode control When the GPIO is selected. − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH= -4 mA, IOL= 4 mA N-ch P-ch P-ch N-ch R R P-ch P-ch N-ch X0A X1A Pull-up resistor Feedback resistor Pull-up resistor Digital input Digital output Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control

Document Number: 002-05657 Rev.*C Page 20 of 77 MB9B120J Series Type Circuit Remarks E − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH= -4 mA, IOL= 4 mA − +B input is available F − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH= -12 mA, IOL= 12 mA − When this pin is used as an I2C pin, the digital output P-ch transistor is always off − +B input is available P-chP-ch N-ch R P-chP-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control

Document Number: 002-05657 Rev.*C Page 21 of 77 MB9B120J Series Type Circuit Remarks G − CMOS level output − CMOS level hysteresis input − With input control − Analog input − 5 V tolerant − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH= -4 mA, IOL= 4 mA − Available to control of PZR registers. − When this pin is used as an I2C pin, the digital output P-ch transistor is always off H CMOS level hysteresis input P-chP-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control Mode input

Document Number: 002-05657 Rev.*C Page 22 of 77 MB9B120J Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

6.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

Document Number: 002-05657 Rev.*C Page 23 of 77 MB9B120J Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

6.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h

Document Number: 002-05657 Rev.*C Page 24 of 77 MB9B120J Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

6.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives.

Document Number: 002-05657 Rev.*C Page 25 of 77 MB9B120J Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVRH pin and AVRL pin near this device. Stabilizing supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub crystal oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.  Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: Approximately 6 pF to 7 pF  Lead type Load capacitance: Approximately 6 pF to 7 pF Using an external clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1(PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.  Example of Using an External Clock Device X0(X0A) X1(PE3), X1A (P47) Can be used as general-purpose I/O ports. Set as External clock input

Document Number: 002-05657 Rev.*C Page 26 of 77 MB9B120J Series Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series. Mode pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. Turning on: VCC → AVRH Turning off: AVRH → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up function of 5 V tolerant I/O Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant I/O. CS Device C VSS GND

Document Number: 002-05657 Rev.*C Page 27 of 77 MB9B120J Series 8. Block Diagram Cortex-M3 Core @72MHz(Max) Flash I/F Clock Reset Generator Dual-Timer WatchDog Timer (Hardware) DMAC 4ch.CSV External Interrupt Controller 7-pin + NMI Power On Reset SRAM0

4 Kbyte

I D Sys CLK MB9BF121J NVIC WatchDog Timer (Software) Security 12-bit A/D Converter SWCLK, SWDIO AVRH, AVRL ANxx TIOAx TIOBx C SWO X0A X1A SCKx SINx SOTx INTx NMIX P0x, P1x, Pxx INITX MODE-Ctrl IRQ-Monitor MD0, MD1 Regulator On-Chip Flash

64 Kbyte

4ch. (with FIFO ch.0/ch.1) GPIO PIN-Function-Ctrl LVD ROM Table SW-DP Main Osc PLL Sub Osc CR 4MHz CR 100kHz LVD Ctrl Base Timer 16-bit 8ch./ 32-bit 4ch. Real-Time Clock RTCCO, SUBOUT Unit 0 QPRC 1ch. AINx BINx ZINx Multi-function Timer 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. Waveform Generator 3ch. A/D Activation Compare 1ch. 16-bit PPG 3ch. IC0x DTTI0X RTO0x FRCKx CROUT Source Clock AHB-APB Bridge: APB0(Max 40MHz) AHB-AHB Bridge Multi-layer AHB (Max 72MHz) AHB-APB Bridge : APB1 (Max 40MHz) AHB-APB Bridge : APB2 (Max 40MHz)

Document Number: 002-05657 Rev.*C Page 28 of 77 MB9B120J Series 9. Memory Size See Memory size in Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF 0xE010_0000 0x4006_1000 0xE000_0000 0x4006_0000 DMAC 0x4003_C000 0x4003_B000 RTC 0x4003_9000 0x4003_8000 MFS 0x4400_0000 0x4003_6000 0x4200_0000 0x4003_5000 LVD/DS mode 0x4003_4000 Reserved 0x4000_0000 0x4003_3000 GPIO 0x4003_2000 Reserved 0x4003_1000 Int-Req.Read 0x2400_0000 0x4003_0000 EXTI 0x4002_F000 Reserved 0x2200_0000 0x4002_E000 CR Trim 0x4002_8000 0x2008_0000 0x4002_7000 A/DC 0x2000_0000 SRAM1 0x4002_6000 QPRC 0x1FF8_0000 SRAM0 0x4002_5000 Base Timer 0x4002_4000 PPG 0x0010_0008 0x0010_0000 Security/CR Trim 0x4002_1000 0x4002_0000 MFT unit0 0x4001_5000 Dual Timer 0x0000_0000 0x4001_3000 0x4001_2000 SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 Flash I/F Reserved Reserved Reserved Reserved Reserved Reserved ReservedSee "lMemory map(2)" for the memory size details. Reserved Reserved Cortex-M3 Private Peripherals 32Mbytes Bit band alias Peripherals Reserved 32Mbytes Bit band alias Reserved Reserved Reserved Flash Reserved

Document Number: 002-05657 Rev.*C Page 29 of 77 MB9B120J Series Memory Map (2) *: See “MB9A420L/120L/MB9B120J Series Flash Programming Manual” to confirm the detail of Flash memory. MB9BF121J 0x2008_0000 0x2000_1000 0x2000_0000 0x1FFF_F000 0x0010_0008 0x0010_0004 CR trimming 0x0010_0000 Security 0x0000_FFF8 0x0000_0000 Reserved SRAM1 4Kbytes Flash 64Kbytes*SA0-7 (8KBx8) Reserved Reserved SRAM0 4Kbytes

Document Number: 002-05657 Rev.*C Page 30 of 77 MB9B120J Series Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB Flash memory I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF APB1 Multi-function timer unit0 0x4002_1000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low-Voltage Detector 0x4003_5800 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_AFFF Reserved 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4005_FFFF AHB Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x41FF_FFFF Reserved

Document Number: 002-05657 Rev.*C Page 31 of 77 MB9B120J Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the L level.  INITX=1 This is the period when the INITX pin is the H level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.

Document Number: 002-05657 Rev.*C Page 32 of 77 MB9B120J Series List of Pin Status Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state TIMER mode, RTC mode or STOP mode state Power supply unstable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at "0" Main crystal oscillator input pin /External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Main crystal oscillator output pin Hi-Z / Internal input fixed at 0 or Input enable Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z / Internal input fixed at 0 C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled

Document Number: 002-05657 Rev.*C Page 33 of 77 MB9B120J Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state TIMER mode, RTC mode or STOP mode state Power supply unstable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 E Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled F GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Sub crystal oscillator input pin /External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled G GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0 or Input enable Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0

Document Number: 002-05657 Rev.*C Page 34 of 77 MB9B120J Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state TIMER mode, RTC mode or STOP mode state Power supply unstable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 H NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected I Serial wire debug selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 J Resource selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected K External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected L Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected

Document Number: 002-05657 Rev.*C Page 35 of 77 MB9B120J Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or SLEEP mode state TIMER mode, RTC mode or STOP mode state Power supply unstable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 M Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected *1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode. *2: Oscillation is stopped at Stop mode.

Document Number: 002-05657 Rev.*C Page 36 of 77 MB9B120J Series 12. Electrical Characteristics

12.1 Absolute Maximum Ratings

Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*1, *2 VCC VSS - 0.5 VSS + 6.5 V Analog reference voltage*1, *3 AVRH VSS - 0.5 VSS + 6.5 V Input voltage*1 VI VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V VSS - 0.5 VSS + 6.5 V 5 V tolerant Analog pin input voltage*1 VIA VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V Output voltage*1 VO VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V Clamp maximum current ICLAMP -2 +2 mA *7 Clamp total maximum current Σ[ICLAMP] +20 mA *7 L level maximum output current*4 IOL - 10 mA 4 mA type 20 mA 12 mA type L level average output current*5 IOLAV - 4 mA 4 mA type 12 mA 12 mA type L level total maximum output current ∑IOL - 100 mA L level total average output current*6 ∑IOLAV - 50 mA H level maximum output current*4 IOH - - 10 mA 4 mA type - 20 mA 12 mA type H level average output current*5 IOHAV - - 4 mA 4 mA type - 12 mA 12 mA type H level total maximum output current ∑IOH - - 100 mA H level total average output current*6 ∑IOHAV - - 50 mA Power consumption PD - 350 mW Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that VSS = 0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is the peak value for a single pin. *5: The average output is the average current for a single pin over a period of 100 ms. *6: The total average output current is the average current for all pins over a period of 100 ms. *7:

• See List of Pin Functions and I/O Circuit Type about +B input available pin.
• Use within recommended operating conditions.
• Use at DC voltage (current) the +B input.
• The +B signal should always be applied a limiting resistance placed between the +B signal and the device.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the device drive current is low, such as in the low-power consumption modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.
• Note that if a +B signal is input when the device power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result.
• The following is a recommended circuit example (I/O equivalent circuit).

Document Number: 002-05657 Rev.*C Page 37 of 77 MB9B120J Series WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. R +B input (0V to 16V) Protection Diode P-ch VCC VCC Limiting resistor N-ch VCC Analog input Digital input Digital output

Document Number: 002-05657 Rev.*C Page 38 of 77 MB9B120J Series

12.2 Recommended Operating Conditions

(VSS = AVRL = 0.0V) Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage VCC - 2.7*2 5.5 V Analog reference voltage AVRH - 2.7 VCC V AVRL - VSS VSS V Smoothing capacitor CS - 1 10 μF For regulator*1 Operating temperature LQB032, WNU032 TA When mounted on four-layer PCB - 40 + 105 °C When mounted on double-sided single-layer PCB - 40 + 85 °C *1: See C Pin in Handling Devices for the connection of the smoothing capacitor. *2: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate only. WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

Document Number: 002-05657 Rev.*C Page 39 of 77 MB9B120J Series

12.3 DC Characteristics

12.3.1 Current Rating

(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Run mode current ICC VCC PLL Run mode CPU: 72 MHz, Peripheral: 36 MHz Instruction on Flash 27 35 mA *1, *5 CPU: 72 MHz, Peripheral: the clock stops NOP operation Instruction on Flash 18 22 mA *1, *5 CPU: 72 MHz, Peripheral: 36 MHz Instruction on RAM 23 29 mA *1 High-speed CR Run mode CPU/ Peripheral: 4 MHz*2 Instruction on Flash 2.2 3.1 mA *1 Sub Run mode CPU/ Peripheral: 32 kHz Instruction on Flash 73 910 μA *1, *6 Low-speed CR Run mode CPU/ Peripheral: 100k Hz Instruction on Flash 105 930 μA *1 Sleep mode current ICCS PLL Sleep mode Peripheral: 36 MHz 17 20 mA *1, *5 High-speed CR Sleep mode Peripheral: 4 MHz*2 1.3 2.2 mA *1 Sub Sleep mode Peripheral: 32 kHz 64 890 μA *1, *6 Low-speed CR Sleep mode Peripheral: 100 kHz 80 910 μA *1 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA = +25°C, VCC = 5.5 V *4: TA = +105°C, VCC = 5.5 V *5: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit)

Document Number: 002-05657 Rev.*C Page 40 of 77 MB9B120J Series (VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Timer mode current ICCT VCC Main Timer mode TA = + 25°C, When LVD is off 3.5 4.1 mA *1 TA = + 105°C, When LVD is off - 4.6 mA *1 ICCT Sub Timer mode TA = + 25°C, When LVD is off 15 45 μA *1 TA = + 105°C, When LVD is off - 740 μA *1 RTC mode current ICCR RTC mode TA = + 25°C, When LVD is off 13 39 μA *1 TA = + 105°C, When LVD is off - 580 μA *1 Stop mode current ICCH Stop mode TA = + 25°C, When LVD is off 12 33 μA *1 TA = + 105°C, When LVD is off - 550 μA *1 *1: When all ports are fixed. *2: VCC = 5.5 V *3: When using the crystal oscillator of 4 MHz (Including the current consumption of the oscillation circuit) *4: When using the crystal oscillator of 32 kHz (Including the current consumption of the oscillation circuit) LVD current (VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Low-Voltage detection circuit (LVD) power supply current ICCLVD VCC At operation for reset VCC = 5.5 V 0.13 0.3 μA At not detect At operation for interrupt VCC = 5.5 V 0.13 0.3 μA At not detect Flash memory current (VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Flash memory write/erase current ICCFLASH VCC At Write/Erase 9.5 11.2 mA A/D convertor current (VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Power supply current ICCAD VCC At operation 0.7 0.9 mA Reference power supply current ICCAVRH AVRH At operation AVRH = 5.5 V 1.1 1.97 mA At stop AVRH = 5.5 V 0.1 1.7 μA

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12.3.2 Pin Characteristics

(VCC = 2.7V to 5.5V, VSS = AVRL = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max H level input voltage (hysteresis input) VIHS CMOS hysteresis input pin, MD0, MD1 - VCC × 0.8 - VCC + 0.3 V

5 V tolerant input

pin - VCC × 0.8 - VSS + 5.5 V L level input voltage (hysteresis input) VILS CMOS hysteresis input pin, MD0, MD1 - VSS - 0.3 - VCC × 0.2 V pin - VSS - 0.3 - VCC × 0.2 V H level output voltage VOH 4 mA type VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 2 mA 12 mA type VCC ≥ 4.5 V, IOH = - 12 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 8 mA L level output voltage VOL 4 mA type VCC ≥ 4.5 V, IOL = 4 mA VSS - 0.4 V VCC < 4.5 V, IOL = 2 mA 12 mA type VCC ≥ 4.5 V, IOL = 12 mA VSS - 0.4 V VCC < 4.5 V, IOL = 8 mA Input leak current IIL - - - 5 - + 5 μA Pull-up resistance value RPU Pull-up pin VCC ≥ 4.5 V 33 50 90 kΩ VCC < 4.5 V - - 180 Input capacitance CIN Other than VCC, VSS, AVRH, AVRL - - 5 15 pF

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12.4 AC Characteristics

12.4.1 Main Clock Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input frequency fCH X0, VCC ≥ 4.5 V 4 48 MHz When crystal oscillator is connected VCC < 4.5 V 4 20 - 4 48 MHz When using external Clock Input clock cycle tCYLH - 20.83 250 ns When using external Clock Input clock pulse width - PWH/tCYLH, PWL/tCYLH 45 55 % When using external Clock Input clock rise time and fall time tCF, tCR - - 5 ns When using external Clock Internal operating clock*1 frequency fCM - - - 72 MHz Master clock fCC - - - 72 MHz Base clock (HCLK/FCLK) fCP0 - - - 40 MHz APB0 bus clock*2 fCP1 - - - 40 MHz APB1 bus clock*2 fCP2 - - - 40 MHz APB2 bus clock*2 Internal operating clock*1 cycle time tCYCC - - 13.8 - ns Base clock (HCLK/FCLK) tCYCP0 - - 25 - ns APB0 bus clock*2 tCYCP1 - - 25 - ns APB1 bus clock*2 tCYCP2 - - 25 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.

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12.4.2 Sub Clock Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Input frequency fCL X0A, X1A - - 32.768 - kHz When crystal oscillator is connected* - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock *: See Sub crystal oscillator in Handling Devices for the crystal oscillator used. X0A

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12.4.3 Built-in CR Oscillation Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRH TA = + 25°C, 3.6 V < VCC ≤ 5.5 V 3.92 4 4.08 MHz When trimming*1 TA =0°C to + 85°C, 3.6 V < VCC ≤ 5.5 V 3.9 4 4.1 TA = - 40°C to + 105°C, 3.6 V < VCC ≤ 5.5 V 3.88 4 4.12 TA = + 25°C, 2.7 V ≤ VCC ≤ 3.6 V 3.94 4 4.06 TA = - 20°C to + 85°C, 2.7 V ≤ VCC ≤ 3.6 V 3.92 4 4.08 TA = - 20°C to + 105°C, 2.7 V ≤ VCC ≤ 3.6 V 3.9 4 4.1 TA = - 40°C to + 105°C, 2.7 V ≤ VCC ≤ 3.6 V 3.88 4 4.12 TA = - 40°C to + 105°C 2.8 4 5.2 When not trimming Frequency stabilization time tCRWT - - - 30 μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming/temperature trimming. *2: This is time from the trim value setting to stable of the frequency of the High-speed CR clock. After setting the trim value, the period when the frequency stability time passes can use the High-speed CR clock as a source clock. Built-in Low-speed CR (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRL - 50 100 150 kHz

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12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of Main PLL)

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiple rate - 5 - 37 multiple PLL macro oscillation clock frequency fPLLO 75 - 150 MHz Main PLL clock frequency*2 fCLKPLL - - 72 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. 12.4.5 Operating Conditions of Main PLL (In the case of using built-in High-speed CR for input clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiple rate - 19 - 35 multiple PLL macro oscillation clock frequency fPLLO 72 - 150 MHz Main PLL clock frequency*2 fCLKPLL - - 72 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: − Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency/temperature has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Main PLL connection

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12.4.6 Reset Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns

12.4.7 Power-on Reset Timing

(VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Power supply shut down time tOFF VCC - 1 - - ms *1 Power ramp rate dV/dt Vcc:0.2 V to 2.70 V 1.2 - 1000 mV/μs *2 Time until releasing Power-on reset tPRT - 0.34 - 3.15 ms *1: VCC must be held below 0.2 V for minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>1 ms). Note: − If tOFF cannot be satisfied designs must assert external reset(INITX) at power-up and at any brownout event per 12. 4. 6. Glossary VDH: detection voltage of Low Voltage detection reset. See “12.6. Low-voltage Detection Characteristics” VDH tPRT Internal RST VCC CPU Operation start RST Active release 0.2V 0.2V tOFF dV/dt0.2V 2.7V

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12.4.8 Base Timer Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - 2tCYCP - ns Trigger input timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Base Timer is connected to, see Block Diagram in this data sheet. tTIWH VIHS VIHS VILS VILS tTIWL tTRGH VIHS VIHS VILS VILS tTRGL ECK TIN TGIN

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12.4.9 CSIO/UART Timing

CSIO (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. − About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. − For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05657 Rev.*C Page 49 of 77 MB9B120J Series Master mode Slave mode tSLSH tSHSL VIH tF tR VIH VOH VIH VIL VIL VOL VIH VIL VIH VIL tSLOVE tIVSHE tSHIXE SCK SOT SIN tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI SCK SOT SIN

Document Number: 002-05657 Rev.*C Page 50 of 77 MB9B120J Series CSIO (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. − About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. − For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05657 Rev.*C Page 51 of 77 MB9B120J Series Master mode Slave mode tSHSL tSLSH VIH tF tR VIH VOH VIL VIL VIL VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSHOVE tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI SCK SOT SIN

Document Number: 002-05657 Rev.*C Page 52 of 77 MB9B120J Series CSIO (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK ↓→ SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK ↓→ SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. − About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. − For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05657 Rev.*C Page 53 of 77 MB9B120J Series Master mode Slave mode *: Changes when writing to TDR register tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI SCK SOT SIN

Document Number: 002-05657 Rev.*C Page 54 of 77 MB9B120J Series CSIO (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. − About the APB bus number which Multi-function Serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. − For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-05657 Rev.*C Page 55 of 77 MB9B120J Series Master mode Slave mode UART external clock input (EXT = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Max Serial clock L pulse width tSLSH CL = 30 pF tCYCP + 10 - ns Serial clock H pulse width tSHSL tCYCP + 10 - ns SCK falling time tF - 5 ns SCK rising time tR - 5 ns tSHSL VIL VIL VIL VIH VIH tR tF tSLSH SCK tSLSH tF tSLOVE VIL VIL VIL VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI SCK SOT SIN

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12.4.10 External Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tINH, tINL FRCKx - 2tCYCP*1 - ns Free-run timer input clock ICxx Input capture DTTIxX - 2tCYCP*1 - ns Wave form generator INTxx, NMIX *2 2tCYCP + 100*1 - ns External interrupt, NMI *3 500 - ns *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which, Multi-function Timer, External interrupt is connected to, see Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in Stop mode, in RTC mode, in Timer mode.

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12.4.11 Quadrature Position/Revolution Counter Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Min Max AIN pin H width tAHL - 2tCYCP* - ns AIN pin L width tALL - BIN pin H width tBHL - BIN pin L width tBLL - Time from AIN pin H level to BIN rise tAUBU PC_Mode2 or PC_Mode3 Time from BIN pin H level to AIN fall tBUAD PC_Mode2 or PC_Mode3 Time from AIN pin L level to BIN fall tADBD PC_Mode2 or PC_Mode3 Time from BIN pin L level to AIN rise tBDAU PC_Mode2 or PC_Mode3 Time from BIN pin H level to AIN rise tBUAU PC_Mode2 or PC_Mode3 Time from AIN pin H level to BIN fall tAUBD PC_Mode2 or PC_Mode3 Time from BIN pin L level to AIN fall tBDAD PC_Mode2 or PC_Mode3 Time from AIN pin L level to BIN rise tADBU PC_Mode2 or PC_Mode3 ZIN pin H width tZHL QCR:CGSC=0 ZIN pin L width tZLL QCR:CGSC=0 Time from determined ZIN level to AIN/BIN rise and fall tZABE QCR:CGSC=1 Time from AIN/BIN rise and fall time to determined ZIN level tABEZ QCR:CGSC=1 *: tCYCP indicates the APB bus clock cycle time. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see Block Diagram in this data sheet. AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL

Document Number: 002-05657 Rev.*C Page 58 of 77 MB9B120J Series BIN tBUAU tAUBD tBDAD tADBU tBHL tBLL tAHL tALL AIN ZIN AIN/BIN ZIN

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12.4.12 I2C Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency fSCL CL = 30 pF, R = (Vp/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCL clock L width tLOW 4.7 - 1.3 - μs SCL clock H width tHIGH 4.0 - 0.6 - μs (Repeated) Start condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns Stop condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between Stop condition and Start condition tBUF 4.7 - 1.3 - μs Noise filter tSP - 2 tCYCP*4 - 2 tCYCP*4 - ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it doesn't extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of “tSUDAT ≥ 250 ns”. *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SCL SDA

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12.4.13 SWD Timing

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max SWDIO setup time tSWS SWCLK, SWDIO - 15 - ns SWDIO hold time tSWH SWCLK, SWDIO - 15 - ns SWDIO delay time tSWD SWCLK, SWDIO - - 45 ns Note: − When the external load capacitance CL = 30 pF. SWD SWDIO (When input) SWCLK SWDIO (When output)

Document Number: 002-05657 Rev.*C Page 61 of 77 MB9B120J Series 12.5 12-bit A/D Converter Electrical characteristics for the A/D converter (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 105°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - - ± 3.0 ± 4.5 LSB AVRH = 2.7 V to 5.5 V Differential Nonlinearity - - - ± 2.5 ± 3.5 LSB Zero transition voltage VZT ANxx - ± 15 ± 20 mV Full-scale transition voltage VFST ANxx - AVRH ± 15 AVRH ± 20 mV Conversion time - - 1.0*1 - - μs Sampling time*2 tS - 0.3 - 10 μs Compare clock cycle*3 tCCK - 50 - 1000 ns State transition time to operation permission tSTT - - - 1.0 μs Analog input capacity CAIN - - - 9.7 pF Analog input resistance RAIN - - - 1.5 kΩ VCC ≥ 4.5 V 2.2 VCC < 4.5 V Interchannel disparity - - - - 4 LSB Analog port input leak current - ANxx - - 5 μA Analog input voltage - ANxx AVRL - AVRH V Reference voltage - AVRH 2.7 - VCC V AVRL VSS - VSS V *1: Conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is when the value of sampling time: 300 ns, the value of sampling time: 700 ns. Ensure that it satisfies the value of sampling time (tS) and compare clock cycle (tCCK). For setting of sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Part. The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: Compare time (tC) is the value of (Equation 2).

Document Number: 002-05657 Rev.*C Page 62 of 77 MB9B120J Series (Equation 1) tS ≥ (RAIN + REXT ) × CAIN × 9 tS: Sampling time RAIN: Input resistance of A/D = 1.5 kΩ at 4.5 V < VCC < 5.5 V Input resistance of A/D = 2.2 kΩ at 2.7 V < VCC < 4.5 V CAIN: Input capacity of A/D = 9.7 pF at 2.7 V < VCC < 5.5 V REXT: Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle REXT Analog signal source RAIN CAIN Comparator ANxx Analog input pin

Document Number: 002-05657 Rev.*C Page 63 of 77 MB9B120J Series Definition of 12-bit A/D Converter Terms  Resolution: Analog variation that is recognized by an A/D converter.  Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.  Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST – VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVRL AVRH AVRL AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFSTtSHSL VZTtR VNT V(N+1)T

Document Number: 002-05657 Rev.*C Page 64 of 77 MB9B120J Series

12.6 Low-Voltage Detection Characteristics

12.6.1 Low-Voltage Detection Reset

(TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHR*1 = 00000 2.25 2.45 2.65 V When voltage drops Released voltage VDH 2.30 2.50 2.70 V When voltage rises Detected voltage VDL SVHR*1 = 00001 2.39 2.60 2.81 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00010 2.48 2.70 2.92 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00011 2.58 2.80 3.02 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00100 2.76 3.00 3.24 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00101 2.94 3.20 3.46 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00110 3.31 3.60 3.89 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 00111 3.40 3.70 4.00 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 01000 3.68 4.00 4.32 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 01001 3.77 4.10 4.43 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises Detected voltage VDL SVHR*1 = 01010 3.86 4.20 4.54 V When voltage drops Released voltage VDH Same as SVHR = 0000 value V When voltage rises LVD stabilization wait time tLVDW - - - 8160 × tCYCP*2 μs LVD detection delay time tLVDDL - - - 200 μs *1: SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is reset to SVHR = 00000 by low voltage detection reset. *2: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-05657 Rev.*C Page 65 of 77 MB9B120J Series

12.6.2 Interrupt of Low-Voltage Detection

(TA = - 40°C to + 105°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHI = 00011 2.58 2.80 3.02 V When voltage drops Released voltage VDH 2.67 2.90 3.13 V When voltage rises Detected voltage VDL SVHI = 00100 2.76 3.00 3.24 V When voltage drops Released voltage VDH 2.85 3.10 3.35 V When voltage rises Detected voltage VDL SVHI = 00101 2.94 3.20 3.46 V When voltage drops Released voltage VDH 3.04 3.30 3.56 V When voltage rises Detected voltage VDL SVHI = 00110 3.31 3.60 3.89 V When voltage drops Released voltage VDH 3.40 3.70 4.00 V When voltage rises Detected voltage VDL SVHI = 00111 3.40 3.70 4.00 V When voltage drops Released voltage VDH 3.50 3.80 4.10 V When voltage rises Detected voltage VDL SVHI = 01000 3.68 4.00 4.32 V When voltage drops Released voltage VDH 3.77 4.10 4.43 V When voltage rises Detected voltage VDL SVHI = 01001 3.77 4.10 4.43 V When voltage drops Released voltage VDH 3.86 4.20 4.54 V When voltage rises Detected voltage VDL SVHI = 01010 3.86 4.20 4.54 V When voltage drops Released voltage VDH 3.96 4.30 4.64 V When voltage rises LVD stabilization wait time tLVDW - - - 8160 × tCYCP* μs LVD detection delay time tLVDDL - - - 200 μs *: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-05657 Rev.*C Page 66 of 77 MB9B120J Series

12.7 Flash Memory Write/Erase Characteristics

12.7.1 Write / Erase time

(VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Value Unit Remarks Typ Max Sector erase time 0.3 0.7 s Includes write time prior to internal erase Half word (16-bit) write time 16 282 μs Not including system-level overhead time Chip erase time 2.4 5.6 s Includes write time prior to internal erase *: The typical value is immediately after shipment, the maximum value is guarantee value under 10,000 cycle of erase/write.

12.7.2 Write cycles and data hold time

Erase/write cycles (cycle) Data hold time (year) Remarks 1,000 20* 10,000 10* *: At average + 85°C

Document Number: 002-05657 Rev.*C Page 67 of 77 MB9B120J Series

12.8 Return Time from Low-Power Consumption Mode

12.8.1 Return Factor: Interrupt

The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tICNT tCYCC μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 43 83 μs Low-speed CR Timer mode 310 620 μs Sub Timer mode 534 724 μs RTC mode, Stop mode 278 479 μs *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.

Document Number: 002-05657 Rev.*C Page 68 of 77 MB9B120J Series Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. − See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual.

Document Number: 002-05657 Rev.*C Page 69 of 77 MB9B120J Series

12.8.2 Return Factor: Reset

The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 2.7V to 5.5V, TA = - 40°C to + 105°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tRCNT 149 264 μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 149 264 μs Low-speed CR Timer mode 318 603 μs Sub Timer mode 308 583 μs RTC mode, Stop mode 248 443 μs *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by INITX) INITX tRCNT Internal reset CPU Operation Start Reset active Release

Document Number: 002-05657 Rev.*C Page 70 of 77 MB9B120J Series Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset tRCNT Internal reset CPU Operation Start Reset active Release *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. − See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depends on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. − The time during the power-on reset/low-voltage detection reset is excluded. See 12.4.7. Power-on Reset Timing in 12.4. AC Characteristics in 12.Electrical Characteristics for the detail on the time during the power-on reset/low -voltage detection reset. − When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset.

Document Number: 002-05657 Rev.*C Page 71 of 77 MB9B120J Series 13. Ordering Information Part number Package MB9BF121JPMC Plastic・LQFP32 (0.8 mm pitch), 32 pin (LQB032) MB9BF121JWQN Plastic・QFN32 (0.5 mm pitch), 32 pin (WNU032)

Document Number: 002-05657 Rev.*C Page 72 of 77 MB9B120J Series 14. Package Dimensions DIMENSIONS SYMBOL MIN. NOM. MAX. A 1.60 A1 0.05 0.15 b 0.32 0.43 c 0.13 0.18 D 9.00 BSC D1 7.00 BSC e 0.80 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70

9.00 BSC

7.00 BSC

0.35 0.25 1 8 e b D 5 7 EE1 3 6

0.10 C A-B D

0.20 C A-B D

b SECTION A-A' c SIDE VIEW TOP VIEW A 0.10 C BOTTOM VIEW 1724 4271 7.0X7.0X1.6 MM LQB032 REV*.* PACKAGE OUTLINE, 32 LEAD LQFP Package Type Package Code LQFP 32 LQB032 002-13879 **

Document Number: 002-05657 Rev.*C Page 73 of 77 MB9B120J Series 2. DIMENSIONING AND TOLERANCIN C CONFORMS TO ASME Y14.5-1994. 3. N IS THE TOTAL NU MBER OF TERMINALS. 4. DIMENSION "b" APPLIES TO META LLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL. THE DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE. 6. MAX. PACKAGE WARPAGE IS 0.05mm. 1. ALL DIMENSIONS ARE IN MILLIMETERS. 7. MAXIMUM ALLOWABL E BURRS IS 0.076mm IN ALL DIRECTIONS. 8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE. 9. BILATERAL COPLAN ARITY ZONE APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. NOTE 10. JEDEC SPEC IFICATION NO. REF : N/A DIMENSIONS NOM.MIN. b E

3.20 BSC

5.00 BSC

D A 0.00 SYMBOL MAX. 0.80 0.05

0.50 BSC

L 0.20 0.25 0.30 E 2 3.20 BSC e c 0.25 REF 0.400.35 0.45 SIDE VIEW BOTTOM VIEWTOP VIEW D A E B 0.10 C 0.10 C 0.10 CA A1 0.08 C C SEATING PLANE

0.10 C A B

e b 0.10 C A B 0.05 C c (ND-1) e INDEX MARK L 9 8 2417 PACKAGE OUTLINE, 32 LEAD QFN Package Type Package Code QFN 32 WNU032 002-15907 **

Document Number: 002-05657 Rev.*C Page 74 of 77 MB9B120J Series 15. Major Changes Spansion Publication Number: DS706-00053 Page Section Change Results Revision 0.1 - - Initial release Revision 1.0 - - Preliminary → Data Sheet - - Company name and layout design change

2 Features Revised I2C operation mode name

4 Features Revised Channel number of MFT A/D activation compare

6 Product Lineup ・Revised channel number of MFT A/D activation compare

・Added notes of Built-in high speed CR accuracy

7 Packages Corrected Package code

9 Pin Assignment Corrected Package code

20 I/O Circuit Type Corrected the remarks of type E and F

29 Block Diagram Revised Channel number of MFT A/D activation compare

3.Dc Characteristics(1) Current Rating Revised the values of “TBD” 3.Ac Characteristics(6)Power-On Reset Timing  Revised the values of “TBD” 3.Ac Characteristics(11) I2c Timing ・Revised I2C operation mode name ・Revised the value of noise filter ・Revised the notes explanation 3.Ac Characteristics(12) Swd Timing Added the value of SWDIO delay time 5. 12-Bit A/D Converter Electrical Characteristics ・Added the value of sampling time ・Revised the notes explanation ・Revised the value of Differential Nonlinearity +/-2.5LSB →+/-3.5LSB ・Deleted (Preliminary value) description 7. Flash Memory Write/Erase Characteristics ・Revised the values of “TBD” ・Revised the notes of Erase/write cycles and data hold time ・Deleted (target value) description 69,71

Electrical Characteristics

1. Return Time From Low-Power Consumption Mode Revised the values of “TBD” Revision 2.0

20 I/O Circuit Type Added about +B input

31 Memory Map

• Memory Map(2) Added the summary of Flash memory sector and the note 1. Absolute Maximum Ratings
• Added the Clamp maximum current
• Added about +B input 2. Recommended Operation Conditions Added the note about less than the minimum power supply voltage 41, 42

1. DC Characteristics (1) Current Rating

• Changed the table format
• Added Main Timer mode current

1. AC Characteristics (4-1) Operating Conditions Of Main PLL (4-2) Operating Conditions Of Main PLL Added the figure of Main PLL connection
2. AC Characteristics (6) Power-On Reset Timing Changed the figure of timing 002-15907 **

Document Number: 002-05657 Rev.*C Page 75 of 77 MB9B120J Series Page Section Change Results 50-57

1. Ac Characteristics (8) Csio/Uart Timing

• Modified from UART Timing to CSIO/UART Timing
• Changed from Internal shift clock operation to Master mode
• Changed from External shift clock operation to Slave mode 5. 12bit A/D Converter Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage NOTE: Please see “Document History” about later revised information.

Document Number: 002-05657 Rev.*C Page 76 of 77 MB9B120J Series Document History Document Title: MB9B120J Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller Document Number: 002-05657 Revision ECN Orig. of Change Submission Date Description of Change ** – AKIH 03/31/2015 Migrated to Cypress and assigned document number 002-05657. No change to document contents or format. *A 5167951 AKIH 03/14/2016 Updated to Cypress format. *B 5543718 YSKA 03/08/2017 “Modified RTC description in “Features, Real-Time Clock(RTC)” Changed starting count value from 01 to 00. Deleted “second , or day of the week” in the Interrupt function (Page 2) Updated “12.4.7 Power -On Reset Timing”. Changed parameter from “Power Supply rising time(tVCCR)[ms]” to “Power ramp rate(dV/dt)[mV/us]” and added some comments (Page 46) Updated Package code and dimensions as follows (Page 7-9, 38, 71-73) FPT-32P-M30 -> LQB032, LCC-32P-M73 -> WNU032 Added the Baud rate spec in “12.5.10 CSIO/UART Timing”(Page 48, 50, 52, 54) *C 5774756 YSAT 06/20/2017 Adapted new Cypress logo

Document Number: 002-05657 Rev.*C June 20, 2017 Page 77 of 77 MB9B120J Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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