MB9B460L

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Document overview

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• PDF pages: 122

Technical content

Datasheet sections

• 4.1 List of Pin Numbers
• 4.2 List of Pin Functions
• 6.1 Precautions for Product Design
• 6.2 Precautions for Package Mounting
• 6.3 Precautions for Use Environment
• 12.1 Absolute Maximum Ratings
• 12.2 Recommended Operating Conditions
• 12.3 DC Characteristics
• 12.3.1 Current Rating
• 12.3.2 Pin Characteristics
• 12.4 AC Characteristics
• 12.4.1 Main Clock Input Characteristics
• 12.4.2 Sub Clock Input Characteristics
• 12.4.3 Built-in CR Oscillation Characteristics
• 12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)
• 12.4.6 Reset Input Characteristics
• 12.4.7 Power-on Reset Timing
• 12.4.8 GPIO Output Characteristics
• 12.4.9 Base Timer Input Timing
• 12.4.10 CSIO/UART Timing
• 12.4.11 External Input Timing
• 12.4.12 Quadrature Position/Revolution Counter Timing
• 12.4.13 I2C Timing
• 12.4.14 JTAG Timing
• 12.7 Low-Voltage Detection Characteristics
• 12.7.1 Low-Voltage Detection Reset
• 12.7.2 Interrupt of Low-Voltage Detection
• 12.8 MainFlash Memory Write/Erase Characteristics
• 12.9 WorkFlash Memory Write/Erase Characteristics
• 12.10 Standby Recovery Time
• 12.10.1 Recovery Cause: Interrupt/WKUP

Features

32-bit Arm® Cortex®-M4F Core  Processor version: r0p1  Up to 160 MHz Frequency Operation  FPU built-in  Support DSP instruction  Memory Protection Unit (MPU): improves the reliability of an embedded system  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management On-Chip Memories [Flash Memory] These series are based on two independent on-chip Flash memories.  MainFlash memory  Up to 512 Kbytes  Built-in Flash Accelerator System with 16 Kbytes trace buffer memory  The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System.  Security function for code protection  WorkFlash memory  32 Kbytes  Read cycle:

• 6wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz
• 4wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz
• 2wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz
• 0wait-cycle: the operation frequency up to 40 MHz  Security function is shared with code protection [SRAM] This is composed of three independent SRAMs (SRAM0, SRAM1, and SRAM2). SRAM0 is connected to I-code bus and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core.  SRAM0: Up to 32 Kbytes  SRAM1: Up to 16 Kbytes  SRAM2: Up to 16 Kbytes CAN Interface (1 Channel)  Compatible with CAN Specification 2.0A/B  Maximum transfer rate: 1 Mbps  Built-in 32 message buffer Multi-Function Serial Interface (Max 6 Channels)  64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length.)  Operation mode is selectable from the followings for each channel.  UART  CSIO  LIN  I2C  UART  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)  Various error detect functions available (parity errors, framing errors, and overrun errors)  CSIO  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detect function available  Serial chip select function (ch.6 only)  Supports high-speed SPI (ch.0 and ch.6 only)  Data length 5 to 16-bit

Document Number: 002-04926 Rev.*B Page 2 of 122 MB9B460L Series  LIN  LIN protocol Rev.2.1 supported  Full-duplex double buffer  Master/Slave mode supported  LIN break field generation (can change to 13 to 16-bit length)  LIN break delimiter generation (can change to 1 to 4-bit length)  Various error detect functions available (parity errors, framing errors, and overrun errors)  I2C  Standard mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported  Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A and ch.4=ch.B) supported DMA Controller (8 Channels) DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.  8 independently configured and operated channels  Transfer can be started by software or request from the built-in peripherals  Transfer address area: 32-bit (4 Gbytes)  Transfer mode: Block transfer/Burst transfer/Demand transfer  Transfer data type: bytes/half-word/word  Transfer block count: 1 to 16  Number of transfers: 1 to 65536 DSTC (Descriptor System data Transfer Controller) (128 Channels) The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the Descriptor system and, following the specified contents of the Descriptor which has already been constructed on the memory, can access directly the memory /peripheral device and performs the data transfer operation. It supports the software activation, the hardware activation and the chain activation functions. A/D Converter (Max 15 Channels) [12-bit A/D Converter]  Successive Approximation type  Built-in 2 units  Conversion time: 0.5 μs @ 5 V  Priority conversion available (priority at 2levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) DA Converter (Max 2 Channels)  R-2R type  12-bit resolution Base Timer (Max 8 Channels) Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for external bus or peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up to 48 high-speed general-purpose I/O ports @ 64 pin Package  Some pin is 5 V tolerant I/O. See 4. Pin Description and 5. I/O Circuit Type for the corresponding pins. Multi-Function Timer (Max 2 Units) The Multi-function timer is composed of the following blocks. Minimum resolution: 6.25 ns  16-bit free-run timer × 3 ch./unit  Input capture × 4 ch./unit  Output compare × 6 ch./unit  A/D activation compare × 6 ch./unit  Waveform generator × 3 ch./unit  16-bit PPG timer × 3 ch./unit The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D convertor activate function  DTIF (Motor emergency stop) interrupt function

Document Number: 002-04926 Rev.*B Page 3 of 122 MB9B460L Series Real-Time Clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute /Second/A day of the week from 00 to 99.  Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. Quadrature Position/Revolution Counter (QPRC) (1 Channel) The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.  The detection edge of the three external event input pins AIN, BIN, and ZIN is configurable.  16-bit position counter  16-bit revolution counter  Two 16-bit compare registers Dual Timer (32-/16-bit Down Counter) The Dual Timer consists of two programmable 32-/16-bit down counters. Operation mode is selectable from the followings for each channel.  Free-running  Periodic (=Reload)  One-shot Watch Counter The Watch counter is used for wake up from the low-power consumption mode. It is possible to select the main clock, sub clock, built-in high-speed CR clock or built-in low-speed CR clock as the clock source. Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz External Interrupt Controller Unit  External interrupt input pin: Max 16 pins  Include one non-maskable interrupt (NMI) Watchdog Timer (2 Channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog. "Hardware" watchdog timer is clocked by low-speed internal CR oscillator. Therefore, "Hardware" watchdog is active in any power saving mode except STOP. CRC (Cyclic Redundancy Check) Accelerator The CRC accelerator helps a verify data transmission or storage integrity. CCITT CRC16 and IEEE-802.3 CRC32 are supported.  CCITT CRC16 Generator Polynomial: 0x1021  IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7 Clock and Reset [Clocks] Five clock sources (2 external oscillators, 2 internal CR oscillator, and Main PLL) that are dynamically selectable.  Main clock: 4 MHz to 48 MHz  Sub Clock: 32.768 kHz  High-speed internal CR Clock: 4 MHz  Low-speed internal CR Clock: 100 kHz  Main PLL Clock [Resets]  Reset requests from INITX pin  Power on reset  Software reset  Watchdog timers reset  Low voltage detector reset  Clock supervisor reset Clock Super Visor (CSV) Clocks generated by internal CR oscillators are used to supervise abnormality of the external clocks.  External OSC clock failure (clock stop) is detected, reset is asserted.  External OSC frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the voltage has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation

Document Number: 002-04926 Rev.*B Page 4 of 122 MB9B460L Series Low-Power Consumption Mode Six low-power consumption modes are supported.  SLEEP  TIMER  RTC  STOP  Deep standby RTC (selectable from with/without RAM retention)  Deep standby stop (selectable from with/without RAM retention) VBAT The consumption power during the RTC operation can be reduced by supplying the power supply independent from the RTC (calendar circuit)/32 kHz oscillation circuit. The following circuits can also be used.  RTC  32 kHz oscillation circuit  Power-on circuit  Back up register: 32 bytes  Port circuit Debug  Serial Wire JTAG Debug Port (SWJ-DP) Unique ID Unique value of the device (41-bit) is set. Power Supply Two Power Supplies (when 64 pin Package) One Power Supply (when 48 pin Package)  Wide range voltage: VCC = 2.7 V to 5.5 V  Power supply for VBAT (only 64 pin Package): VBAT = 2.7 V to 5.5 V

Document Number: 002-04926 Rev.*B Page 6 of 122 MB9B460L Series

Document Number: 002-04926 Rev.*B Page 7 of 122 MB9B460L Series 1. Product Lineup Memory Size Product Name MB9BF464K/L MB9BF465K/L MB9BF466K/L MainFlash memory 256 Kbytes 384 Kbytes 512 Kbytes WorkFlash memory 32 Kbytes 32 Kbytes 32 Kbytes On-chip SRAM 32 Kbytes 48 Kbytes 64 Kbytes SRAM0 16 Kbytes 24 Kbytes 32 Kbytes SRAM1 8 Kbytes 12 Kbytes 16 Kbytes SRAM1 8 Kbytes 12 Kbytes 16 Kbytes Function Product Name MB9BF464K MB9BF465K MB9BF466K MB9BF464L MB9BF465L MB9BF466L Pin count 48 64 CPU Cortex-M4F, MPU, NVIC 128ch. Freq. 160 MHz Power supply voltage range 2.7 V to 5.5 V CAN 1ch. DMAC 8ch. DSTC 128ch. Multi-function Serial Interface (UART/CSIO/LIN/I 6ch. (Max) (In ch.1, only I2C is available.) 6ch. (Max) Base Timer (PWC/Reload timer/PWM/PPG) 8ch. (Max) MF Timer A/D activation compare 6ch. 1 unit 2 units (Max) Input capture 4ch. Free-run timer 3ch. Output compare 6ch. Waveform generator 3ch. PPG 3ch. QPRC 1ch. Dual Timer 1 unit Real-Time Clock 1 unit Watch Counter 1 unit CRC Accelerator Yes Watchdog Timer 1ch. (SW) + 1ch. (HW) External Interrupts 15 pins (Max) + NMI × 1 16 pins (Max) + NMI × 1 I/O Ports 33 pins (Max) 48 pins (Max) 12-bit A/D Converter 8ch. (2 units) 15ch. (2 units) 12-bit D/A Converter 2 units (Max) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. Built-in CR High-speed 4 MHz Low-speed 100 kHz Debug Function SWJ-DP Unique ID Yes Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. built-in CR.

Document Number: 002-04926 Rev.*B Page 8 of 122 MB9B460L Series 2. Packages Product Name Package MB9BF464K MB9BF465K MB9BF466K MB9BF464L MB9BF465L MB9BF466L LQFP: LQG064 (0.65mm pitch) -  LQFP: LQD064 (0.5mm pitch) -  LQFP: LQA048 (0.5mm pitch)  - QFN: VNC064 (0.5mm pitch) -  QFN: VNA048 (0.5mm pitch)  - : Supported Note: − See 14. Package Dimensions for detailed information on each package.

Document Number: 002-04926 Rev.*B Page 9 of 122 MB9B460L Series 3. Pin Assignment LQD064/LQG064 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81 P80 VCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P62/AN13/SIN1_1/RX0_0/TIOB3_1/INT14_1 P63/AN12/SIN0_1/TX0_0/TIOA3_1/INT13_1/ADTG_4 P64/AN11/SOT0_1/TIOB2_1/INT12_1 P65/AN10/SCK0_1/TIOA2_1/INT11_1/RTCCO_0/SUBOUT_0 P66/AN09/INT10_1/IC13_0/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO VCC 1 48 P26/AN08/SIN1_0/INT09_1/IC12_0 P50/AIN0_0/INT00_0/TIOA0_0/CTS4_0 2 47 P25/AN07/SOT1_0/INT08_1/IC11_0/CROUT_0 P51/BIN0_0/INT01_0/TIOB0_0/RTS4_0 3 46 P24/AN06/SCK1_0/INT07_1/IC10_0 P52/IC00_0/ZIN0_0/INT02_0/TIOA1_0/SIN4_0 4 45 P23/AN05/SCK0_0/TIOB1_1/INT06_1/DTTI1X_0 P53/IC01_0/INT03_0/TIOB1_0/SOT4_0 5 44 P22/AN04/SOT0_0/TIOA1_1/INT05_1/FRCK1_0 P54/IC02_0/INT04_0/TIOA2_0/SCK4_0 6 43 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1/RTO15_0 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 7 42 AVR H P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 8 41 AVR L P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 9 40 AVSS P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 10 39 AVC C P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 11 38 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTO14_0/RTCCO_1/SUBOUT_1/WKUP1 P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 12 37 P13/AN01/SOT6_0/TIOB7_1/RTO13_0/IC00_1/TX0_1 P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 13 36 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/RTO12_0/IC01_1/RX0_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 14 35 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/RTO11_0/IC02_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 15 34 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/RTO10_0/IC03_1 VSS 16 33 VCC P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP INITX C VSS VCC P40/TIOA7_0/INT14_0 P41/TIOB7_0/INT15_0/ADTG_1/WKUP3 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 64

Document Number: 002-04926 Rev.*B Page 10 of 122 MB9B460L Series VNC064 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81 P80 VCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P62/AN13/SIN1_1/RX0_0/TIOB3_1/INT14_1 P63/AN12/SIN0_1/TX0_0/TIOA3_1/INT13_1/ADTG_4 P64/AN11/SOT0_1/TIOB2_1/INT12_1 P65/AN10/SCK0_1/TIOA2_1/INT11_1/RTCCO_0/SUBOUT_0 P66/AN09/INT10_1/IC13_0/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO VCC 1 48 P26/AN08/SIN1_0/INT09_1/IC12_0 P50/AIN0_0/INT00_0/TIOA0_0/CTS4_0 2 47 P25/AN07/SOT1_0/INT08_1/IC11_0/CROUT_0 P51/BIN0_0/INT01_0/TIOB0_0/RTS4_0 3 46 P24/AN06/SCK1_0/INT07_1/IC10_0 P52/IC00_0/ZIN0_0/INT02_0/TIOA1_0/SIN4_0 4 45 P23/AN05/SCK0_0/TIOB1_1/INT06_1/DTTI1X_0 P53/IC01_0/INT03_0/TIOB1_0/SOT4_0 5 44 P22/AN04/SOT0_0/TIOA1_1/INT05_1/FRCK1_0 P54/IC02_0/INT04_0/TIOA2_0/SCK4_0 6 43 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1/RTO15_0 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 7 42 AVR H P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 8 41 AVR L P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 9 40 AVSS P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 10 39 AVC C P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 11 38 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTO14_0/RTCCO_1/SUBOUT_1/WKUP1 P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 12 37 P13/AN01/SOT6_0/TIOB7_1/RTO13_0/IC00_1/TX0_1 P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 13 36 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/RTO12_0/IC01_1/RX0_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 14 35 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/RTO11_0/IC02_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 15 34 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/RTO10_0/IC03_1 VSS 16 33 VCC P46/X0A P47/X1A VBAT P48/VREGCTL P49/VWAKEUP INITX C VSS VCC P40/TIOA7_0/INT14_0 P41/TIOB7_0/INT15_0/ADTG_1/WKUP3 PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN- 64

Document Number: 002-04926 Rev.*B Page 11 of 122 MB9B460L Series LQA048 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81 P80 VCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P66/AN09/INT10_1/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO VCC 1 36 P23/AN05/SCK0_0/TIOB1_1/INT06_1 P54/IC02_0/INT04_0/TIOA2_0 2 35 P22/AN04/SOT0_0/TIOA1_1/INT05_1 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 3 34 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1 P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 4 33 AVR H P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 5 32 AVR L P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 6 31 AVSS P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 7 30 AVC C P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 8 29 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTCCO_1/SUBOUT_1/WKUP1 P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 9 28 P13/AN01/SOT6_0/TIOB7_1/IC00_1/TX0_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 10 27 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/IC01_1/RX0_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 11 26 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/IC02_1 VSS 12 25 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/IC03_1 P46/X0A P47/X1A VCC INITX C VSS VCC PE0/MD1 MD0 PE2/X0 PE3/X1 VSS LQFP - 48

Document Number: 002-04926 Rev.*B Page 12 of 122 MB9B460L Series VNA048 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P81 P80 VCC P60/SCK1_1/NMIX/WKUP0/IC01_2 P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2 P66/AN09/INT10_1/CROUT_1 P00/TRSTX P01/TCK/SWCLK P02/TDI P03/TMS/SWDIO P04/TDO/SWO VCC 1 36 P23/AN05/SCK0_0/TIOB1_1/INT06_1 P54/IC02_0/INT04_0/TIOA2_0 2 35 P22/AN04/SOT0_0/TIOA1_1/INT05_1 P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 3 34 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1 P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 4 33 AVR H P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 5 32 AVR L P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 6 31 AVSS P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 7 30 AVC C P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 8 29 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTCCO_1/SUBOUT_1/WKUP1 P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 9 28 P13/AN01/SOT6_0/TIOB7_1/IC00_1/TX0_1 P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 10 27 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/IC01_1/RX0_1 P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 11 26 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/IC02_1 VSS 12 25 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/IC03_1 P46/X0A P47/X1A VCC INITX C VSS VCC PE0/MD1 MD0 PE2/X0 PE3/X1 VSS QFN - 48

Document Number: 002-04926 Rev.*B Page 13 of 122 MB9B460L Series 4. Pin Description

4.1 List of Pin Numbers

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Pin Name I/O Circuit Type Pin State Type LQFP64 QFN64 LQFP48 QFN48 1 1 VCC - - 2 - P50 E K AIN0_0 INT00_0 TIOA0_0 CTS4_0 3 - P51 E K BIN0_0 INT01_0 TIOB0_0 RTS4_0 4 - P52 I K IC00_0 ZIN0_0 INT02_0 TIOA1_0 SIN4_0 5 - P53 N K IC01_0 INT03_0 TIOB1_0 SOT4_0 (SDA4_0) P54 N K IC02_0 INT04_0 TIOA2_0 - SCK4_0 (SCL4_0) 7 3 P55 I K IC03_0 INT05_0 TIOB2_0 SIN3_0 8 4 P56 N K FRCK0_0 INT06_0 TIOA3_0 SOT3_0 (SDA3_0)

Document Number: 002-04926 Rev.*B Page 14 of 122 MB9B460L Series Pin No Pin Name I/O Circuit Type Pin State Type LQFP64 QFN64 LQFP48 QFN48 9 5 P57 N K DTTI0X_0 INT07_0 TIOB3_0 SCK3_0 (SCL3_0) ADTG_0 10 6 P30 G K RTO00_0 AIN0_1 INT08_0 TIOA4_0 SIN2_0 11 7 P31 G K RTO01_0 BIN0_1 INT09_0 TIOB4_0 SOT2_0 (SDA2_0) 12 8 P32 G K RTO02_0 ZIN0_1 INT10_0 TIOA5_0 SCK2_0 (SCL2_0) 13 9 P33 G K RTO03_0 INT11_0 TIOB5_0 SIN4_1 14 10 P34 G K RTO04_0 INT12_0 TIOA6_0 SOT4_1 (SDA4_1) 15 11 P35 G Q WKUP2 RTO05_0 INT13_0 TIOB6_0 SCK4_1 (SCL4_1)

Document Number: 002-04926 Rev.*B Page 15 of 122 MB9B460L Series Pin No Pin Name I/O Circuit Type Pin State Type LQFP64 QFN64 LQFP48 QFN48 16 12 VSS - - 17 13 P46 P S X0A 18 14 P47 Q T X1A

19 VBAT - -

15 VCC - -

E K TIOA7_0 INT14_0 27 - P41 E Q TIOB7_0 INT15_0 ADTG_1 WKUP3 28 20 PE0 C E MD1 29 21 MD0 J D 30 22 PE2 A A X0 31 23 PE3 A B X1 32 24 VSS - - 33 - VCC - - 34 25 P10 R J DA0 TIOA4_1 INT00_1 AIN0_2 IC03_1 - RTO10_0 35 26 P11 R J DA1 ADTG_2 SCS6_0 TIOB4_1 INT01_1 BIN0_2 IC02_1 - RTO11_0

Document Number: 002-04926 Rev.*B Page 16 of 122 MB9B460L Series Pin No Pin Name I/O Circuit Type Pin State Type LQFP64 QFN64 LQFP48 QFN48 36 27 P12 M M AN00 SCK6_0 TIOA7_1 INT02_1 ZIN0_2 IC01_1 RX0_1 - RTO12_0 37 28 P13 M L AN01 SOT6_0 (SDA6_0) TIOB7_1 IC00_1 TX0_1 - RTO13_0 38 29 P20 F O AN02 SIN6_0 TIOA0_1 INT03_1 RTCCO_1 SUBOUT_1 WKUP1 - RTO14_0 39 30 AVCC - - 40 31 AVSS - - 41 32 AVRL - - 42 33 AVRH - - 43 34 P21 F M AN03 ADTG_3 SIN0_0 TIOB0_1 INT04_1 - RTO15_0 44 35 P22 F M AN04 SOT0_0 (SDA0_0) TIOA1_1 INT05_1 - FRCK1_0 45 36 P23 F M AN05 SCK0_0 (SCL0_0) TIOB1_1 INT06_1 - DTTI1X_0

Document Number: 002-04926 Rev.*B Page 17 of 122 MB9B460L Series Pin No Pin Name I/O Circuit Type Pin State Type LQFP64 QFN64 LQFP48 QFN48 46 - P24 F M AN06 SCK1_0 (SCL1_0) INT07_1 IC10_0 47 - P25 F M AN07 SOT1_0 (SDA1_0) INT08_1 IC11_0 CROUT_0 48 - P26 F M AN08 SIN1_0 INT09_1 IC12_0 49 37 P04 E G TDO SWO 50 38 P03 E G TMS SWDIO 51 39 P02 E G TDI 52 40 P01 E G TCK SWCLK 53 41 P00 E G TRSTX 54 42 P66 F M AN09 INT10_1 CROUT_1 - IC13_0 55 - P65 L M AN10 SCK0_1 (SCL0_1) TIOA2_1 INT11_1 RTCCO_0 SUBOUT_0 56 - P64 L M AN11 SOT0_1 (SDA0_1) TIOB2_1 INT12_1

Document Number: 002-04926 Rev.*B Page 18 of 122 MB9B460L Series Pin No Pin Name I/O Circuit Type Pin State Type LQFP64 QFN64 LQFP48 QFN48 57 - P63 F M AN12 SIN0_1 TX0_0 TIOA3_1 INT13_1 ADTG_4 58 - P62 F M AN13 SIN1_1 RX0_0 TIOB3_1 INT14_1 59 43 P61 F M AN14 ADTG_5 SOT1_1 (SDA1_1) INT15_1 IC00_2 60 44 P60 I F SCK1_1 (SCK1_1) NMIX WKUP0 IC01_2 61 45 VCC - - 62 46 P80 H R 63 47 P81 H R 64 48 VSS - -

Document Number: 002-04926 Rev.*B Page 19 of 122 MB9B460L Series

4.2 List of Pin Functions

The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin Function Pin Name Function Description Pin No LQFP64 QFN64 LQFP48 QFN48 ADC ADTG_0 A/D converter external trigger input pin 9 5 ADTG_1 27 - ADTG_2 35 26 ADTG_3 43 34 ADTG_4 57 - ADTG_5 59 43 AN00 A/D converter analog input pin. ANxx describes ADC ch.xx. 36 27 AN01 37 28 AN02 38 29 AN03 43 34 AN04 44 35 AN05 45 36 AN06 46 - AN07 47 - AN08 48 - AN09 54 42 AN10 55 - AN11 56 - AN12 57 - AN13 58 - AN14 59 43 Base Timer TIOA0_0 Base timer ch.0 TIOA pin 2 - TIOA0_1 38 29 TIOB0_0 Base timer ch.0 TIOB pin 3 - TIOB0_1 43 34 Base Timer TIOA1_0 Base timer ch.1 TIOA pin 4 - TIOA1_1 44 35 TIOB1_0 Base timer ch.1 TIOB pin 5 - TIOB1_1 45 36 Base Timer TIOA2_0 Base timer ch.2 TIOA pin 6 2 TIOA2_1 55 - TIOB2_0 Base timer ch.2 TIOB pin 7 3 TIOB2_1 56 - Base Timer TIOA3_0 Base timer ch.3 TIOA pin 8 4 TIOA3_1 57 - TIOB3_0 Base timer ch.3 TIOB pin 9 5 TIOB3_1 58 - Base Timer TIOA4_0 Base timer ch.4 TIOA pin 10 6 TIOA4_1 34 25 TIOB4_0 Base timer ch.4 TIOB pin 11 7 TIOB4_1 35 26 Base Timer TIOA5_0 Base timer ch.5 TIOA pin 12 8 TIOB5_0 Base timer ch.5 TIOB pin 13 9

Document Number: 002-04926 Rev.*B Page 20 of 122 MB9B460L Series Pin Function Pin Name Function Description Pin No LQFP64 QFN64 LQFP48 QFN48 Base Timer TIOA6_0 Base timer ch.6 TIOA pin 14 10 TIOB6_0 Base timer ch.6 TIOB pin 15 11 Base Timer TIOA7_0 Base timer ch.7 TIOA pin 26 - TIOA7_1 36 27 TIOB7_0 Base timer ch.7 TIOB pin 27 - TIOB7_1 37 28 CAN 0 TX0_0 CAN interface ch.0 TX output pin 57 - TX0_1 37 28 RX0_0 CAN interface ch.0 RX output pin 58 - RX0_1 36 27 Debugger SWCLK Serial wire debug interface clock input pin 52 40 SWDIO Serial wire debug interface data input / output pin 50 38 SWO Serial wire viewer output pin 49 37 TCK JTAG test clock input pin 52 40 TDI JTAG test data input pin 51 39 TDO JTAG debug data output pin 49 37 TMS JTAG test mode state input/output pin 50 38 TRSTX JTAG test reset Input pin 53 41 External Interrupt INT00_0 External interrupt request 00 input pin 2 - INT00_1 34 25 INT01_0 External interrupt request 01 input pin 3 - INT01_1 35 26 INT02_0 External interrupt request 02 input pin 4 - INT02_1 36 27 INT03_0 External interrupt request 03 input pin 5 - INT03_1 38 29 INT04_0 External interrupt request 04 input pin 6 2 INT04_1 43 34 INT05_0 External interrupt request 05 input pin 7 3 INT05_1 44 35

Document Number: 002-04926 Rev.*B Page 21 of 122 MB9B460L Series Pin Function Pin Name Function Description Pin No LQFP64 QFN64 LQFP48 QFN48 External Interrupt INT06_0 External interrupt request 06 input pin 8 4 INT06_1 45 36 INT07_0 External interrupt request 07 input pin 9 5 INT07_1 46 - INT08_0 External interrupt request 08 input pin 10 6 INT08_1 47 - INT09_0 External interrupt request 09 input pin 11 7 INT09_1 48 - INT10_0 External interrupt request 10 input pin 12 8 INT10_1 54 42 INT11_0 External interrupt request 11 input pin 13 9 INT11_1 55 - INT12_0 External interrupt request 12 input pin 14 10 INT12_1 56 - INT13_0 External interrupt request 13 input pin 15 11 INT13_1 57 - INT14_0 External interrupt request 14 input pin 26 - INT14_1 58 - INT15_0 External interrupt request 15 input pin 27 - INT15_1 59 43 NMIX Non-Maskable Interrupt input pin 60 44 GPIO P00 General-purpose I/O port 0 53 41 P01 52 40 P02 51 39 P03 50 38 P04 49 37 P10 General-purpose I/O port 1 34 25 P11 35 26 P12 36 27 P13 37 28 P20 General-purpose I/O port 2 38 29 P21 43 34 P22 44 35 P23 45 36 P24 46 - P25 47 - P26 48 - P30 General-purpose I/O port 3 10 6 P31 11 7 P32 12 8 P33 13 9 P34 14 10 P35 15 11

Document Number: 002-04926 Rev.*B Page 22 of 122 MB9B460L Series Pin Function Pin Name Function Description Pin No LQFP64 QFN64 LQFP48 QFN48 GPIO P40 General-purpose I/O port 4 26 - P41 27 - P46 17 13 P47 18 14 P48 20 - P49 21 - P50 General-purpose I/O port 5 2 - P51 3 - P52 4 - P53 5 - P54 6 2 P55 7 3 P56 8 4 P57 9 5 P60 General-purpose I/O port 6 60 44 P61 59 43 P62 58 - P63 57 - P64 56 - P65 55 - P66 54 42 P80 General-purpose I/O port 8 62 46 P81 63 47 PE0 General-purpose I/O port E 28 20 PE2 30 22 PE3 31 23

Document Number: 002-04926 Rev.*B Page 23 of 122 MB9B460L Series Pin Function Pin Name Function Description Pin No LQFP64 QFN64 LQFP48 QFN48 Multi- function Serial SIN0_0 Multi-function serial interface ch.0 input pin 43 34 SIN0_1 57 - SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA0 when it is used in an I C (operation mode 4). 44 35 SOT0_1 (SDA0_1) 56 - SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a CSIO (operation modes 2) and as SCL0 when it is used in an I C (operation mode 4). 45 36 SCK0_1 (SCL0_1) 55 - Multi- function Serial SIN1_0 Multi-function serial interface ch.1 input pin 48 - SIN1_1 58 - SOT1_0 (SDA1_0) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA1 when it is used in an I C (operation mode 4). 47 - SOT1_1 (SDA1_1) 59 43 SCK1_0 (SCL1_0) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a CSIO (operation modes 2) and as SCL1 when it is used in an I C (operation mode 4). 46 - SCK1_1 (SCL1_1) 60 44 Multi- function Serial SIN2_0 Multi-function serial interface ch.2 input pin 10 6 SOT2_0 (SDA2_0) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA2 when it is used in an I C (operation mode 4). 11 7 SCK2_0 (SCL2_0) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a CSIO (operation modes 2) and as SCL2 when it is used in an I C (operation mode 4). 12 8

Document Number: 002-04926 Rev.*B Page 24 of 122 MB9B460L Series Pin Function Pin Name Function Description Pin No LQFP64 QFN64 LQFP48 QFN48 Multi- function Serial SIN3_0 Multi-function serial interface ch.3 input pin 7 3 SOT3_0 (SDA3_0) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA3 when it is used in an I C (operation mode 4). 8 4 SCK3_0 (SCL3_0) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a CSIO (operation modes 2) and as SCL3 when it is used in an I C (operation mode 4). 9 5 Multi- function Serial SIN4_0 Multi-function serial interface ch.4 input pin 4 - SIN4_1 13 9 SOT4_0 (SDA4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA4 when it is used in an I C (operation mode 4). 5 - SOT4_1 (SDA4_1) 14 10 SCK4_0 (SCL4_0) Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a CSIO (operation modes 2) and as SCL4 when it is used in an I C (operation mode 4). 6 - SCK4_1 (SCL4_1) 15 11 CTS4_0 Multi-function serial interface ch.4 CTS input pin 2 - RTS4_0 Multi-function serial interface ch.4 RTS output pin 3 - Multi- function Serial SIN6_0 Multi-function serial interface ch.6 input pin 38 29 SOT6_0 (SDA6_0) This pin operates as SOT6 when it is used in a UART/CSIO/LIN (operation modes 0 to 3) and as SDA6 when it is used in an I C (operation mode 4). 37 28 SCK6_0 (SCL6_0) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a CSIO (operation modes 2) and as SCL6 when it is used in an I C (operation mode 4). 36 27 SCS6_0 Multi-function serial interface ch.6 serial chip select pin 35 26

Document Number: 002-04926 Rev.*B Page 25 of 122 MB9B460L Series Pin Function Pin Name Function Description Pin No LQFP64 QFN64 LQFP48 QFN48 Multi- function Timer DTTI0X_0 Input signal controlling wave form generator outputs RTO00 to RTO05 of Multi-function timer 0. 9 5 FRCK0_0 16-bit free-run timer ch.0 external clock input pin 8 4 IC00_0 16-bit input capture ch.0 input pin of Multi-function timer 0. ICxx describes channel number. 4 - IC00_1 37 28 IC00_2 59 43 IC01_0 5 - IC01_1 36 27 IC01_2 60 44 IC02_0 6 2 IC02_1 35 26 IC03_0 7 3 IC03_1 34 25 RTO00_0 (PPG00_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 10 6 RTO01_0 (PPG00_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 11 7 RTO02_0 (PPG02_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 12 8 RTO03_0 (PPG02_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 13 9 RTO04_0 (PPG04_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 14 10 RTO05_0 (PPG04_0) Wave form generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 15 11

Document Number: 002-04926 Rev.*B Page 26 of 122 MB9B460L Series Pin Function Pin Name Function Description Pin No LQFP64 QFN64 LQFP48 QFN48 Multi- function Timer DTTI1X_0 Input signal controlling wave form generator outputs RTO10 to RTO15 of Multi-function timer 1. 45 - FRCK1_0 16-bit free-run timer ch.1 external clock input pin 44 - IC10_0 16-bit input capture ch.1 input pin of Multi-function timer 1. ICxx describes channel number. 46 - IC11_0 47 - IC12_0 48 - IC13_0 54 - RTO10_0 (PPG10_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 34 - RTO11_0 (PPG10_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG10 when it is used in PPG1 output modes. 35 - RTO12_0 (PPG12_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 36 - RTO13_0 (PPG12_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG12 when it is used in PPG1 output modes. 37 - RTO14_0 (PPG14_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 38 - RTO15_0 (PPG14_0) Wave form generator output pin of Multi-function timer 1. This pin operates as PPG14 when it is used in PPG1 output modes. 43 - Quadrature Position/ Revolution Counter AIN0_0 QPRC ch.0 AIN input pin 2 - AIN0_1 10 6 AIN0_2 34 25 BIN0_0 QPRC ch.0 BIN input pin 3 - BIN0_1 11 7 BIN0_2 35 26 ZIN0_0 QPRC ch.0 ZIN input pin 4 - ZIN0_1 12 8 ZIN0_2 36 36

Document Number: 002-04926 Rev.*B Page 27 of 122 MB9B460L Series Pin Function Pin Name Function Description Pin No LQFP64 QFN64 LQFP48 QFN48 Real-time clock RTCCO_0 0.5 seconds pulse output pin of Real-time clock Sub clock output pin 55 - RTCCO_1 38 29 SUBOUT_0 Sub clock output pin 55 - SUBOUT_1 38 29 Low-Power Consumpti on Mode WKUP0 Deep standby mode return signal input pin 0 60 44 WKUP1 Deep standby mode return signal input pin 1 38 29 WKUP2 Deep standby mode return signal input pin 2 15 11 WKUP3 Deep standby mode return signal input pin 3 27 - DAC DA0 D/A converter ch.0 analog output pin 34 25 DA1 D/A converter ch.1 analog output pin 35 26 VBAT VREGCTL On-board regulator control pin 20 - VWAKEUP The return signal input pin from a hibernation state 21 - Reset INITX External Reset Input pin. A reset is valid when INITX="L". 22 16 Mode MD1 Mode 1 pin. During serial programming to Flash memory, MD1="L" must be input. 28 20 MD0 Mode 0 pin. During normal operation, MD0="L" must be input. During serial programming to Flash memory, MD0="H" must be input. 29 21 Power VCC Power supply Pin 1 1 - 15 25 19 33 - 61 45 GND VSS GND Pin 16 12 24 18 32 24 64 48 Clock X0 Main clock (oscillation) input pin 30 22 X1 Main clock (oscillation) I/O pin 31 23 X0A Sub clock (oscillation) input pin 17 13 X1A Sub clock (oscillation) I/O pin 18 14 CROUT_0 Built-in high-speed CR-osc clock output port 47 - CROUT_1 54 42 Analog Power AVCC A/D converter and D/A converter analog power supply pin 39 30 AVRH A/D converter analog reference voltage input pin 42 33 VBAT Power VBAT VBAT power supply pin. Backup power supply (battery etc.) and system power supply. 19 - Analog GND AVSS A/D converter and D/A converter GND pin 40 31 AVRL A/D converter analog reference voltage input pin 41 32 C pin C Power supply stabilization capacity pin 23 17 Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller.

Document Number: 002-04926 Rev.*B Page 28 of 122 MB9B460L Series 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function When the main oscillation is selected. − Oscillation feedback resistor : Approximately 1 MΩ − With Standby mode control When the GPIO is selected. − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA B − CMOS level hysteresis input − Pull-up resistor : Approximately 50 kΩ P-chP-ch N-ch R R P-chP-ch N-ch Standby mode control Digital input Standby mode control Digital output Digital output Clock input Digital input Standby mode control Pull-up resistor control Pull-up resistor control Digital output Digital output Pull-up resistor Digital input

Document Number: 002-04926 Rev.*B Page 29 of 122 MB9B460L Series Type Circuit Remarks C − Open drain output − CMOS level hysteresis input E − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA F − CMOS level output − CMOS level hysteresis input − With input control − Analog input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − When this pin is used as an I C pin, the digital output P-ch transistor is always off N-ch P-chP-ch N-ch R P-chP-ch N-ch R Digital input Digital output Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control

Document Number: 002-04926 Rev.*B Page 30 of 122 MB9B460L Series Type Circuit Remarks G − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -12 mA, IOL = 12 mA − When this pin is used as an I C pin, the digital output P-ch transistor is always off H − CMOS level output − CMOS level hysteresis input − With standby mode control − IOH = -20.5 mA, IOL = 18.5 mA P-chP-ch N-ch R P-ch N-ch R Standby mode control Pull-up resistor control Digital input Digital output Digital output Digital output Digital input Digital output Standby mode control

Document Number: 002-04926 Rev.*B Page 31 of 122 MB9B460L Series Type Circuit Remarks I − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − 5 V tolerant − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − Available to control of PZR registers. − When this pin is used as an I C pin, the digital output P-ch transistor is always off J CMOS level hysteresis input L − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -8 mA, IOL = 8 mA − When this pin is used as an I C pin, the digital output P-ch transistor is always off P-chP-ch N-ch R P-chP-ch N-ch R Standby mode control Pull-up resistor control Digital input Digital output Digital output Mode input Digital output Digital output Pull-up resistor control Digital input Standby mode control

Document Number: 002-04926 Rev.*B Page 32 of 122 MB9B460L Series Type Circuit Remarks M − CMOS level output − CMOS level hysteresis input − With input control − Analog input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -8 mA, IOL = 8 mA − When this pin is used as an I C pin, the digital output P-ch transistor is always off N − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA (GPIO) − IOL = 20 mA (Fast Mode Plus) − When this pin is used as an I C pin, the digital output P-ch transistor is always off P-chP-ch N-ch R P-ch N-ch R P-ch N-ch Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control Digital output Digital output Pull-up resistor control Digital input Standby mode control Fast mode control

Document Number: 002-04926 Rev.*B Page 33 of 122 MB9B460L Series Type Circuit Remarks O − CMOS level output − CMOS level hysteresis input − 5 V tolerant − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual P − CMOS level output − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual P-ch P-ch N-ch R P-ch P-ch N-ch R Digital output Digital output Digital input Pull-up resistor control Standby mode control Digital output Digital output Digital input Pull-up resistor control Standby mode control OSC X0A

Document Number: 002-04926 Rev.*B Page 34 of 122 MB9B460L Series Type Circuit Remarks Q It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected. − Oscillation feedback resistor : Approximately 10 MΩ − With Standby mode control When the GPIO is selected. − CMOS level output. − CMOS level hysteresis input − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -4 mA, IOL = 4 mA − For I/O setting, refer to VBAT Domain in the Peripheral Manual R − CMOS level output − CMOS level hysteresis input − With input control − Analog output − With pull-up resistor control − With standby mode control − Pull-up resistor : Approximately 50 kΩ − IOH = -12 mA, IOL = 12 mA (4.5 V to 5.5 V) − IOH = -8 mA, IOL = 8 mA (2.7 V to 4.5 V) P-ch P-ch N-ch R RX P-chP-ch N-ch R X1A Digital output Digital output Digital input Pull-up resistor control Standby mode control OSC Standby mode control Clock input Pull-up resistor control Digital input Standby mode control Analog output Digital output Digital output

Document Number: 002-04926 Rev.*B Page 35 of 122 MB9B460L Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

6.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev ice, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-Up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

Document Number: 002-04926 Rev.*B Page 36 of 122 MB9B460L Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

6.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress's recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and have established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h

Document Number: 002-04926 Rev.*B Page 37 of 122 MB9B460L Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of Styrofoam or other highly static-prone materials for storage of completed board assemblies.

6.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives.

Document Number: 002-04926 Rev.*B Page 38 of 122 MB9B460L Series 7. Handling Devices Power Supply Pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each POWER pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and VSS near this device. Power Supply Pins A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power supply. Crystal Oscillator Circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Sub Crystal Oscillator This series sub oscillator circuit is low gain to keep the low current consumption. The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation.

• Surface mount type Size: More than 3.2 mm × 1.5 mm Load capacitance: Approximately 6 pF to 7 pF
• Lead type Load capacitance: Approximately 6 pF to 7 pF Using an External Clock When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1 (PE3) can be used as a general-purpose I/O port. Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port. Example of Using an External Clock Device X0(X0A) X1(PE3), X1A (P47) Can be used as general-purpose I/O ports. Set as External clock input

Document Number: 002-04926 Rev.*B Page 39 of 122 MB9B460L Series Handling when Using Multi-Function Serial Pin as I2C Pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF. C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7 μF would be recommended for this series. Mode Pins (MD0) Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on Power-on Turn power on/off in the following order or at the same time. The device operates normally after all power on. In the case of 64pin package, VBAT only Power-on is possible when turns all power on and Hibernation control is setting and then except for VBAT turns power off. About Hibernation control, see Chapter 7-2: VBAT Domain (A) in FM4 Family Peripheral Manual (002-04856). If not using the A/D converter and D/A converter, connect AVCC = VCC and AVSS = VSS. Turning on: VBAT → VCC VCC → AVCC → AVRH Turning off: AVRH → AVCC → VCC VCC → VBAT Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in Features among the Products with Different Memory Sizes and between Flash Products and MASK Products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Pull-Up Function of 5 V Tolerant I/O Please do not input the signal more than VCC voltage at the time of pull-up function use of 5V tolerant I/O. Device C VSS CS GND

Document Number: 002-04926 Rev.*B Page 40 of 122 MB9B460L Series Handling when Using Debug Pins When debug pins (TDO/TMS/TDI/TCK/TRSTX or SWO/SWDIO/SWCLK) are set to GPIO or other peripheral functions, only set them as output, do not set them as input.

Document Number: 002-04926 Rev.*B Page 41 of 122 MB9B460L Series 8. Block Diagram Cortex-M4F Core @160 MHz(Max) MainFlash I/F Clock Reset Generator Dual-Timer Watchdog Timer (Hardware) DMAC 8ch. Watch Counter Unit 0 CSV External Interrupt Controller 16pin + NMI Power-On Reset SRAM0 16/24/32 Kbytes AHB -AP B Bridg e APB ax 160 M Hz SRAM1 8/12/16 Kbytes AHB -APB Bridge AP B 0(M ax M Hz I D Sys CLK MB9BF464K/L, F465K/L, F466K/L AHB -APB Bridge APB ax M Hz NVIC Watchdog Timer (Software) Security Unit 1 TRSTX,TCK, TDI,TMS AVCC, AVSS, AVRH ANxx TIOAx TIOBx C TDO X0A X1A SCKx SINx SOTx INTxx NMIX P0x, P1x, PEx INITX MODE-Ctrl IRQ-Monitor MD0, MD1 Regulator CRC Accelerator AHB -AHB Bridg e ADTGx RTS4 CTS4 MainFlash

512 Kbytes/

384 Kbytes/

256 Kbytes

6ch. HW flow control(ch.4) GPIO PIN-Function- Ctrl LVD M ulti -layer AHB ax M Hz ROM Table SWJ-DP Main Osc PLL CR 100 kHz LVD Ctrl Base Timer 16-bit 16ch./ 32-bit 8ch. Peripheral Clock Gating Low-speed CR Prescaler RTCCO, SUBOUT Deep Standby Ctrl WKUPx 16-bit Free-run Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. A/D Activation Compare 6ch. 16-bit PPG 3ch. DTTIxX FRCKx QPRC 1ch.BINx ZINx ICxx RTOxx AINx 12-bit A/D Converter Multi-function Timer × 2 Waveform Generator 3ch. MPUFPU 12-bit D/A Converter 2units SRAM2 8/12/16 Kbytes WorkFlash

32 KbytesWorkFlash I/F

(16 Kbytes) DSTC CAN TX0, RX0 CAN Prescaler VREGCTL VWAKEUP DAx Real-Time Clock Port Ctrl. Sub Osc VBAT Domain VBAT Domain CR

4 MHz

Document Number: 002-04926 Rev.*B Page 42 of 122 MB9B460L Series 9. Memory Size See Memory size in 1. Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0x4007_0000 0x4006_F000 GPIO 0xFFFF_FFFF 0x4006_3000 0x4006_2000 CAN ch.0 0xE010_0000 0x4006_1000 DSTC 0x4006_0000 DMAC 0xE000_0000 0x4003_C800 0x4003_C100 Peripheral Clock Gating 0x4003_C000 Low Speed CR Prescaler 0x6000_0000 0x4003_B000 RTC/Port Ctrl 0x4003_A000 Watch Counter 0x4003_9000 CRC 0x4400_0000 0x4003_8000 MFS 0x4003_7000 CAN prescaler 0x4200_0000 0x4003_6000 Reserved 0x4003_5000 LVD/DS mode 0x4003_4000 Reserved 0x4000_0000 0x4003_3000 D/AC 0x4003_2000 Reserved 0x4003_1000 Int-Req.Read 0x2400_0000 0x4003_0000 EXTI 0x4002_F000 Reserved 0x2200_0000 0x4002_E000 CR Trim 0x4002_8000 0x2010_0000 0x4002_7000 A/DC 0x200E_0000 WorkFlash I/F 0x4002_6000 QPRC 0x200C_0000 WorkFlash 0x4002_5000 Base Timer 0x4002_4000 PPG 0x2004_4000 0x2004_0000 SRAM2 0x4002_2000 0x2003_C000 SRAM1 0x4002_1000 MFT Unit1 0x2000_0000 Reserved 0x4002_0000 MFT Unit0 0x1FFF_8000 SRAM0 0x0050_0000 Reserved 0x4001_6000 0x0040_0000 Security/CR Trim 0x4001_5000 Dual Timer 0x4001_3000 0x4001_2000 SW WDT 0x0000_0000 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 MainFlash I/F Reserved Reserved Reserved Reserved

32 Mbytes

See "Memory Map (2)" for the memory size details. MainFlash Reserved Reserved

Document Number: 002-04926 Rev.*B Page 43 of 122 MB9B460L Series Memory Map (2) MB9BF466K/L MB9BF465K/L MB9BF464K/L 0x2008_0000 0x2008_0000 0x2008_0000 0x200C_8000 0x200C_8000 0x200C_8000 0x200C_0000 0x200C_0000 0x200C_0000 0x2004_4000 0x2004_3000 0x2004_2000 0x2004_0000 0x2004_0000 0x2004_0000 0x2003_E000 0x2003_D000 0x2003_C000 0x2000_0000 0x2000_0000 0x2000_0000 0x1FFF_C000 0x1FFF_A000 0x1FFF_8000 0x0050_0000 0x0050_0000 0x0050_0000 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_2000 CR trimming 0x0040_0000 Security 0x0040_0000 Security 0x0040_0000 Security 0x0008_0000 0x0006_0000 0x0004_0000 0x0000_0000 0x0000_0000 0x0000_0000 SRAM2

8 Kbytes

16 Kbytes

12 Kbytes

384 Kbytes

24 Kbytes

32 Kbytes

512 Kbytes

Document Number: 002-04926 Rev.*B Page 44 of 122 MB9B460L Series Peripheral Address Map Start Address End Address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB MainFlash I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Dual-Timer 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF APB1 Multi-function timer unit0 0x4002_1000 0x4002_1FFF Multi-function timer unit1 0x4002_2000 0x4003_FFFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Quadrature Position/Revolution Counter 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Internal CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Request Batch-Read Function 0x4003_2000 0x4003_4FFF Reserved 0x4003_3000 0x4003_3FFF D/A Converter 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_57FF Low Voltage Detector 0x4003_5800 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_6FFF Reserved 0x4003_7000 0x4003_7FFF CAN prescaler 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF CRC 0x4003_A000 0x4003_AFFF Watch Counter 0x4003_B000 0x4003_BFFF RTC/Port Ctrl 0x4003_C000 0x4003_C0FF Low-speed CR Prescaler 0x4003_C100 0x4003_C7FF Peripheral Clock Gating 0x4003_C800 0x4003_FFFF Reserved 0x4004_0000 0x4005_FFFF AHB Reserved 0x4006_0000 0x4006_0FFF DMAC register 0x4006_1000 0x4006_1FFF DSTC register 0x4006_2000 0x4006_2FFF CAN ch.0 0x4006_3000 0x4006_EFFF Reserved 0x4006_F000 0x4006_FFFF GPIO 0x4006_7000 0x41FF_FFFF Reserved 0x200E_0000 0x200E_FFFF WorkFlash I/F register

Document Number: 002-04926 Rev.*B Page 45 of 122 MB9B460L Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX=0 This is the period when the INITX pin is the L level.  INITX=1 This is the period when the INITX pin is the H level.  SPL=0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL=1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep standby mode, pins switch to the general-purpose I/O port.  Setting prohibition Prohibition of a setting by specification limitation.

Document Number: 002-04926 Rev.*B Page 46 of 122 MB9B460L Series List of Pin Status Pin Status Type Function Group Power-on Reset or Low-Voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - A GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Main crystal oscillator input pin/ External main clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled B GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Main crystal oscillator output pin Hi-Z / Internal input fixed at "0"/ or Input enabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z / Internal input fixed at 0 C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled

Document Number: 002-04926 Rev.*B Page 47 of 122 MB9B460L Series Pin Status Type Function Group Power-on Reset or Low-Voltage Detection State INITX Input State Device Internal Reset State Run Mode or SLEEP Mode State TIMER Mode, RTC Mode, or STOP Mode State Deep Standby RTC Mode or Deep Standby STOP Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - E Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled GPIO selected Hi-Z / Input enabled GPIO selected F NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state G JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected J Analog output selected Setting disabled Setting disabled Setting disabled Maintain previous state *2 *3 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected K External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected

Document Number: 002-04926 Rev.*B Page 48 of 122 MB9B460L Series Pin Status Type Function Group Power-on Reset or Low-Voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - L Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected M Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected

Document Number: 002-04926 Rev.*B Page 49 of 122 MB9B460L Series Pin Status Type Function Group Power-on Reset or Low-Voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - O Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z Hi-Z Input enabled Hi-Z Input enabled Hi-Z / Internal input fixed at 0 GPIO selected P Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected

Document Number: 002-04926 Rev.*B Page 50 of 122 MB9B460L Series Pin Status Type Function Group Power-on Reset or Low-Voltage Detection State INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - Q WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected R GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at "0" Hi-Z / Input enabled Hi-Z / Internal input fixed at "0" Hi-Z / Input enabled GPIO selected *1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Maintain previous state at timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode. *3: Maintain previous state at timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode.

Document Number: 002-04926 Rev.*B Page 51 of 122 MB9B460L Series List of VBAT Domain Pin Status VBAT Pin Status Type Function Group Power-on Reset*1 INITX Input State Device Internal Reset State Run Mode or Sleep Mode State Timer Mode, RTC Mode, or Stop Mode State Deep Standby RTC Mode or Deep Standby Stop Mode State Return from Deep Standby Mode State VBAT RTC Mode State Return from VBAT RTC Mode State Power Supply Unstable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable Power Supply Stable ‐ INITX=0 INITX=1 INITX=1 INITX=1 INITX=1 INITX=1 - - ‐ ‐ ‐ ‐ SPL=0 SPL=1 SPL=0 SPL=1 - - - S GPIO selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Setting prohibition - Sub crystal oscillator input pin / External sub clock input selected Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Maintain previous state Maintain previous state T GPIO selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Setting prohibition - External sub clock input selected Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0/ or Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state/When oscillation stops, Hi-Z Maintain previous state/ When oscillation stops, Hi-Z *2 Maintain previous state/ When oscillation stops, Hi-Z *2 Maintain previous state/ When oscillation stops, Hi-Z *2 Maintain previous state Maintain previous state Maintain previous state U Resource selected Hi-Z Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected *1: When VBAT and VCC power on. *2: When The SOSCNTL bit in the WTOSCCNT Register is “0”, Sub crystal oscillator output pin is maintain previous state. When The SOSCNTL bit in the WTOSCCNT Register is “1”, Oscillation is stopped at STOP mode and Deep standby STOP mode.

Document Number: 002-04926 Rev.*B Page 52 of 122 MB9B460L Series 12. Electrical Characteristics

12.1 Absolute Maximum Ratings

Power supply voltage * , * VCC VSS - 0.5 VSS + 6.5 V Power supply voltage (VBAT) * 1 , VBAT VSS - 0.5 VSS + 6.5 V Analog power supply voltage * 1 , AVCC VSS - 0.5 VSS + 6.5 V Analog reference voltage * 1 , AVRH VSS - 0.5 VSS + 6.5 V Input voltage * VI VSS - 0.5 VCC + 0.5 (≤ 6.5V) V VSS - 0.5 VSS + 6.5 V 5 V tolerant Analog pin input voltage * VIA VSS - 0.5 AVCC + 0.5 (≤ 6.5V) V Output voltage * VO VSS - 0.5 VCC + 0.5 (≤ 6.5V) V "L" level maximum output current * IOL - 10 mA 4 mA type 20 mA 8 mA type 20 mA 12 mA type 22.4 mA I C Fm+ "L" level average output current * IOLAV - 4 mA 4 mA type 8 mA 8 mA type 12 mA 12 mA type 20 mA I C Fm+ "L" level total maximum output current ∑IOL - 100 mA "L" level total average output current * ∑IOLAV - 50 mA "H" level maximum output current * IOH - - 10 mA 4 mA type - 20 mA 8 mA type - 20 mA 12 mA type "H" level average output current * IOHAV - - 4 mA 4 mA type - 8 mA 8 mA type - 12 mA 12 mA type "H" level total maximum output current ∑IOH - - 100 mA "H" level total average output current * ∑IOHAV - - 50 mA Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: VBAT must not drop below VSS - 0.5 V. *4: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is turned on. *5: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *6: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100ms period. *7: The total average output current is defined as the average current value flowing through all of corresponding pins for a period of 100 ms. WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

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12.2 Recommended Operating Conditions

Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage VCC - 2.7 *3 5.5 V Power supply voltage (VBAT) VBAT - 2.7 5.5 V Analog power supply voltage AVCC - 2.7 5.5 V AVCC=VCC Analog reference voltage AVRH - *1 AVCC V Smoothing capacitor CS - 1 10 μF for built-in regulator *4 Operating temperature Junction temperature Tj - - 40 + 125 °C Ambient temperature TA - - 40 *2 °C *1: The minimum value of Analog reference voltage depends on the value of compare clock cycle (Tcck). See "5. 12-bit A/D Converter" for the details. *2: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed the junction temperature (Tj). The calculation formula of the ambient temperature (TA) is shown below. TA(Max) = Tj(Max) - Pd(Max) × θja Pd: Power dissipation (W) θja: Package thermal resistance (°C/W) Pd (Max) = VCC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH)) IOL: L level output current IOH: H level output current VOL: L level output voltage VOH: H level output voltage *3: In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built-in High-speed CR (including Main PLL is used) or built-in Low-speed CR is possible to operate only. *4: See "C pin" in "Handling Devices" for the connection of the smoothing capacitor. Package thermal resistance and maximum permissible power for each package are shown below. The operation is guaranteed maximum permissible power or less for semiconductor devices. Table for Package Thermal Resistance and Maximum Permissible Power Package Printed Circuit Board Thermal resistance θja (°C/W) Maximum permissible Power (mW) TA=+85°C TA=+105°C LQA048 (0.5mm pitch) Single-layered both sides 87 460 230 4 layers 53 755 377 VNA048 (0.5mm pitch) Single-layered both sides 30 1333 667 4 layers 24 1667 833 LQD064 (0.5mm pitch) Single-layered both sides 70 571 286 4 layers 45 889 444 LQG064 (0.65mm pitch) Single-layered both sides 61 656 328 4 layers 40 1000 500 VNC064 (0.5mm pitch) Single-layered both sides 24 1667 833 4 layers 21 1905 952 WARNING: − The recommended operating conditions are required to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

Document Number: 002-04926 Rev.*B Page 54 of 122 MB9B460L Series Calculation Method of Power Dissipation (Pd) The power dissipation is shown in the following formula. Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH)) IOL: "L" level output current IOH: "H" level output current VOL: "L" level output voltage VOH: "H" level output voltage ICC is a current consumed in device. It can be analyzed as follows. ICC = ICC(INT) + ΣICC(IO) ICC(INT): Current consumed in internal logic and memory, etc. through regulator ΣICC(IO): Sum of current (I/O switching current) consumed in output pin For ICC (INT), it can be anticipated by "12.3.1 Current Rating" in "12.3 DC Characteristics" (This rating value does not include ICC (IO) for a value at pin fixed). For Icc (IO), it depends on system used by customers. The calculation formula is shown below. ICC(IO) = (CINT + CEXT) × VCC × fsw CINT: Pin internal load capacitance CEXT: External load capacitance of output pin fSW: Pin switching frequency Parameter Symbol Conditions Capacitance Value Pin internal load capacitance CINT 4 mA type 1.93 pF 8 mA type 3.45 pF 12 mA type 3.42 pF Calculate I CC (Max) as follows when the power dissipation can be evaluated. 1. Measure current value ICC (Typ) at normal temperature (+25°C). 2. Add maximum leak current value ICC (leak_max) at operating on a value in (1). ICC(Max) = ICC(Typ) + ICC(leak_max) Parameter Symbol Conditions Current Value Maximum leak current at operating ICC(leak_max) Tj = +125 °C 28 mA Tj = +105 °C 17 mA Tj = +85 °C 13 mA

Document Number: 002-04926 Rev.*B Page 55 of 122 MB9B460L Series Current Explanation Diagram A V ・・・ ・・・ ・・・ V A A Regulator Logic Flash RAM ICC ICC(INT) ΣICC(IO) IOL VOL VOH IOH ICC(IO) Chip VCC CEXT Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH)) ICC = ICC(INT)＋ΣICC(IO)

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12.3 DC Characteristics

12.3.1 Current Rating

Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current I CC VCC Normal operation (PLL) *5, *6

160 MHz 44 72

144 MHz 40 67

120 MHz 34 60

100 MHz 29 55

80 MHz 23 48

60 MHz 18 42

40 MHz 13 37

20 MHz 7.7 31 8 MHz 4.6 27 4 MHz 3.6 26

160 MHz 30 58

144 MHz 27 54

120 MHz 23 49

100 MHz 20 46

80 MHz 16 41

60 MHz 13 38

40 MHz 9 33

20 MHz 5.7 30 8 MHz 3.7 27

4 MHz 3 26

Name Conditions Frequency*7 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (PLL)

160 MHz 64 101

144 MHz 60 96

120 MHz 52 88

100 MHz 46 81

80 MHz 39 73

60 MHz 32 65

40 MHz 25 58

20 MHz 15 47

8 MHz 7.8 39 4 MHz 5.2 36

160 MHz 47 80

144 MHz 43 75

120 MHz 39 71

100 MHz 35 66

80 MHz 30 61

60 MHz 25 55

40 MHz 20 50

20 MHz 13 42

8 MHz 6.7 36 4MHz 4.6 34 *1: TA=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are input and are fixed at "0". *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When operating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1) *6: Data access is nothing to MainFlash memory *7: Frequency is a value of HCLK. PCLK0=PCLK2=HCLK/2, PCLK1=HCLK *8: When stopping flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)

Document Number: 002-04926 Rev.*B Page 57 of 122 MB9B460L Series Parameter Symbol Pin Name Conditions Frequency*4 (MHz) Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (PLL)

72 MHz 41 75

60 MHz 36 69

48 MHz 31 64

36 MHz 25 57

24 MHz 18 50

12 MHz 11 42

8 MHz 8.1 39 4 MHz 5.4 37

72 MHz 32 63

60 MHz 28 58

48 MHz 24 54

36 MHz 20 50

24 MHz 15 45

12 MHz 9.1 38 8 MHz 6.9 36 4 MHz 4.6 34 *1: TA=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are input and are fixed at "0". *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00) Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICC VCC Normal operation (built-in high-speed CR) *5 4 MHz 3.3 29 mA When all peripheral clocks are ON 2.8 29 mA When all peripheral clocks are OFF Normal operation (sub oscillation) *5 32 kHz 0.51 27 mA When all peripheral clocks are ON 0.50 27 mA When all peripheral clocks are OFF Normal operation (built-in low-speed CR) *5 100 kHz 0.54 27 mA When all peripheral clocks are ON 0.52 27 mA When all peripheral clocks are OFF *1: TA=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are input and are fixed at "0". *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000)

Document Number: 002-04926 Rev.*B Page 58 of 122 MB9B460L Series Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC Sleep operation (PLL)

160 MHz 28 58

144 MHz 25 55

120 MHz 21 50

100 MHz 18 46

80 MHz 15 43

60 MHz 12 39

40 MHz 8.8 36 20 MHz 5.6 32 8 MHz 3.8 30 4 MHz 3.2 29

160 MHz 14 44

144 MHz 13 43

120 MHz 11 40

100 MHz 9.7 38 80 MHz 8.1 36 60 MHz 6.7 34 40 MHz 5.2 32 20 MHz 3.7 30 8 MHz 2.9 29 4 MHz 2.6 29 Parameter Symbol Pin Name Conditions Frequency*5 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC Sleep operation (PLL)

72 MHz 19 47

60 MHz 16 43

48 MHz 13 40

36 MHz 10 37

24 MHz 7.8 34 12 MHz 5.2 31 8 MHz 4.3 30 4 MHz 3.5 29 72 MHz 8.8 36 mA When all peripheral clocks are OFF 60 MHz 7.7 35 48 MHz 6.6 34 36 MHz 5.5 32 24 MHz 4.4 31 12 MHz 3.4 30

8 MHz 3 29

4 MHz 2.7 29 *1: TA=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are input and are fixed at "0". *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK

Document Number: 002-04926 Rev.*B Page 59 of 122 MB9B460L Series Parameter Symbol Pin Name Conditions Frequency*4 Value Unit Remarks Typ*1 Max*2 Power supply current ICCS VCC Sleep operation (built-in high-speed CR) 1.3 27 mA When all peripheral clocks are ON 0.91 27 mA When all peripheral clocks are OFF Sleep operation (sub oscillation) 32 kHz 0.49 27 mA When all peripheral clocks are ON 0.48 27 mA When all peripheral clocks are OFF Sleep operation (built-in low-speed CR) 100 kHz 0.51 27 mA When all peripheral clocks are ON 0.49 27 mA When all peripheral clocks are OFF *1: TA=+25 °C, VCC=3.3 V *2: Tj=+125 °C, VCC=5.5 V *3: When all ports are input and are fixed at "0". *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2

Document Number: 002-04926 Rev.*B Page 60 of 122 MB9B460L Series Parameter Symbol Pin Name Conditions Frequency Value Unit Remarks Typ*1 Max*2 Power supply current ICCH VCC STOP mode - 0.25 1.0 mA *3, *4 T A=+25°C - 11 mA *3, *4 TA =+85°C - 14 mA *3, *4 TA =+105°C ICCT TIMER mode (built-in high-speed CR) TA =+25°C - 12 mA *3, *4 TA =+85°C - 15 mA *3, *4 TA =+105°C TIMER mode (sub oscillation) 32 kHz 0.25 1.0 mA *3, *4 TA =+25°C - 11 mA *3, *4 T A =+85°C - 14 mA *3, *4 TA =+105°C TIMER mode (built-in low-speed CR) 100 kHz 0.26 1.0 mA *3, *4 TA =+25°C - 11 mA *3, *4 TA =+85°C - 14 mA *3, *4 TA =+105°C ICCR RTC mode (sub oscillation) 32 kHz 0.25 1.0 mA *3, *4 TA =+25°C - 11 mA *3, *4 TA =+85°C - 14 mA *3, *4 TA =+105°C *1: VCC=3.3 V *2: VCC=5.5 V *3: When all ports are input and are fixed at "0". *4: When LVD is OFF

Document Number: 002-04926 Rev.*B Page 61 of 122 MB9B460L Series Parameter Symbol Pin Name Conditions Frequency Value Unit Remarks Typ*1 Max*2 Power supply current ICCHD VCC Deep standby STOP mode (When RAM is OFF)*6 27 140 µA *3, *4 TA=+25°C - 590 µA *3, *4 TA =+85°C - 770 µA *3, *4 TA =+105°C Deep standby STOP mode (When RAM is ON)*6 32 180 µA *3, *4 TA =+25°C - 870 µA *3, *4 TA =+85°C - 1200 µA *3, *4 TA =+105°C ICCRD Deep standby RTC mode (When RAM is OFF)*7 32 kHz 27 140 µA *3, *4 TA =+25°C - 590 µA *3, *4 TA =+85°C - 770 µA *3, *4 TA =+105°C Deep standby RTC mode (When RAM is ON)*7 32 180 µA *3, *4 TA =+25°C - 870 µA *3, *4 TA =+85°C - 1200 µA *3, *4 TA =+105°C ICCVBAT VBAT RTC stop*9 - TA =+25°C TA =+85°C TA =+105°C RTC operation *8, *9 32 kHz 1.3 2.4 µA *3, *4 TA =+25°C - 6.2 µA *3, *4 TA =+85°C - 12 µA *3, *4 TA =+105°C *1: VCC=3.3 V *2: VCC=5.5 V *3: When all ports are input and are fixed at "0". *4: When LVD is OFF *5: When sub oscillation is OFF *6: When 48 pin Package, add supply current of RTC stop. *7: When 48 pin Package, add supply current of RTC operation. *8: When using the crystal oscillator of 32 kHz (including the current consumption of the oscillation circuit). *9: In the case of setting RTC after VCC power on.

Document Number: 002-04926 Rev.*B Page 62 of 122 MB9B460L Series Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Low-voltage detection circuit (LVD) power supply current I CCLVD VCC At operation - 4 7 μA For occurrence of interrupt Main flash memory write/erase current I CCFLASH At Write/Erase - 13.4 15.9 mA Work flash memory write/erase current I CCWFLASH At Write/Erase - 11.5 13.6 mA Peripheral Current Dissipation Clock System Peripheral Unit Frequency (MHz) Unit Remarks 40 80 160 HCLK GPIO All ports 0.21 0.43 0.92 mA DMAC - 0.71 1.43 2.74 DSTC - 0.36 0.72 1.46 CAN 1ch. 0.03 0.06 0.11 PCLK1 Base timer 4ch. 0.18 0.36 0.70 mA Multi-functional timer/PPG 1 unit/4ch. 0.57 1.13 2.24 Quadrature position/Revolution counter 1 unit 0.04 0.08 0.16 A/DC 1 unit 0.21 0.40 0.79 PCLK2 Multi-function serial 1ch. 0.33 0.67 - mA

Document Number: 002-04926 Rev.*B Page 63 of 122 MB9B460L Series

12.3.2 Pin Characteristics

(VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max "H" level input voltage (hysteresis input) V IHS CMOS hysteresis input pin, MD0, MD1 - VCC×0.8 - VCC + 0.3 V 5V tolerant input pin - V CC×0.8 - VSS + 5.5 V Input pin doubled as I C Fm+ - VCC×0.7 - VSS + 5.5 V "L" level input voltage (hysteresis input) V ILS CMOS hysteresis input pin, MD0, MD1 - VSS - 0.3 - VCC×0.2 V 5V tolerant input pin - V SS - 0.3 - VCC×0.2 V Input pin doubled as I C Fm+ - VSS - VCC×0.3 V "H" level output voltage VOH 4mA type VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 2 mA 8mA type VCC ≥ 4.5 V, IOH = - 8 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 4 mA 12mA type VCC ≥ 4.5 V, IOH = - 12 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 8 mA The pin doubled as I C Fm+ VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V At GPIO VCC < 4.5 V, IOH = - 3 mA

Document Number: 002-04926 Rev.*B Page 64 of 122 MB9B460L Series Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max "L" level output voltage VOL 4 mA type VCC ≥ 4.5 V, IOL = 4 mA VSS - 0.4 V VCC < 4.5 V, IOL = 2 mA 8 mA type VCC ≥ 4.5 V, IOH = 8 mA VSS - 0.4 V VCC < 4.5 V, IOH = 4 mA 12 mA type VCC ≥ 4.5 V, IOL = 12 mA VSS - 0.4 V VCC < 4.5 V, IOL = 8 mA The pin doubled as I C Fm+ VCC ≥ 4.5 V, IOH = 4 mA VSS - 0.4 V At GPIO VCC < 4.5 V, IOH = 3 mA VCC ≤ 5.5 V, IOH = 20 mA At I C Fm+ Input leak current IIL - - - 5 - + 5 μA Pull-up resistor value RPU Pull-up pin VCC ≥ 4.5 V 25 50 100 kΩ VCC < 4.5 V 30 80 200 Input capacitance CIN Other than VCC, VBAT, VSS, AVCC, AVSS, AVRH - - 5 15 pF

Document Number: 002-04926 Rev.*B Page 65 of 122 MB9B460L Series

12.4 AC Characteristics

12.4.1 Main Clock Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input frequency fCH X0, VCC ≥ 4.5 V 4 48 MHz When crystal oscillator is connected VCC < 4.5 V 4 20 VCC ≥ 4.5 V 4 48 MHz When using external clock VCC < 4.5 V 4 20 Input clock cycle tCYLH VCC ≥ 4.5 V 20.83 250 ns When using external clock VCC < 4.5 V 50 250 Input clock pulse width - PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock Input clock rising time and falling time tCF, tCR - - 5 ns When using external clock Internal operating clock* frequency fCC - - - 160 MHz Base clock (HCLK/FCLK) fCP0 - - - 80 MHz APB0 bus clock* fCP1 - - - 160 MHz APB1 bus clock* fCP2 - - - 80 MHz APB2 bus clock* Internal operating clock* cycle time tCYCC - - 6.25 - ns Base clock (HCLK/FCLK) tCYCP0 - - 12.5 - ns APB0 bus clock* tCYCP1 - - 6.25 - ns APB1 bus clock* tCYCP2 - - 12.5 - ns APB2 bus clock* *1: For more information about each internal operating clock, see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main part (002-04856). *2: For about each APB bus which each peripheral is connected to, see 8. Block Diagram in this data sheet. 0.8 × Vcc tCYLH 0.8 × Vcc 0.2 × Vcc 0.2 × Vcc 0.8 × Vcc PWLPWH tCF tCR

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12.4.2 Sub Clock Input Characteristics

(VBAT = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Input frequency 1/ tCYLL X0A, X1A - - 32.768 - kHz When crystal oscillator is connected - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock In the case of 48 pin Package, VBAT is VCC.

12.4.3 Built-in CR Oscillation Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRH TJ = -20°C to +105°C 3.92 4 4.08 MHz When trimming * TJ = - 40°C to +125°C 3.88 4 4.12 TJ = - 40°C to +125°C 3 4 5 When not trimming Frequency stabilization time tCRWT - - - 30 μS *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature trimming. *2: This is the time to stabilize the frequency of high-speed CR clock after setting trimming value. This period is able to use high-speed CR clock as source clock. Built-in Low-Speed CR (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Condition Value Unit Remarks Min Typ Max Clock frequency fCRL - 50 100 150 kHz 0.8 × Vcc tCYLL 0.8 × Vcc 0.2 × Vcc 0.2 × Vcc 0.8 × Vcc PWLPWH X0A VBAT VBAT VBAT VBAT 0.8 × VBAT

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12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time* (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiplication rate - 13 - 80 multiplier PLL macro oscillation clock frequency fPLLO 200 - 320 MHz Main PLL clock frequency* fCLKPLL - - 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see CHPATER 2-1: Clock in FM4 Family Peripheral Manual Main part (002-04856). 12.4.5 Operating Conditions of Main PLL (In the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time* (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate - 50 - 75 multiplier PLL macro oscillation clock frequency fPLLO 190 - 320 MHz Main PLL clock frequency* fCLKPLL - - 160 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main part (002-04856). Note: − Make sure to input to the main PLL source clock, the high-speed CR clock (CLKHC) that the frequency and temperature has been trimmed.

12.4.6 Reset Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Condition Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns

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12.4.7 Power-on Reset Timing

(VSS = 0V, TA = - 40°C to + 85°C ) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Typ Max Power supply shut down time tOFF VCC - 50 - - ms *1 Power ramp rate dV/dt VCC: 0.2V to 2.70V 1.3 - 1000 mV /µs *2 Time until releasing Power-on reset tPRT - 0.33 - 0.60 ms *1: VCC must be held below 0.2V for a minimum period of tOFF. Improper initialization may occur if this condition is not met. *2: This dV/dt characteristic is applied at the power-on of cold start (tOFF>50ms). Note: − tOFF must be satisfied. When tOFF cannot be satisfied, assert external reset (INITX) at power-up and at any brownout event. Glossary  VDH: detection voltage of Low-Voltage detection reset. See 12.7 Low-Voltage Detection Characteristics.

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12.4.8 GPIO Output Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Min Max Output frequency tPCYCLE Pxx* VCC ≥ 4.5 V - 50 MHz VCC < 4.5 V - 32 MHz *: GPIO is a target. Pxx tPCYCLE

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12.4.9 Base Timer Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - 2tCYCP - ns Trigger Input Timing (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see 8. Block Diagram in this data sheet. tTIWH VIHS VIHS VILS VILS tTIWL tTRGH VIHS VIHS VILS VILS tTRGL ECK TIN TGIN

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12.4.10 CSIO/UART Timing

Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-04926 Rev.*B Page 72 of 122 MB9B460L Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI tSLSH tSHSL VIH tF tR VIH VOH VIH VIL VIL VOL VIH VIL VIH VIL tSLOVE tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04926 Rev.*B Page 73 of 122 MB9B460L Series Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-04926 Rev.*B Page 74 of 122 MB9B460L Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI tSHSL tSLSH VIH tFtR VIH VOH VILVIL VIL VOL VIH VIL VIH VIL tSHOVE tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04926 Rev.*B Page 75 of 122 MB9B460L Series Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation CYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 50 - 30 - ns SCK↓→SIN hold time tSLIXI SCKx, SINx 0 - 0 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 10 - 10 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-04926 Rev.*B Page 76 of 122 MB9B460L Series MS bit = 0 MS bit = 1 *: Changes when writing to TDR register tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04926 Rev.*B Page 77 of 122 MB9B460L Series Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx - 30 + 30 - 20 + 20 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx 50 - 30 - ns SCK↑→SIN hold time tSHIXI SCKx, SINx 0 - 0 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 50 - 30 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 10 - 10 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 30 pF.

Document Number: 002-04926 Rev.*B Page 78 of 122 MB9B460L Series MS bit = 0 MS bit = 1 tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI tSHSLtR tSLSH tF tSLOVE VIL VILVIL VIH VIHVIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04926 Rev.*B Page 79 of 122 MB9B460L Series High-Speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5V VCC ≥ 4.5V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns 12.5* SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE SCKx, 5 - 5 - ns SINx SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select: SIN0_1, SOT0_1, SCK0_1 − Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

Document Number: 002-04926 Rev.*B Page 80 of 122 MB9B460L Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOL VOL VOL VIH VIL VIH VIL tSLOVI tIVSHI tSHIXI tSLSH tSHSL VIH tF tR VIH VOH VIH VIL VIL VOL VIH VIL VIH VIL tSLOVE tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04926 Rev.*B Page 81 of 122 MB9B460L Series High-Speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx - 12.5 - ns 12.5* SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select: SIN0_1, SOT0_1, SCK0_1 − Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

Document Number: 002-04926 Rev.*B Page 82 of 122 MB9B460L Series MS bit = 0 MS bit = 1 tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI tSHSL tSLSH VIH tFtR VIH VOH VILVIL VIL VOL VIH VIL VIH VIL tSHOVE tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04926 Rev.*B Page 83 of 122 MB9B460L Series High-Speed Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx - 12.5 - ns 12.5* SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns SOT→SCK↓ delay time tSOVLI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select: SIN0_1, SOT0_1, SCK0_1 − Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

Document Number: 002-04926 Rev.*B Page 84 of 122 MB9B460L Series MS bit = 0 MS bit = 1 *: Changes when writing to TDR register tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04926 Rev.*B Page 85 of 122 MB9B460L Series High-Speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Internal shift clock operation tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↓→SOT delay time tSLOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↑ setup time tIVSHI SCKx, SINx - 12.5 - ns 12.5* SCK↑→SIN hold time tSHIXI SCKx, SINx 5 - 5 - ns SOT→SCK↑ delay time tSOVHI SCKx, SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↓→SOT delay time tSLOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↑ setup time tIVSHE SCKx, SINx 5 - 5 - ns SCK↑→SIN hold time tSHIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select: SIN0_1, SOT0_1, SCK0_1 − Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)

Document Number: 002-04926 Rev.*B Page 86 of 122 MB9B460L Series MS bit = 0 MS bit = 1 tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI tSHSLtR tSLSH tF tSLOVE VIL VILVIL VIH VIHVIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN SCK SOT SIN

Document Number: 002-04926 Rev.*B Page 87 of 122 MB9B460L Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↓setup time tCSSI Internal shift clock operation SCK↑→SCS↑ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns SCS↓→SCK↓setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 - 25 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual. − When the external load capacitance CL = 30 pF.

Document Number: 002-04926 Rev.*B Page 88 of 122 MB9B460L Series MS bit = 0 MS bit = 1 tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 002-04926 Rev.*B Page 89 of 122 MB9B460L Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↓→SCK↑setup time tCSSI Internal shift clock operation SCK↓→SCS↑ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns SCS↓→SCK↑setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↓→SCS↑ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↓→SOT delay time tDSE - 25 - 25 ns SCS↑→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF.

Document Number: 002-04926 Rev.*B Page 90 of 122 MB9B460L Series MS bit = 0 MS bit = 1 tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 002-04926 Rev.*B Page 91 of 122 MB9B460L Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↓setup time tCSSI Internal shift clock operation SCK↑→SCS↓ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns SCS↑→SCK↓setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↑→SOT delay time tDSE - 25 - 25 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF.

Document Number: 002-04926 Rev.*B Page 92 of 122 MB9B460L Series MS bit = 0 MS bit = 1 tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 002-04926 Rev.*B Page 93 of 122 MB9B460L Series When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max SCS↑→SCK↑setup time tCSSI Internal shift clock operation SCK↓→SCS↓ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns SCS deselect time tCSDI (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns SCS↑→SCK↑setup time tCSSE External shift clock operation 3tCYCP+15 - 3tCYCP+15 - ns SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns SCS↑→SOT delay time tDSE - 25 - 25 ns SCS↓→SOT delay time tDEE 0 - 0 - ns (*1): CSSU bit value×serial chip select timing operating clock cycle [ns] (*2): CSHD bit value×serial chip select timing operating clock cycle [ns] (*3): CSDS bit value×serial chip select timing operating clock cycle [ns] Notes: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − About CSSU, CSHD, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main part (002-04856). − When the external load capacitance CL = 30 pF.

Document Number: 002-04926 Rev.*B Page 94 of 122 MB9B460L Series MS bit = 0 MS bit = 1 tCSSI tCSHI tCSDI tCSSE tCSHE tCSDE tDEE tDSE SCS output SCK output SOT (SPI=0) SOT (SPI=1) SCS input SCK input SOT (SPI=0) SOT (SPI=1)

Document Number: 002-04926 Rev.*B Page 95 of 122 MB9B460L Series External Clock (EXT = 1): when in Asynchronous Mode Only (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Condition Value Unit Remarks Min Max Serial clock "L" pulse width tSLSH CL = 30 pF tCYCP + 10 - ns Serial clock "H" pulse width tSHSL tCYCP + 10 - ns SCK falling time tF - 5 ns SCK rising time tR - 5 ns tSHSL VIL VIL VIL VIH VIH VIH tR tFtSLSH SCK

Document Number: 002-04926 Rev.*B Page 96 of 122 MB9B460L Series

12.4.11 External Input Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max Input pulse width tINH, tINL ADTG - 2tCYCP* - ns A/D converter trigger input FRCKx Free-run timer input clock ICxx Input capture DTTIxX - 2tCYCP* - ns Waveform generator INT00 to INT31, NMIX - 2tCYCP + 100* - ns External interrupt, NMI 500* - ns WKUPx - 500* - ns Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which the A/D converter, multi-function timer, external interrupt are connected to, see 8. Block Diagram in this data sheet. *2: When in Stop mode, in timer mode. *3: When in deep standby RTC mode, in Deep Standby Stop mode. tINH tINL VILS VILS VIHS VIHS

Document Number: 002-04926 Rev.*B Page 97 of 122 MB9B460L Series

12.4.12 Quadrature Position/Revolution Counter Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Value Unit Min Max AIN pin H width tAHL - 2tCYCP* - ns AIN pin L width tALL - BIN pin H width tBHL - BIN pin L width tBLL - BIN rising time from AIN pin H level tAUBU PC_Mode2 or PC_Mode3 AIN falling time from BIN pin H level tBUAD PC_Mode2 or PC_Mode3 BIN falling time from AIN pin L level tADBD PC_Mode2 or PC_Mode3 AIN rising time from BIN pin L level tBDAU PC_Mode2 or PC_Mode3 AIN rising time from BIN pin H level tBUAU PC_Mode2 or PC_Mode3 BIN falling time from AIN pin H level tAUBD PC_Mode2 or PC_Mode3 AIN falling time from BIN pin L level tBDAD PC_Mode2 or PC_Mode3 BIN rising time from AIN pin L level tADBU PC_Mode2 or PC_Mode3 ZIN pin H width tZHL QCR:CGSC = 0 ZIN pin L width tZLL QCR:CGSC = 0 AIN/BIN rising and falling time from determined ZIN level tZABE QCR:CGSC = 1 Determined ZIN level from AIN/BIN rising and falling time tABEZ QCR:CGSC = 1 *: tCYCP indicates the APB bus clock cycle time except stop when in Stop mode, in timer mode. About the APB bus number which Quadrature Position/Revolution Counter is connected to, see 8. Block Diagram in this data sheet. AIN BIN tAUBU tBUAD tADBD tBDAU tAHL tALL tBHL tBLL

Document Number: 002-04926 Rev.*B Page 98 of 122 MB9B460L Series BIN tBUAU tAUBD tBDAD tADBU tBHL tBLL tAHL tALL AIN tZHL tZLL tZABE tABEZ ZIN ZIN AIN/BIN

Document Number: 002-04926 Rev.*B Page 99 of 122 MB9B460L Series

12.4.13 I2C Timing

Standard-Mode, Fast-Mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Standard-Mode Fast-Mode Unit Remarks Min Max Min Max SCL clock frequency FSCL CL = 30 pF, R = (Vp/IOL)* 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCL clock "L" width tLOW 4.7 - 1.3 - μs SCL clock "H" width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45* 0 0.9* μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between "STOP condition" and "START condition" tBUF 4.7 - 1.3 - μs Noise filter tSP

2 MHz ≤

tCYCP<40 MHz 2tCYCP* - 2tCYCP* - ns

40 MHz ≤

tCYCP<60 MHz 4tCYCP* - 4tCYCP* - ns

60 MHz ≤

tCYCP<80 MHz 6tCYCP*4 - 6tCYCP* - ns

80 MHz ≤

tCYCP<100 MHz 8tCYCP* - 8tCYCP* - ns

100 MHz ≤

tCYCP<120 MHz 10tCYCP* - 10tCYCP* - ns

120 MHz ≤

tCYCP<140 MHz 12tCYCP* - 12tCYCP* - ns

140 MHz ≤

tCYCP<160 MHz 14tCYCP* - 14tCYCP* - ns

160 MHz ≤

tCYCP<180 MHz 16tCYCP* - 16tCYCP* - ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see "8. Block Diagram" in this data sheet. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency.

Document Number: 002-04926 Rev.*B Page 100 of 122 MB9B460L Series Fast Mode Plus (Fm+) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Fast Mode Plus (Fm+)*6 Unit Remarks Min Max SCL clock frequency FSCL CL = 30 pF, R = (Vp/IOL)* 0 1000 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 0.26 - μs SCL clock "L" width tLOW 0.5 - μs SCL clock "H" width tHIGH 0.26 - μs SCL clock frequency tSUSTA 0.26 - μs (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDDAT 0 0.45* μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 50 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 0.26 - μs Bus free time between "STOP condition" and "START condition" tBUF 0.5 - μs Noise filter tSP tCYCP<80 MHz 6 tCYCP* - ns tCYCP<100 MHz 8 tCYCP* - ns tCYCP<120 MHz 10 tCYCP* - ns tCYCP<140 MHz 12 tCYCP* - ns tCYCP<160 MHz 14 tCYCP* - ns tCYCP<180 MHz 16 tCYCP* - ns *1: R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see 8. Block Diagram in this data sheet. To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more. *5: The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. *6: When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I2C Fm+ in the EPFR register. See CHAPTER 12: I/O Port in FM4 Family Peripheral Manual Main part (002-04856) for the details. tLOW tHDSTA tHDDAT tHIGH tSUDAT tSUSTA tHDSTA tSP tSUSTO tBUFSDA SCL

Document Number: 002-04926 Rev.*B Page 101 of 122 MB9B460L Series

12.4.14 JTAG Timing

(VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions Value Unit Remarks Min Max TMS, TDI setup time tJTAGS TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TMS, TDI hold time tJTAGH TCK, TMS, TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TDO delay time tJTAGD TCK, TDO VCC ≥ 4.5 V - 25 ns VCC < 4.5 V - 45 Note: − When the external load capacitance CL= 30 pF. VOH VOH VOL VOL VOH VOL VOH VOL tJTAGS tJTAGD tJTAGH TCK TMS/TDI TDO

Document Number: 002-04926 Rev.*B Page 102 of 122 MB9B460L Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V) Parameter Symbol Pin Name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - -4.5 - +4.5 LSB AVRH = 2.7 V to 5.5 V Differential Nonlinearity - - -2.5 - +2.5 LSB Zero transition voltage VZT AN00 to AN14 -15 - +15 mV Full-scale transition voltage VFST AN00 to AN14 AVRH - 15 - AVRH + 15 mV Conversion time - - 0.5* - - μs AVCC ≥ 4.5V Sampling time Ts - *2 - 10 μs AVCC ≥ 4.5V *2 - AVCC < 4.5V Compare clock cycle* Tcck - 25 - 1000 ns AVCC ≥ 4.5V 50 - 1000 AVCC < 4.5V State transition time to operation permission Tstt - - - 1.0 μs Power supply current (analog + digital) - AVCC - 0.69 0.92 mA A/D 1 unit operation - 0.3 12 μA When A/D stop Reference power supply current (AVRH) - AVRH - 1.1 1.97 mA A/D 1unit operation AVRH=5.5 V 0.2 4.2 μA When A/D stop Analog input capacity CAIN - - - 10 pF Analog input resistance RAIN - - - 1.2 kΩ AVCC ≥ 4.5 V 1.8 AVCC < 4.5 V Interchannel disparity - - - - 4 LSB Analog port input leak current - AN00 to AN14 - - 5 μA Analog input voltage - AN00 to AN14 AVSS - AVRH V Reference voltage - AVRH 4.5 - AVCC V Tcck < 50 ns 2.7 - AVCC Tcck ≥ 50 ns *1: The conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is when the value of sampling time: 150 ns, the value of compare time: 350 ns (AVCC ≥ 4.5 V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting*4 of sampling time and compare clock cycle, see CHAPTER 1-1: A/D Converter in FM4 Family Peripheral Manual Analog macro part (002-04860). The register setting of the A/D Converter is reflected by the peripheral clock timing. The sampling and compare clock are set at Base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: The compare time (Tc) is the value of (Equation 2). *4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling clock and compare clock are set in base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see 8. Block Diagram in this data sheet.

Document Number: 002-04926 Rev.*B Page 103 of 122 MB9B460L Series (Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9 Ts: Sampling time RAIN: Input resistance of A/D = 1.2 kΩ at 4.5 V < AVCC < 5.5 V Input resistance of A/D = 1.8 kΩ at 2.7 V < AVCC < 4.5 V CAIN: Input capacity of A/D = 10 pF at 2.7 V < AVCC < 5.5 V Rext: Output impedance of external circuit (Equation 2) Tc = Tcck × 14 Tc: Compare time Tcck: Compare clock cycle CAIN Analog signal source AN00 to AN14 Analog input pin Comparator Rext RAIN

Document Number: 002-04926 Rev.*B Page 104 of 122 MB9B460L Series Definition of 12-bit A/D Converter Terms  Resolution: Analog variation that is recognized by an A/D converter.  Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.  Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVss AVRH AVss AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T

Document Number: 002-04926 Rev.*B Page 105 of 122 MB9B460L Series 12.6 12-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V) Parameter Symbol Pin Name Value Unit Remarks Min Typ Max Resolution - DAx - - 12 bit Conversion time tc20 0.56 0.69 0.81 μs Load 20pF tc100 2.79 3.42 4.06 μs Load 100pF Integral Nonlinearity* INL -16 - +16 LSB Differential Nonlinearity* DNL -0.98 - +1.5 LSB Output voltage offset VOFF - - 10.0 mV When setting 0x000 -20.0 - +1.4 mV When setting 0xFFF Analog output impedance RO 3.10 3.80 4.50 kΩ D/A operation 2.0 - - MΩ When D/A stop Power supply current* IDDA AVCC 260 330 410 μA D/A 1unit operation AVCC=3.3 V 400 519 620 μA D/A 1unit operation AVCC=5.0 V IDSA - - 14 μA When D/A stop *: During no load

Document Number: 002-04926 Rev.*B Page 106 of 122 MB9B460L Series

12.7 Low-Voltage Detection Characteristics

12.7.1 Low-Voltage Detection Reset

Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL - 2.25 2.45 2.65 V When voltage drops Released voltage VDH - 2.30 2.50 2.70 V When voltage rises

12.7.2 Interrupt of Low-Voltage Detection

Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDL SVHI = 00111 2.58 2.8 3.02 V When voltage drops Released voltage VDH 2.67 2.9 3.13 V When voltage rises Detected voltage VDL SVHI = 00100 2.76 3.0 3.24 V When voltage drops Released voltage VDH 2.85 3.1 3.34 V When voltage rises Detected voltage VDL SVHI = 01100 2.94 3.2 3.45 V When voltage drops Released voltage VDH 3.04 3.3 3.56 V When voltage rises Detected voltage VDL SVHI = 01111 3.31 3.6 3.88 V When voltage drops Released voltage VDH 3.40 3.7 3.99 V When voltage rises Detected voltage VDL SVHI = 01110 3.40 3.7 3.99 V When voltage drops Released voltage VDH 3.50 3.8 4.10 V When voltage rises Detected voltage VDL SVHI = 01001 3.68 4.0 4.32 V When voltage drops Released voltage VDH 3.77 4.1 4.42 V When voltage rises Detected voltage VDL SVHI = 01000 3.77 4.1 4.42 V When voltage drops Released voltage VDH 3.86 4.2 4.53 V When voltage rises Detected voltage VDL SVHI = 11000 3.86 4.2 4.53 V When voltage drops Released voltage VDH 3.96 4.3 4.64 V When voltage rises LVD stabilization wait time TLVDW - - - 4480×tCYCP* μs *: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-04926 Rev.*B Page 107 of 122 MB9B460L Series

12.8 MainFlash Memory Write/Erase Characteristics

(VCC = 2.7V to 5.5V) Parameter Value Unit Remarks Min Typ Max Sector erase time Large Sector 0.7 3.7 s Includes write time prior to internal erase Small Sector 0.3 1.1 Half word (16-bit) write time Write cycles < 100 times - 12 100 μs Not including system-level overhead time Write cycles > 100 times 200 Chip erase time - 8.0 38.4 s Includes write time prior to internal erase Write cycles and data hold time Erase/Write Cycles (Cycle) Data Hold Time (Year) 1,000 20 * 10,000 10 * 100,000 5 * *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at +85°C).

12.9 WorkFlash Memory Write/Erase Characteristics

(VCC = 2.7V to 5.5V) Parameter Value Unit Remarks Min Typ Max Sector erase time - 0.3 1.5 s Includes write time prior to internal erase Half word (16-bit) write time - 20 200 μs Not including system-level overhead time Chip erase time - 1.2 6 s Includes write time prior to internal erase Write cycles and data hold time Erase/Write Cycles (Cycle) Data Hold Time (Year) 1,000 20 * 10,000 10 * 100,000 5 * *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result into average temperature value at +85°C).

Document Number: 002-04926 Rev.*B Page 108 of 122 MB9B460L Series

12.10 Standby Recovery Time

12.10.1 Recovery Cause: Interrupt/WKUP

The time from recovery cause reception of the internal circuit to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode Ticnt HCLK×1 μs High-speed CR Timer mode Main Timer mode PLL Timer mode 40 80 μs Low-speed CR timer mode 450 900 μs Sub timer mode 896 1136 μs RTC mode stop mode (High-speed CR /Main/PLL run mode return) 316 581 μs RTC mode stop mode (Low-speed CR/sub run mode return) 270 540 μs Deep standby RTC mode Deep standby stop mode 365 667 μs without RAM retention 365 667 μs with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in External Interrupt Recovery*) Ext.INT Ticnt Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.

Document Number: 002-04926 Rev.*B Page 109 of 122 MB9B460L Series Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*) Internal Resource INT Ticnt Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each Low-Power consumption modes. See CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main part (002-04856). − When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See CHAPTER 6: Low Power Consumption Mode in FM4 Family Peripheral Manual Main part (002-04856).

Document Number: 002-04926 Rev.*B Page 110 of 122 MB9B460L Series

12.10.2 Recovery Cause: Reset

The time from reset release to the program operation start is shown. Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode Trcnt 155 266 μs High-speed CR timer mode Main timer mode PLL timer mode 155 266 μs Low-speed CR timer mode 315 567 μs Sub timer mode 315 567 μs RTC mode Stop mode 315 567 μs Deep standby RTC mode Deep standby stop mode 336 667 μs without RAM retention μs with RAM retention *: The maximum value depends on the built-in CR accuracy. Example of Standby Recovery Operation (when in INITX Recovery) INITX Trcnt Internal RST CPU Operation Start RST Active Release

Document Number: 002-04926 Rev.*B Page 111 of 122 MB9B460L Series Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*) Internal Resource RST Trcnt Internal RST CPU Operation Start RST Active Release *: Depending on the standby mode, the reset issue from the internal resource is not included in the recovery cause. Notes: − The return factor is different in each Low-Power consumption modes. See CHAPTER 6: Low Power Consumption Mode and Operations of Standby Modes in FM4 Family Peripheral Manual Main part (002-04856). − The time during the power-on reset/low-voltage detection reset is excluded to the recovery source. See 12.4.7.Power-on Reset Timing in 12.4.AC Characteristics in 12. Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. − When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset.

Document Number: 002-04926 Rev.*B Page 112 of 122 MB9B460L Series 13. Ordering Information Part Number Package MB9BF464LPMC1 Plastic・LQFP (0.5mm pitch), 64 pin (LQD064) MB9BF465LPMC1 MB9BF466LPMC1 MB9BF464LPMC Plastic・LQFP (0.65mm pitch), 64 pin (LQG064) MB9BF465LPMC MB9BF466LPMC MB9BF464KPMC Plastic・LQFP (0.5mm pitch), 48 pin (LQA048) MB9BF465KPMC MB9BF466KPMC MB9BF464LQN Plastic・QFN (0.5mm pitch), 64 pin (VNC064) MB9BF465LQN MB9BF466LQN MB9BF464KQN Plastic・QFN (0.5mm pitch), 48 pin (VNA048) MB9BF465KQN MB9BF466KQN

Document Number: 002-04926 Rev.*B Page 113 of 122 MB9B460L Series 002-11499 14. Package Dimensions Package Type Package Code LQFP 64pin (0.5mm pitch) LQD064 DIMENSIONS SYMBOL MIN . NOM. MAX. 07.1A A1 0.00 0.20 b 0.15 0.2 c 0.09 0.20 D 12.00 BSC. D1 10.00 BSC. e 0.50 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70 12.00 BSC. 10.00 BSC. D e 1 16 5 7 E 0.2 0 C A-B D b 0.1 0 C A-B D 0.0 8 C A-B D 752 A A10.25 b SECTION A -A' L1 L A SEATING PLANE 0.0 8 C SIDE VIEW TOP VIEW BOTTOM VIEW 3348 116 33 48 PACKAGE OUTLINE, 64 LEAD LQFP 10.0X10 .0X1.7 MM LQD064 Rev

Document Number: 002-04926 Rev.*B Page 114 of 122 MB9B460L Series 002-13881 ** Package Type Package Code LQFP 64pin (0.65mm pitch) LQG064 DIM ENSION SYMBOL MIN. NOM. MAX. A 1.70 A1 0.00 0.20 b 0.27 0.32 0.37 c 0.09 0.20 D 14.00 BSC D1 12.00 BSC e 0.65 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70

14.00 BSC

12.00 BSC

0° 8°θ D e 1 16 EE1 5 7

0.20 C A-B D

b

0.10 C A-B D

0.13 C A-B D 8

0.10 C A SEATING PLANE b SECTION A -A' c θ A A10.2 5 10L1 L SIDE VIEW TOP VIEW BOTTOM VIEW 3348 116 8433 12.0X12 .0X1.7 MM LQG064 REV** PACKAGE OUTLINE, 64 LEAD LQFP

Document Number: 002-04926 Rev.*B Page 115 of 122 MB9B460L Series 002-13731 ** Package Type Package Code LQFP 48pin (0.5mm pitch) LQA048 DIM ENSIONS SYM BOL M IN. NOM . M AX. A 1.70 A1 0.00 0.20 b 0.15 0.27 c 0.09 0.20 D 9.00 BSC D1 7.00 BSC e 0.50 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70

9.00 BSC

7.00 BSC

0° 8°θ D e 1 12 EE1 5 7 b

0.80 C A-B D

A SEATING PLANE θ A A10.25 b SECTION A-A' c L 0.80 C 4813 36 25 25 36 7.0X7.0X1.7 MM LQA048 REV** PACKAGE OUTLINE, 48 LEAD LQFP

Document Number: 002-04926 Rev.*B Page 116 of 122 MB9B460L Series 002-13234 ** Package Type Package Code QFN 64pin (0.5mm pitch) VNC064 DIMENSIONS NOM.MIN. b E

5.50 BSC

D A 0.00 SYMBOL MAX. 0.90 0.05 2. DIMENSIONING AND TOLERANCINCCONFORMSTO ASME Y14.5- 1994. 3. N ISTHE TOTAL NUMBEROF TERMINALS. 4. DIMENSION "b"APPLIESTO METALLIZED TERMINAL AND ISM EASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINALHAS THE OPTIONAL RADIUSON THE OTHEREND OF THE TERMINAL. THE DIMENSION "b"SHOULD NOTBE MEASURED IN THATRADIUSAREA. 5. ND REFERTO THE NUMBEROF TERMINALSON D ORESID E. 6. MAX. PACKAGE WARPAGE IS0.05mm. 1. ALL DIMENSIONSARE IN MILLIMETERS.

0.50 BSC

L 0.20 0.25 0.30 E 2 5.50 BSC e R 0.20 REF 7. MAXIMUM ALLOWABLE BURRSIS0.076mm IN ALL DIRECTIONS. 8. PIN #1 ID ON TOP WILLBELOCATED W ITHIN INDICATED ZONE. 9. BILATERAL COPLANARITY ZONE APPLIESTO THE EXPOSEDHEAT SINK SLUG ASWELL ASTHE TERMINALS. 0.400.35 0.45 NOTE 10. JEDECSPEC IFICATIONNO . REF: N/A SIDE VIEW BOTTOM VIEW TOP VIEW D A E B 0.10 C 0.10 C 0.10 CA 0.05 C C SEATING PLANE

0.10 C A B

e b 0.10 C A B 0.05 C R ( N D -1)× e IND EX MA RK L 9 12 3625 PACKAGEOUTLINE, 48 LEAD QFN

Document Number: 002-04926 Rev.*B Page 117 of 122 MB9B460L Series 002-15528 ** Package Type Package Code QFN 48pin (0.5mm pitch) VNA048 DIMENSIONS NOM.MIN. b E D A 0.00 SYMBOL MAX. 0.90 0.05 2. DIMENSIONING AND TOLERANCINCCONFORMSTO ASME Y14.5- 1994. 3. N ISTHE TOTAL NUMBEROF TERMINALS. 4. DIMENSION "b"APPLIESTO METALLIZED TERMINAL AND ISM EASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINALHAS THE OPTIONAL RADIUSON THE OTHEREND OF THE TERMINAL. THE DIMENSION "b"SHOULD NOTBE MEASURED IN THATRADIUSAREA. 5. ND REFERTO THE NUMBEROF TERMINALSON D ORESID E. 6. MAX. PACKAGE WARPAGE IS0.05mm. 1. ALL DIMENSIONSARE IN MILLIMETERS. L 0.20 0.25 0.30 E 2 5.50 BSC e R 0.20 REF 7. MAXIMUM ALLOWABLE BURRSIS0.076mm IN ALL DIRECTIONS. 8. PIN #1 ID ON TOP WILLBELOCATED W ITHIN INDICATED ZONE. 9. BILATERAL COPLANARITY ZONE APPLIESTO THE EXPOSEDHEAT SINK SLUG ASWELL ASTHE TERMINALS. 0.400.35 0.45 NOTE 10. JEDECSPEC IFICATIONNO . REF: N/A SIDE VIEW BOTTOM VIEW TOP VIEW D A E B 0.10 C 0.10 C 0.10 CA 0.05 C C SEATING PLANE e b 0.10 C A B 0.05 C R ( N D -1)× e IND EX MA RK L 9 12 3625 PACKAGEOUTLINE, 48 LEAD QFN

Document Number: 002-04926 Rev.*B Page 118 of 122 MB9B460L Series 15. Major Changes Spansion Publication Number: DS709-00006 Page Section Change Results - - Preliminary → Data Sheet 31 to 34 ■I/O CIRCUIT TYPE Added the following description to Remarks of Type F, G, I, L, M, N : When this pin is used as an I2C pin, the digital output P-ch transistor is always off 35 to 36 Added the following description to Remarks of Type O, P, Q: For I/O setting, refer to VBAT Domain in the PERIPHERAL MANUAL 43 ■HANDLING DEVICES Handling when using debug pins Added new section 44 ■BLOCK DIAGRAM Revised the block diagram ■ELECTRICAL CHARACTERISTICS 2. Recommended Operating Conditions Added the note to “AVRH” Revised “Table for package thermal resistance and maximum permissible power”

58 Revised “Icc(leakmax)”

■ELECTRICAL CHARACTERISTICS 3. DC Characteristics (1) Current Rating

• Revised the value of TBD
• Added the note to “ICC”
• Added the note to “ICCVBAT” ■ELECTRICAL CHARACTERISTICS 4. AC Characteristics (2) Sub Clock Input Characteristics Revised the waveform chart : VCC → VBAT ■ELECTRICAL CHARACTERISTICS 4. AC Characteristics (3) Built-in CR OscillationCharacteristics
• Revised the value of TBD
• Revised the table and the note of “Built-in High-speed CR” ■ELECTRICAL CHARACTERISTICS 4. AC Characteristics (4-1) Operating Conditions of Main PLL(In the case of using main clock for input clock of PLL)
• Revised the table and the note ■ELECTRICAL CHARACTERISTICS 4. AC Characteristics (4-2) Operating Conditions of Main PLL(In the case of using built-in high-speed CR clock for input clock of main PLL)
• Revised the value of TBD
• Revised the table and the note 106 ■ELECTRICAL CHARACTERISTICS 5. 12-bit A/D Converter ・Electrical Characteristics for the A/D Converter
• Revised the value of TBD
• Revised the condition of the electrical characteristics table
• Revised the description of "Reference voltage" 109 ■ELECTRICAL CHARACTERISTICS 6. 12-bit D/A Converter ・Electrical Characteristics for the D/A Converter
• Revised the value of TBD
• Revised the condition of the electrical characteristics table
• Revised the remarks of “IDDA” 112 ■ELECTRICAL CHARACTERISTICS 11. Standby Recovery Time (1) Recovery cause: Interrupt/WKUP
• Revised the value of TBD
• Revised the table of Recovery count time 114 ■ELECTRICAL CHARACTERISTICS 11. Standby Recovery Time (2) Recovery cause:Reset
• Revised the value of TBD
• Revised the table of Recovery count time NOTE: Please see “Document History” about later revised information.

Document Number: 002-04926 Rev.*B Page 119 of 122 MB9B460L Series Document History Document Title: MB9B460L Series 32-Bit Arm® Cortex®-M4F, FM4 Microcontroller Document Number: 002-04926 Revision ECN Orig. of Change Submission Date Description of Change ** - AKIH 12/25/2013 Migrated to Cypress and assigned document number 002-04926. No change to document contents or format. *A 5273878 AKIH 05/12/2016 Updated to Cypress format. *B 5555936 YSKA 12/15/2017 Added an explanation of product category in introduction (Page 1). Changed an explanation from “from 01 to 99” to “from 00 to 99” in Real-Time Clock (RTC) (Page 3) of Features, and Deleted “Second/A day of the week” of interrupt function. Divided an explanation into 64 pin and 48 pin in Power Supply (Page 4) of Features. Changed package code as the following in chapter : 2. Packages (Page 8) 3. Pin Assignment (Page 9 - 12)

12.2 Recommended Operating Conditions (Page 53)

13.Ordering Information (Page 112) 14. Package Dimensions (Page 113-117). FTP-48P-M49 -> LQA048, LCC-48P-M73 -> VNA048, FTP-64P-M38 -> LQD064, FTP-64P-M39 -> LQG064, LCC-64P-M24 -> VNC064 Changed 15 pin (Page 14) at LQFP48 from VBAT to VCC in 4.1 List of Pin Numbers. Added 15 pin (Page 27) to VCC of Power at LQFP48, Deleted 15 pin from VBAT of VBAT Power at LQFP48 in 4.2 List of Pin Functions. Added Note for JTAG pin (Page 27) in 4. Pin Description. Added an explanation in Notes on Power-on (Page 39) of 7. Handling Devices. Corrected "total maximum output current" to "total average output current" at ∑ IOLAV in 12.1 Absolute Maximum Ratings (Page52). Added Smoothing capacitor to Parameter, and Add remarks *4 in 12.2 Recommended Operating Conditions (Page 53). Changed remark *3 to "When all ports are input and are fixed at "0"." in 12.3.1 Current Rating (Page 56 - 61). In 12.3.1 Current Rating, Added remark *6 to ICCHD, Added remark *7 to ICCRD, Added remark *8/*9 to ICCVBAT/RTC operation, and Added remark *9 to ICCVBAT/RTC stop (Page 61). Added an explanation for 48 pin package in 12.4.2 Sub Clock Input Characteristics (Page 66). Changed Parameter “Power supply rising time (t VCCR)” to “Power ramp rate (dV/dt)” in 12.4.7 Power-on Reset Timing, Changed the minimum to 1.3mV/μs, Changed the maximum to 1000mV/μs, and Added remarks and note (Page 68). Deleted setting value “SPI=1” and “MS=0” at using chip select in 12.4.10 UART

Document Number: 002-04926 Rev.*B Page 120 of 122 MB9B460L Series Revision ECN Orig. of Change Submission Date Description of Change Timing, and Added “MS bit = 0” and “MS bit = 1” on the Figure (Page 88-94). Corrected "Analog port input current" to "Analog port input leak current" in 12.5 12-bit A/D Converter (Page 102). Reflected the following items in "Datasheet Errata for the MB9B460L Series (002-04927)". Added “IOH = -20.5 mA, IOL = 18.5 mA” to remarks in Type H (Page 30) of 5.I/O Circuit Type. Added “Pull-up resister : Approximately 50 kΩ” to remarks in Type I (Page 31) of 5.I/O Circuit Type. Modified S/T of VBAT Pin Status Type and remark *2 in List of VBAT Domain Pin Status (Page 51) of 11.Pin Status in Each CPU State. Added remarks *3 in 12.2 Recommended Operating Conditions (Page 53). Added Frequency stabilization time to Parameter, and Added remarks *2 in Built-in High-speed CR of 12.4.3 Built-in CR Oscillation Characteristics (Page 66). Added Conversion time to Parameter in Electrical Characteristics for the D/A Converter of 12.6 12-bit D/A Converter (Page 105). Revised Recovery Count Time of 12.10.1 Recovery cause: Interrupt/WKUP (Page 108) as follows. - Typical Value of Sub timer mode is 896μs. - Typical Value of RTC mode stop mode (High-speed CR / Main/PLL run mode return) is 316μs. - Typical Value of RTC mode stop mode (Low-speed CR / sub run mode return) is 270μs, and Max Value is 540μs. - Typical Value of Deep standby RTC mode without RAM retention is 365μs. - Typical Value of Deep standby RTC mode with RAM retention is 365μs. Revised Recovery Count Time of 12.10.2 Recovery cause: Reset (Page 110) as follows. - Typical Value of Sleep mode is 155μs. - Typical Value of High-speed CR timer mode is 155μs. - Typical Value of Low-speed CR timer mode is 315μs. - Typical Value of Sub timer mode is 315μs. - Typical Value of RTC mode stop mode is 315μs, Max Value is 567μs. - Typical Value of Deep standby RTC mode without RAM retention is 336μs. - Typical Value of Deep standby RTC mode with RAM retention is 336μs. (Page 71) Added the Baud rate spec in “12.4.10 CSIO/UART Timing”.(Page 71, 73, 75, 77) Modified the expression for “Reference power supply current” from “between AVRH and AVSS” to “AVRH” in chapter 12.5. 12-bit A/D Converter (Page 102) Moved the value(1.0) in “State transition time to operation permission” from minimum to maximum.(Page 102) Modified the expression of Built-in CR in “1. Product Lineup”(Page 7) Modified the mode name of I C as follows(Page 2, 99)

Document Number: 002-04926 Rev.*B Page 121 of 122 MB9B460L Series Revision ECN Orig. of Change Submission Date Description of Change High-speed mode  Fast-mode, Typical Mode  Standard-mode Modified the typo as below.(Page 71, 73, 75, 77) SCLKx_0  SCKx_0 Modified typo in the “Recovery Count Time” table in 12.10.1 Recovery cause: Interrupt/WKUP (Page 108) and 12.10.2 Recovery Cause: Reset (Page 110) as follows. Old) Deep standby RTC mode with RAM retention Deep standby stop mode with RAM retention New) Deep standby RTC mode Deep standby stop mode

Document Number: 002-04926 Rev.*B December 15, 2017 Page 122 of 122 MB9B460L Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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