MB9A1A0N

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Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 99

Technical content

Datasheet sections

• 6.1 Precautions for Product Design
• 6.2 Precautions for Package Mounting
• 6.3 Precautions for Use Environment
• 12.1 Absolute Maximum Ratings
• 12.2 Recommended Operating Conditions
• 12.3 DC Characteristics
• 12.3.1 Current Rating
• 12.3.2 Pin Characteristics
• 12.4 AC Characteristics
• 12.4.1 Main Clock Input Characteristics
• 12.4.2 Sub Clock Input Characteristics
• 12.4.3 Built-in CR Oscillation Characteristics
• 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
• 12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock
• 12.4.6 Reset Input Characteristics
• 12.4.7 Power-on Reset Timing
• 12.4.8 Base Timer Input Timing
• 12.4.9 CSIO/UART Timing
• 12.4.10 External Input Timing
• 12.4.11 I2C Timing
• 12.4.12 JTAG Timing
• 12.7 Low-Voltage Detection Characteristics
• 12.7.1 Low-Voltage Detection Reset
• 12.7.2 Interrupt of Low-Voltage Detection
• 12.8 Flash Memory Write/Erase Characteristics
• 12.8.1 Write / Erase time
• 12.8.2 Write cycles and data hold time
• 12.9 Return Time from Low-Power Consumption Mode
• 12.9.1 Return Factor: Interrupt/WKUP
• 12.9.2 Return Factor: Reset

Features

32-bit ARM® Cortex®-M3 Core  Processor version: r2p1  Up to 20 MHz Operation Frequency  Integrated Nested Vectored Interrupt Controller (NVIC): 1 channel NMI (non-maskable interrupt) and 32 channels' peripheral interrupts and 8 priority levels  24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory]  Up to 128 Kbytes  Read cycle: 0 wait-cycle  Security function for code protection [SRAM] This series contains a total of up to 16 Kbyte on-chip SRAM that is connected to System bus of Cortex-M3 core.  SRAM1: Up to 16 Kbytes Multi-function Serial Interface (Max 8 channels) Operation mode is selectable from the followings for each channel.  UART  CSIO  I2C [UART]  Full duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO]  Full duplex double buffer  Built-in dedicated baud rate generator  Overrun error detection function available [I2C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported A/D Converter (Max 16 channels) [12-bit A/D Converter]  Successive Approximation type  Conversion time: Min 1.0 μs  Priority conversion available (priority at 2levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion: 4steps) D/A Converter (Max 2 channels)  R-2R type  10-bit resolution Base Timer (Max 8 channels) Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer

Document Number: 002-05675 Rev.*C Page 2 of 99 MB9A1A0N Series General-Purpose I/O Port This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up to 84 high-speed general-purpose I/O Ports@100 pin Package  Some ports are 5 V tolerant I/O See List of Pin Functions and I/O Circuit Type to confirm the corresponding pins. Multi-function Timer The Multi-function timer is composed of the following blocks.  16-bit free-run timer × 3ch.  Input capture × 4ch.  Output compare × 6ch.  A/D activation compare × 1ch.  Waveform generator × 3ch.  16-bit PPG timer × 3ch. IGBT mode is contained The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D convertor activate function  DTIF (Motor emergency stop) interrupt function HDMI-CEC/Remote Control Receiver (Up to 2 channels) HDMI- CEC receiver / Remote control receiver  Operating modes supporting the following standards can be selected  SIRCS  NEC/Association for Electric Home Appliances  HDMI-CEC  Capable of adjusting detection timings for start bit and data bit  Equipped with noise filter HDMI-CEC transmitter  Header block automatic transmission by judging Signal free  Generating status interrupt by detecting Arbitration lost  Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data  Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK) Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.  The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. External Interrupt Controller Unit  Up to 16 external interrupt input pins  Include one non-maskable interrupt (NMI) input pin Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog. The Hardware watchdog timer is clocked by the built-in Low-speed CR oscillator. Therefore, the Hardware watchdog is active in any low-power consumption mode except RTC, Stop, Deep Standby RTC and Deep Standby Stop modes. Clock and Reset [Clocks] Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL).  Main Clock: 4 MHz to 20 MHz  Sub Clock: 32.768 kHz  Built-in High-speed CR Clock: 4 MHz  Built-in Low-speed CR Clock: 100 kHz  Main PLL Clock

Document Number: 002-05675 Rev.*C Page 3 of 99 MB9A1A0N Series [Resets]  Reset requests from INITX pin  Power-on reset  Software reset  Watchdog timers reset  Low-voltage detection reset  Clock Super Visor reset Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.  If external clock failure (clock stop) is detected, reset is asserted.  If external frequency anomaly is detected, interrupt or reset is asserted. Low-Voltage Detector (LVD) This Series includes 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage that has been set, Low-Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation Low-Power Consumption Mode Six low-power consumption modes supported.  Sleep  Timer  RTC  Stop  Deep Standby RTC  Deep Standby Stop The back up register is 16 bytes. Debug Serial Wire JTAG Debug Port (SWJ-DP) Power Supply Wide range voltage: VCC = 1.8 V to 5.5 V

Document Number: 002-05675 Rev.*C Page 5 of 99 MB9A1A0N Series

Document Number: 002-05675 Rev.*C Page 6 of 99 MB9A1A0N Series 1. Product Lineup Memory size Product name MB9AF1A1L/M/N MB9AF1A2L/M/N On-chip Flash memory 64 Kbytes 128 Kbytes On-chip SRAM SRAM1 12 Kbytes 16 Kbytes Function Product name MB9AF1A1L MB9AF1A2L MB9AF1A1M MB9AF1A2M MB9AF1A1N MB9AF1A2N Pin count 64 80 100 CPU Cortex-M3 Freq. 20 MHz Power supply voltage range 1.8 V to 5.5 V Multi-function Serial Interface (UART/CSIO/I2C) 8ch. (Max) Base Timer (PWC/ Reload timer/PWM/PPG) 8ch. (Max) MF- Timer A/D activation compare 1ch. 1 unit (Max) Input capture 4ch. Free-run timer 3ch. Output compare 6ch. Waveform generator 3ch. PPG (IGBT mode) 3ch. HDMI-CEC/ Remote Control Receiver 2ch. (Max) Real-time clock (RTC) 1 unit Watchdog timer 1ch. (SW) + 1ch. (HW) External Interrupts 8 pins (Max)+ NMI × 1 11 pins (Max)+ NMI × 1 16 pins (Max)+ NMI × 1 General-purpose I/O ports 52 pins (Max) 67 pins (Max) 84 pins (Max) 12-bit A/D converter 9ch. (1 unit) 12ch. (1 unit) 16ch. (1 unit) 10-bit D/A converter 2ch. (Max) CSV (Clock Super Visor) Yes LVD (Low-Voltage Detector) 2ch. Built-in CR High-speed 4 MHz Low-speed 100 kHz Debug Function SWJ-DP Note: − All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Electrical Characteristics 12.4 AC Characteristics 12.4.3 Built-in CR Oscillation Characteristics for accuracy of built-in CR.

Document Number: 002-05675 Rev.*C Page 7 of 99 MB9A1A0N Series 2. Packages Product name Package MB9AF1A1L MB9AF1A2L MB9AF1A1M MB9AF1A2M MB9AF1A1N MB9AF1A2N LQFP: LQD064 (0.5mm pitch)  - - LQFP: LQG064 (0.65mm pitch)  - - LQFP: LQH080 (0.5mm pitch) -  - LQFP: LQJ080 (0.65mm pitch) -  - LQFP: LQI100 (0.5mm pitch) - -  QFP: PQH100 (0.65mm pitch) - -  : Supported Note: − See Package Dimensions for detailed information on each package.

Document Number: 002-05675 Rev.*C Page 8 of 99 MB9A1A0N Series 3. Pin Assignment LQD064/LQG064 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P82 / SCK7_2 P81 / SOT7_2 P80 / SIN7_2 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P62 / SCK5_0 / ADTG_3 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX VCC 1 48 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 47 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 46 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 45 P19 / AN09 / SCK2_2 P30 / TIOB0_1 / INT03_2 5 44 P18 / AN08 / SOT2_2 P31 / SCK6_1 / TIOB1_1 / INT04_2 6 43 AVSS P32 / SOT6_1 / TIOB2_1 / INT05_2 7 42 AVRH P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 8 41 AVCC P39 / DTTI0X_0 / ADTG_2 9 40 P17 / AN07 / SIN2_2 / INT04_1 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 10 39 P15 / AN05 / IC03_2 P3B / TIOA1_1 / RTO01_0 11 38 P14 / AN04 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 12 37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 13 36 P12 / AN02 / SOT1_1 / IC00_2 P3E / TIOA4_1 / RTO04_0 14 35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 P3F / TIOA5_1 / RTO05_0 15 34 P10 / AN00 VSS 16 33 VCC C VCC P46 / X0A P47 / X1A INITX P49 / TIOB0_0 P4A / TIOB1_0 P4B / TIOB2_0 / IGTRG P4C / SCK7_1 / TIOB3_0 / CEC0 P4D / SOT7_1 / TIOB4_0 / DA0 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS LQFP - 64

Document Number: 002-05675 Rev.*C Page 9 of 99 MB9A1A0N Series LQH080/LQJ080 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P82 / SCK7_2 P81 / SOT7_2 P80 / SIN7_2 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P62 / SCK5_0 / ADTG_3 P63 / INT03_0 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0E / CTS4_0 / TIOB3_2 P0D / RTS4_0 / TIOA3_2 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P07 / ADTG_0 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX VCC 1 60 P20 / INT05_0 / CROUT_0 P50 / SIN3_1 / INT00_0 2 59 P21 / SIN0_0 / INT06_1 / WKUP2 P51 / SOT3_1 / INT01_0 3 58 P22 / SOT0_0 / TIOB7_1 P52 / SCK3_1 / INT02_0 4 57 P23 / SCK0_0 / TIOA7_1 P53 / SIN6_0 / TIOA1_2 / INT07_2 5 56 P1B / AN11 / SOT4_1 / IC01_1 P54 / SOT6_0 / TIOB1_2 6 55 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1 P55 / SCK6_0 / ADTG_1 7 54 P19 / AN09 / SCK2_2 P56 / INT08_2 8 53 P18 / AN08 / SOT2_2 P30 / TIOB0_1 / INT03_2 9 52 AVSS P31 / SCK6_1 / TIOB1_1 / INT04_2 10 51 AVRH P32 / SOT6_1 / TIOB2_1 / INT05_2 11 50 AVCC P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 12 49 P17 / AN07 / SIN2_2 / INT04_1 P39 / DTTI0X_0 / ADTG_2 13 48 P16 / AN06 / SCK0_1 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 14 47 P15 / AN05 / SOT0_1 / IC03_2 P3B / TIOA1_1 / RTO01_0 15 46 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 16 45 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 17 44 P12 / AN02 / SOT1_1 / IC00_2 P3E / TIOA4_1 / RTO04_0 18 43 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 P3F / TIOA5_1 / RTO05_0 19 42 P10 / AN00 VSS 20 41 VCC P44 / TIOA4_0 P45 / TIOA5_0 C VSS VCC P46 / X0A P47 / X1A INITX P48 / SIN3_2 / INT14_1 P49 / SOT3_2 / TIOB0_0 P4A / SCK3_2 / TIOB1_0 P4B / TIOB2_0 / IGTRG P4C / SCK7_1 / TIOB3_0 / CEC0 P4D / SOT7_1 / TIOB4_0 / DA0 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS LQFP - 80

Document Number: 002-05675 Rev.*C Page 10 of 99 MB9A1A0N Series LQI100 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P82 / SCK7_2 P81 / SOT7_2 P80 / SIN7_2 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P62 / SCK5_0 / ADTG_3 P63 / INT03_0 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0E / CTS4_0 / TIOB3_2 P0D / RTS4_0 / TIOA3_2 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P09 / RTS4_2 / TIOB0_2 P08 / CTS4_2 / TIOA0_2 P07 / SCK4_2 / ADTG_0 P06 / SOT4_2 / TIOB5_2 / INT01_1 P05 / SIN4_2 / TIOA5_2 / INT00_1 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX VCC 100 VCC 1 75 VSS P50 / SIN3_1 / INT00_0 2 74 P20 / INT05_0 / CROUT_0 P51 / SOT3_1 / INT01_0 3 73 P21 / SIN0_0 / INT06_1 / WKUP2 P52 / SCK3_1 / INT02_0 4 72 P22 / SOT0_0 / TIOB7_1 P53 / SIN6_0 / TIOA1_2 / INT07_2 5 71 P23 / SCK0_0 / TIOA7_1 / RTO00_1 P54 / SOT6_0 / TIOB1_2 6 70 P1F / AN15 / FRCK0_1 / ADTG_5 P55 / SCK6_0 / ADTG_1 7 69 P1E / AN14 / RTS4_1 / DTTI0X_1 P56 / INT08_2 8 68 P1D / AN13 / CTS4_1 / IC03_1 P30 / TIOB0_1 / INT03_2 9 67 P1C / AN12 / SCK4_1 / IC02_1 P31 / SCK6_1 / TIOB1_1 / INT04_2 10 66 P1B / AN11 / SOT4_1 / IC01_1 P32 / SOT6_1 / TIOB2_1 / INT05_2 11 65 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1 P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 12 64 P19 / AN09 / SCK2_2 P34 / TIOB4_1 / FRCK0_0 13 63 P18 / AN08 / SOT2_2 P35 / TIOB5_1 / INT08_1 / IC03_0 14 62 AVSS P36 / SIN5_2 / INT09_1 / IC02_0 15 61 AVRH P37 / SOT5_2 / INT10_1 / IC01_0 16 60 AVCC P38 / SCK5_2 / INT11_1 / IC00_0 17 59 P17 / AN07 / SIN2_2 / INT04_1 P39 / DTTI0X_0 / ADTG_2 18 58 P16 / AN06 / SCK0_1 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 19 57 P15 / AN05 / SOT0_1 / IC03_2 P3B / TIOA1_1 / RTO01_0 20 56 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 21 55 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 22 54 P12 / AN02 / SOT1_1 / IC00_2 P3E / TIOA4_1 / RTO04_0 23 53 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 P3F / TIOA5_1 / RTO05_0 24 52 P10 / AN00 VSS 25 51 VCC VCC P40 / TIOA0_0 / INT12_1 P41 / TIOA1_0 / INT13_1 P42 / TIOA2_0 P43 / TIOA3_0 / ADTG_7 P44 / TIOA4_0 P45 / TIOA5_0 C VSS VCC P46 / X0A P47 / X1A INITX P48 / SIN3_2 / INT14_1 P49 / SOT3_2 / TIOB0_0 P4A / SCK3_2 / TIOB1_0 P4B / TIOB2_0 / IGTRG P4C / SCK7_1 / TIOB3_0 / CEC0 P4D / SOT7_1 / TIOB4_0 / DA0 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS LQFP - 100

Document Number: 002-05675 Rev.*C Page 11 of 99 MB9A1A0N Series PQH100 (TOP VIEW) Note: − The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. P50 / SIN3_1 / INT00_0 VCC VSS P82 / SCK7_2 P81 / SOT7_2 P80 / SIN7_2 P60 / SIN5_0 / TIOA2_2 / INT15_1 / WKUP3 / CEC1 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P62 / SCK5_0 / ADTG_3 P63 / INT03_0 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0E / CTS4_0 / TIOB3_2 P0D / RTS4_0 / TIOA3_2 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P09 / RTS4_2 / TIOB0_2 P08 / CTS4_2 / TIOA0_2 P07 / SCK4_2 / ADTG_0 P06 / SOT4_2 / TIOB5_2 / INT01_1 P05 / SIN4_2 / TIOA5_2 / INT00_1 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX VCC VSS P20 / INT05_0 / CROUT_0 P21 / SIN0_0 / INT06_1 / WKUP2 P51 / SOT3_1 / INT01_0 81 50 P22 / SOT0_0 / TIOB7_1 P52 / SCK3_1 / INT02_0 82 49 P23 / SCK0_0 / TIOA7_1 / RTO00_1 P53 / SIN6_0 / TIOA1_2 / INT07_2 83 48 P1F / AN15 / FRCK0_1 / ADTG_5 P54 / SOT6_0 / TIOB1_2 84 47 P1E / AN14 / RTS4_1 / DTTI0X_1 P55 / SCK6_0 / ADTG_1 85 46 P1D / AN13 / CTS4_1 / IC03_1 P56 / INT08_2 86 45 P1C / AN12 / SCK4_1 / IC02_1 P30 / TIOB0_1 / INT03_2 87 44 P1B / AN11 / SOT4_1 / IC01_1 P31 / SCK6_1 / TIOB1_1 / INT04_2 88 43 P1A / AN10 / SIN4_1 / INT05_1 / IC00_1 P32 / SOT6_1 / TIOB2_1 / INT05_2 89 42 P19 / AN09 / SCK2_2 P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 90 41 P18 / AN08 / SOT2_2 P34 / TIOB4_1 / FRCK0_0 91 40 AVSS P35 / TIOB5_1 / INT08_1 / IC03_0 92 39 AVRH P36 / SIN5_2 / INT09_1 / IC02_0 93 38 AVCC P37 / SOT5_2 / INT10_1 / IC01_0 94 37 P17 / AN07 / SIN2_2 / INT04_1 P38 / SCK5_2 / INT11_1 / IC00_0 95 36 P16 / AN06 / SCK0_1 P39 / DTTI0X_0 / ADTG_2 96 35 P15 / AN05 / SOT0_1 / IC03_2 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 97 34 P14 / AN04 / SIN0_1 / INT03_1 / IC02_2 P3B / TIOA1_1 / RTO01_0 98 33 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3C / TIOA2_1 / RTO02_0 99 32 P12 / AN02 / SOT1_1 / IC00_2 P3D / TIOA3_1 / RTO03_0 100 31 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / WKUP1 P3E / TIOA4_1 / RTO04_0 P3F / TIOA5_1 / RTO05_0 VSS VCC P40 / TIOA0_0 / INT12_1 P41 / TIOA1_0 / INT13_1 P42 / TIOA2_0 P43 / TIOA3_0 / ADTG_7 P44 / TIOA4_0 P45 / TIOA5_0 C VSS VCC P46 / X0A P47 / X1A INITX P48 / SIN3_2 / INT14_1 P49 / SOT3_2 / TIOB0_0 P4A / SCK3_2 / TIOB1_0 P4B / TIOB2_0 / IGTRG P4C / SCK7_1 / TIOB3_0 / CEC0 P4D / SOT7_1 / TIOB4_0 / DA0 P4E / SIN7_1 / TIOB5_0 / INT06_2 / DA1 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS VCC P10 / AN00 QFP - 100

Document Number: 002-05675 Rev.*C Page 12 of 99 MB9A1A0N Series 4. List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Pin name I/O circuit type Pin state type LQFP-64 LQFP-80 LQFP-100 QFP-100 1 1 1 79 VCC - 2 2 2 80 P50 E F INT00_0 SIN3_1 3 3 3 81 P51 E F INT01_0 SOT3_1 (SDA3_1) 4 4 4 82 P52 E F INT02_0 SCK3_1 (SCL3_1) - 5 5 83 P53 E F SIN6_0 TIOA1_2 INT07_2 - 6 6 84 P54 E H SOT6_0 (SDA6_0) TIOB1_2 - 7 7 85 P55 E H SCK6_0 (SCL6_0) ADTG_1 - 8 8 86 P56 E O INT08_2 5 9 9 87 P30 E F TIOB0_1 INT03_2 6 10 10 88 P31 E F TIOB1_1 SCK6_1 (SCL6_1) INT04_2 7 11 11 89 P32 E F TIOB2_1 SOT6_1 (SDA6_1) INT05_2

Document Number: 002-05675 Rev.*C Page 13 of 99 MB9A1A0N Series Pin No Pin name I/O circuit type Pin state type LQFP-64 LQFP-80 LQFP-100 QFP-100 8 12 12 90 P33 E F INT04_0 TIOB3_1 SIN6_1 ADTG_6 - - 13 91 P34 E H FRCK0_0 TIOB4_1 - - 14 92 P35 E F IC03_0 TIOB5_1 INT08_1 - - 15 93 P36 E F IC02_0 SIN5_2 INT09_1 - - 16 94 P37 E F IC01_0 SOT5_2 (SDA5_2) INT10_1 - - 17 95 P38 E F IC00_0 SCK5_2 (SCL5_2) INT11_1 9 13 18 96 P39 E H DTTI0X_0 ADTG_2 10 14 19 97 P3A E H RTO00_0 (PPG00_0) TIOA0_1 RTCCO_2 SUBOUT_2 11 15 20 98 P3B E H RTO01_0 (PPG00_0) TIOA1_1 12 16 21 99 P3C E H RTO02_0 (PPG02_0) TIOA2_1

Document Number: 002-05675 Rev.*C Page 14 of 99 MB9A1A0N Series Pin No Pin name I/O circuit type Pin state type LQFP-64 LQFP-80 LQFP-100 QFP-100 13 17 22 100 P3D E H RTO03_0 (PPG02_0) TIOA3_1 14 18 23 1 P3E E H RTO04_0 (PPG04_0) TIOA4_1 15 19 24 2 P3F E H RTO05_0 (PPG04_0) TIOA5_1 16 20 25 3 VSS - - - 26 4 VCC - - - 27 5 P40 E F TIOA0_0 INT12_1 - - 28 6 P41 E F TIOA1_0 INT13_1 - - 29 7 P42 E H TIOA2_0 - - 30 8 P43 E H TIOA3_0 ADTG_7 - 21 31 9 P44 E H TIOA4_0 - 22 32 10 P45 E H TIOA5_0 17 23 33 11 C - - 24 34 12 VSS - 18 25 35 13 VCC - 19 26 36 14 P46 D M X0A 20 27 37 15 P47 D N X1A 21 28 38 16 INITX B C - 29 39 17 P48 E F INT14_1 SIN3_2

Document Number: 002-05675 Rev.*C Page 15 of 99 MB9A1A0N Series Pin No Pin name I/O circuit type Pin state type LQFP-64 LQFP-80 LQFP-100 QFP-100 30 40 18 P49 E H TIOB0_0 - SOT3_2 (SDA3_2) 31 41 19 P4A E H TIOB1_0 - SCK3_2 (SCL3_2) 24 32 42 20 P4B E H TIOB2_0 IGTRG 25 33 43 21 P4C G Q TIOB3_0 SCK7_1 (SCL7_1) CEC0 26 34 44 22 P4D J T TIOB4_0 SOT7_1 (SDA7_1) DA0 27 35 45 23 P4E J S TIOB5_0 INT06_2 SIN7_1 DA1 28 36 46 24 PE0 C P MD1 29 37 47 25 MD0 H D 30 38 48 26 PE2 A A 31 39 49 27 PE3 A B 32 40 50 28 VSS - 33 41 51 29 VCC - 34 42 52 30 P10 F J AN00 35 43 53 31 P11 F L AN01 SIN1_1 INT02_1 FRCK0_2 WKUP1

Document Number: 002-05675 Rev.*C Page 16 of 99 MB9A1A0N Series Pin No Pin name I/O circuit type Pin state type LQFP-64 LQFP-80 LQFP-100 QFP-100 36 44 54 32 P12 F J AN02 SOT1_1 (SDA1_1) IC00_2 37 45 55 33 P13 F J AN03 SCK1_1 (SCL1_1) IC01_2 RTCCO_1 SUBOUT_1 46 56 34 P14 F K AN04 IC02_2 INT03_1 - SIN0_1 47 57 35 P15 F J AN05 IC03_2 - SOT0_1 (SDA0_1) - 48 58 36 P16 F J AN06 SCK0_1 (SCL0_1) 40 49 59 37 P17 F K AN07 SIN2_2 INT04_1 41 50 60 38 AVCC - 42 51 61 39 AVRH - 43 52 62 40 AVSS - 44 53 63 41 P18 F J AN08 SOT2_2 (SDA2_2) 45 54 64 42 P19 F J AN09 SCK2_2 (SCL2_2)

Document Number: 002-05675 Rev.*C Page 17 of 99 MB9A1A0N Series Pin No Pin name I/O circuit type Pin state type LQFP-64 LQFP-80 LQFP-100 QFP-100 - 55 65 43 P1A F K AN10 SIN4_1 INT05_1 IC00_1 - 56 66 44 P1B F J AN11 SOT4_1 (SDA4_1) IC01_1 - - 67 45 P1C F J AN12 SCK4_1 (SCL4_1) IC02_1 - - 68 46 P1D F J AN13 CTS4_1 IC03_1 - - 69 47 P1E F J AN14 RTS4_1 DTTI0X_1 - - 70 48 P1F F J AN15 ADTG_5 FRCK0_1 46 57 71 49 P23 E H SCK0_0 (SCL0_0) TIOA7_1 - - RTO00_1 47 58 72 50 P22 E H SOT0_0 (SDA0_0) TIOB7_1 48 59 73 51 P21 E G SIN0_0 INT06_1 WKUP2 - 60 74 52 P20 E F INT05_0 CROUT_0

Document Number: 002-05675 Rev.*C Page 18 of 99 MB9A1A0N Series Pin No Pin name I/O circuit type Pin state type LQFP-64 LQFP-80 LQFP-100 QFP-100 - - 75 53 VSS - - - 76 54 VCC - 49 61 77 55 P00 E E TRSTX 50 62 78 56 P01 E E TCK SWCLK 51 63 79 57 P02 E E TDI 52 64 80 58 P03 E E TMS SWDIO 53 65 81 59 P04 E E TDO SWO - - 82 60 P05 E F TIOA5_2 SIN4_2 INT00_1 - - 83 61 P06 E F TIOB5_2 SOT4_2 (SDA4_2) INT01_1 84 62 P07 E H ADTG_0 - SCK4_2 (SCL4_2) - - 85 63 P08 E H TIOA0_2 CTS4_2 - - 86 64 P09 E H TIOB0_2 RTS4_2 54 67 87 65 P0A G F SIN4_0 INT00_2 55 68 88 66 P0B G H SOT4_0 (SDA4_0) TIOB6_1 56 69 89 67 P0C G H SCK4_0 (SCL4_0) TIOA6_1

Document Number: 002-05675 Rev.*C Page 19 of 99 MB9A1A0N Series Pin No Pin name I/O circuit type Pin state type LQFP-64 LQFP-80 LQFP-100 QFP-100 - 70 90 68 P0D E H RTS4_0 TIOA3_2 - 71 91 69 P0E E H CTS4_0 TIOB3_2 57 72 92 70 P0F E I NMIX CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 - 73 93 71 P63 E O INT03_0 58 74 94 72 P62 E H SCK5_0 (SCL5_0) ADTG_3 59 75 95 73 P61 E H SOT5_0 (SDA5_0) TIOB2_2 DTTI0X_2 60 76 96 74 P60 G R SIN5_0 TIOA2_2 INT15_1 WKUP3 CEC1 61 77 97 75 P80 G H SIN7_2 62 78 98 76 P81 G H SOT7_2 (SDA7_2) 63 79 99 77 P82 G H SCK7_2 (SCL7_2) 64 80 100 78 VSS -

Document Number: 002-05675 Rev.*C Page 20 of 99 MB9A1A0N Series List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function Pin name Function description Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 ADC ADTG_0 A/D converter external trigger input pin - 66 84 62 ADTG_1 - 7 7 85 ADTG_2 9 13 18 96 ADTG_3 58 74 94 72 ADTG_4 - - - - ADTG_5 - - 70 48 ADTG_6 8 12 12 90 ADTG_7 - - 30 8 ADTG_8 - - - - AN00 A/D converter analog input pin. ANxx describes ADC ch.xx. 34 42 52 30 AN01 35 43 53 31 AN02 36 44 54 32 AN03 37 45 55 33 AN04 38 46 56 34 AN05 39 47 57 35 AN06 - 48 58 36 AN07 40 49 59 37 AN08 44 53 63 41 AN09 45 54 64 42 AN10 - 55 65 43 AN11 - 56 66 44 AN12 - - 67 45 AN13 - - 68 46 AN14 - - 69 47 AN15 - - 70 48

Document Number: 002-05675 Rev.*C Page 21 of 99 MB9A1A0N Series Pin function Pin name Function description Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 Base Timer TIOA0_0 Base timer ch.0 TIOA pin - - 27 5 TIOA0_1 10 14 19 97 TIOA0_2 - - 85 63 TIOB0_0 Base timer ch.0 TIOB pin 22 30 40 18 TIOB0_1 5 9 9 87 TIOB0_2 - - 86 64 Base Timer TIOA1_0 Base timer ch.1 TIOA pin - - 28 6 TIOA1_1 11 15 20 98 TIOA1_2 - 5 5 83 TIOB1_0 Base timer ch.1 TIOB pin 23 31 41 19 TIOB1_1 6 10 10 88 TIOB1_2 - 6 6 84 Base Timer TIOA2_0 Base timer ch.2 TIOA pin - - 29 7 TIOA2_1 12 16 21 99 TIOA2_2 60 76 96 74 TIOB2_0 Base timer ch.2 TIOB pin 24 32 42 20 TIOB2_1 7 11 11 89 TIOB2_2 59 75 95 73 Base Timer TIOA3_0 Base timer ch.3 TIOA pin - - 30 8 TIOA3_1 13 17 22 100 TIOA3_2 - 70 90 68 TIOB3_0 Base timer ch.3 TIOB pin 25 33 43 21 TIOB3_1 8 12 12 90 TIOB3_2 - 71 91 69 Base Timer TIOA4_0 Base timer ch.4 TIOA pin - 21 31 9 TIOA4_1 14 18 23 1 TIOA4_2 - - - - TIOB4_0 Base timer ch.4 TIOB pin 26 34 44 22 TIOB4_1 - - 13 91 TIOB4_2 - - - - Base Timer TIOA5_0 Base timer ch.5 TIOA pin - 22 32 10 TIOA5_1 15 19 24 2 TIOA5_2 - - 82 60 TIOB5_0 Base timer ch.5 TIOB pin 27 35 45 23 TIOB5_1 - - 14 92 TIOB5_2 - - 83 61 Base Timer TIOA6_1 Base timer ch.6 TIOA pin 56 69 89 67 TIOB6_1 Base timer ch.6 TIOB pin 55 68 88 66 Base Timer TIOA7_0 Base timer ch.7 TIOA pin - - - - TIOA7_1 46 57 71 49 TIOA7_2 - - - - TIOB7_0 Base timer ch.7 TIOB pin - - - - TIOB7_1 47 58 72 50 TIOB7_2 - - - -

Document Number: 002-05675 Rev.*C Page 22 of 99 MB9A1A0N Series Pin function Pin name Function description Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 Debugger SWCLK Serial wire debug interface clock input pin 50 62 78 56 SWDIO Serial wire debug interface data input / output pin 52 64 80 58 SWO Serial wire viewer output pin 53 65 81 59 TRSTX JTAG reset input pin 49 61 77 55 TCK JTAG test clock input pin 50 62 78 56 TDI JTAG test data input pin 51 63 79 57 TMS JTAG test mode state input/output pin 52 64 80 58 TDO JTAG debug data output pin 53 65 81 59 External Interrupt INT00_0 External interrupt request 00 input pin 2 2 2 80 INT00_1 - - 82 60 INT00_2 54 67 87 65 INT01_0 External interrupt request 01 input pin 3 3 3 81 INT01_1 - - 83 61 INT02_0 External interrupt request 02 input pin 4 4 4 82 INT02_1 35 43 53 31 INT03_0 External interrupt request 03 input pin - 73 93 71 INT03_1 38 46 56 34 INT03_2 5 9 9 87 INT04_0 External interrupt request 04 input pin 8 12 12 90 INT04_1 40 49 59 37 INT04_2 6 10 10 88 INT05_0 External interrupt request 05 input pin - 60 74 52 INT05_1 - 55 65 43 INT05_2 7 11 11 89 INT06_1 External interrupt request 06 input pin 48 59 73 51 INT06_2 27 35 45 23 INT07_2 External interrupt request 07 input pin - 5 5 83 INT08_1 External interrupt request 08 input pin - - 14 92 INT08_2 - 8 8 86 INT09_1 External interrupt request 09 input pin - - 15 93 INT10_1 External interrupt request 10 input pin - - 16 94 INT11_1 External interrupt request 11 input pin - - 17 95 INT12_1 External interrupt request 12 input pin - - 27 5 INT13_1 External interrupt request 13 input pin - - 28 6 INT14_1 External interrupt request 14 input pin - 29 39 17 INT15_1 External interrupt request 15 input pin 60 76 96 74 NMIX Non-Maskable Interrupt input pin 57 72 92 70

Document Number: 002-05675 Rev.*C Page 23 of 99 MB9A1A0N Series Pin function Pin name Function description Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 GPIO P00 General-purpose I/O port 0 49 61 77 55 P01 50 62 78 56 P02 51 63 79 57 P03 52 64 80 58 P04 53 65 81 59 P05 - - 82 60 P06 - - 83 61 P07 - 66 84 62 P08 - - 85 63 P09 - - 86 64 P0A 54 67 87 65 P0B 55 68 88 66 P0C 56 69 89 67 P0D - 70 90 68 P0E - 71 91 69 P0F 57 72 92 70 P10 General-purpose I/O port 1 34 42 52 30 P11 35 43 53 31 P12 36 44 54 32 P13 37 45 55 33 P14 38 46 56 34 P15 39 47 57 35 P16 - 48 58 36 P17 40 49 59 37 P18 44 53 63 41 P19 45 54 64 42 P1A - 55 65 43 P1B - 56 66 44 P1C - - 67 45 P1D - - 68 46 P1E - - 69 47 P1F - - 70 48 P20 General-purpose I/O port 2 - 60 74 52 P21 48 59 73 51 P22 47 58 72 50 P23 46 57 71 49

Document Number: 002-05675 Rev.*C Page 24 of 99 MB9A1A0N Series Pin function Pin name Function description Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 GPIO P30 General-purpose I/O port 3 5 9 9 87 P31 6 10 10 88 P32 7 11 11 89 P33 8 12 12 90 P34 - - 13 91 P35 - - 14 92 P36 - - 15 93 P37 - - 16 94 P38 - - 17 95 P39 9 13 18 96 P3A 10 14 19 97 P3B 11 15 20 98 P3C 12 16 21 99 P3D 13 17 22 100 P3E 14 18 23 1 P3F 15 19 24 2 P40 General-purpose I/O port 4 - - 27 5 P41 - - 28 6 P42 - - 29 7 P43 - - 30 8 P44 - 21 31 9 P45 - 22 32 10 P46 19 26 36 14 P47 20 27 37 15 P48 - 29 39 17 P49 22 30 40 18 P4A 23 31 41 19 P4B 24 32 42 20 P4C 25 33 43 21 P4D 26 34 44 22 P4E 27 35 45 23 P50 General-purpose I/O port 5 2 2 2 80 P51 3 3 3 81 P52 4 4 4 82 P53 - 5 5 83 P54 - 6 6 84 P55 - 7 7 85 P56 - 8 8 86 P60 General-purpose I/O port 6 60 76 96 74 P61 59 75 95 73 P62 58 74 94 72 P63 - 73 93 71 P80 General-purpose I/O port 8 61 77 97 75 P81 62 78 98 76 P82 63 79 99 77 PE0 General-purpose I/O port E 28 36 46 24 PE2 30 38 48 26 PE3 31 39 49 27

Document Number: 002-05675 Rev.*C Page 25 of 99 MB9A1A0N Series Pin function Pin name Function description Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 Multi- function Serial SIN0_0 Multi-function serial interface ch.0 input pin 48 59 73 51 SIN0_1 - 46 56 34 SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA0 when it is used in an I2C (operation mode 4). 47 58 72 50 SOT0_1 (SDA0_1) - 47 57 35 SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 4). 46 57 71 49 SCK0_1 (SCL0_1) - 48 58 36 Multi- function Serial SIN1_1 Multi-function serial interface ch.1 input pin 35 43 53 31 SOT1_1 (SDA1_1) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). 36 44 54 32 SCK1_1 (SCL1_1) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). 37 45 55 33 Multi- function Serial SIN2_2 Multi-function serial interface ch.2 input pin 40 49 59 37 SOT2_2 (SDA2_2) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). 44 53 63 41 SCK2_2 (SCL2_2) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). 45 54 64 42

Document Number: 002-05675 Rev.*C Page 26 of 99 MB9A1A0N Series Pin function Pin name Function description Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 Multi- function Serial SIN3_1 Multi-function serial interface ch.3 input pin 2 2 2 80 SIN3_2 - 29 39 17 SOT3_1 (SDA3_1) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). 3 3 3 81 SOT3_2 (SDA3_2) - 30 40 18 SCK3_1 (SCL3_1) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). 4 4 4 82 SCK3_2 (SCL3_2) - 31 41 19 Multi- function Serial SIN4_0 Multi-function serial interface ch.4 input pin 54 67 87 65 SIN4_1 - 55 65 43 SIN4_2 - - 82 60 SOT4_0 (SDA4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). 55 68 88 66 SOT4_1 (SDA4_1) - 56 66 44 SOT4_2 (SDA4_2) - - 83 61 SCK4_0 (SCL4_0) Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). 56 69 89 67 SCK4_1 (SCL4_1) - - 67 45 SCK4_2 (SCL4_2) - - 84 62 RTS4_0 Multi-function serial interface ch.4 RTS output pin - 70 90 68 RTS4_1 - - 69 47 RTS4_2 - - 86 64 CTS4_0 Multi-function serial interface ch.4 CTS input pin - 71 91 69 CTS4_1 - - 68 46 CTS4_2 - - 85 63

Document Number: 002-05675 Rev.*C Page 27 of 99 MB9A1A0N Series Pin function Pin name Function description Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 Multi- function Serial SIN5_0 Multi-function serial interface ch.5 input pin 60 76 96 74 SIN5_2 - - 15 93 SOT5_0 (SDA5_0) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 4). 59 75 95 73 SOT5_2 (SDA5_2) - - 16 94 SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). 58 74 94 72 SCK5_2 (SCL5_2) - - 17 95 Multi- function Serial SIN6_0 Multi-function serial interface ch.6 input pin - 5 5 83 SIN6_1 8 12 12 90 SOT6_0 (SDA6_0) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 4). - 6 6 84 SOT6_1 (SDA6_1) 7 11 11 89 SCK6_0 (SCL6_0) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). - 7 7 85 SCK6_1 (SCL6_1) 6 10 10 88 Multi- function Serial SIN7_1 Multi-function serial interface ch.7 input pin 27 35 45 23 SIN7_2 61 77 97 75 SOT7_1 (SDA7_1) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). 26 34 44 22 SOT7_2 (SDA7_2) 62 78 98 76 SCK7_1 (SCL7_1) Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). 25 33 43 21 SCK7_2 (SCL7_2) 63 79 99 77

Document Number: 002-05675 Rev.*C Page 28 of 99 MB9A1A0N Series Pin function Pin name Function description Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 Multi- function Timer DTTI0X_0 Input signal of waveform generator to control outputs RTO00 to RTO05 of Multi-function timer 0 9 13 18 96 DTTI0X_1 - - 69 47 DTTI0X_2 59 75 95 73 FRCK0_0 16-bit free-run timer ch.0 external clock input pin - - 13 91 FRCK0_1 - - 70 48 FRCK0_2 35 43 53 31 IC00_0 16-bit input capture input pin of Multi-function timer 0. ICxx describes a channel number. - - 17 95 IC00_1 - 55 65 43 IC00_2 36 44 54 32 IC01_0 - - 16 94 IC01_1 - 56 66 44 IC01_2 37 45 55 33 IC02_0 - - 15 93 IC02_1 - - 67 45 IC02_2 38 46 56 34 IC03_0 - - 14 92 IC03_1 - - 68 46 IC03_2 39 47 57 35 RTO00_0 (PPG00_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. 10 14 19 97 RTO00_1 RTO01_0 (PPG00_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output mode. 11 15 20 98 RTO02_0 (PPG02_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. 12 16 21 99 RTO03_0 (PPG02_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output mode. 13 17 22 100 RTO04_0 (PPG04_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. 14 18 23 1 RTO05_0 (PPG04_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output mode. 15 19 24 2 IGTRG PPG IGBT mode external trigger input pin 24 32 42 20

Document Number: 002-05675 Rev.*C Page 29 of 99 MB9A1A0N Series Pin function Pin name Function description Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 Real-time clock RTCCO_0 Pulse output pin of Real-time clock 57 72 92 70 RTCCO_1 37 45 55 33 RTCCO_2 10 14 19 97 SUBOUT_0 Sub clock output pin 57 72 92 70 SUBOUT_1 37 45 55 33 SUBOUT_2 10 14 19 97 Low- Power Consumption Mode WKUP0 Deep standby mode return signal input pin 0 57 72 92 70 WKUP1 Deep standby mode return signal input pin 1 35 43 53 31 WKUP2 Deep standby mode return signal input pin 2 48 59 73 51 WKUP3 Deep standby mode return signal input pin 3 60 76 96 74 DAC DA0 D/A converter ch.0 analog output pin 26 34 44 22 DA1 D/A converter ch.1 analog output pin 27 35 45 23 HDMI- CEC CEC0 HDMI-CEC ch.0 pin 25 33 43 21 CEC1 HDMI-CEC ch.1 pin 60 76 96 74

Document Number: 002-05675 Rev.*C Page 30 of 99 MB9A1A0N Series Pin function Pin name Function description Pin No LQFP-64 LQFP-80 LQFP-100 QFP-100 Reset INITX External Reset Input Pin. A reset is valid when INITX = L. 21 28 38 16 Mode MD0 Mode 0 pin. During normal operation, MD0 = L must be input. During serial programming to Flash memory, MD0 = H must be input. 29 37 47 25 MD1 Mode 1 pin. During normal operation, input is not needed. During serial programming to Flash memory, MD1 = L must be input. 28 36 46 24 Power VCC Power supply pin 1 1 1 79 - - 26 4 18 25 35 13 33 41 51 29 - - 76 54 GND VSS GND pin 16 20 25 3 - 24 34 12 32 40 50 28 - - 75 53 64 80 100 78 Clock X0 Main clock (oscillation) input pin 30 38 48 26 X0A Sub clock (oscillation) input pin 19 26 36 14 X1 Main clock (oscillation) I/O pin 31 39 49 27 X1A Sub clock (oscillation) I/O pin 20 27 37 15 CROUT_0 Built-in High-speed CR-osc clock output port - 60 74 52 CROUT_1 57 72 92 70 Analog Power AVCC A/D converter and D/A converter analog power supply pin 41 50 60 38 AVRH A/D converter analog reference voltage input pin 42 51 61 39 Analog GND AVSS A/D converter and D/A converter GND pin 43 52 62 40 C pin C Power supply stabilization capacity pin 17 23 33 11 Note: − While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller.

Document Number: 002-05675 Rev.*C Page 31 of 99 MB9A1A0N Series 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function. When the main oscillation is selected.

• Oscillation feedback resistor : Approximately 1 MΩ
• With standby mode control When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA B
• CMOS level hysteresis input
• Pull-up resistor : Approximately 50 kΩ P-ch P-ch N-ch R R P-ch P-ch N-ch Pull-up resistor Feedback resistor Pull-up resistor Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control Pull-up resistor Digital input

Document Number: 002-05675 Rev.*C Page 32 of 99 MB9A1A0N Series Type Circuit Remarks C

• Open drain output
• CMOS level hysteresis input D It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected.
• Oscillation feedback resistor : Approximately 5 MΩ
• With standby mode control When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA N-ch P-ch P-ch N-ch R R P-ch P-ch N-ch X0A X1A Pull-up resistor Feedback resistor Pull-up resistor Digital input Digital output Digital output Digital output Pull-up resistor control Digital input Standby mode control Clock input Standby mode control Digital input Standby mode control Digital output Digital output Pull-up resistor control

Document Number: 002-05675 Rev.*C Page 33 of 99 MB9A1A0N Series Type Circuit Remarks E

• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off F
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off P-chP-ch N-ch R P-chP-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode control Digital output Digital output Pull-up resistor control Digital input Standby mode control Analog input Input control

Document Number: 002-05675 Rev.*C Page 34 of 99 MB9A1A0N Series Type Circuit Remarks G

• CMOS level output
• CMOS level hysteresis input
• With standby mode control
• 5 V tolerant input
• IOH = -4 mA, IOL = 4 mA
• Available to control PZR registers. P0B, P0C, P4C, P60, P81, P82 only.
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off H CMOS level hysteresis input J
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog output
• With pull-up resistor control
• With standby mode control
• Pull-up resistor : Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off P-ch N-ch R P-chP-ch N-ch R Mode input Digital output Digital output Digital input Standby mode control Pull-up resistor control Analog output Digital output Digital output Digital input Standby mode control

Document Number: 002-05675 Rev.*C Page 35 of 99 MB9A1A0N Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

6.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

Document Number: 002-05675 Rev.*C Page 36 of 99 MB9A1A0N Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

6.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress Inc. recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress Inc. packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h

Document Number: 002-05675 Rev.*C Page 37 of 99 MB9A1A0N Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

6.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives.

Document Number: 002-05675 Rev.*C Page 38 of 99 MB9A1A0N Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Using an external clock To use the external clock, set general-purpose I/O ports to input the clock to X0/PE2 and X0A/P46 pin. Handling when using Multi-function serial pin as I2C pin If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external I2C bus system with power OFF.  Example of Using an External Clock Device X0/PE2 (X0A/P46) X1/PE3 (X1A/P47) Can be used as general-purpose I/O ports. Set as general-purpose I/O ports.

Document Number: 002-05675 Rev.*C Page 39 of 99 MB9A1A0N Series C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7μF would be recommended for this series. Mode pins (MD0, MD1) Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on: VCC  AVCC  AVRH Turning off: AVRH  AVCC  VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Device C VSS Cs GND

Document Number: 002-05675 Rev.*C Page 40 of 99 MB9A1A0N Series 8. Block Diagram Flash I/FCortex-M3 Core @20MHz(Max) Clock Reset Generator Watchdog Timer (Hardware) On-Chip Flash 64/128Kbyte Multi-Function Timer ×1 Multi-Function Serial IF 8ch. HW flow control(ch.4)* 16-bit FreeRun Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. Waveform Generator 3ch. A/D Activation Compare 1ch. 16-bit PPG 3ch. GPIO CSV External Interrupt Controller 16-pin + NMI ROM TableSWJ-DP Multi-layer AHB (Max 20MHz) AHB-APB Bridge : APB1 (Max 20MHz) SRAM1 12/16Kbyte AHB-APB Bridge: APB0 (Max 20MHz) I D Sys MB9AF1A1/1A2 AHB-APB Bridge : APB2 (Max 20MHz) Base Timer 16-bit 8ch./ 32-bit 4ch. NVIC Watchdog Timer (Software) Security 12-bit A/D Converter Unit 0 TRSTX,TCK, TDI,TMS AVCC, AVSS,AVRH ANxx TIOAx TIOBx IC0x DTTI0X RTO0x FRCK0 TDO SCKx SINx SOTx INTxx NMIX P0x, P1x, Pxx INITX MODE-Ctrl IRQ-Monitor PIN-Function-Ctrl MD1, MD0 ADTGx SUBOUT Deep Standby Ctrl WKUPx RTCCO LVD Power On Reset CRegulator LVD Ctrl CECx HDMI-CEC/ Remote Receiver Control Real Time Clock 10-bit D/A Converter 2ch. DAx CTS4 RTS4 IGTRG PLL CLK X0A X1A CR 100kHz Source Clock CROUT Main Osc Sub Osc CR 4MHz *: For the MB9AF1A1L and MB9AF1A2L, Multi-function Serial Interface does not support hardware flow control in these products.

Document Number: 002-05675 Rev.*C Page 41 of 99 MB9A1A0N Series 9. Memory Size See Memory size in Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF 0xE010_0000 0xE000_0000 0x4003_C000 0x4003_B000 RTC 0x4003_9000 0x4003_8000 MFS 0x4400_0000 0x4003_6000 0x4200_0000 0x4003_5000 LVD/DS mode 0x4003_4000 HDMI-CEC/ Remote Control Receiver 0x4000_0000 0x4003_3000 GPIO 0x4003_2000 Reserved 0x4003_1000 Int-Req.Read 0x2400_0000 0x4003_0000 EXTI 0x4002_F000 Reserved 0x2200_0000 0x4002_E000 CR Trim 0x4002_9000 0x4002_8000 D/AC 0x4002_7000 A/DC 0x4002_6000 Reserved 0x2008_0000 0x4002_5000 Base Timer 0x2000_0000 SRAM1 0x4002_4000 PPG 0x0010_0008 0x4002_1000 0x0010_0000 Security/CR Trim 0x4002_0000 MFT unit0 0x4001_3000 0x0000_0000 0x4001_2000 SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 Flash I/F See " Memory Map (2)" for the memory size details. Flash Reserved Reserved Reserved Reserved Cortex-M3 Private Peripherals Reserved Reserved Reserved Reserved 32Mbytes Bit band alias 32Mbytes Bit band alias Reserved Peripherals Reserved Reserved Reserved

Document Number: 002-05675 Rev.*C Page 42 of 99 MB9A1A0N Series Memory Map (2) *: See MB9AAA0N/1A0N/A30N/130N/130L Series Flash Programming Manual to confirm the detail of Flash memory. MB9AF1A2L/M/N MB9AF1A1L/M/N 0x2008_0000 0x2008_0000 0x2000_4000 0x2000_3000 0x2000_0000 0x2000_0000 0x0010_0008 0x0010_0008 0x0010_0004 CR trimming 0x0010_0004 CR trimming 0x0010_0000 Security 0x0010_0000 Security 0x0002_0000 0x0001_0000 0x0000_0000 SA1 (4 KB) 0x0000_0000 SA1 (4 KB) Flash 128 Kbytes Flash 64 Kbytes SA3 (64 KB) SA2 (60 KB) SA2 (60 KB) SRAM1

16 Kbytes

12 Kbytes

Document Number: 002-05675 Rev.*C Page 43 of 99 MB9A1A0N Series Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB Flash memory I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Reserved 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF APB1 Multi-function timer unit0 0x4002_1000 0x4002_1FFF Reserved 0x4002_2000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Reserved 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_8FFF D/A Converter 0x4002_9000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External Interrupt 0x4003_1000 0x4003_1FFF Interrupt Source Check Register 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF HDMI-CEC/ Remote Control Receiver 0x4003_5000 0x4003_50FF Low-Voltage Detector 0x4003_5100 0x4003_5FFF Deep standby mode Controller 0x4003_6000 0x4003_6FFF Reserved 0x4003_7000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial 0x4003_9000 0x4003_9FFF Reserved 0x4003_A000 0x4003_AFFF Reserved 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4004_FFFF AHB Reserved 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF Reserved 0x4006_1000 0x4006_1FFF Reserved 0x4006_2000 0x4006_2FFF Reserved 0x4006_3000 0x4006_3FFF Reserved 0x4006_4000 0x41FF_FFFF Reserved

Document Number: 002-05675 Rev.*C Page 44 of 99 MB9A1A0N Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX = 0 This is the period when the INITX pin is the L level.  INITX = 1 This is the period when the INITX pin is the H level.  SPL = 0 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 0.  SPL = 1 This is the status that the standby pin level setting bit (SPL) in the standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep Standby mode, pins switch to the general-purpose I/O port.

Document Number: 002-05675 Rev.*C Page 45 of 99 MB9A1A0N Series List of Pin Status Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - A Main crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state / When oscillation stops*1, output maintains previous state / Internal input fixed at 0 Hi-Z / Input enabled / When oscillation stops*1, Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state B Main crystal oscillator output pin Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z output / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z output Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z output Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z output / Internal input fixed at 0 Maintain previous state / When oscillation stops*1, Hi-Z output / Internal input fixed at 0 Maintain previous state When oscillation stops*1, Hi-Z output / Internal input fixed at 0 GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled

Document Number: 002-05675 Rev.*C Page 46 of 99 MB9A1A0N Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled E JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 F External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Output maintains previous state / Internal input fixed at 0 Maintain previous state G WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Output maintains previous state / Internal input fixed at 0 Maintain previous state

Document Number: 002-05675 Rev.*C Page 47 of 99 MB9A1A0N Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - H Resource selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Output maintains previous state / Internal input fixed at 0 Maintain previous state I NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state J Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Output maintains previous state / Internal input fixed at 0 Maintain previous state

Document Number: 002-05675 Rev.*C Page 48 of 99 MB9A1A0N Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - K Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected Output maintains previous state / Internal input fixed at 0 Maintain previous state L Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected Output maintains previous state / Internal input fixed at "0" Maintain previous state

Document Number: 002-05675 Rev.*C Page 49 of 99 MB9A1A0N Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - M Sub crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state / When oscillation stops*2, output maintains previous state / Internal input fixed at 0 Hi-Z / Input enabled / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, output maintains previous state / Internal input fixed at 0 Hi-Z / Input enabled / When oscillation stops*2, Hi-Z / Internal input fixed at Maintain previous state When Return from Deep Standby STOP mode, GPIO is selected GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state N Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at Maintain previous state When oscillation stops*2, Hi-Z / Internal input fixed at 0 GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state O External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 Output maintains previous state / Internal input fixed at 0 Maintain previous state

Document Number: 002-05675 Rev.*C Page 50 of 99 MB9A1A0N Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - P Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / input enabled Maintain previous state Hi-Z / input enabled Maintain previous state Q CEC enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Output maintains previous state / Internal input fixed at 0 Maintain previous state R CEC enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected Maintain previous state GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Output maintains previous state / Internal input fixed at 0 Maintain previous state

Document Number: 002-05675 Rev.*C Page 51 of 99 MB9A1A0N Series Pin status type Function group Power-on reset or low-voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - S Analog output selected Setting disabled Setting disabled Setting disabled Maintain previous state *3 *4 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Output maintains previous state / Internal input fixed at 0 Maintain previous state T Analog output selected Setting disabled Setting disabled Setting disabled Maintain previous state *3 *4 GPIO selected Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Output maintains previous state / Internal input fixed at 0 Maintain previous state *1: Oscillation is stopped at Sub run mode, Low-speed CR Run mode, Sub Sleep mode, Low-speed CR Sleep mode, Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Oscillation is stopped at Stop mode and Deep Standby Stop mode. *3: Maintain previous state at Timer mode. GPIO selected Internal input fixed at 0 at RTC mode, Stop mode. *4: Maintain previous state at Timer mode. Hi-Z/Internal input fixed at 0 at RTC mode, Stop mode.

Document Number: 002-05675 Rev.*C Page 52 of 99 MB9A1A0N Series 12. Electrical Characteristics

12.1 Absolute Maximum Ratings

Power supply voltage*1,*2 VCC VSS - 0.5 VSS + 6.5 V Analog power supply voltage*1,*3 AVCC VSS - 0.5 VSS + 6.5 V Analog reference voltage*1,*3 AVRH VSS - 0.5 VSS + 6.5 V Input voltage*1 VI VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V VSS - 0.5 VSS + 6.5 V 5V tolerant Analog pin input voltage*1 VIA VSS - 0.5 AVCC + 0.5 (≤ 6.5 V) V Output voltage*1 VO VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V L level maximum output current*4 IOL - 10 mA L level average output current*5 IOLAV - 4 mA L level total maximum output current ∑IOL - 100 mA L level total average output current*6 ∑IOLAV - 50 mA H level maximum output current*4 IOH - - 10 mA H level average output current*5 IOHAV - - 4 mA H level total maximum output current ∑IOH - - 100 mA H level total average output current*6 ∑IOHAV - - 50 mA Power consumption PD - 400 mW Storage temperature TSTG - 55 + 150 C *1: These parameters are based on the condition that VSS = AVSS = 0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. WARNING: − Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.

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12.2 Recommended Operating Conditions

(VSS = AVSS = 0.0V) Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage VCC - 1.8 5.5 V Analog power supply voltage AVCC - 1.8 5.5 V AVCC = VCC Analog reference voltage AVRH - 2.7 AVCC V AVCC ≥ 2.7 V AVCC AVCC < 2.7 V Smoothing capacitor CS - 1 10 μF For built-in Regulator * Operating Temperature LQD064, LQG064, LQH080, LQJ080, LQI100, PQH100 TA - - 40 + 85 C *: See C Pin in Handling Devices for the smoothing capacitor. WARNING: − The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.

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12.3 DC Characteristics

12.3.1 Current Rating

(VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ*3 Max*4 Power supply current ICC VCC PLL Run mode CPU: 20 MHz, Peripheral: 20 MHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 19 24 mA *1, *5 CPU: 20 MHz, Peripheral: clock stopped, NOP operation 9.5 12.5 mA *1, *5 High-spee d CR Run mode CPU/Peripheral: 4 MHz*2 Flash memory 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 4.5 5 mA *1 Sub Run mode CPU/Peripheral: 32 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 Low-speed CR Run mode CPU/Peripheral: 100 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 0.3 0.95 mA *1 ICCS PLL Sleep mode Peripheral: 20 MHz 8 10.5 mA *1, *5 High-spee d CR Sleep mode Peripheral: 4 MHz*2 2 2.5 mA *1 Sub Sleep mode Peripheral: 32 kHz 0.2 0.45 mA *1, *6 Low-speed CR Sleep mode Peripheral: 100 kHz 0.25 0.65 mA *1 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=3.3 V *4: TA=+85°C, VCC=5.5 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

Document Number: 002-05675 Rev.*C Page 55 of 99 MB9A1A0N Series Parameter Symbol Pin name Conditions Value Unit Remarks Typ*2 Max*3 Power supply current ICCT VCC Main Timer mode TA = + 25°C, When LVD is off 0.9 3.3 mA *1, *4 TA = + 85°C, When LVD is off 1.5 3.5 mA *1, *4 Sub Timer mode TA = + 25°C, When LVD is off 7.5 60 μA *1, *5 TA = + 85°C, When LVD is off 16 150 μA *1, *5 ICCR RTC mode TA = + 25C, When LVD is off 1.5 6.5 μA *1, *5 TA = + 85C, When LVD is off 6 79 μA *1, *5 ICCH Stop mode TA = + 25C, When LVD is off 0.6 5 μA *1 TA = + 85C, When LVD is off 4.2 77 μA *1 ICCRD Deep Standby RTC mode TA = + 25C, When LVD is off 1.3 4.5 μA *1, *5 TA = + 85C, When LVD is off 3 22 μA *1, *5 ICCHD Deep Standby Stop mode TA = + 25C, When LVD is off 0.4 3 μA *1 TA = + 85C, When LVD is off 1.4 20 μA *1 *1: When all ports are fixed. *2: VCC=3.3 V *3: VCC=5.5 V *4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

Document Number: 002-05675 Rev.*C Page 56 of 99 MB9A1A0N Series Low Voltage Detection Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ* Max Low-voltage detection circuit (LVD) power supply current ICCLVD VCC For occurrence of reset or for occurrence of interrupt in normal mode operation 10 20 μA When not detected For occurrence of reset and for occurrence of interrupt in normal mode operation 14 30 μA For occurrence of interrupt in low-power mode operation 0.3 2 μA When not detected *: When VCC = 3.3 V Flash Memory Current (VCC = 1.8 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Flash memory write/erase current ICCFLASH VCC At Write/Erase 10.8 11.9 mA A/D Converter Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Power supply current ICCAD AVCC At 1unit operation 1.4 2.5 mA At stop 0.1 0.35 μA Reference power supply current ICCAVRH AVRH At 1unit operation AVRH=5.5 V 0.5 1.5 mA At stop 0.1 0.3 μA D/A Converter Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Power supply current IDDA AVCC At D/A 1ch. operation AVCC=3.3 V 314 440 μA *1, *2 At D/A 1ch. operation AVCC=5.0 V 476 670 μA *1, *2 IDSA At D/A stop - 1.0 μA *1 *1: No-load *2: Generates the max current by the CODE about 0x200

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12.3.2 Pin Characteristics

(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max H level input voltage (hysteresis input) VIHS MD0, MD1, PE0, PE2, PE3, P46, P47, P3A, P3B, P3C, P3D, P3E, P3F, INITX - VCC × 0.8 - VCC + 0.3 V P0A, P0B, P0C, P4C, P60, P80, P81, P82 - VCC × 0.7 - VSS + 5.5 V 5V tolerant CMOS hysteresis input pins other than the above - VCC × 0.7 - VCC + 0.3 V L level input voltage (hysteresis input) VILS MD0, MD1, PE0, PE2, PE3, P46, P47, INITX - VSS - 0.3 - VCC × 0.2 V CMOS hysteresis input pins other than the above - VSS - 0.3 - VCC × 0.3 V H level output voltage VOH Pxx VCC ≥ 4.5 V, IOH = - 4 mA VCC - 0.5 - VCC V VCC < 4.5 V, IOH = - 1 mA L level output voltage VOL Pxx VCC ≥ 4.5 V, IOL = 4 mA VSS - 0.4 V VCC < 4.5 V, IOL = 2 mA Input leak current IIL - - - 5 - + 5 μA CEC0, CEC1 VCC = AVCC = AVRH = VSS = AVSS = 0.0 V - - + 1.8 Pull-up resistor value RPU Pull-up pin VCC ≥ 4.5 V 25 50 100 kΩ VCC  4.5 V 40 100 400 Input capacitance CIN Other than VCC, VSS, AVCC, AVSS, AVRH - - 5 15 pF

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12.4 AC Characteristics

12.4.1 Main Clock Input Characteristics

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input frequency fCH X0, VCC ≥ 2.0 V 4 20 MHz When crystal oscillator is connected VCC  2.0 V 4 4 MHz VCC ≥ 4.5 V 4 20 MHz When using external clock VCC  4.5 V 4 16 MHz Input clock cycle tCYLH VCC ≥ 4.5 V 50 250 ns When using external clock VCC  4.5 V 62.5 250 ns Input clock pulse width - PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock Input clock rising time and falling time tCF, tCR - - 5 ns When using external clock Internal operating clock*1 frequency fCM - - - 20 MHz Master clock fCC - - - 20 MHz Base clock (HCLK/FCLK) fCP0 - - - 20 MHz APB0 bus clock*2 fCP1 - - - 20 MHz APB1 bus clock*2 fCP2 - - - 20 MHz APB2 bus clock*2 Internal operating clock*1 cycle time tCYCC - - 50 - ns Base clock (HCLK/FCLK) tCYCP0 - - 50 - ns APB0 bus clock*2 tCYCP1 - - 50 - ns APB1 bus clock*2 tCYCP2 - - 50 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.

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12.4.2 Sub Clock Input Characteristics

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max Input frequency fCL X0A, X1A - - 32.768 - kHz When crystal oscillator is connected - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock

12.4.3 Built-in CR Oscillation Characteristics

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRH VCC ≥ 2.2 V TA = + 25C 3.92 4 4.08 MHz When trimming*1 TA = - 40C to + 85C 3.8 4 4.2 TA = - 40C to + 85C 2.3 - 7.03 When not trimming VCC < 2.2 V TA = + 25C 3.4 4 4.6 MHz When trimming*1 TA = - 40C to + 85C 3.16 4 4.84 TA = - 40C to + 85C 2.3 - 7.03 When not trimming Frequency stabilization time tCRWT - - - 10 μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming. *2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. X0A

Document Number: 002-05675 Rev.*C Page 60 of 99 MB9A1A0N Series Built-in Low-speed CR (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRL - 50 100 150 kHz

12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency fPLLI 4 - 20 MHz PLL multiplication rate - 1 - 5 multiplier PLL macro oscillation clock frequency fPLLO 10 - 20 MHz Main PLL clock frequency*2 fCLKPLL - - 20 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual.

12.4.5 Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input clock

of the Main PLL) (VCC = 2.2V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate - 3 - 4 multiplier PLL macro oscillation clock frequency fPLLO 11.4 - 16.8 MHz Main PLL clock frequency*2 fCLKPLL - - 16.8 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: − Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency.

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12.4.6 Reset Input Characteristics

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns 1.5 - ms When RTC mode or Stop mode 1.5 - ms When Deep Standby mode

12.4.7 Power-on Reset Timing

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Power supply rising time dV/dt VCC 0.1 - - V/ms Power supply shut down time tOFF 1 - - ms Reset release voltage VDETH 1.44 1.60 1.76 V When voltage rises Reset detection voltage VDETL 1.39 1.55 1.71 V When voltage drops Time until releasing Power-on reset tPRT 0.46 - 11.4 ms dV/dt ≥ 0.1mV/μs Reset detection delay time tOFFD - - 0.4 ms dV/dt ≥ -0.04mV/μs High-speed CR clock (CLKHC) PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Main PLL connection Main clock (CLKMO) K divider

Document Number: 002-05675 Rev.*C Page 62 of 99 MB9A1A0N Series VDETH tPRT Internal reset VCC CPU Operation start Reset active Release 0.2V 0.2V tOFF dt dV VDETL tOFFD Reset active

12.4.8 Base Timer Input Timing

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK, TIN) - 2tCYCP - ns tTIWH VIHS VIHS VILS VILS tTIWL ECK TIN

Document Number: 002-05675 Rev.*C Page 63 of 99 MB9A1A0N Series Trigger input timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns Note: − tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. tTRGH VIHS VIHS VILS VILS tTRGL TGIN

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12.4.9 CSIO/UART Timing

CSIO (SPI = 0, SCINV = 0) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions VCC  2.7 V 2.7 V ≤ VCC 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Min Max Baud rate - - - - 5 - 5 - 5 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - 4tCYCP - ns SCK   SOT delay time tSLOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns SIN  SCK  setup time tIVSHI SCKx, SINx 75 - 50 - 30 - ns SCK   SIN hold time tSHIXI SCKx, SINx 0 - 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK   SOT delay time tSLOVE SCKx, SOTx - 75 - 50 - 30 ns SIN  SCK  setup time tIVSHE SCKx, SINx 10 - 10 - 10 - ns SCK   SIN hold time tSHIXE SCKx, SINx 20 - 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 - 5 ns Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF.

Document Number: 002-05675 Rev.*C Page 65 of 99 MB9A1A0N Series Master mode Slave mode tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI SCK SOT SIN tSHSL tSLSH VIH tF tR VIH VOH VIL VIL VIL VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSHOVE

Document Number: 002-05675 Rev.*C Page 66 of 99 MB9A1A0N Series CSIO (SPI = 0, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions VCC  2.7 V 2.7 V ≤ VCC  4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Min Max Baud rate - - - - 5 - 5 - 5 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - 4tCYCP - ns SCK   SOT delay time tSHOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns SIN  SCK  setup time tIVSLI SCKx, SINx 75 - 50 - 30 - ns SCK   SIN hold time tSLIXI SCKx, SINx 0 - 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK   SOT delay time tSHOVE SCKx, SOTx - 75 - 50 - 30 ns SIN  SCK  setup time tIVSLE SCKx, SINx 10 - 10 - 10 - ns SCK   SIN hold time tSLIXE SCKx, SINx 20 - 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 - 5 ns Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF.

Document Number: 002-05675 Rev.*C Page 67 of 99 MB9A1A0N Series Master mode Slave mode tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI SCK SOT SIN tSHSL tSLSH VIH tF tR VIH VOH VIL VIL VIL VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSHOVE

Document Number: 002-05675 Rev.*C Page 68 of 99 MB9A1A0N Series CSIO (SPI = 1, SCINV = 0) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions VCC  2.7 V 2.7 V ≤ VCC  4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Min Max Baud rate - - - - 5 - 5 - 5 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - 4tCYCP - ns SCK   SOT delay time tSHOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns SIN  SCK  setup time tIVSLI SCKx, SINx 75 - 50 - 30 - ns SCK   SIN hold time tSLIXI SCKx, SINx 0 - 0 - 0 - ns SOT  SCK  delay time tSOVLI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK   SOT delay time tSHOVE SCKx, SOTx - 75 - 50 - 30 ns SIN  SCK  setup time tIVSLE SCKx, SINx 10 - 10 - 10 - ns SCK   SIN hold time tSLIXE SCKx, SINx 20 - 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 - 5 ns Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF.

Document Number: 002-05675 Rev.*C Page 69 of 99 MB9A1A0N Series Master mode Slave mode *: Changes when writing to TDR register tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI SCK SOT SIN tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN

Document Number: 002-05675 Rev.*C Page 70 of 99 MB9A1A0N Series CSIO (SPI = 1, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions VCC  2.7 V 2.7 V ≤ VCC  4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Min Max Baud rate - - - - 5 - 5 - 5 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - 4tCYCP - ns SCK   SOT delay time tSLOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns SIN  SCK  setup time tIVSHI SCKx, SINx 75 - 50 - 30 - ns SCK  SIN hold time tSHIXI SCKx, SINx 0 - 0 - 0 - ns SOT  SCK  delay time tSOVHI SCKx, SOTx 2tCYCP - 30 - 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK   SOT delay time tSLOVE SCKx, SOTx - 75 - 50 - 30 ns SIN  SCK  setup time tIVSHE SCKx, SINx 10 - 10 - 10 - ns SCK   SIN hold time tSHIXE SCKx, SINx 20 - 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 - 5 ns Notes: − The above characteristics apply to clock synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance CL = 50 pF.

Document Number: 002-05675 Rev.*C Page 71 of 99 MB9A1A0N Series Master mode Slave mode UART external clock input (EXT = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Conditions Value Unit Remarks Min Max Serial clock L pulse width tSLSH CL = 50 pF tCYCP + 10 - ns Serial clock H pulse width tSHSL tCYCP + 10 - ns SCK falling time tF - 5 ns SCK rising time tR - 5 ns tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI SCK SOT SIN tSHSL tR tSLSH tF tSLOVE VIL VIL VIL VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN t SHSL V I L V I L V I L V IH V IH V IH tR tF t SLSH SCK

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12.4.10 External Input Timing

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tINH, tINL ADTG - 2tCYCP*1 - ns A/D converter trigger input FRCKx Free-run timer input clock ICxx Input capture DTTIxX - 2tCYCP*1 - ns Waveform generator IGTRG - 2tCYCP*1 - ns PPG IGBT mode INTxx, NMIX *2 2tCYCP + 100*1 - ns External interrupt, NMI *3 500 - ns WKUPx *4 500 - ns Deep standby wake up *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the A/D converter, Multi-function Timer, PPG, External interrupt, Deep Standby mode Controller are connected to, see Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in Timer mode, in RTC mode, in Stop mode. *4: When in Deep Standby RTC mode, in Deep Standby Stop mode.

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12.4.11 I2C Timing

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency fSCL CL = 50 pF, R = (VP/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA   SCL  tHDSTA 4.0 - 0.6 - μs SCL clock L width tLOW 4.7 - 1.3 - μs SCL clock H width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL   SDA  tSUSTA 4.7 - 0.6 - μs Data hold time SCL   SDA   tHDDAT 0 3.45*2 0 0.9*3 μs Data setup time SDA    SCL  tSUDAT 250 - 100 - ns STOP condition setup time SCL   SDA  tSUSTO 4.0 - 0.6 - μs Bus free time between STOP condition and START condition tBUF 4.7 - 1.3 - μs Noise filter tSP - 2 tCYCP*4 - 2 tCYCP*4 - ns *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number which I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL

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12.4.12 JTAG Timing

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max TMS,TDI setup time tJTAGS TCK, TMS,TDI VCC ≥ 4.5 V 15 - ns VCC  4.5 V TMS,TDI hold time tJTAGH TCK, TMS,TDI VCC ≥ 4.5 V 15 - ns VCC  4.5 V TDO delay time tJTAGD TCK, TDO VCC ≥ 4.5 V - 30 ns 2.7 V ≤VCC  4.5 V - 45 VCC  2.7 V - 60 Note: − When the external load capacitance CL = 50 pF. TCK TMS/TDI TDO

Document Number: 002-05675 Rev.*C Page 75 of 99 MB9A1A0N Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity INL - - ± 2.5 ± 3.0 LSB AVCC ≥ 2.7 V - ± 3.5 ± 4.0 LSB AVCC < 2.7 V Differential Nonlinearity DNL - - ± 1.8 ± 1.9 LSB AVCC ≥ 2.7 V - ± 2.7 ± 2.9 LSB AVCC < 2.7 V Zero transition voltage VZT ANxx - ± 9 ± 20 mV Full-scale transition voltage VFST ANxx - AVRH ± 9 AVRH ± 20 mV Conversion time*1 - - 1.0 - - μs AVCC ≥ 2.7 V 4.0 AVCC < 2.7 V Sampling time*2 tS - 0.3 - 10 μs AVCC ≥ 2.7 V 1.2 AVCC < 2.7 V Compare clock cycle*3 tCCK - 50 - 1000 ns AVCC ≥ 2.7 V 200 AVCC < 2.7 V Period of operation enable state transitions tSTT - - - 1 μs Analog input capacity CAIN - - - 15 pF Analog input resistor RAIN - - - 0.9 kΩ AVCC ≥ 4.5 V 1.6 2.7 V ≤ AVCC < 4.5 V 4.0 AVCC < 2.7 V Interchannel disparity - - - - 4 LSB Analog port input leak current - ANxx - - 0.3 μA Analog input voltage - ANxx AVSS - AVRH V Reference voltage - AVRH 2.7 - AVCC V AVCC ≥ 2.7 V AVCC AVCC < 2.7 V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 2.7 V, HCLK=20 MHz sampling time: 0.3 μs, compare time: 0.7 μs AVCC < 2.7 V, HCLK=20 MHz sampling time: 1.2 μs, compare time: 2.8 μs Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting*4 of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Part. The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: A necessary sampling time changes by external impedance. Ensure to set the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2).

Document Number: 002-05675 Rev.*C Page 76 of 99 MB9A1A0N Series (Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: Sampling time RAIN: input resistor of A/D = 0.9 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V input resistor of A/D = 1.6 kΩ at 2.7 V ≤ AVCC < 4.5 V input resistor of A/D = 4.0 kΩ at 1.8 V ≤ AVCC < 2.7 V CAIN: input capacity of A/D = 15 pF at 1.8 V ≤ AVCC ≤ 5.5 V REXT: Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle REXT ANxx Analog input pin RAIN CAIN Analog Signal source Comparator

Document Number: 002-05675 Rev.*C Page 77 of 99 MB9A1A0N Series Definition of 12-bit A/D Converter Terms

• Resolution: Analog variation that is recognized by an A/D converter.
• Integral Nonlinearity: Deviation of the line between the zero-transition point (0b000000000000←→0b000000000001) and the full-scale transition point (0b111111111110←→0b111111111111) from the actual conversion characteristics.
• Differential Nonlinearity: Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVSS AVRH AVSS AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T

Document Number: 002-05675 Rev.*C Page 78 of 99 MB9A1A0N Series 12.6 10-bit D/A Converter Electrical Characteristics for the D/A Converter (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40C to + 85C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - DAx - - 10 bit Conversion time tC20 0.37 0.53 0.69 μs Load 20 pF tC100 1.87 2.67 3.47 μs Load 100 pF Integral Nonlinearity INL -4.0 - +4.0 LSB * Differential Nonlinearity DNL -0.9 - +0.9 LSB * Output Voltage offset VOFF - - 10.0 mV Code is 0x000 -50.0 - +5.5 mV Code is 0x3FF Analog output impedance RO 2.45 3.50 4.55 kΩ D/A operation 5.0 9.0 - MΩ D/A stop Output undefined period tR - - 250 ns *: No-load

Document Number: 002-05675 Rev.*C Page 79 of 99 MB9A1A0N Series

12.7 Low-Voltage Detection Characteristics

12.7.1 Low-Voltage Detection Reset

(TA = - 40C to + 85C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDLR SVHR = 0001 1.43 1.53 1.63 V When voltage drops Released voltage VDHR 1.53 1.63 1.73 V When voltage rises Detected voltage VDLR SVHR = 0100 1.80 1.93 2.06 V When voltage drops Released voltage VDHR 1.90 2.03 2.16 V When voltage rises LVD stabilization wait time tLVDRW - - - 633 × tCYCP* μs Detection delay time tLVDRD dV/dt ≥ -4mV/μs - - 60 μs *: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-05675 Rev.*C Page 80 of 99 MB9A1A0N Series

12.7.2 Interrupt of Low-Voltage Detection

(TA = - 40C to + 85C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDLI SVHI = 0000 1.87 2.00 2.13 V When voltage drops Released voltage VDHI 1.97 2.10 2.23 V When voltage rises Detected voltage VDLI SVHI = 0001 1.96 2.10 2.24 V When voltage drops Released voltage VDHI 2.06 2.20 2.34 V When voltage rises Detected voltage VDLI SVHI = 0010 2.05 2.20 2.35 V When voltage drops Released voltage VDHI 2.15 2.30 2.45 V When voltage rises Detected voltage VDLI SVHI = 0011 2.15 2.30 2.45 V When voltage drops Released voltage VDHI 2.25 2.40 2.55 V When voltage rises Detected voltage VDLI SVHI = 0100 2.24 2.40 2.56 V When voltage drops Released voltage VDHI 2.34 2.50 2.66 V When voltage rises Detected voltage VDLI SVHI = 0101 2.33 2.50 2.67 V When voltage drops Released voltage VDHI 2.43 2.60 2.77 V When voltage rises Detected voltage VDLI SVHI = 0110 2.43 2.60 2.77 V When voltage drops Released voltage VDHI 2.53 2.70 2.87 V When voltage rises Detected voltage VDLI SVHI = 0111 2.61 2.80 2.99 V When voltage drops Released voltage VDHI 2.71 2.90 3.09 V When voltage rises Detected voltage VDLI SVHI = 1000 2.80 3.00 3.20 V When voltage drops Released voltage VDHI 2.90 3.10 3.30 V When voltage rises Detected voltage VDLI SVHI = 1001 2.99 3.20 3.41 V When voltage drops Released voltage VDHI 3.09 3.30 3.51 V When voltage rises Detected voltage VDLI SVHI = 1010 3.36 3.60 3.84 V When voltage drops Released voltage VDHI 3.46 3.70 3.94 V When voltage rises Detected voltage VDLI SVHI = 1011 3.45 3.70 3.95 V When voltage drops Released voltage VDHI 3.55 3.80 4.05 V When voltage rises Detected voltage VDLI SVHI = 1100 3.73 4.00 4.27 V When voltage drops Released voltage VDHI 3.83 4.10 4.37 V When voltage rises Detected voltage VDLI SVHI = 1101 3.83 4.10 4.37 V When voltage drops Released voltage VDHI 3.93 4.20 4.47 V When voltage rises Detected voltage VDLI SVHI = 1110 3.92 4.20 4.48 V When voltage drops Released voltage VDHI 4.02 4.30 4.58 V When voltage rises LVD stabilization wait time tLVDIW - - - 633 × tCYCP* μs Detection delay time tLVDID dV/dt ≥ - 4mV/μs - - 60 μs *: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-05675 Rev.*C Page 81 of 99 MB9A1A0N Series Low power mode (TA = - 40C to + 85C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDLIL SVHI = 0000 1.80 2.00 2.20 V When voltage drops Released voltage VDHIL 1.90 2.10 2.30 V When voltage rises Detected voltage VDLIL SVHI = 0001 1.89 2.10 2.31 V When voltage drops Released voltage VDHIL 1.99 2.20 2.41 V When voltage rises Detected voltage VDLIL SVHI = 0010 1.98 2.20 2.42 V When voltage drops Released voltage VDHIL 2.08 2.30 2.52 V When voltage rises Detected voltage VDLIL SVHI = 0011 2.07 2.30 2.53 V When voltage drops Released voltage VDHIL 2.17 2.40 2.63 V When voltage rises Detected voltage VDLIL SVHI = 0100 2.16 2.40 2.64 V When voltage drops Released voltage VDHIL 2.26 2.50 2.74 V When voltage rises Detected voltage VDLIL SVHI = 0101 2.25 2.50 2.75 V When voltage drops Released voltage VDHIL 2.35 2.60 2.85 V When voltage rises Detected voltage VDLIL SVHI = 0110 2.34 2.60 2.86 V When voltage drops Released voltage VDHIL 2.44 2.70 2.96 V When voltage rises Detected voltage VDLIL SVHI = 0111 2.52 2.80 3.08 V When voltage drops Released voltage VDHIL 2.62 2.90 3.18 V When voltage rises Detected voltage VDLIL SVHI = 1000 2.70 3.00 3.30 V When voltage drops Released voltage VDHIL 2.80 3.10 3.40 V When voltage rises Detected voltage VDLIL SVHI = 1001 2.88 3.20 3.52 V When voltage drops Released voltage VDHIL 2.98 3.30 3.62 V When voltage rises Detected voltage VDLIL SVHI = 1010 3.24 3.60 3.96 V When voltage drops Released voltage VDHIL 3.34 3.70 4.06 V When voltage rises Detected voltage VDLIL SVHI = 1011 3.33 3.70 4.07 V When voltage drops Released voltage VDHIL 3.43 3.80 4.17 V When voltage rises Detected voltage VDLIL SVHI = 1100 3.60 4.00 4.40 V When voltage drops Released voltage VDHIL 3.70 4.10 4.50 V When voltage rises Detected voltage VDLIL SVHI = 1101 3.69 4.10 4.51 V When voltage drops Released voltage VDHIL 3.79 4.20 4.61 V When voltage rises Detected voltage VDLIL SVHI = 1110 3.78 4.20 4.62 V When voltage drops Released voltage VDHIL 3.88 4.30 4.72 V When voltage rises LVD stabilization wait time tLVDILW - - - 8039 × tCYCP* μs Detection delay time tLVDILD dV/dt ≥ - 0.4mV/μs - - 800 μs *: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-05675 Rev.*C Page 82 of 99 MB9A1A0N Series

12.8 Flash Memory Write/Erase Characteristics

12.8.1 Write / Erase time

(VCC = 2.0V to 5.5V, TA = - 40C to + 85C) Parameter Value Unit Remarks Typ* Max* Sector erase time Large Sector 1.6 7.5 s Includes write time prior to internal erase Small Sector 0.4 2.1 Half word (16-bit) write time 25 400 μs Not including system-level overhead time. Chip erase time 4 19.2 s Includes write time prior to internal erase *: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle of erase/write.

12.8.2 Write cycles and data hold time

Erase/write cycles (cycle) Data hold time (year) Remarks 1,000 20 * 10,000 10 * 100,000 5* *: At average + 85C

Document Number: 002-05675 Rev.*C Page 83 of 99 MB9A1A0N Series

12.9 Return Time from Low-Power Consumption Mode

12.9.1 Return Factor: Interrupt/WKUP

The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tICNT tCYCC μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 40 80 μs Low-speed CR Timer mode 630 1260 μs Sub Timer mode 630 1260 μs RTC mode, Stop mode 1083 2100 μs Deep Standby RTC mode Deep Standby Stop mode 1099 2127 μs *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.

Document Number: 002-05675 Rev.*C Page 84 of 99 MB9A1A0N Series Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual.

Document Number: 002-05675 Rev.*C Page 85 of 99 MB9A1A0N Series

12.9.2 Return Factor: Reset

The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tRCNT 359 647 μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 359 647 μs Low-speed CR Timer mode 929 1787 μs Sub Timer mode 929 1787 μs RTC/Stop mode 1099 2127 μs Deep Standby RTC mode Deep Standby Stop mode 1099 2127 μs *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by INITX) INITX tRCNT Internal reset CPU Operation Start Reset active Release

Document Number: 002-05675 Rev.*C Page 86 of 99 MB9A1A0N Series Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset tRCNT Internal reset CPU Operation Start Reset active Release *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: − The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. − When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. − The time during the power-on reset/low-voltage detection reset is excluded. See (12.4.7) Power-on Reset Timing in 12.4 AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. − When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. − The internal resource reset means the watchdog reset and the CSV reset.

Document Number: 002-05675 Rev.*C Page 87 of 99 MB9A1A0N Series 13. Ordering Information Part number On-chip Flash memory On-chip MB9AF1A1LPMC1-G-SNE2 64 Kbyte 12 Kbyte Plastic  LQFP (0.5mm pitch), 64-pin (LQD064) Tray MB9AF1A2LPMC1-G-SNE2 128 Kbyte 16 Kbyte MB9AF1A1LPMC-G-SNE2 64 Kbyte 12 Kbyte Plastic  LQFP (0.65mm pitch), 64-pin (LQG064) MB9AF1A2LPMC-G-UNE2 128 Kbyte 16 Kbyte MB9AF1A1MPMC-G-UNE2 64 Kbyte 12 Kbyte Plastic  LQFP (0.5mm pitch), 80-pin (LQH080) MB9AF1A2MPMC-G-UNE2 128 Kbyte 16 Kbyte MB9AF1A1MPMC1-G-SNE2 64 Kbyte 12 Kbyte Plastic  LQFP (0.65mm pitch), 80-pin (LQJ080) MB9AF1A2MPMC1-G-UNE2 128 Kbyte 16 Kbyte MB9AF1A1NPMC-G-SNE2 64 Kbyte 12 Kbyte Plastic  LQFP (0.5mm pitch), 100-pin (LQI100) MB9AF1A2NPMC-G-UNE2 128 Kbyte 16 Kbyte MB9AF1A1NPF-G-SNE1 64 Kbyte 12 Kbyte Plastic  QFP (0.65mm pitch), 100-pin (PQH100) MB9AF1A2NPF-G-SNE1 128 Kbyte 16 Kbyte

Document Number: 002-05675 Rev.*C Page 88 of 99 MB9A1A0N Series 14. Package Dimensions Package Type Package Code LQFP 64 LQD064 DIMENSIONS SYMBOL MIN. NOM. MAX. 07.1A A1 0.00 0.20 b 0.15 0.2 c 0.09 0.20 D 12.00 BSC. D1 10.00 BSC. e 0.50 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70 12.00 BSC. 10.00 BSC. D e 1 16 5 7 E

0.20 C A-B D

b

0.10 C A-B D

0.08 C A-B D

A A10.25 b SECTION A-A' L1 L A SEATING PLANE 0.08 C SIDE VIEW TOP VIEW BOTTOM VIEW 3348 116 33 48 PACKAGE OUTLINE, 64 LEAD LQFP 10.0X10.0X1.7 MM LQD064 Rev 002-11499

Document Number: 002-05675 Rev.*C Page 89 of 99 MB9A1A0N Series Package Type Package Code LQFP 64 LQG064 DIMENSION SYMBOL MIN. NOM. MAX. A 1.70 A1 0.00 0.20 b 0.27 0.32 0.37 c 0.09 0.20 D 14.00 BSC D1 12.00 BSC e 0.65 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70

14.00 BSC

12.00 BSC

D e 1 16 EE1 5 7 b

0.13 C A-B D 8

0.10 C A SEATI NG PLA NE b SECTION A -A' c A A10.25 10L1 L SIDE VIEW TOP VIEW BOTTOM VIEW 3348 116 8433 12.0X12.0X1.7 MM LQG064 REV PACKAGE OUTLINE, 64 LEAD LQFP 002-13881

Document Number: 002-05675 Rev.*C Page 90 of 99 MB9A1A0N Series Package Type Package Code LQFP 80 LQH080 DIMENSIONS MIN. NOM. MAX. 07.1A A1 0.05 0.15 b 0.15 0.27 c 0.09 0.20 D 14.00 BSC. D1 12.00 BSC. e 0.50 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70 14.00 BSC. 12.00 BSC. SYMBOL BOTTOM VIEW A A10.25 D e b D E 5 7 752 10 b SECTION A-A' SEATING PLANE 0.08 C A L SIDE VIEW TOP VIEW 1406 0614 120 PACKAGE OUTLINE, 80 LEAD LQFP 12.0X12.0X1.7 MM LQH080 Rev 002-11501

Document Number: 002-05675 Rev.*C Page 91 of 99 MB9A1A0N Series Package Type Package Code LQFP 80 LQJ080 DIMENSIONS SYMBOL MIN. NOM. MAX. A 1.70 A1 0.00 0.20 b 0.16 0.38 c 0.09 0.20 D 16.00 BSC D1 14.00 BSC e 0.65 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70

16.00 BSC

0.32 D e 021 EE1 5 7 b A SEATING PLANE A A10.25 10 b SECTION A-A' c L 0.10 C ddd C A-B D 4160 0614 14.0X14.0X1.7 MM LQJ080 REV PACKAGE OUTLINE, 80 LEAD LQFP 002-14043

Document Number: 002-05675 Rev.*C Page 92 of 99 MB9A1A0N Series Package Type Package Code LQFP 100 LQI100 NOTES : 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DATUM PLANE H IS LOCATED AT THE BOTTOM OF THE MOLD PARTING LINE COINCIDENT WITH WHERE THE LEAD EXITS THE BODY. 3. DATUMS A-B AND D TO BE DETERMINED AT DATUM PLANE H. 4. TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PRE SIDE. DIMENSIONS D1 AND E1 INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 6. DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. 7. REGARDLESS OF THE RELATIVE SIZE OF THE UPPER AND LOWER BODY SECTIONS. DIMENSIONS D1 AND E1 ARE DETERMINED AT THE LARGEST FEATURE OF THE BODY EXCLUSIVE OF MOLD FLASH AND GATE BURRS. BUT INCLUDING ANY MISMATCH BETWEEN THE UPPER AND LOWER SECTIONS OF THE MOLDER BODY. 8. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. THE DAMBAR PROTRUSION (S) SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED b MAXIMUM BY MORE THAN 0.08mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE LEAD FOOT. 9. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10mm AND 0.25mm FROM THE LEAD TIP. 10. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY. DIMENSIONS SYMBOL MIN. NOM. MAX. A 1.70 A1 0.05 0.15 b 0.15 0.27 c 0.09 0.20 D 16.00 BSC D1 14.00 BSC e 0.50 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70 A A10.250.08 C 100 D E1 E e b SECTION A-A' c A 5 7 L b D E1 E 5 7 5175 SIDE VIEW TOP VIEW BOTTOM VIEW DETAIL A 125 5715 100 PACKAGE OUTLINE, 100 LEAD LQFP 14.0X14.0X1.7 MM LQI100 REV*A 002-11500 *A

Document Number: 002-05675 Rev.*C Page 93 of 99 MB9A1A0N Series Package Type Package Code QFP 100 PQH100 DIMENSIONS SYMBOL MIN. NOM. MAX. A 3.35 A1 0.05 0.45 b 0.27 0.32 0.37 c 0.11 0.23 D 23.90 BSC D1 20.00 BSC e 0.65 BSC E L 0.73 0.88 1.03 L1 1.95 REF L2 0.25 BSC

17.90 BSC

e b D 5 7 EE1

0.40 C A-B D

b SECTION A-A' SIDE VIEW TOP VIEW A 0.10 C DETAIL A 5180 130 10031 0815 BOTTOM VIEW PACKAGE OUTLINE, 100 LEAD QFP 20.00X14.00X3.35 MM PQH100 REV 002-15156

Document Number: 002-05675 Rev.*C Page 94 of 99 MB9A1A0N Series 15. Errata This chapter describes the errata for MB9A1A0N Series. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions.

15.1 Part Numbers Affected

MB9AF1A1LPMC1-G-SNE2, MB9AF1A2LPMC1-G-SNE2, MB9AF1A1LPMC-G-SNE2, MB9AF1A2LPMC-G-SNE2, MB9AF1A2LPMC-G-UNE2, MB9AF1A1MPMC-G-SNE2, MB9AF1A1MPMC-G-UNE2, MB9AF1A2MPMC-G-SNE2, MB9AF1A2MPMC-G-UNE2, MB9AF1A1MPMC1-G-SNE2, MB9AF1A2MPMC1-G-SNE2, MB9AF1A2MPMC1-G-UNE2, MB9AF1A1NPMC-G-SNE2, MB9AF1A2NPMC-G-SNE2, MB9AF1A2NPMC-G-UNE2, MB9AF1A1NPF-G-SNE1, MB9AF1A2NPF-G-SNE1

15.2 Qualification Status

Product Status: In Production − Qual.

15.3 Errata Summary

This table defines the errata applicability to available devices. Items Part Number Silicon Revision Fix Status [15.4.1] HDMI-CEC polling message issue Refer to 15.1 Initial Rev Next silicon is not planned [15.4.2] RTC delay issue Refer to 15.1 Initial Rev Next silicon is not planned

15.4 Errata Detail

15.4.1 HDMI-CEC polling message issue

 PROBLEM DEFINITION Error#1) While MCU sends a Polling Message, it always returns a NACK to a message coming to the MCU from another node. Error#2) MCU always waits for 7-bit signal free on CEC line before it drives the line even when the last line initiator was another node.  PARAMETERS AFFECTED N/A  TRIGGER CONDITION(S) This error always happens.  SCOPE OF IMPACT MCU does not reply properly to another node.  WORKAROUND The software workaround is applied to Error #1. 1. Store 0x0 to SFREE register. 2. Monitor CEC line with GPIO and wait until 1 lasts for the signal free time. 3. Store frame data to TXDATA register and store 0x0F to RCADR1 or RCADR2 register. It sends a message after 3~4 clocks of 32.768 kHz clock when TXDATA is stored 0x0F.

Document Number: 002-05675 Rev.*C Page 95 of 99 MB9A1A0N Series If the device receives a frame from another node within 2~3 clocks after storing TXDATA, the bus error occurs and if the device receives a frame from another node within 3~4 clocks after storing TXDATA, the arbitration lost occurs. In these cases: 4-A-1. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK 4-A-2. Return back to step 2 above If the device receives a frame from another node within 1~2 clocks after storing TXDATA, take these steps. 4-B-1. Monitor CEC line with GPIO after 50us from storing TXDATA 4-B-2. Set TXEN to 1 -> 0 -> 1 immediately when GPIO finds state low on the CEC line 4-B-3. Set RCADR1 or RCADR2 to former value from 0x0F to reply ACK 4-B-4. Return back to step 2 above For Error #2, there is no software workaround, but signal free time of fixed 7-bit does not violate HDMI-CEC specification. The specification says signal free time must be more than and equals to 5-bit.  FIX STATUS The user uses the workaround to avoid the issue. The next silicon fixing the issue is not planned.

15.4.2 RTC delay issue

 PROBLEM DEFINITION RTC delays when software reset or APB2 reset occurs.  PARAMETERS AFFECTED N/A  TRIGGER CONDITION(S) This error happens when software reset or APB2 reset occurs.  SCOPE OF IMPACT RTC delays and does not time correctly.  WORKAROUND RTC block is supplied with sub-clock. Both software reset and APB2 reset disable two clocks of sub-clock to RTC block. The workaround is to count occurrence of software and APB2 reset and calculate how many clocks of sub-clock were disabled and add one second to RTC counter when accumulated disabled sub-clock period reaches one second.  FIX STATUS The user uses the workaround to avoid the issue. The next silicon fixing the issue is not planned.

Document Number: 002-05675 Rev.*C Page 96 of 99 MB9A1A0N Series Major Changes Spansion Publication Number: DS706-00068 Page Section Change Results Revision 0.1 - - Initial release Revision 1.0 - - Changed from Preliminary to Full Producton - - Deleted a part of QFN

43 BLOCK DIAGRAM Added note for MB9AF1AxL

58,59 ELECTRICAL CHARACTERISTICS 3.DC Characteristics (1) Current Rating Revised the values of “TBD” Revision 2.0

2 Features

• On-chip Memories Changed the description of on-chip SRAM 7 - 31 Packages Pin Assignment List of Pin Functions Deleted QFN package

40 Handling Devices

Crystal oscillator circuit Added the following description "Evaluate oscillation of your using crystal oscillator by your mount board."

44 Memory Map

• Memory map(2) Added the summary of Flash memory sector 57 - 59

Electrical Characteristics

1. DC Characteristics (1) Current rating

• Changed the table format
• Added Main Timer mode current
• Added Flash Memory Current
• Moved A/D Converter Current
• Moved D/A Converter Current

1. DC Characteristics (2) Pin Characteristics Added the input leak current of CEC port at power off
2. AC Characteristics (4-1) Operating Conditions of Main PLL (4-2) Operating Conditions of Main PLL

• Added the figure of Main PLL connection

1. AC Characteristics (6) Power-on Reset Timing

• Changed the figure of timing
• Changed from Reset release delay time(tOND) to Time until releasing Power-on reset(tPRT) 66 - 73

1. AC Characteristics (8) CSIO/UART Timing

• Modified from UART Timing to CSIO/UART Timing
• Changed from Internal shift clock operation to Master mode
• Changed from External shift clock operation to Slave mode 5. 12bit A/D Converter
• Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage
• Added Conversion time at AVCC < 2.7 V

1. Low-voltage Detection Characteristics Deleted the figure
2. Flash Memory Write/Erase Characteristics Change to the erase time of include write time prior to internal erase

Document Number: 002-05675 Rev.*C Page 97 of 99 MB9A1A0N Series Page Section Change Results 85 - 88

1. Return Time from Low-Power Consumption Mode Added Return Time from Low-Power Consumption Mode NOTE: Please see “Document History” about later revised information.

Document Number: 002-05675 Rev.*C Page 98 of 99 MB9A1A0N Series Document History Document Title: MB9A1A0N Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller Document Number: 002-05675 Revision ECN Orig. of Change Submission Date Description of Change ** - AKIH 06/30/2015 Migrated to Cypress and assigned document number 002-05675. No change to document contents or format. *A 5193131 AKIH 03/31/2016 Updated to Cypress format. *B 5513616 HTER 02/08/2017 Modified RTC description in “Features, Real-Time Clock(RTC)”. Changed starting count value from 01 to 00. Deleted “second, or day of the week” in the Interrupt function. (Page 2) Changed package code as the following table in following section. 2. Package (Page 7) 3. Pin Assignment (Page 8 -11) 12. Electrical Characteristics (Page 53) 13. Ordering Information (Page 87) 14. Package Dimensions (Page 88 - 93) Before After FPT-64P-M38 LQD064 FPT-64P-M39 LQG064 FPT-80P-M37 LQH080 FPT-80P-M40 LQJ080 FPT-100P-M23 LQI100 FPT-100P-M06 PQH100 Added the Baud rate spec in “12.4.9 CSIO/UART Timing” (Page 64 - 70) Changed Part numbers in 13. Ordering Information (Page 87) “MB9AF1A2LPMC-G-SNE2” to “MB9AF1A2LPMC-G-UNE2” “MB9AF1A2MPMC-G-SNE2” to “MB9AF1A2MPMC-G-UNE2” “MB9AF1A2NPMC-G-SNE2” to “MB9AF1A2NPMC-G-UNE2” “MB9AF1A1MPMC-G-SNE2” to “MB9AF1A1MPMC-G-UNE2” “MB9AF1A2MPMC1-G-SNE2” to “MB9AF1A2MPMC1-G-UNE2” Added 15. Errata (Page 94 - 95) *C 5768635 YSAT 06/12/2017 Adapted new cypress logo

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