MB9A130LB

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Document overview

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• PDF pages: 86

Technical content

Datasheet sections

• 6.1 Precautions for Product Design
• 6.2 Precautions for Package Mounting
• 6.3 Precautions for Use Environment
• 12.1 Absolute Maximum Ratings
• 12.2 Recommended Operating Conditions
• 12.3 DC Characteristics
• 12.3.1 Current Rating
• 12.3.2 Pin Characteristics
• 12.4 AC Characteristics
• 12.4.1 Main Clock Input Characteristics
• 12.4.2 Sub Clock Input Characteristics
• 12.4.3 Built-in CR Oscillation Characteristics
• 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)
• 12.4.6 Reset Input Characteristics
• 12.4.7 Power-on Reset Timing
• 12.4.8 Base Timer Input Timing
• 12.4.9 CSIO/UART Timing
• 12.4.10 External Input Timing
• 12.4.11 I2C Timing
• 12.4.12 JTAG Timing
• 12.6 Low-Voltage Detection Characteristics
• 12.6.1 Low-Voltage Detection Reset
• 12.6.2 Interrupt of Low-voltage Detection
• 12.7 Flash Memory Write/Erase Characteristics
• 12.7.1 Write / Erase time
• 12.7.2 Write cycles and data hold time
• 12.8 Return Time from Low-Power Consumption Mode
• 12.8.1 Return Factor: Interrupt/WKUP
• 12.8.2 Return Factor: Reset

Features

32-bit ARM® Cortex®-M3 Core  Processor version: r2p1  Up to 20 MHz Operation Frequency  Integrated Nested Vectored Interrupt Controller (NVIC): 1 channel NMI (non-maskable interrupt) and 32 channels' peripheral interrupts and 8 priority levels  24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory]  Up to 128 Kbytes  Read cycle: 0 wait-cycle  Security function for code protection [SRAM] This series contains 8 Kbyte on-chip SRAM that is connected to System bus of Cortex-M3 core.  SRAM1: 8 Kbytes Multi-function Serial Interface (Max 8 channels) Operation mode is selectable from the followings for each channel.  UART  CSIO  I2C [UART]  Full-duplex double buffer  Selection with or without parity supported  Built-in dedicated baud rate generator  External clock available as a serial clock  Various error detection functions available (parity errors, framing errors, and overrun errors) [CSIO]  Full-duplex double buffer  Built-in dedicated baud rate generator  Overrun error detection function available [I2C] Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported A/D Converter (Max 8 channels) [12-bit A/D Converter]  Successive Approximation type  Conversion time: Min. 1.0 μs  Priority conversion available (priority at 2 levels)  Scanning conversion mode  Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps) Base Timer (Max 8 channels) Operation mode is selectable from the followings for each channel.  16-bit PWM timer  16-bit PPG timer  16-/32-bit reload timer  16-/32-bit PWC timer

Document Number: 002-05671 Rev.*B Page 2 of 86 MB9A130LB Series General Purpose I/O Port This series can use its pins as general purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated.  Capable of pull-up control per pin  Capable of reading pin level directly  Built-in the port relocate function  Up to 52 fast general purpose I/O Ports@64 pin Package  Some pins are 5V tolerant I/O See List of Pin Functions and I/O Circuit Type to confirm the corresponding pins. Multi-function Timer The Multi-function timer is composed of the following blocks.  16-bit free-run timer × 3 ch.  Input capture × 4 ch.  Output compare × 6 ch.  A/D activation compare × 1 ch.  Waveform generator × 3 ch.  16-bit PPG timer × 3 ch. The following function can be used to achieve the motor control.  PWM signal output function  DC chopper waveform output function  Dead time function  Input capture function  A/D convertor activate function  DTIF (Motor emergency stop) interrupt function Real-time clock (RTC) The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 00 to 99.  Interrupt function with specifying date and time (Year/Month/Day/Hour/Minute) is available. This function is also available by specifying only Year, Month, Day, Hour or Minute.  Timer interrupt function after set time or each set time.  Capable of rewriting the time with continuing the time count.  Leap year automatic count is available. External Interrupt Controller Unit  Up to 8 external interrupt input pins  Include one non-maskable interrupt (NMI) input pin Watchdog Timer (2 channels) A watchdog timer can generate interrupts or a reset when a time-out value is reached. This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog. Hardware watchdog timer is clocked by built-in Low-speed CR oscillator. Therefore, Hardware watchdog is active in any low power consumption mode except RTC and Stop and Deep Standby RTC and Deep Standby Stop modes. Clock and Reset [Clocks] Five clock sources (2 external oscillators, 2 built-in CR oscillators, and Main PLL) that are dynamically selectable.  Main Clock: 4 MHz to 20 MHz  Sub Clock: 32.768 kHz  Built-in High-speed CR Clock: 4 MHz  Built-in Low-speed CR Clock: 100 kHz  Main PLL Clock [Resets]  Reset requests from INITX pin  Power on reset  Software reset  Watchdog timers reset  Low voltage detector reset  Clock supervisor reset Clock Super Visor (CSV) Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.  If external clock failure (clock stop) is detected, reset is asserted.  If external frequency anomaly is detected, interrupt or reset is asserted. Low Voltage Detector (LVD) This Series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage has been set, Low Voltage Detector generates an interrupt or reset.  LVD1: error reporting via interrupt  LVD2: auto-reset operation

Document Number: 002-05671 Rev.*B Page 3 of 86 MB9A130LB Series Low Power Consumption Mode Six low power consumption modes supported.  Sleep  Timer  RTC  Stop  Deep Standby RTC  Deep Standby Stop Back up register is 16 bytes. Debug Serial Wire JTAG Debug Port (SWJ-DP) Power Supply Wide range voltage: VCC = 1.8 V to 5.5 V

Document Number: 002-05671 Rev.*B Page 5 of 86 MB9A130LB Series

Document Number: 002-05671 Rev.*B Page 6 of 86 MB9A130LB Series 1. Product Lineup Memory size Product name MB9AF131KB/LB MB9AF132KB/LB On-chip Flash 64 Kbytes 128 Kbytes On-chip SRAM SRAM1 8 Kbytes 8 Kbytes Function Product name MB9AF131KB MB9AF132KB MB9AF131LB MB9AF132LB Pin count 48 64 CPU Cortex-M3 Freq. 20 MHz Power supply voltage range 1.8 V to 5.5 V MF Serial Interface (UART/CSIO/I2C) 4 ch. (Max) (CSIO and I2C is Max 3 ch.) 8 ch. (Max) Base Timer (PWC/ Reload timer/PWM/PPG) 8 ch. (Max) MF- Timer A/D activation compare 1 ch. 1 unit (Max) Input capture 4 ch. Free-run timer 3 ch. Output compare 6 ch. Waveform generator 3 ch. PPG 3 ch. Real-time clock 1 unit Watchdog timer 1 ch. (SW) + 1 ch. (HW) External Interrupts 6 pins (Max) + NMI × 1 8 pins (Max) + NMI × 1 general purpose I/O ports 37 pins (Max) 52 pins (Max) 12-bit A/D converter 6 ch. (1 unit) 8 ch. (1 unit) CSV (Clock Super Visor) Yes LVD (Low Voltage Detector) 2 ch. Built-in CR High-speed 4 MHz Low-speed 100 kHz Debug Function SWJ-DP Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package. It is necessary to use the port relocate function of the I/O port according to your function use. See Electrical Characteristics (12.4) AC Characteristics (12.4.3) Built-in CR Oscillation Characteristics for accuracy of built-in CR.

Document Number: 002-05671 Rev.*B Page 7 of 86 MB9A130LB Series 2. Packages Product name Package MB9AF131KB MB9AF132KB MB9AF131LB MB9AF132LB LQFP: LQA048 (0.5mm pitch)  - QFN: VNA048  - LQFP: LQD064 (0.5mm pitch) -  LQFP: LQG064 (0.65mm pitch) -  QFN: VNC064 -  : Supported Note: See Package Dimensions for detailed information on each package.

Document Number: 002-05671 Rev.*B Page 8 of 86 MB9A130LB Series 3. Pin Assignment LQA048 (TOP VIEW) Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P82 P81 P80 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX VCC 1 36 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 35 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 34 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 33 AVSS P39 / DTTI0X_0 / ADTG_2 5 32 AVRH P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 6 31 AVCC P3B / TIOA1_1 / RTO01_0 7 30 P15 / AN05 / IC03_2 P3C / TIOA2_1 / RTO02_0 8 29 P14 / AN04 / INT03_1 / IC02_2 P3D / TIOA3_1 / RTO03_0 9 28 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3E / TIOA4_1 / RTO04_0 10 27 P12 / AN02 / SOT1_1 / IC00_2 P3F / TIOA5_1 / RTO05_0 11 26 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 VSS 12 25 P10 / AN00 C VCC P46 / X0A P47 / X1A INITX P49 / TIOB0_0 P4A / TIOB1_0 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS LQFP - 48

Document Number: 002-05671 Rev.*B Page 9 of 86 MB9A130LB Series VNA048 (TOP VIEW) Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P82 P81 P80 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX VCC 1 36 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 35 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 34 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 33 AVSS P39 / DTTI0X_0 / ADTG_2 5 32 AVRH P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 6 31 AVCC P3B / TIOA1_1 / RTO01_0 7 30 P15 / AN05 / IC03_2 P3C / TIOA2_1 / RTO02_0 8 29 P14 / AN04 / INT03_1 / IC02_2 P3D / TIOA3_1 / RTO03_0 9 28 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3E / TIOA4_1 / RTO04_0 10 27 P12 / AN02 / SOT1_1 / IC00_2 P3F / TIOA5_1 / RTO05_0 11 26 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 VSS 12 25 P10 / AN00 C VCC P46 / X0A P47 / X1A INITX P49 / TIOB0_0 P4A / TIOB1_0 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS QFN - 48

Document Number: 002-05671 Rev.*B Page 10 of 86 MB9A130LB Series LQD064/LQG064 (TOP VIEW) Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P82 P81 P80 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P62 / SCK5_0 / ADTG_3 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX VCC 1 48 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 47 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 46 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 45 P19 / SCK2_2 P30 / TIOB0_1 / INT03_2 5 44 P18 / AN08 / SOT2_2 P31 / SCK6_1 / TIOB1_1 / INT04_2 6 43 AVSS P32 / SOT6_1 / TIOB2_1 / INT05_2 7 42 AVRH P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 8 41 AVCC P39 / DTTI0X_0 / ADTG_2 9 40 P17 / AN07 / SIN2_2 / INT04_1 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 10 39 P15 / AN05 / IC03_2 P3B / TIOA1_1 / RTO01_0 11 38 P14 / AN04 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 12 37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 13 36 P12 / AN02 / SOT1_1 / IC00_2 P3E / TIOA4_1 / RTO04_0 14 35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 P3F / TIOA5_1 / RTO05_0 15 34 P10 / AN00 VSS 16 33 VCC C VCC P46 / X0A P47 / X1A INITX P49 / TIOB0_0 P4A / TIOB1_0 P4B / TIOB2_0 P4C / SCK7_1 / TIOB3_0 P4D / SOT7_1 / TIOB4_0 P4E / SIN7_1 / TIOB5_0 / INT06_2 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS LQFP - 64

Document Number: 002-05671 Rev.*B Page 11 of 86 MB9A130LB Series VNC064 (TOP VIEW) Note: The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. VSS P82 P81 P80 P60 / SIN5_0 / TIOA2_2 / INT15_1 / IC00_0 / WKUP3 P61 / SOT5_0 / TIOB2_2 / DTTI0X_2 P62 / SCK5_0 / ADTG_3 P0F / NMIX / CROUT_1 / RTCCO_0 / SUBOUT_0 / WKUP0 P0C / SCK4_0 / TIOA6_1 P0B / SOT4_0 / TIOB6_1 P0A / SIN4_0 / INT00_2 P04 / TDO / SWO P03 / TMS / SWDIO P02 / TDI P01 / TCK / SWCLK P00 / TRSTX VCC 1 48 P21 / SIN0_0 / INT06_1 / WKUP2 P50 / SIN3_1 / INT00_0 2 47 P22 / SOT0_0 / TIOB7_1 P51 / SOT3_1 / INT01_0 3 46 P23 / SCK0_0 / TIOA7_1 P52 / SCK3_1 / INT02_0 4 45 P19 / SCK2_2 P30 / TIOB0_1 / INT03_2 5 44 P18 / AN08 / SOT2_2 P31 / SCK6_1 / TIOB1_1 / INT04_2 6 43 AVSS P32 / SOT6_1 / TIOB2_1 / INT05_2 7 42 AVRH P33 / SIN6_1 / TIOB3_1 / INT04_0 / ADTG_6 8 41 AVCC P39 / DTTI0X_0 / ADTG_2 9 40 P17 / AN07 / SIN2_2 / INT04_1 P3A / TIOA0_1 / RTO00_0 / RTCCO_2 / SUBOUT_2 10 39 P15 / AN05 / IC03_2 P3B / TIOA1_1 / RTO01_0 11 38 P14 / AN04 / INT03_1 / IC02_2 P3C / TIOA2_1 / RTO02_0 12 37 P13 / AN03 / SCK1_1 / IC01_2 / RTCCO_1 / SUBOUT_1 P3D / TIOA3_1 / RTO03_0 13 36 P12 / AN02 / SOT1_1 / IC00_2 P3E / TIOA4_1 / RTO04_0 14 35 P11 / AN01 / SIN1_1 / INT02_1 / FRCK0_2 / IC02_0 / WKUP1 P3F / TIOA5_1 / RTO05_0 15 34 P10 / AN00 VSS 16 33 VCC C VCC P46 / X0A P47 / X1A INITX P49 / TIOB0_0 P4A / TIOB1_0 P4B / TIOB2_0 P4C / SCK7_1 / TIOB3_0 P4D / SOT7_1 / TIOB4_0 P4E / SIN7_1 / TIOB5_0 / INT06_2 PE0 / MD1 MD0 PE2 / X0 PE3 / X1 VSS QFN - 64

Document Number: 002-05671 Rev.*B Page 12 of 86 MB9A130LB Series 4. List of Pin Functions List of pin numbers The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin No Pin name I/O circuit type Pin state type LQFP-64 QFN-64 LQFP-48 QFN-48 1 1 VCC - 2 2 P50 G F INT00_0 SIN3_1 3 3 P51 G F INT01_0 SOT3_1 (SDA3_1) 4 4 P52 G F INT02_0 SCK3_1 (SCL3_1) 5 - P30 E F TIOB0_1 INT03_2 6 - P31 E F TIOB1_1 SCK6_1 (SCL6_1) INT04_2 7 - P32 E F TIOB2_1 SOT6_1 (SDA6_1) INT05_2 8 - P33 E F INT04_0 TIOB3_1 SIN6_1 ADTG_6 9 5 P39 E H DTTI0X_0 ADTG_2 10 6 P3A E H RTO00_0 (PPG00_0) TIOA0_1 RTCCO_2 SUBOUT_2

Document Number: 002-05671 Rev.*B Page 13 of 86 MB9A130LB Series Pin No Pin name I/O circuit type Pin state type LQFP-64 QFN-64 LQFP-48 QFN-48 11 7 P3B E H RTO01_0 (PPG00_0) TIOA1_1 12 8 P3C E H RTO02_0 (PPG02_0) TIOA2_1 13 9 P3D E H RTO03_0 (PPG02_0) TIOA3_1 14 10 P3E E H RTO04_0 (PPG04_0) TIOA4_1 15 11 P3F E H RTO05_0 (PPG04_0) TIOA5_1 16 12 VSS - 17 13 C - 18 14 VCC - 19 15 P46 D M X0A 20 16 P47 D N X1A 21 17 INITX B C 22 18 P49 E H TIOB0_0 23 19 P4A E H TIOB1_0 24 - P4B E H TIOB2_0

Document Number: 002-05671 Rev.*B Page 14 of 86 MB9A130LB Series Pin No Pin name I/O circuit type Pin state type LQFP-64 QFN-64 LQFP-48 QFN-48 25 - P4C E H TIOB3_0 SCK7_1 (SCL7_1) 26 - P4D E H TIOB4_0 SOT7_1 (SDA7_1) 27 - P4E E F TIOB5_0 INT06_2 SIN7_1 28 20 PE0 C P MD1 29 21 MD0 H D 30 22 PE2 A A 31 23 PE3 A B 32 24 VSS - 33 - VCC - 34 25 P10 F J AN00 35 26 P11 F L AN01 SIN1_1 INT02_1 FRCK0_2 IC02_0 WKUP1 36 27 P12 F J AN02 SOT1_1 (SDA1_1) IC00_2 37 28 P13 F J AN03 SCK1_1 (SCL1_1) IC01_2 RTCCO_1 SUBOUT_1

Document Number: 002-05671 Rev.*B Page 15 of 86 MB9A130LB Series Pin No Pin name I/O circuit type Pin state type LQFP-64 QFN-64 LQFP-48 QFN-48 38 29 P14 F K AN04 INT03_1 IC02_2 39 30 P15 F J AN05 IC03_2 40 - P17 F K AN07 SIN2_2 INT04_1 41 31 AVCC - 42 32 AVRH - 43 33 AVSS - 44 - P18 F J AN08 SOT2_2 (SDA2_2) 45 - P19 E H SCK2_2 (SCL2_2) 46 34 P23 G H SCK0_0 (SCL0_0) TIOA7_1 47 35 P22 G H SOT0_0 (SDA0_0) TIOB7_1 48 36 P21 G G SIN0_0 INT06_1 WKUP2 49 37 P00 E E TRSTX 50 38 P01 E E TCK SWCLK 51 39 P02 E E TDI

Document Number: 002-05671 Rev.*B Page 16 of 86 MB9A130LB Series Pin No Pin name I/O circuit type Pin state type LQFP-64 QFN-64 LQFP-48 QFN-48 52 40 P03 E E TMS SWDIO 53 41 P04 E E TDO SWO 54 - P0A E F SIN4_0 INT00_2 55 - P0B E H SOT4_0 (SDA4_0) TIOB6_1 56 - P0C E H SCK4_0 (SCL4_0) TIOA6_1 57 42 P0F E I NMIX CROUT_1 RTCCO_0 SUBOUT_0 WKUP0 58 - P62 I H SCK5_0 (SCL5_0) ADTG_3 59 43 P61 I H SOT5_0 (SDA5_0) TIOB2_2 DTTI0X_2 60 44 P60 I G SIN5_0 TIOA2_2 INT15_1 IC00_0 WKUP3 61 45 P80 G O 62 46 P81 G O 63 47 P82 G O 64 48 VSS -

Document Number: 002-05671 Rev.*B Page 17 of 86 MB9A130LB Series List of pin functions The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these pins, there are multiple pins that provide the same function for the same channel. Use the extended port function register (EPFR) to select the pin. Pin function Pin name Function description Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 ADC ADTG_2 A/D converter external trigger input pin 9 5 ADTG_3 58 - ADTG_6 8 - AN00 A/D converter analog input pin. ANxx describes ADC ch.xx. 34 25 AN01 35 26 AN02 36 27 AN03 37 28 AN04 38 29 AN05 39 30 AN07 40 - AN08 44 - Base Timer TIOA0_1 Base timer ch.0 TIOA pin 10 6 TIOB0_0 Base timer ch.0 TIOB pin 22 18 TIOB0_1 5 - Base Timer TIOA1_1 Base timer ch.1 TIOA pin 11 7 TIOB1_0 Base timer ch.1 TIOB pin 23 19 TIOB1_1 6 - Base Timer TIOA2_1 Base timer ch.2 TIOA pin 12 8 TIOA2_2 60 44 TIOB2_0 Base timer ch.2 TIOB pin 24 - TIOB2_1 7 - TIOB2_2 59 43 Base Timer TIOA3_1 Base timer ch.3 TIOA pin 13 9 TIOB3_0 Base timer ch.3 TIOB pin 25 - TIOB3_1 8 - Base Timer TIOA4_1 Base timer ch.4 TIOA pin 14 10 TIOB4_0 Base timer ch.4 TIOB pin 26 - Base Timer TIOA5_1 Base timer ch.5 TIOA pin 15 11 TIOB5_0 Base timer ch.5 TIOB pin 27 - Base Timer TIOA6_1 Base timer ch.6 TIOA pin 56 - TIOB6_1 Base timer ch.6 TIOB pin 55 - Base Timer TIOA7_1 Base timer ch.7 TIOA pin 46 34 TIOB7_1 Base timer ch.7 TIOB pin 47 35 Debugger SWCLK Serial wire debug interface clock input pin 50 38 SWDIO Serial wire debug interface data input / output pin 52 40 SWO Serial wire viewer output pin 53 41 TRSTX JTAG reset Input pin 49 37 TCK JTAG test clock input pin 50 38 TDI JTAG test data input pin 51 39 TMS JTAG test mode state input/output pin 52 40 TDO JTAG debug data output pin 53 41

Document Number: 002-05671 Rev.*B Page 18 of 86 MB9A130LB Series Pin function Pin name Function description Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 External Interrupt INT00_0 External interrupt request 00 input pin 2 2 INT00_2 54 - INT01_0 External interrupt request 01 input pin 3 3 INT02_0 External interrupt request 02 input pin 4 4 INT02_1 35 26 INT03_1 External interrupt request 03 input pin 38 29 INT03_2 5 - INT04_0 External interrupt request 04 input pin 8 - INT04_1 40 - INT04_2 6 - INT05_2 External interrupt request 05 input pin 7 - INT06_1 External interrupt request 06 input pin 48 36 INT06_2 27 - INIT15_1 External interrupt request 15 input pin 60 44 NMIX Non-Maskable Interrupt input pin 57 42 GPIO P00 General-purpose I/O port 0 49 37 P01 50 38 P02 51 39 P03 52 40 P04 53 41 P0A 54 - P0B 55 - P0C 56 - P0F 57 42 P10 General-purpose I/O port 1 34 25 P11 35 26 P12 36 27 P13 37 28 P14 38 29 P15 39 30 P17 40 - P18 44 - P19 45 - P21 General-purpose I/O port 2 48 36 P22 47 35 P23 46 34

Document Number: 002-05671 Rev.*B Page 19 of 86 MB9A130LB Series Pin function Pin name Function description Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 GPIO P30 General-purpose I/O port 3 5 - P31 6 - P32 7 - P33 8 - P39 9 5 P3A 10 6 P3B 11 7 P3C 12 8 P3D 13 9 P3E 14 10 P3F 15 11 P46 General-purpose I/O port 4 19 15 P47 20 16 P49 22 18 P4A 23 19 P4B 24 - P4C 25 - P4D 26 - P4E 27 - P50 General-purpose I/O port 5 2 2 P51 3 3 P52 4 4 P60 General-purpose I/O port 6 60 44 P61 59 43 P62 58 - P80 General-purpose I/O port 8 61 45 P81 62 46 P82 63 47 PE0 General-purpose I/O port E 28 20 PE2 30 22 PE3 31 23

Document Number: 002-05671 Rev.*B Page 20 of 86 MB9A130LB Series Pin function Pin name Function description Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 Multi- function Serial SIN0_0 Multi-function serial interface ch.0 input pin 48 36 SOT0_0 (SDA0_0) Multi-function serial interface ch.0 output pin. This pin operates as SOT0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA0 when it is used in an I2C (operation mode 4). 47 35 SCK0_0 (SCL0_0) Multi-function serial interface ch.0 clock I/O pin. This pin operates as SCK0 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL0 when it is used in an I2C (operation mode 4). 46 34 Multi- function Serial SIN1_1 Multi-function serial interface ch.1 input pin 35 26 SOT1_1 (SDA1_1) Multi-function serial interface ch.1 output pin. This pin operates as SOT1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA1 when it is used in an I2C (operation mode 4). 36 27 SCK1_1 (SCL1_1) Multi-function serial interface ch.1 clock I/O pin. This pin operates as SCK1 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL1 when it is used in an I2C (operation mode 4). 37 28 Multi- function Serial SIN2_2 Multi-function serial interface ch.2 input pin 40 - SOT2_2 (SDA2_2) Multi-function serial interface ch.2 output pin. This pin operates as SOT2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA2 when it is used in an I2C (operation mode 4). 44 - SCK2_2 (SCL2_2) Multi-function serial interface ch.2 clock I/O pin. This pin operates as SCK2 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL2 when it is used in an I2C (operation mode 4). 45 -

Document Number: 002-05671 Rev.*B Page 21 of 86 MB9A130LB Series Pin function Pin name Function description Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 Multi- function Serial SIN3_1 Multi-function serial interface ch.3 input pin 2 2 SOT3_1 (SDA3_1) Multi-function serial interface ch.3 output pin. This pin operates as SOT3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA3 when it is used in an I2C (operation mode 4). 3 3 SCK3_1 (SCL3_1) Multi-function serial interface ch.3 clock I/O pin. This pin operates as SCK3 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL3 when it is used in an I2C (operation mode 4). 4 4 Multi- function Serial SIN4_0 Multi-function serial interface ch.4 input pin 54 - SOT4_0 (SDA4_0) Multi-function serial interface ch.4 output pin. This pin operates as SOT4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA4 when it is used in an I2C (operation mode 4). 55 - SCK4_0 (SCL4_0) Multi-function serial interface ch.4 clock I/O pin. This pin operates as SCK4 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL4 when it is used in an I2C (operation mode 4). 56 - Multi- function Serial SIN5_0 Multi-function serial interface ch.5 input pin 60 44 SOT5_0 (SDA5_0) Multi-function serial interface ch.5 output pin. This pin operates as SOT5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA5 when it is used in an I2C (operation mode 4). 59 43 SCK5_0 (SCL5_0) Multi-function serial interface ch.5 clock I/O pin. This pin operates as SCK5 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL5 when it is used in an I2C (operation mode 4). 58 -

Document Number: 002-05671 Rev.*B Page 22 of 86 MB9A130LB Series Pin function Pin name Function description Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 Multi- function Serial SIN6_1 Multi-function serial interface ch.6 input pin 8 - SOT6_1 (SDA6_1) Multi-function serial interface ch.6 output pin. This pin operates as SOT6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA6 when it is used in an I2C (operation mode 4). 7 - SCK6_1 (SCL6_1) Multi-function serial interface ch.6 clock I/O pin. This pin operates as SCK6 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL6 when it is used in an I2C (operation mode 4). 6 - Multi- function Serial SIN7_1 Multi-function serial interface ch.7 input pin 27 - SOT7_1 (SDA7_1) Multi-function serial interface ch.7 output pin. This pin operates as SOT7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SDA7 when it is used in an I2C (operation mode 4). 26 - SCK7_1 (SCL7_1) Multi-function serial interface ch.7 clock I/O pin. This pin operates as SCK7 when it is used in a UART/CSIO (operation modes 0 to 2) and as SCL7 when it is used in an I2C (operation mode 4). 25 -

Document Number: 002-05671 Rev.*B Page 23 of 86 MB9A130LB Series Pin function Pin name Function description Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 Multi- function Timer DTTI0X_0 Input signal of waveform generator to control outputs RTO00 to RTO05 of Multi-function timer 0 9 5 DTTI0X_2 59 43 FRCK0_2 16-bit free-run timer ch.0 external clock input pin 35 26 IC00_0 16-bit input capture input pin of Multi-function timer 0. ICxx describes a channel number. 60 44 IC00_2 36 27 IC01_2 37 28 IC02_0 35 26 IC02_2 38 29 IC03_2 39 30 RTO00_0 (PPG00_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 10 6 RTO01_0 (PPG00_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG00 when it is used in PPG0 output modes. 11 7 RTO02_0 (PPG02_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 12 8 RTO03_0 (PPG02_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG02 when it is used in PPG0 output modes. 13 9 RTO04_0 (PPG04_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 14 10 RTO05_0 (PPG04_0) Waveform generator output pin of Multi-function timer 0. This pin operates as PPG04 when it is used in PPG0 output modes. 15 11 Real-time clock RTCCO_0 0.5 seconds pulse output pin of Real-time clock 57 42 RTCCO_1 37 28 RTCCO_2 10 6 SUBOUT_0 Sub clock output pin 57 42 SUBOUT_1 37 28 SUBOUT_2 10 6 Low Power Consumption Mode WKUP0 Deep stand-by mode return signal input pin 0 57 42 WKUP1 Deep stand-by mode return signal input pin 1 35 26 WKUP2 Deep stand-by mode return signal input pin 2 48 36 WKUP3 Deep stand-by mode return signal input pin 3 60 44

Document Number: 002-05671 Rev.*B Page 24 of 86 MB9A130LB Series Pin function Pin name Function description Pin No LQFP-64 QFN-64 LQFP-48 QFN-48 Reset INITX External Reset Input pin. A reset is valid when INITX = L. 21 17 Mode MD0 Mode 0 pin. During normal operation, MD0 = L must be input During serial programming to flash memory, MD0 = H must be input. 29 21 MD1 Mode 1 pin. During normal operation, input is not needed During serial programming to flash memory, MD1 = L must be input. 28 20 Power VCC Power supply pin 1 1 18 14 33 - GND VSS GND pin 16 12 32 24 64 48 Clock X0 Main clock (oscillation) input pin 30 22 X0A Sub clock (oscillation) input pin 19 15 X1 Main clock (oscillation) I/O pin 31 23 X1A Sub clock (oscillation) I/O pin 20 16 CROUT_1 Built-in High-speed CR-osc clock output port 57 42 ADC Power AVCC A/D converter analog power pin 41 31 AVRH A/D converter analog reference voltage input pin 42 32 ADC GND AVSS A/D converter GND pin 43 33 C pin C Power stabilization capacity pin 17 13 Note: While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller.

Document Number: 002-05671 Rev.*B Page 25 of 86 MB9A130LB Series 5. I/O Circuit Type Type Circuit Remarks A It is possible to select the main oscillation / GPIO function. When the main oscillation is selected.

• Oscillation feedback resistor : Approximately 1 MΩ
• With Standby control When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby control
• Pull-up resistor : Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA P-ch P-ch N-ch R R P-ch P-ch N-ch Pull-up resistor Feedback resistor Pull-up resistor Digital output Digital output Pull-up resistor control Digital input Standby mode Control Clock input Standby mode Control Digital input Standby mode Control Digital output Digital output Pull-up resistor control

Document Number: 002-05671 Rev.*B Page 26 of 86 MB9A130LB Series Type Circuit Remarks B

• CMOS level hysteresis input
• Pull-up resistor : Approximately 50 kΩ C
• Open drain output
• CMOS level hysteresis input N-ch Pull-up resistor Digital input Digital input Digital output

Document Number: 002-05671 Rev.*B Page 27 of 86 MB9A130LB Series Type Circuit Remarks D It is possible to select the sub oscillation / GPIO function When the sub oscillation is selected.

• Oscillation feedback resistor : Approximately 5 MΩ
• With Standby control When the GPIO is selected.
• CMOS level output.
• CMOS level hysteresis input
• With pull-up resistor control
• With standby control
• Pull-up resistor : Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA P-ch P-ch N-ch R R P-ch P-ch N-ch X0A X1A Pull-up resistor Feedback resistor Pull-up resistor Digital output Digital output Pull-up resistor control Digital input Standby mode Control Clock input Standby mode Control Digital input Standby mode Control Digital output Digital output Pull-up resistor control

Document Number: 002-05671 Rev.*B Page 28 of 86 MB9A130LB Series Type Circuit Remarks E

• CMOS level output
• CMOS level hysteresis input
• With pull-up resistor control
• With standby control
• Pull-up resistor : Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off F
• CMOS level output
• CMOS level hysteresis input
• With input control
• Analog input
• With pull-up resistor control
• With standby control
• Pull-up resistor : Approximately 50 kΩ
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off P-chP-ch N-ch R P-chP-ch N-ch R Digital output Digital output Pull-up resistor control Digital input Standby mode Control Digital output Digital output Pull-up resistor control Digital input Standby mode Control Analog input Input control

Document Number: 002-05671 Rev.*B Page 29 of 86 MB9A130LB Series Type Circuit Remarks G

• CMOS level output
• CMOS level hysteresis input
• With standby control
• 5 V tolerant input
• IOH = -4 mA, IOL = 4 mA
• Available to control of PZR registers. Only P22, P23, P51, P52
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off H CMOS level hysteresis input I
• CMOS level output
• CMOS level hysteresis input
• With standby control
• IOH = -4 mA, IOL = 4 mA
• When this pin is used as an I2C pin, the digital output P-ch transistor is always off P-ch N-ch R P-ch N-ch R Mode input Digital output Digital output Digital input Standby mode control Digital output Digital output Digital input Standby mode control

Document Number: 002-05671 Rev.*B Page 30 of 86 MB9A130LB Series 6. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

6.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

Document Number: 002-05671 Rev.*B Page 31 of 86 MB9A130LB Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

6.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress' recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 3. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 4. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 5. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 6. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h

Document Number: 002-05671 Rev.*B Page 32 of 86 MB9A130LB Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

6.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives.

Document Number: 002-05671 Rev.*B Page 33 of 86 MB9A130LB Series 7. Handling Devices Power supply pins In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with each Power supply pins and GND pins of this device at low impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between each Power supply pins and GND pins, between AVCC pin and AVSS pin near this device. Stabilizing power supply voltage A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary fluctuation on switching the power supply. Crystal oscillator circuit Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by ground plane as this is expected to produce stable operation. Evaluate oscillation of your using crystal oscillator by your mount board. Using an external clock To use the external clock, set general-purpose I/O ports to input the clock to X0/PE2 and X0A/P46 pins. Handling when using Multi-function serial pin as I2C pin If it is using the Multi-function serial pin as I2C pins, P-ch transistor of digital output is always disable. However, I2C pins need to keep the electrical characteristic like other pins and not to connect to external I2C bus system with power OFF.  Example of Using an External Clock Device X0/PE2 (X0A/P46) X1/PE3 (X1A/P47) Can be used as general-purpose I/O ports. Set as general-purpose I/O ports.

Document Number: 002-05671 Rev.*B Page 34 of 86 MB9A130LB Series C Pin This series contains the regulator. Be sure to connect a smoothing capacitor (CS) for the regulator between the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. However, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. A smoothing capacitor of about 4.7uF would be recommended for this series. Mode pins (MD0, MD1) Connect the MD pin (MD0, MD1) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for switching the pin level and rewriting the Flash memory data. It is because of preventing the device erroneously switching to test mode due to noise. Notes on power-on Turn power on/off in the following order or at the same time. If not using the A/D converter, connect AVCC = VCC and AVSS = VSS. Turning on: VCC → AVCC → AVRH Turning off: AVRH → AVCC → VCC Serial Communication There is a possibility to receive wrong data due to the noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. If an error is detected, retransmit the data. Differences in features among the products with different memory sizes and between Flash memory products and MASK products The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between Flash memory products and MASK products are different because chip layout and memory structures are different. If you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics. Device C VSS CS GND

Document Number: 002-05671 Rev.*B Page 35 of 86 MB9A130LB Series 8. Block Diagram Flash I/FCortex-M3 Core @20MHz(Max) Clock Reset Generator Watchdog Timer (Hardware) On-Chip Flash 64/128Kbytes Multi-Function Timer ×1 Multi-Function Serial I/F 8ch. 16-bit FreeRun Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. Waveform Generator 3ch. A/D Activation Compare 1ch. 16-bit PPG 3ch. Real-Time Clock GPIO CSV PLL External Interrupt Controller 8-pin + NMI ROM TableSWJ-DP Multi-layer AHB (Max 20MHz) AHB-APB Bridge : APB1 (Max 20MHz) SRAM1 8Kbytes AHB-APB Bridge: APB0 (Max 20MHz) I D Sys CLK MB9AF131/132 AHB-APB Bridge : APB2 (Max 20MHz) Base Timer 16-bit 8ch. / 32-bit 4ch. NVIC Watchdog Timer (Software) Security 12-bit A/D Converter Unit 0 TRSTX,TCK, TDI,TMS AVCC, AVSS,AVRH ANxx TIOAx TIOBx IC0x DTTI0X RTO0x FRCK0 TDO X0A X1A SCKx SINx SOTx INTxx NMIX P0x, P1x, Pxx INITX MODE-Ctrl IRQ-Monitor PIN-Function-Ctrl MD1, MD0 CR 100kHz ADTG_x SUBOUT Deep Standby Ctrl WKUPx RTCCO LVD Power On Reset CRegulator LVD Ctrl Source Clock CROUT Main Osc Sub Osc CR 4MHz

Document Number: 002-05671 Rev.*B Page 36 of 86 MB9A130LB Series 9. Memory Size See Memory size in Product Lineup to confirm the memory size. 10. Memory Map Memory Map (1) Peripherals Area 0x41FF_FFFF 0xFFFF_FFFF 0xE010_0000 0xE000_0000 0x4003_C000 0x4003_B000 RTC 0x4003_9000 0x4003_8000 MFS 0x4400_0000 0x4003_6000 0x4200_0000 0x4003_5000 LVD/DS mode 0x4003_4000 Reserved 0x4000_0000 0x4003_3000 GPIO 0x4003_2000 Reserved 0x4003_1000 Int-Req.Read 0x2400_0000 0x4003_0000 EXTI 0x4002_F000 Reserved 0x2200_0000 0x4002_E000 CR Trim 0x4002_8000 0x2008_0000 0x4002_7000 A/DC 0x2000_0000 SRAM1 0x4002_6000 Reserved 0x4002_5000 Base Timer 0x4002_4000 PPG 0x0010_0008 0x0010_0000 Security/CR Trim 0x4002_1000 0x4002_0000 MFT unit0 0x0000_0000 0x4001_3000 0x4001_2000 SW WDT 0x4001_1000 HW WDT 0x4001_0000 Clock/Reset 0x4000_1000 0x4000_0000 Flash I/F Reserved Peripherals Reserved 32Mbytes Bit band alias Reserved Reserved Reserved Reserved Cortex-M3 Private Peripherals Reserved Reserved Reserved32Mbytes Bit band alias See "lMemory map(2)" for the memory size details. Reserved Reserved Flash Reserved

Document Number: 002-05671 Rev.*B Page 37 of 86 MB9A130LB Series Memory Map (2) *: See MB9AAA0N/1A0N/A30N/130N/130L Series Flash Programming Manual to confirm the detail of Flash memory. MB9AF132KB/LB MB9AF131KB/LB 0x2008_0000 0x2008_0000 0x2000_2000 0x2000_2000 0x2000_0000 0x2000_0000 0x0010_0008 0x0010_0008 0x0010_0004 CR trimming 0x0010_0004 CR trimming 0x0010_0000 Security 0x0010_0000 Security 0x0002_0000 0x0001_0000 0x0000_0000 SA1 (4 KB) 0x0000_0000 SA1 (4 KB) Flash 64 Kbytes SA2 (60 KB) SA3 (64 KB) SA2 (60 KB) Flash 128 Kbytes Reserved Reserved Reserved Reserved Reserved SRAM1

8 Kbytes

Document Number: 002-05671 Rev.*B Page 38 of 86 MB9A130LB Series Peripheral Address Map Start address End address Bus Peripherals 0x4000_0000 0x4000_0FFF AHB Flash I/F register 0x4000_1000 0x4000_FFFF Reserved 0x4001_0000 0x4001_0FFF APB0 Clock/Reset Control 0x4001_1000 0x4001_1FFF Hardware Watchdog timer 0x4001_2000 0x4001_2FFF Software Watchdog timer 0x4001_3000 0x4001_4FFF Reserved 0x4001_5000 0x4001_5FFF Reserved 0x4001_6000 0x4001_FFFF Reserved 0x4002_0000 0x4002_0FFF APB1 Multi-function timer unit0 0x4002_1000 0x4002_1FFF Reserved 0x4002_2000 0x4002_3FFF Reserved 0x4002_4000 0x4002_4FFF PPG 0x4002_5000 0x4002_5FFF Base Timer 0x4002_6000 0x4002_6FFF Reserved 0x4002_7000 0x4002_7FFF A/D Converter 0x4002_8000 0x4002_DFFF Reserved 0x4002_E000 0x4002_EFFF Built-in CR trimming 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF APB2 External Interrupt Controller 0x4003_1000 0x4003_1FFF Interrupt Source Check Register 0x4003_2000 0x4003_2FFF Reserved 0x4003_3000 0x4003_3FFF GPIO 0x4003_4000 0x4003_4FFF Reserved 0x4003_5000 0x4003_50FF Low Voltage Detector 0x4003_5100 0x4003_5FFF Deep stand-by mode Controller 0x4003_6000 0x4003_6FFF Reserved 0x4003_7000 0x4003_7FFF Reserved 0x4003_8000 0x4003_8FFF Multi-function serial Interface 0x4003_9000 0x4003_9FFF Reserved 0x4003_A000 0x4003_AFFF Reserved 0x4003_B000 0x4003_BFFF Real-time clock 0x4003_C000 0x4003_FFFF Reserved 0x4004_0000 0x4004_FFFF AHB Reserved 0x4005_0000 0x4005_FFFF Reserved 0x4006_0000 0x4006_0FFF Reserved 0x4006_1000 0x4006_1FFF Reserved 0x4006_2000 0x4006_2FFF Reserved 0x4006_3000 0x4006_3FFF Reserved 0x4006_4000 0x41FF_FFFF Reserved

Document Number: 002-05671 Rev.*B Page 39 of 86 MB9A130LB Series 11. Pin Status in Each CPU State The terms used for pin status have the following meanings.  INITX = 0 This is the period when the INITX pin is the L level.  INITX = 1 This is the period when the INITX pin is the H level.  SPL = 0 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to 0.  SPL = 1 This is the status that standby pin level setting bit (SPL) in standby mode control register (STB_CTL) is set to 1.  Input enabled Indicates that the input function can be used.  Internal input fixed at 0 This is the status that the input function cannot be used. Internal input is fixed at L.  Hi-Z Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.  Setting disabled Indicates that the setting is disabled.  Maintain previous state Maintains the state that was immediately prior to entering the current mode. If a built-in peripheral function is operating, the output follows the peripheral function. If the pin is being used as a port, that output is maintained.  Analog input is enabled Indicates that the analog input is enabled.  Trace output Indicates that the trace function can be used.  GPIO selected In Deep Standby mode, pins switch to the general-purpose I/O port.

Document Number: 002-05671 Rev.*B Page 40 of 86 MB9A130LB Series List of Pin Status Pin status type Function group Power-o n reset or low voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - A Main crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled External main clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state / When oscillation stop*1, output maintain previous state / Internal input fixed at 0 Hi-Z / Input enabled / When oscillation stop*1, Hi-Z / Internal input fixed at 0 Output maintain previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Output maintain previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Output maintain previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state B Main crystal oscillator output pin Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stop*1, Hi-Z output / Internal input fixed at 0 Maintain previous state / When oscillation stop*1, Hi-Z output / Internal input fixed at 0 Maintain previous state / When oscillation stop*1, Hi-Z output / Internal input fixed at 0 Maintain previous state / When oscillation stop*1, Hi-Z output / Internal input fixed at 0 Maintain previous state / When oscillation stop*1, Hi-Z output / Internal input fixed at 0 Maintain previous state / When oscillation stop*1, Hi-Z output / Internal input fixed at "0" GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state C INITX input pin Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled Pull-up / Input enabled

Document Number: 002-05671 Rev.*B Page 41 of 86 MB9A130LB Series Pin status type Function group Power-o n reset or low voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - D Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled E JTAG selected Hi-Z Pull-up / Input enabled Pull-up / Input enabled Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state Maintain previous state GPIO selected Setting disabled Setting disabled Setting disabled Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 F External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Maintain previous state G WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state GPIO selected Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Maintain previous state H Resource selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Maintain previous state Maintain previous state

Document Number: 002-05671 Rev.*B Page 42 of 86 MB9A130LB Series Pin status type Function group Power-o n reset or low voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - I NMIX selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state WKUP input enabled Hi-Z / WKUP input enabled GPIO selected Resource other than above selected Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state J Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Resource other than above selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO selected Hi-Z / Internal input fixed at 0 GPIO selected GPIO selected Maintain previous state Maintain previous state K Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled External interrupt enabled selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Maintain previous state GPIO selected Hi-Z / Internal input fixed at 0 GPIO selected Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Maintain previous state

Document Number: 002-05671 Rev.*B Page 43 of 86 MB9A130LB Series Pin status type Function group Power-o n reset or low voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - L Analog input selected Hi-Z Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled Hi-Z / Internal input fixed at 0 / Analog input enabled WKUP enabled Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 WKUP input enabled Hi-Z / WKUP input enabled GPIO selected External interrupt enabled selected Maintain previous state GPIO selected Hi-Z / Internal input fixed at 0 Resource other than above selected Hi-Z / Internal input fixed at 0 GPIO selected Maintain previous state Maintain previous state M Sub crystal oscillator input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled External sub clock input selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state / When oscillation stop*2, output maintain previous state / Internal input fixed at 0 Hi-Z / Input enabled / When oscillation stop*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stop*2, output maintain previous state / Internal input fixed at 0 Hi-Z / Input enabled / When oscillation stop*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When Return from Deep Stand-by STOP mode, GPIO selected GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Output maintain previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Output maintain previous state / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state

Document Number: 002-05671 Rev.*B Page 44 of 86 MB9A130LB Series Pin status type Function group Power-o n reset or low voltage detection state INITX input state Device internal reset state Run mode or Sleep mode state Timer mode, RTC mode, or Stop mode state Deep Standby RTC mode or Deep Standby Stop mode state Return from Deep Standby mode state Power supply unstable Power supply stable Power supply stable Power supply stable Power supply stable Power supply stable - INITX = 0 INITX = 1 INITX = 1 INITX = 1 INITX = 1 INITX = 1 - - - - SPL = 0 SPL = 1 SPL = 0 SPL = 1 - N Sub crystal oscillator output pin Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 Maintain previous state / When oscillation stops*2, Hi-Z / Internal input fixed at 0 GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state Hi-Z / Internal input fixed at 0 Maintain previous state O GPIO Hi-Z Hi-Z / Input enabled Hi-Z / Input enabled Maintain previous state Maintain previous state Hi-Z / Internal input fixed at 0 GPIO/ Internal input fixed at 0 Hi-Z / Internal input fixed at 0 Maintain previous state P Mode input pin Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled Input enabled GPIO selected Setting disabled Setting disabled Setting disabled Maintain previous state Maintain previous state Hi-Z / Input enabled Maintain previous state Hi-Z / Input enabled Maintain previous state *1: Oscillation is stopped at Sub run mode, Low-speed CR Run mode, Sub Sleep mode, Low-speed CR Sleep mode, Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep Standby RTC mode, and Deep Standby Stop mode. *2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.

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12.1 Absolute Maximum Ratings

Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*1,*2 VCC VSS - 0.5 VSS + 6.5 V Analog power supply voltage*1,*3 AVCC VSS - 0.5 VSS + 6.5 V Analog reference voltage*1,*3 AVRH VSS - 0.5 VSS + 6.5 V Input voltage*1 VI VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V VSS - 0.5 VSS + 6.5 V 5V tolerant Analog pin input voltage*1 VIA VSS - 0.5 AVCC + 0.5 (≤ 6.5 V) V Output voltage*1 VO VSS - 0.5 VCC + 0.5 (≤ 6.5 V) V L level maximum output current*4 IOL - 10 mA L level average output current*5 IOLAV - 4 mA L level total maximum output current ∑IOL - 60 mA L level total average output current*6 ∑IOLAV - 30 mA H level maximum output current*4 IOH - -10 mA H level average output current*5 IOHAV - - 4 mA H level total maximum output current ∑IOH - -60 mA H level total average output current*6 ∑IOHAV - -30 mA Power consumption PD - 400 mW Storage temperature TSTG - 55 + 150 °C *1: These parameters are based on the condition that VSS = AVSS = 0.0 V. *2: VCC must not drop below VSS - 0.5 V. *3: Be careful not to exceed VCC + 0.5 V, for example, when the power is turned on. *4: The maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *5: The average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *6: The total average output current is defined as the average current value flowing through all of corresponding pins for a 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

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12.2 Recommended Operating Conditions

(VSS = AVSS = 0.0V) Parameter Symbol Conditions Value Unit Remarks Min Max Power supply voltage VCC - 1.8 5.5 V Analog power supply voltage AVCC - 1.8 5.5 V AVCC = VCC Analog reference voltage AVRH - 2.7 AVCC V AVCC ≥ 2.7 V AVCC AVCC AVCC < 2.7 V Smoothing capacitor CS - 1 10 μF For built-in Regulator * Operating Temperature LQA048, VNA048, LQD064, LQG064, VNC064 TA - - 40 + 85 °C *: See C Pin in Handling Devices for the connection of the smoothing capacitor. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.

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12.3 DC Characteristics

12.3.1 Current Rating

(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ*3 Max*4 Power supply current ICC VCC PLL Run mode CPU: 20 MHz, Peripheral: 20 MHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 20 25 mA *1, *5 CPU: 20 MHz, Peripheral: clock stopped, NOP operation 10 15 mA *1, *5 High-speed CR Run mode CPU/Peripheral: 4 MHz*2 Flash memory 0 Wait FRWTR.RWT = 00 FSYNDN.SD = 000 4.5 5 mA *1 Sub Run mode CPU/Peripheral: 32 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 Low-speed CR Run mode CPU/Peripheral: 100 kHz, Flash memory 0 Wait, FRWTR.RWT = 00, FSYNDN.SD = 000 0.3 0.45 mA *1 ICCS PLL Sleep mode Peripheral: 20 MHz 9 13 mA *1, *5 High-speed CR Sleep mode Peripheral: 4 MHz*2 2 2.5 mA *1 Sub Sleep mode Peripheral: 32 kHz 0.1 0.2 mA *1, *6 Low-speed CR Sleep mode Peripheral: 100 kHz 0.2 0.35 mA *1 *1: When all ports are fixed. *2: When setting it to 4 MHz by trimming. *3: TA=+25°C, VCC=3.3 V *4: TA=+85°C, VCC=5.5 V *5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

Document Number: 002-05671 Rev.*B Page 48 of 86 MB9A130LB Series Parameter Symbol Pin name Conditions Value Unit Remarks Typ*2 Max*3 Power supply current ICCT VCC Main Timer mode TA = + 25°C, When LVD is off 1 3.6 mA *1, *4 TA = + 85°C, When LVD is off 1.7 3.9 mA *1, *4 Sub Timer mode TA = + 25°C, When LVD is off 8.5 70 μA *1, *5 TA = + 85°C, When LVD is off 18 170 μA *1, *5 ICCR RTC mode TA = + 25C, When LVD is off 1.8 7.5 μA *1, *5 TA = + 85C, When LVD is off 7 62 μA *1, *5 ICCH Stop mode TA = + 25C, When LVD is off 0.7 7 μA *1 TA = + 85C, When LVD is off 6 60 μA *1 ICCRD Deep Standby RTC mode TA = + 25C, When LVD is off 1.6 3 μA *1, *5 TA = + 85C, When LVD is off 3.6 14.5 μA *1, *5 ICCHD Deep Standby Stop mode TA = + 25C, When LVD is off 0.5 2.5 μA *1 TA = + 85C, When LVD is off 2.5 12.5 μA *1 *1: When all ports are fixed. *2: VCC = 3.3 V *3: VCC = 5.5 V *4: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit) *5: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)

Document Number: 002-05671 Rev.*B Page 49 of 86 MB9A130LB Series Low Voltage Detection Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40C to + 85C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ* Max Low-voltage detection circuit (LVD) power supply current ICCLVD VCC For occurrence of reset or for occurrence of interrupt in normal mode operation 10 20 μA When not detected For occurrence of reset and for occurrence of interrupt in normal mode operation 14 30 μA For occurrence of interrupt in low-power mode operation 0.3 2 μA When not detected *: When VCC = 3.3 V Flash Memory Current (VCC = 1.8 V to 5.5 V, VSS = 0 V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Flash memory write/erase current ICCFLASH VCC At Write/Erase 10.8 11.9 mA A/D Converter Current (VCC = AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0 V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Typ Max Power supply current ICCAD AVCC At 1unit operation 1.4 2.5 mA At stop 0.1 0.35 μA Reference power supply current ICCAVRH AVRH At 1unit operation AVRH=5.5 V 0.8 1.5 mA At stop 0.1 0.3 μA

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12.3.2 Pin Characteristics

(VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Typ Max H level input voltage (hysteresis input) VIHS MD0, MD1, PE0, PE2, PE3, P46, P47, INITX - VCC × 0.8 - VCC + 0.3 V P21, P22, P23, P50, P51, P52, P80, P81, P82 - VCC× 0.7 - VSS +

5.5 V 5V tolerant

• VCC × 0.7 - VCC + 0.3 V L level input voltage (hysteresis input) VILS MD0, MD1, PE0, PE2, PE3, P46, P47, INITX - VSS - 0.3 - VCC× 0.2 V CMOS hysteresis input pins other than the above - VSS - 0.3 - VCC× 0.3 V H level output voltage VOH Pxx VCC ≥ 4.5 V IOH = - 4 mA VCC - 0.5 - VCC V VCC < 4.5 V IOH = - 1 mA VCC - 0.5 - VCC L level output voltage VOL Pxx VCC ≥ 4.5 V IOL = 4 mA VSS - 0.4 V VCC < 4.5 V IOL = 2 mA Input leak current IIL - - - 5 - +5 μA Pull-up resistance value RPU Pull-up pin VCC ≥ 4.5 V 25 50 100 kΩ VCC < 4.5 V 40 100 400 Input capacitance CIN Other than VCC, VSS, AVCC, AVSS, AVRH - - 5 15 pF

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12.4 AC Characteristics

12.4.1 Main Clock Input Characteristics

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input frequency fCH X0, VCC ≥ 2.0 V 4 20 MHz When crystal oscillator is connected VCC < 2.0 V 4 4 MHz VCC ≥ 4.5 V 4 20 MHz When using external clock VCC < 4.5 V 4 16 MHz Input clock cycle tCYLH VCC ≥ 4.5 V 50 250 ns When using external clock VCC < 4.5 V 62.5 250 ns Input clock pulse width - PWH/tCYLH, PWL/tCYLH 45 55 % When using external clock Input clock rise time and fall time tCF, tCR - - 5 ns When using external clock Internal operating clock*1 frequency fCM - - - 20 MHz Master clock fCC - - - 20 MHz Base clock (HCLK/FCLK) fCP0 - - - 20 MHz APB0 bus clock*2 fCP1 - - - 20 MHz APB1 bus clock*2 fCP2 - - - 20 MHz APB2 bus clock*2 Internal operating clock*1 cycle time tCYCC - - 50 - ns Base clock (HCLK/FCLK) tCYCP0 - - 50 - ns APB0 bus clock*2 tCYCP1 - - 50 - ns APB1 bus clock*2 tCYCP2 - - 50 - ns APB2 bus clock*2 *1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral Manual. *2: For about each APB bus which each peripheral is connected to, see Block Diagram in this data sheet.

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12.4.2 Sub Clock Input Characteristics

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Condition s Value Unit Remarks Min Typ Max Input frequency fCL X0A, X1A - - 32.768 - kHz When crystal oscillator is connected - 32 - 100 kHz When using external clock Input clock cycle tCYLL - 10 - 31.25 μs When using external clock Input clock pulse width - PWH/tCYLL, PWL/tCYLL 45 - 55 % When using external clock

12.4.3 Built-in CR Oscillation Characteristics

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRH VCC ≥ 2.2 V TA = + 25°C 3.92 4 4.08 MHz When trimming*1 TA = - 40°C to + 85°C 3.8 4 4.2 TA = - 40°C to + 85°C 2.3 - 7.03 When not trimming VCC < 2.2 V TA = + 25°C 3.4 4 4.6 MHz When trimming*1 TA = - 40°C to + 85°C 3.16 4 4.84 TA = - 40°C to + 85°C 2.3 - 7.03 When not trimming Frequency stabilization time tCRWT - - - 10 μs *2 *1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency trimming. *2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value. This period is able to use High-speed CR clock as source clock. Built-in Low-speed CR (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Clock frequency fCRL - 50 100 150 kHz X0A

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12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL)

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency fPLLI 4 - 20 MHz PLL multiplication rate - 1 - 5 multiplier PLL macro oscillation clock frequency fPLLO 10 - 20 MHz Main PLL clock frequency*2 fCLKPLL - - 20 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock(CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. 12.4.5 Operating Conditions of Main PLL (In the case of using built-in High-speed CR clock for input clock of Main PLL) (VCC = 2.2V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 200 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiplication rate - 3 - 4 multiplier PLL macro oscillation clock frequency fPLLO 11.4 - 16.8 MHz Main PLL clock frequency*2 fCLKPLL - - 16.8 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock(CLKPLL), see Chapter 2-1: Clock in FM3 Family Peripheral Manual. Note: Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the frequency has been trimmed. When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. High-speed CR clock (CLKHC) PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Main PLL connection Main clock (CLKMO) K divider

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12.4.6 Reset Input Characteristics

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Reset input time tINITX INITX - 500 - ns 1.5 - ms When RTC mode or Stop mode 1.5 - ms When Deep Standby mode

12.4.7 Power-on Reset Timing

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Power supply rising time dV/dt VCC 0.1 - - V/ms Power supply shut down time tOFF 1 - - ms Reset release voltage VDETH 1.44 1.60 1.76 V When voltage rises Reset detection voltage VDETL 1.39 1.55 1.71 V When voltage drops Time until releasing Power-on reset tPRT 0.46 - 11.4 ms dV/dt ≥ 0.1mV/μs Reset detection delay time tOFFD - - 0.4 ms dV/dt ≥ -0.04mV/μs VDETH tPRT Internal reset VCC CPU Operation start Reset active Release 0.2V 0.2V tOFF dt dV VDETL tOFFD Reset active

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12.4.8 Base Timer Input Timing

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTIWH, tTIWL TIOAn/TIOBn (when using as ECK,TIN) - 2tCYCP - ns Trigger input timing (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max Input pulse width tTRGH, tTRGL TIOAn/TIOBn (when using as TGIN) - 2tCYCP - ns Note: tCYCP indicates the APB bus clock cycle time. About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet. tTIWH VIHS VIHS VILS VILS tTIWL tTRGH VIHS VIHS VILS VILS tTRGL ECK TIN TGIN

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12.4.9 CSIO/UART Timing

CSIO (SPI = 0, SCINV = 0) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V 2.7 V ≤ VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Min Max Baud rate - - - - 5 - 5 - 5 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 75 - 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 75 - 50 - 30*1 ns 40*2 SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 - 5 ns *1 When PZR = 0. *2 When PZR = 1. Notes: The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF.

Document Number: 002-05671 Rev.*B Page 57 of 86 MB9A130LB Series Master mode Slave mode tSHSL tSLSH VIH tF tR VIH VOH VIL VIL VIL VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSHOVE tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI SCK SOT SIN

Document Number: 002-05671 Rev.*B Page 58 of 86 MB9A130LB Series CSIO (SPI = 0, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V 2.7 V ≤ VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Min Max Baud rate - - - - 5 - 5 - 5 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 75 - 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI SCKx, SINx 0 - 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 75 - 50 - 30*1 ns 40*2 SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx, SINx 20 - 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 - 5 ns *1 When PZR = 0. *2 When PZR = 1. Notes: The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF.

Document Number: 002-05671 Rev.*B Page 59 of 86 MB9A130LB Series Master mode Slave mode tSHSL tSLSH VIH tF tR VIH VOH VIL VIL VIL VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSHOVE tSCYC VOH VOH VOH VOL VOL VIH VIL VIH VIL tSHOVI tIVSLI tSLIXI SCK SOT SIN

Document Number: 002-05671 Rev.*B Page 60 of 86 MB9A130LB Series CSIO (SPI = 1, SCINV = 0) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V 2.7 V ≤ VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Min Max Baud rate - - - - 5 - 5 - 5 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns SIN → SCK ↓ setup time tIVSLI SCKx, SINx 75 - 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI SCKx, SINx 0 - 0 - 0 - ns SOT → SCK ↓ delay time tSOVLI SCKx, SOTx 2tCYCP – 30 - 2tCYCP - 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx, SOTx - 75 - 50 - 30*1 ns 40*2 SIN → SCK ↓ setup time tIVSLE SCKx, SINx 10 - 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx, SINx 20 - 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 - 5 ns *1 When PZR = 0. *2 When PZR = 1. Notes: The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF.

Document Number: 002-05671 Rev.*B Page 61 of 86 MB9A130LB Series Master mode Slave mode *: Changes when writing to TDR register tF tR tSLSH tSHSL tSHOVE VIL VIL VIH VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLE tSLIXE SCK SOT SIN tSOVLI tSCYC tSHOVI VOL VOL VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSLI tSLIXI SCK SOT SIN

Document Number: 002-05671 Rev.*B Page 62 of 86 MB9A130LB Series CSIO (SPI = 1, SCINV = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 2.7 V 2.7 V ≤ VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Min Max Baud rate - - - - 5 - 5 - 5 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - 4tCYCP - ns SCK ↓ → SOT delay time tSLOVI SCKx, SOTx -40 +40 -30 +30 -20 +20 ns SIN → SCK ↑ setup time tIVSHI SCKx, SINx 75 - 50 - 30 - ns SCK ↑ → SIN hold time tSHIXI SCKx, SINx 0 - 0 - 0 - ns SOT → SCK ↑ delay time tSOVHI SCKx, SOTx 2tCYCP - 30 - 2tCYCP – 30 - 2tCYCP - 30 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - tCYCP + 10 - ns SCK ↓ → SOT delay time tSLOVE SCKx, SOTx - 75 - 50 - 30*1 ns 40*2 SIN → SCK ↑ setup time tIVSHE SCKx, SINx 10 - 10 - 10 - ns SCK ↑ → SIN hold time tSHIXE SCKx, SINx 20 - 20 - 20 - ns SCK falling time tF SCKx - 5 - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 - 5 ns *1 When PZR = 0. *2 When PZR = 1. Notes: The above characteristics apply to clock synchronous mode. tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function serial is connected to, see Block Diagram in this data sheet. These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. When the external load capacitance CL = 50 pF.

Document Number: 002-05671 Rev.*B Page 63 of 86 MB9A130LB Series Master mode Slave mode UART external clock input (EXT = 1) (VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Max Serial clock L pulse width tSLSH CL = 50 pF tCYCP + 10 - ns Serial clock H pulse width tSHSL tCYCP + 10 - ns SCK falling time tF - 5 ns SCK rising time tR - 5 ns t SHSL V I L V I L V I L V IH V IH V IH tR tF t SLSH tSHSL tR tSLSH tF tSLOVE VIL VIL VIL VIH VIH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHE tSHIXE SCK SOT SIN tSCYC tSLOVI VOL VOH VOH VOH VOL VOH VOL VIH VIL VIH VIL tIVSHI tSHIXI tSOVHI SCK SOT SIN SCK

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12.4.10 External Input Timing

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Condition s Value Unit Remarks Min Max Input pulse width tINH, tINL ADTG - 2tCYCP*1 - ns A/D converter trigger input FRCKx Free-run timer input clock ICxx Input capture DTTIxX - 2tCYCP*1 - ns Waveform generator INTxx, NMIX *2 2tCYCP + 100*1 - ns External interrupt NMI *3 500 - ns WKUPx *4 500 - ns Deep Standby wake up *1: tCYCP indicates the APB bus clock cycle time. About the APB bus number which A/D converter, Multi-function Timer, External interrupt, Deep Standby mode Controller is connected to, see Block Diagram in this data sheet. *2: When in Run mode, in Sleep mode. *3: When in Timer mode, in RTC mode, in Stop mode. *4: When in Deep Standby RTC mode, in Deep Standby Stop mode.

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12.4.11 I2C Timing

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency fSCL CL = 50 pF, R = (VP/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCL clock L width tLOW 4.7 - 1.3 - μs SCL clock H width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between STOP condition and START condition tBUF 4.7 - 1.3 - μs Noise filter tSP - 2 tCYCP*4 - 2 tCYCP*4 - ns *1: R and CL represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively. VP indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal. *3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number which I2C is connected to, see Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. SDA SCL

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12.4.12 JTAG Timing

(VCC = 1.8V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max TMS,TDI setup time tJTAGS TCK, TMS,TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TMS,TDI hold time tJTAGH TCK, TMS,TDI VCC ≥ 4.5 V 15 - ns VCC < 4.5 V TDO delay time tJTAGD TCK, TDO VCC ≥ 4.5 V - 30 ns 2.7 V ≤ VCC < 4.5 V - 45 VCC < 2.7 V - 60 Note: When the external load capacitance CL = 50 pF. TCK TMS/TDI TDO

Document Number: 002-05671 Rev.*B Page 67 of 86 MB9A130LB Series 12.5 12-bit A/D Converter Electrical characteristics for the A/D converter (VCC = AVCC = 1.8V to 5.5V, VSS = AVSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity INL - - - ± 3.0 LSB AVCC ≥ 2.7 V - - ± 5.0 LSB AVCC < 2.7 V Differential Nonlinearity DNL - - - ± 1.9 LSB AVCC ≥ 2.7 V - - ± 2.9 LSB AVCC < 2.7 V Zero transition voltage VZT ANxx - - ± 20 mV Full-scale transition voltage VFST ANxx - - AVRH ± 20 mV Conversion time*1 - - 1.0 - - μs AVCC ≥ 2.7 V 4.0 AVCC < 2.7 V Sampling time*2 tS - 0.3 - 10 μs AVCC ≥ 2.7 V 1.2 AVCC < 2.7 V Compare clock cycle*3 tCCK - 50 - 1000 ns AVCC ≥ 2.7 V 200 AVCC < 2.7 V Period of operation enable state transitions tSTT - - - 1 μs Analog input capacity CAIN - - - 15 pF Analog input resistor RAIN - - - 0.9 kΩ AVCC ≥ 4.5 V 1.6 2.7 V ≤ AVCC < 4.5 V 4.0 AVCC < 2.7 V Interchannel disparity - - - - 4 LSB Analog port input leak current - ANxx - - 0.3 μA Analog input voltage - ANxx AVSS - AVRH V Reference voltage - AVR H 2.7 - AVCC V AVCC ≥ 2.7 V AVCC AVCC < 2.7 V *1: The conversion time is the value of sampling time (tS) + compare time (tC). The condition of the minimum conversion time is the following. AVCC ≥ 2.7 V, HCLK=20 MHz sampling time: 0.3 μs, compare time: 0.7 μs AVCC < 2.7 V, HCLK=20 MHz sampling time: 1.2 μs, compare time: 2.8 μs Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK). For setting*4 of the sampling time and compare clock cycle, see Chapter 1-1: A/D Converter in FM3 Family Peripheral Manual Analog Macro Part. The register settings of the A/D Converter are reflected in the operation according to the APB bus clock timing. For the number of the APB bus to which the A/D Converter is connected, see Block Diagram. The Base clock (HCLK) is used to generate the sampling time and the compare clock cycle. *2: A necessary sampling time changes by external impedance. Ensure to set the sampling time to satisfy (Equation 1). *3: The compare time (tC) is the value of (Equation 2).

Document Number: 002-05671 Rev.*B Page 68 of 86 MB9A130LB Series (Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9 tS: Sampling time RAIN: Input resistor of A/D = 0.9 kΩ at 4.5 V ≤ AVCC ≤ 5.5 V Input resistor of A/D = 1.6 kΩ at 2.7 V ≤ AVCC < 4.5 V Input resistor of A/D = 4.0 kΩ at 1.8 V ≤ AVCC < 2.7 V CAIN: Input capacity of A/D = 15 pF at 1.8 V ≤ AVCC ≤ 5.5 V REXT: Output impedance of external circuit (Equation 2) tC = tCCK × 14 tC: Compare time tCCK: Compare clock cycle Analog signal source ANxx Analog input pin Comparator Rext RAIN CAIN

Document Number: 002-05671 Rev.*B Page 69 of 86 MB9A130LB Series Definition of 12-bit A/D Converter Terms

• Resolution : Analog variation that is recognized by an A/D converter.
• Integral Nonlinearity : Deviation of the line between the zero-transition point (0b000000000000 ←→ 0b000000000001) and the full-scale transition point (0b111111111110 ←→ 0b111111111111) from the actual conversion characteristics.
• Differential Nonlinearity : Deviation from the ideal value of the input voltage that is required to change the output code by 1 LSB. Integral Nonlinearity of digital output N = VNT - {1LSB × (N - 1) + VZT} [LSB] 1LSB Differential Nonlinearity of digital output N = V(N + 1) T - VNT - 1 [LSB] 1LSB 1LSB = VFST - VZT 4094 N: A/D converter digital output value. VZT: Voltage at which the digital output changes from 0x000 to 0x001. VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF. VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN. Integral Nonlinearity Differential Nonlinearity Digital output Digital output Actual conversion characteristics Actual conversion characteristics Ideal characteristics (Actually- measured value) Actual conversion characteristics Actual conversion characteristics (Actually-measured value) (Actually-measured value) Ideal characteristics (Actually-measured value) Analog input Analog input (Actually-measured value) 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF AVSS AVRH AVSS AVRH 0x(N-2) 0x(N-1) 0x(N+1) 0xN {1 LSB(N-1) + VZT} VNT VFST VZT VNT V(N+1)T

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12.6 Low-Voltage Detection Characteristics

12.6.1 Low-Voltage Detection Reset

(TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDLR SVHR = 0001 1.43 1.53 1.63 V When voltage drops Released voltage VDHR 1.53 1.63 1.73 V When voltage rises Detected voltage VDLR SVHR = 0100 1.80 1.93 2.06 V When voltage drops Released voltage VDHR 1.90 2.03 2.16 V When voltage rises LVD stabilization wait time tLVDRW - - - 633 × tCYCP * μs Detection delay time tLVDRD dV/dt ≥ -4mV/µs - - 60 μs *: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-05671 Rev.*B Page 71 of 86 MB9A130LB Series

12.6.2 Interrupt of Low-voltage Detection

(TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDLI SVHI = 0000 1.87 2.00 2.13 V When voltage drops Released voltage VDHI 1.97 2.10 2.23 V When voltage rises Detected voltage VDLI SVHI = 0001 1.96 2.10 2.24 V When voltage drops Released voltage VDHI 2.06 2.20 2.34 V When voltage rises Detected voltage VDLI SVHI = 0010 2.05 2.20 2.35 V When voltage drops Released voltage VDHI 2.15 2.30 2.45 V When voltage rises Detected voltage VDLI SVHI = 0011 2.15 2.30 2.45 V When voltage drops Released voltage VDHI 2.25 2.40 2.55 V When voltage rises Detected voltage VDLI SVHI = 0100 2.24 2.40 2.56 V When voltage drops Released voltage VDHI 2.34 2.50 2.66 V When voltage rises Detected voltage VDLI SVHI = 0101 2.33 2.50 2.67 V When voltage drops Released voltage VDHI 2.43 2.60 2.77 V When voltage rises Detected voltage VDLI SVHI = 0110 2.43 2.60 2.77 V When voltage drops Released voltage VDHI 2.53 2.70 2.87 V When voltage rises Detected voltage VDLI SVHI = 0111 2.61 2.80 2.99 V When voltage drops Released voltage VDHI 2.71 2.90 3.09 V When voltage rises Detected voltage VDLI SVHI = 1000 2.80 3.00 3.20 V When voltage drops Released voltage VDHI 2.90 3.10 3.30 V When voltage rises Detected voltage VDLI SVHI = 1001 2.99 3.20 3.41 V When voltage drops Released voltage VDHI 3.09 3.30 3.51 V When voltage rises Detected voltage VDLI SVHI = 1010 3.36 3.60 3.84 V When voltage drops Released voltage VDHI 3.46 3.70 3.94 V When voltage rises Detected voltage VDLI SVHI = 1011 3.45 3.70 3.95 V When voltage drops Released voltage VDHI 3.55 3.80 4.05 V When voltage rises Detected voltage VDLI SVHI = 1100 3.73 4.00 4.27 V When voltage drops Released voltage VDHI 3.83 4.10 4.37 V When voltage rises Detected voltage VDLI SVHI = 1101 3.83 4.10 4.37 V When voltage drops Released voltage VDHI 3.93 4.20 4.47 V When voltage rises Detected voltage VDLI SVHI = 1110 3.92 4.20 4.48 V When voltage drops Released voltage VDHI 4.02 4.30 4.58 V When voltage rises LVD stabilization wait time tLVDIW - - - 633 × tCYCP* μs Detection delay time tLVDID dV/dt ≥ -4mV/µs - - 60 μs *: tCYCP indicates the APB2 bus clock cycle time.

Document Number: 002-05671 Rev.*B Page 72 of 86 MB9A130LB Series Low power mode (TA = - 40°C to + 85°C) Parameter Symbol Conditions Value Unit Remarks Min Typ Max Detected voltage VDLIL SVHI = 0000 1.80 2.00 2.20 V When voltage drops Released voltage VDHIL 1.90 2.10 2.30 V When voltage rises Detected voltage VDLIL SVHI = 0001 1.89 2.10 2.31 V When voltage drops Released voltage VDHIL 1.99 2.20 2.41 V When voltage rises Detected voltage VDLIL SVHI = 0010 1.98 2.20 2.42 V When voltage drops Released voltage VDHIL 2.08 2.30 2.52 V When voltage rises Detected voltage VDLIL SVHI = 0011 2.07 2.30 2.53 V When voltage drops Released voltage VDHIL 2.17 2.40 2.63 V When voltage rises Detected voltage VDLIL SVHI = 0100 2.16 2.40 2.64 V When voltage drops Released voltage VDHIL 2.26 2.50 2.74 V When voltage rises Detected voltage VDLIL SVHI = 0101 2.25 2.50 2.75 V When voltage drops Released voltage VDHIL 2.35 2.60 2.85 V When voltage rises Detected voltage VDLIL SVHI = 0110 2.34 2.60 2.86 V When voltage drops Released voltage VDHIL 2.44 2.70 2.96 V When voltage rises Detected voltage VDLIL SVHI = 0111 2.52 2.80 3.08 V When voltage drops Released voltage VDHIL 2.62 2.90 3.18 V When voltage rises Detected voltage VDLIL SVHI = 1000 2.70 3.00 3.30 V When voltage drops Released voltage VDHIL 2.80 3.10 3.40 V When voltage rises Detected voltage VDLIL SVHI = 1001 2.88 3.20 3.52 V When voltage drops Released voltage VDHIL 2.98 3.30 3.62 V When voltage rises Detected voltage VDLIL SVHI = 1010 3.24 3.60 3.96 V When voltage drops Released voltage VDHIL 3.34 3.70 4.06 V When voltage rises Detected voltage VDLIL SVHI = 1011 3.33 3.70 4.07 V When voltage drops Released voltage VDHIL 3.43 3.80 4.17 V When voltage rises Detected voltage VDLIL SVHI = 1100 3.60 4.00 4.40 V When voltage drops Released voltage VDHIL 3.70 4.10 4.50 V When voltage rises Detected voltage VDLIL SVHI = 1101 3.69 4.10 4.51 V When voltage drops Released voltage VDHIL 3.79 4.20 4.61 V When voltage rises Detected voltage VDLIL SVHI = 1110 3.78 4.20 4.62 V When voltage drops Released voltage VDHIL 3.88 4.30 4.72 V When voltage rises LVD stabilization wait time tLVDILW - - - 8039 × tCYCP * μs Detection delay time tLVDILD dV/dt ≥ -0.4mV/μs - - 800 μs *: tCYCP indicates the APB2 bus clock cycle time.

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12.7 Flash Memory Write/Erase Characteristics

12.7.1 Write / Erase time

(VCC = 2.0V to 5.5V, TA = - 40°C to + 85°C) Parameter Value Unit Remarks Typ* Max* Sector erase time Large Sector 1.6 7.5 s Includes write time prior to internal erase Small Sector 0.4 2.1 Half word (16-bit) write time 25 400 μs Not including system-level overhead time. Chip erase time 4 19.2 s Includes write time prior to internal erase *: The typical value is immediately after shipment, the maximum value is guarantee value under 100,000 cycle of erase/write.

12.7.2 Write cycles and data hold time

Erase/write cycles (cycle) Data hold time (year) Remarks 1,000 20* 10,000 10* 100,000 5* *: At average + 85C

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12.8 Return Time from Low-Power Consumption Mode

12.8.1 Return Factor: Interrupt/WKUP

The return time from Low-Power consumption mode is indicated as follows. It is from receiving the return factor to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tICNT tCYCC μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 40 80 μs Low-speed CR Timer mode 630 1260 μs Sub Timer mode 630 1260 μs RTC mode, Stop mode 1083 2100 μs Deep Standby RTC mode Deep Standby Stop mode 1099 2127 μs *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by external interrupt*) External interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: External interrupt is set to detecting fall edge.

Document Number: 002-05671 Rev.*B Page 75 of 86 MB9A130LB Series Operation example of return from Low-Power consumption mode (by internal resource interrupt*) Internal resource interrupt tICNT Interrupt factor accept CPU Operation Start Active Interrupt factor clear by CPU *: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode. Notes: The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual.

Document Number: 002-05671 Rev.*B Page 76 of 86 MB9A130LB Series

12.8.2 Return Factor: Reset

The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to starting the program operation. Return Count Time (VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Typ Max* Sleep mode tRCNT 359 647 μs High-speed CR Timer mode, Main Timer mode, PLL Timer mode 359 647 μs Low-speed CR Timer mode 929 1787 μs Sub Timer mode 929 1787 μs RTC/Stop mode 1099 2127 μs Deep Standby RTC mode Deep Standby Stop mode 1099 2127 μs *: The maximum value depends on the accuracy of built-in CR. Operation example of return from Low-Power consumption mode (by INITX) INITX tRCNT Internal reset CPU Operation Start Reset active Release

Document Number: 002-05671 Rev.*B Page 77 of 86 MB9A130LB Series Operation example of return from low power consumption mode (by internal resource reset*) Internal resource reset tRCNT Internal reset CPU Operation Start Reset active Release *: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode. Notes: The return factor is different in each Low-Power consumption modes. See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family Peripheral Manual. When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3 Family Peripheral Manual. The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on Reset Timing in 12.4 AC Characteristics in Electrical Characteristics for the detail on the time during the power-on reset/low-voltage detection reset. When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait time or the Main PLL clock stabilization wait time. The internal resource reset means the watchdog reset and the CSV reset.

Document Number: 002-05671 Rev.*B Page 78 of 86 MB9A130LB Series 13. Ordering Information Part number On-chip Flash memory On-chip MB9AF131KBPMC-G-SNE2 64 Kbyte 8 Kbyte Plastic  LQFP (0.5mm pitch), 48-pin (LQA048) Tray MB9AF132KBPMC-G-SNE2 128 Kbyte 8 Kbyte MB9AF131KBQN-G-AVE2 64 Kbyte 8 Kbyte Plastic  QFN (0.5mm pitch), 48-pin (VNA048) MB9AF132KBQN-G-AVE2 128 Kbyte 8 Kbyte MB9AF131LBPMC1-G-SNE2 64 Kbyte 8 Kbyte Plastic  LQFP (0.5mm pitch), 64-pin (LQD064) MB9AF132LBPMC1-G-SNE2 128 Kbyte 8 Kbyte MB9AF131LBPMC-G-SNE2 64 Kbyte 8 Kbyte Plastic  LQFP (0.65mm pitch), 64-pin (LQG064) MB9AF132LBPMC-G-SNE2 128 Kbyte 8 Kbyte MB9AF131LBQN-G-AVE2 64 Kbyte 8 Kbyte Plastic  QFN (0.5mm pitch), 64-pin (VNC064) MB9AF132LBQN-G-AVE2 128 Kbyte 8 Kbyte

Document Number: 002-05671 Rev.*B Page 79 of 86 MB9A130LB Series 14. Package Dimensions Package Type Package Code LQFP 48 (0.5mm pitch) LQA048 DIMENSIONS SYMBOL MIN. NOM. MAX. A 1.70 A1 0.00 0.20 b 0.15 0.27 c 0.09 0.20 D 9.00 BSC D1 7.00 BSC e 0.50 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70

9.00 BSC

7.00 BSC

D e 1 12 EE1 5 7

0.20 C A-B D

b

0.10 C A-B D

0.80 C A-B D

A SEATING PLANE A A10.25 b SECTION A-A' c L 0.80 C 4813 36 25 25 36 7.0X7.0X1.7 MM LQA048 REV PACKAGE OUTLINE, 48 LEAD LQFP 002-13731

Document Number: 002-05671 Rev.*B Page 80 of 86 MB9A130LB Series Package Type Package Code QFN 48 VNA048 DIMENSIONS NOM.MIN. b E

5.50 BSC

D A 0.00 SYMBOL MAX. 0.90 0.05 2. DIMENSIONING AND TOLERANCINC CONFORMS TO ASME Y14.5-1994. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP.IF THE TERMINAL HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL.THE DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUS AREA. 5. ND REFER TO THE NUMBER OF TERMINALS ON D OR E SIDE. 6. MAX. PACKAGE WARPAGE IS 0.05mm. 1. ALL DIMENSIONS ARE IN MILLIMETERS.

0.50 BSC

L 0.20 0.25 0.30 E 2 5.50 BSC e R 0.20 REF 7. MAXIMUM ALLOWABLE BURRS IS 0.076mm IN ALL DIRECTIONS. 8. PIN #1 ID ON TOP WILL BE LOCATED WITHIN INDICATED ZONE. 9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSEDHEAT SINK SLUG AS WELL AS THE TERMINALS. 0.400.35 0.45 NOTE 10. JEDEC SPEC IFICATIONNO . REF : N/A SIDE VIEW BOTTOM VIEW TOP VIEW D A E B 0.10 C 0.10 C 0.10 CA 0.05 C C SEATING PLANE

0.10 C A B

e b 0.10 C A B 0.05 C R (ND-1) e INDEX MARK L 9 12 3625 PACKAGE OUTLINE, 48 LEAD QFN 002-15528 **

Document Number: 002-05671 Rev.*B Page 81 of 86 MB9A130LB Series Package Type Package Code LQFP 64 (0.5mm pitch) LQD064 DIMENSIONS SYMBOL MIN. NOM. MAX. 07.1A A1 0.00 0.20 b 0.15 0.2 c 0.09 0.20 D 12.00 BSC. D1 10.00 BSC. e 0.50 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70 12.00 BSC. 10.00 BSC. D e 1 16 5 7 E b

0.08 C A-B D

A A10.25 b SECTION A-A' L1 L A SEATING PLANE 0.08 C SIDE VIEW TOP VIEW BOTTOM VIEW 3348 116 33 48 PACKAGE OUTLINE, 64 LEAD LQFP 10.0X10.0X1.7 MM LQD064 Rev 002-11499

Document Number: 002-05671 Rev.*B Page 82 of 86 MB9A130LB Series Package Type Package Code LQFP 64 (0.65mm pitch) LQG064 DIMENSION SYMBOL MIN. NOM. MAX. A 1.70 A1 0.00 0.20 b 0.27 0.32 0.37 c 0.09 0.20 D 14.00 BSC D1 12.00 BSC e 0.65 BSC E L 0.45 0.60 0.75 L1 0.30 0.50 0.70

14.00 BSC

12.00 BSC

D e 1 16 EE1 5 7 b

0.13 C A-B D 8

0.10 C A SEATI NG PLA NE b SECTION A -A' c A A10.25 10L1 L SIDE VIEW TOP VIEW BOTTOM VIEW 3348 116 8433 12.0X12.0X1.7 MM LQG064 REV PACKAGE OUTLINE, 64 LEAD LQFP 002-13881

Document Number: 002-05671 Rev.*B Page 83 of 86 MB9A130LB Series Package Type Package Code QFN 64 VNC064 DIMENSIONS NOM.MIN. b E

6.00 BSC

D A 0.00 SYMBOL MAX. 0.90 0.05 L 0.35 0.450.40 0.20 0.25 0.30 E 2 6.00 BSC e N 64

0.20 REFR

BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE. MAXIMUM ALLOWABLE BURR IS 0.076mm IN ALL DIRECTIONS. DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED N IS THE TOTAL NUMBER OF TERMINALS. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. NOTES: MAX. PACKAGE WARPAGE IS 0.05mm. HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA. ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE OR E SIDE. SINK SLUG AS WELL AS THE TERMINALS. BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL SIDE VIEW BOTTOM VIEWTOP VIEW D A E B 0.10 C 0.10 C 0.10 CA 0.05 C C SEATINGPLANE 0.05 C (ND-1) e INDEXMARK L 8433 PACKAGE OUTLINE, 64 LEAD QFN 002-13234 **

Document Number: 002-05671 Rev.*B Page 84 of 86 MB9A130LB Series 15. Major Changes Spansion Publication Number: DS706-00066 Page Section Change Results Revision 1.0 - - Initial release Revision 2.0

2 Features

• On-chip Memories Changed the description of on-chip SRAM

33 Handling Devices Added "· Stabilizing power supply voltage"

33 Handling Devices

Crystal oscillator circuit Added the following description "Evaluate oscillation of your using crystal oscillator by your mount board."

37 Memory Map

Memory map(2) Added the summary of Flash memory sector 47 - 49

Electrical Characteristics

1. DC Characteristics (1) Current rating

• Changed the table format
• Added Timer mode current
• Added Flash Memory Current
• Moved A/D Converter Current

1. AC Characteristics (4-1) Operating Conditions of Main PLL (4-2) Operating Conditions of Main PLL

• Added the figure of Main PLL connection

1. AC Characteristics (6) Power-on Reset Timing

• Changed the figure of timing
• Changed from Reset release delay time(tOND) to Time until releasing Power-on reset(tPRT) 56 - 63

1. AC Characteristics (8) CSIO/UART Timing

• Modified from UART Timing to CSIO/UART Timing
• Changed from Internal shift clock operation to Master mode
• Changed from External shift clock operation to Slave mode 5. 12bit A/D Converter
• Added the typical value of Integral Nonlinearity, Differential Nonlinearity, Zero transition voltage and Full-scale transition voltage
• Added Conversion time at AVCC < 2.7 V

1. Low-voltage Detection Characteristics Deleted the figure
2. Flash Memory Write/Erase Characteristics Change to the erase time of include write time prior to internal erase 74 - 77
3. Return Time from Low-Power Consumption Mode Added Return Time from Low-Power Consumption Mode NOTE: Please see “Document History” about later revised information.

Document Number: 002-05671 Rev.*B Page 85 of 86 MB9A130LB Series Document History Document Title: MB9A130LB Series 32-bit ARM® Cortex®-M3 FM3 Microcontroller Document Number: 002-05671 Revision ECN Orig. of Change Submission Date Description of Change ** - AKIH 06/09/2015 Migrated to Cypress and assigned document number 002-05671. No change to document contents or format. *A 5162460 AKIH 03/10/2016 Updated to Cypress format. *B 5742425 YSKA 05/23/2017 Adapted new Cypress logo Modified RTC description in “Features, Real-Time Clock(RTC)”. Changed starting count value from 01 to 00. Deleted “second, or day of the week” in the Interrupt function. Changed package code as the following in chapter : 2. Packages 3. Pin Assignment 13. Ordering Information 14. Package Dimensions. FPT-48P-M49 -> LQA048, LCC-48P-M73 -> VNA048 FTP-64P-M38 -> LQD064, FPT-64P-M39 -> LQG064, LCC-64P-M24 -> VNC064 Corrected “J-TAG" to “JTAG" in 4. List of Pin Functions. Added Note for JTAG pin in 4. List of Pin Functions. Added the Baud rate spec in 12.4.9 CSIO/UART Timing.

Document Number: 002-05671 Rev.*B May 23, 2017 Page 86 of 86 MB9A130LB Series Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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