MB88152A

MB88152A CYPRESS | Alldatasheet

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The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix “CY”. How to Check the Ordering Part Number 1. Go to www.cypress.com/pcn. 2. Enter the keyword (for example, ordering part number) in the SEARCH PCNS field and click Apply. 3. Click the corresponding title from the search results. 4. Download the Affected Parts List file, which has details of all changes For More Information Please contact your local sales office for additional information about Cypress products and solutions. About Cypress Cypress is the leader in advanced embedded system solutions for the world's most innovative automotive, industrial, smart home appliances, consumer electronics and medical products. Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and development resources on the planet enabling them to disrup t markets by creating new product categories in record time. To learn more, go to www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 002-08308 Rev. *B Revised Monday, December 25, 2017 MB88152A Spread Spectrum Clock Generator MB88152A is a clock generator for EMI (Electro Magnetic Interference) reduction. The peak of unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate periodically with the internal mod- ulator. It corresponds to both of the center spread which modulates input frequency as Middle Centered and down spread which modulates so as not to exceed input frequency.

Features

■ Input frequency : 16.6 MHz to 134 MHz ■ Output frequency : 16.6 MHz to 134 MHz ■ Modulation rate : ± 0.5%, ± 1.5% (Center spread), − 1.0%, − 3.0% (Down spread) ■ Equipped with oscillation circuit: Range of oscillation 16.6 MHz to 48 MHz ■ Modulation clock output Duty : 40% to 60% ■ Modulation clock Cycle-Cycle Jitter : Less than 100 ps ■ Low current consumption by CMOS process : 5.0 mA (24 MHz : Typ-sample, no load) ■ Power supply voltage : 3.3 V ± 0.3 V ■ Operating temperature : − 40° to +85 °C ■ Package : SOP 8-pin

Document Number: 002-08308 Rev. *B Page 3 of 24 MB88152A 1. Product Line-up MB88152A has three kinds of input frequency, and two kinds of modulation type (center/down spread), total six line-ups. 2. Pin Assignment 3. Pin Description Product Input/Output Frequency Modulation Type Modulation Enable Pin MB88152A-100 16.6 MHz to 134 MHz Down spread No MB88152A-101 16.6 MHz to 67 MHz Yes MB88152A-111 16.6 MHz to 67 MHz Center spread Yes MB88152A-112 40 MHz to 134 MHz Pin Name I/O Pin No. Description XIN I 1 Crystal resonator conn ection pin/clock input pin XOUT O 2 Crystal resonator connection pin V SS − 3G N D p i n SEL I 4 Modulation rate setting pin CKOUT O 5 Modulated clock output pin VDD − 6 Power supply voltage pin FREQ/FREQ0 I 7 Frequency setting pin XENS/FREQ1 I 8 Modulation enable setting pin/frequency setting pin XIN XOUT V SS SEL XENS FREQ V DD CKOUT XIN XOUT V SS SEL FREQ1 FREQ0 V DD CKOUT MB88152A-101 MB88152A-111 MB88152A-112 MB88152A-100 SOB008 SOB008 TOP VIEW

Document Number: 002-08308 Rev. *B Page 4 of 24 MB88152A 4. I/O Circuit Type Note: For XIN and XOUT pins, refer to “Oscillation Circuit”. Pin Circuit Type Remarks SEL FREQ FREQ0 FREQ1 XENS CMOS hysteresis input CKOUT ■ CMOS output ■ IOL = 4 mA

Document Number: 002-08308 Rev. *B Page 5 of 24 MB88152A 5. Handling Devices Preventing Latch-up A latch-up can occur if, on this device, (a) a voltage higher than VDD or a voltage lower than VSS is applied to an input or output pin or (b) a voltage higher than the rating is applied between VDD and VSS pins. The latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use this device, be very careful not to exceed the max- imum rating. Handling Unused Pins ■ Do not leave an unused input pin open, since it may cause a malfunction. Handle by, using a pull-up or pull-down resistor. ■ Unused output pin should be opened. The Attention when the External Clock is Used ■ Input the clock to XIN pin, and XOUT pin should be opened when you use the external clock. ■ Please pay attention so that an overshoot and an undershoot do not occur to an input clock of XIN pin. Power Supply Pins ■ Please design connecting the power supply pin of this device by as low impedance as possible from the current supply source. ■ We recommend connecting electrolytic capacitor (about 10 μF) and the ceramic capacitor (about 0.01 μF) in parallel between VSS and VDD pins near the device, as a bypass capacitor. Oscillation Circuit ■ Noise near the XIN and XOUT pins may cause the device to malfunction. Design printed circuit boards so that electric wiring of XIN or XOUT pin and resonator (or ceramic oscillator) do not intersect other wiring. ■ Design the printed circuit board that surrounds the XIN and XOUT pins with ground.

Document Number: 002-08308 Rev. *B Page 6 of 24 MB88152A 6. Block Diagram VDD CKOUT VSS Rf = 1 MΩ SEL XOUT XIN FREQ/FREQ0 XENS/FREQ1 M N L IDAC ICO PLL block Modulation rate setting Frequency setting Modulation enable / Frequency setting Reference clock Clock output Reference clock Phase compare V/I conversion Modulation clock outputLoop filter Modulation logic MB88152A PLL block Modulation rate setting/ Modulation enable setting Charge pump A glitchless IDAC (current output D/A converter) provides precise modulation, thereby dramatically reducing EMI.

Document Number: 002-08308 Rev. *B Page 7 of 24 MB88152A 7. Pin Setting When changing the pin setting, the stabilization wait time for the modulation clock is required. The stabilization wait time for the mod- ulation clock takes the maximum value of Lock-Up time in “AC Characteristics of Electrical Characteristics”.

7.1 Modulation Enable Setting

Note: MB88152A-100 and MB88152A-110 do not have XENS pin.

7.2 SEL Modulation Rate Setting

Note: The modulation rate can be changed at the level of the terminal.

7.3 Frequency Setting

Note: MB88152A-100 and MB88152A-110 do not have FREQ pin. Note: MB88152A-101, MB88152A-111 and MB88152A-112 have neither FREQ0 pin nor FREQ1 pin. XENS Modulation L Modulation MB88152A-101, MB88152A-111, MB88152A-112H No modulation SEL Modulation Rate Remarks L ± 0.5% MB88152A-111, MB88152A-112 Center spread − 1.0% MB88152A-100, MB88152A-101 Down spread H ± 1.5% MB88152A-111, MB88152A-112 Center spread − 3.0% MB88152A-100, MB88152A-101 Down spread FREQ Frequency L 16.6 MHz to 40 MHz MB88152A-101, MB88152A-111

40 MHz to 80 MHz MB88152A-112

H 33 MHz to 67 MHz MB88152A-101, MB88152A-111

66 MHz to 134 MHz MB88152A-112

L L 16.6 MHz to 40 MHz MB88152A-100 L H 33 MHz to 67 MHz H L 40 MHz to 80 MHz H H 66 MHz to 134 MHz

Document Number: 002-08308 Rev. *B Page 8 of 24 MB88152A

7.3.1 Center Spread

Spectrum is spread (modulated) by centering on the input frequency.

7.3.2 Down Spread

Spectrum is spread (modulated) below the input frequency. −3.0% Radiation level 3.0% modulation width Frequency Input frequency Center spread example of ± 1.5% Modulation rate −3.0% Radiation level Input frequency Frequency Down spread example of − 3.0% Modulation rate 3.0% modulation width

Document Number: 002-08308 Rev. *B Page 9 of 24 MB88152A 8. Absolute Maximum Ratings WARNING: Semiconductor devices can be permanently da maged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Parameter Symbol Rating Unit Min Max Power supply voltagea a. The parameter is based on V SS = 0.0 V. VDD − 0.5 + 4.0 V Input voltagea VI VSS − 0.5 V DD + 0.5 V Output voltagea VO VSS − 0.5 V DD + 0.5 V Storage temperature T ST − 55 + 125 °C Operation junction temperature T J − 40 + 125 °C Output current I O − 14 + 14 mA Overshoot V IOVER − VDD + 1.0 (tOVER ≤ 50 ns) V Undershoot V IUNDER VSS − 1.0 (tUNDER ≤ 50 ns) − V Overshoot/Undershoot tOVER ≤ 50 ns VIUNDER ≤ VSS − 1.0 V VDD VSSInput pin VIOVER ≤ VDD + 1.0 V tUNDER ≤ 50 ns

Document Number: 002-08308 Rev. *B Page 10 of 24 MB88152A 9. Recommended Operating Conditions (VSS = 0.0 V) WARNING: The recommended operating conditions are r equired in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Parameter Symbol Pin Conditions Value Unit Min Typ Max Power supply voltage V DD VDD − 3.0 3.3 3.6 V “H” level input voltage V IH SEL, FREQ/FREQ0, XENS/FREQ1 − VDD x 0.8 − VDD + 0.3 V XIN 16.6 MHz to 100 MHz V DD x 0.8 − VDD + 0.3 V 100 MHz to 134 MHz V DD x 0.9 − VDD + 0.3 V “L” level input voltage V IL SEL, FREQ/FREQ0, XENS/FREQ1 − VSS − VDD x 0.2 V XIN 16.6 MHz to 100 MHz V SS − VDD x 0.2 V 100 MHz to 134 MHz V SS − VDD x 0.1 V Input clock duty cycle tDCI XIN 16.6 MHz to 100 MHz 40 50 60 %

100 MHz to 134 MHz 45 50 55

40 MHz to 100 MHz

0.0475 x fin − 1.75 −− V/ns Input frequency

100 MHz to 134 MHz

3 −− Operating temperature Input clock duty cycle (tDCI = tb/ta) XIN ta tb 1.5 V

Document Number: 002-08308 Rev. *B Page 11 of 24 MB88152A trin tfin XIN Note: SRIN = (VDD x 0.80 - VDD x 0.20) /trin, SRIN = (VDD x 0.80 - VDD x 0.20) /tfin VDD x 0.80 VDD x 0.20 Input clock slew rate (SRIN)

Document Number: 002-08308 Rev. *B Page 12 of 24 MB88152A 10. Electrical Characteristics

10.1 DC Characteristics

(Ta = −40°C to + 85°C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Parameter Symbol Pin Conditions Value Unit Min Typ Max Power supply current I CC VDD 24 MHz output No load capacitance − 5.0 7.0 mA Output voltage V OH CKOUT “H” level output IOH = − 4 mA VDD − 0.5 − VDD V VOL “L” level output IOL = 4 mA VSS − 0.4 V Output impedance Z O CKOUT 16.6 MHz to 134 MHz − 45 −Ω Input capacitance C IN XIN, SEL, FREQ/ FREQ0, XENS/ FREQ1 Ta = + 25 °C VDD = VI = 0.0 V f = 1 MHz −− 16 pF Load capacitance C L CKOUT 16.6 MHz to 67 MHz −− 15 pF

67 MHz to 100 MHz −− 10

100 MHz to 134 MHz −− 7

Document Number: 002-08308 Rev. *B Page 13 of 24 MB88152A

10.2 AC Characteristics

(Ta = −40°C to + 85°C, VDD = 3.3 V ± 0.3 V, VSS = 0.0 V) Parameter Symbol Pin Conditions Value Unit Min Typ Max Oscillation frequency f x XIN, XOUT Fundamental oscillation 16.6 − 40 MHz 3rd over tone 40 − 48 Input frequency f in XIN MB88152A-100 16.6 − 134 MHz MB88152A-101/111 16.6 − 67 MB88152A-112 40 − 134 Output frequency f OUT CKOUT MB88152A-100 16.6 − 134 MHz MB88152A-101/111 16.6 − 67 MB88152A-112 40 − 134 Output slew rate SR CKOUT 0.4 V to 2.4 V Load capacitance 15 pF 0.4 − 4.0 V/ns Output clock duty cycle t DCC CKOUT 1.5 V 40 − 60 % Modulation frequency (Number of input clocks per modulation) fMOD (nMOD) CKOUT MB88152A-100 FREQ[1 : 0] = (00) fin/2640 (2640) fin/2280 (2280) fin/1920 (1920) kHz (clks) MB88152A-100 FREQ[1 : 0] = (01) fin/4400 (4400) fin/3800 (3800) fin/3200 (3200) MB88152A-100 FREQ[1 : 0] = (10) fin/5280 (5280) fin/4560 (4560) fin/3840 (3840) MB88152A-100 FREQ[1 : 0] = (11) fin/8800 (8800) fin/7600 (7600) fin/6400 (6400) MB88152A-101/111 FREQ = 0 fin/2640 (2640) fin/2280 (2280) fin/1920 (1920) MB88152A-101/111 FREQ = 1 fin/4400 (4400) fin/3800 (3800) fin/3200 (3200) MB88152A-112 FREQ = 0 fin/5280 (5280) fin/4560 (4560) fin/3840 (3840) MB88152A-112 FREQ = 1 fin/8800 (8800) fin/7600 (7600) fin/6400 (6400) Lock-Up time t LK CKOUT 16.6 MHz to 80 MHz − 25 m s

80 MHz to 134 MHz − 38

Cycle-cycle jitter t JC CKOUT No load capacitance, Ta = + 25 °C, VDD = 3.3 V −− 100 ps-rms

Document Number: 002-08308 Rev. *B Page 14 of 24 MB88152A <Definition of modulation frequency and number of input clocks per modulation> ■ MB88152A contains the modulation period to realize the efficient EMI reduction. ■ The modulation period fMOD depends on the input frequency and changes between fMOD (Min) and fMOD (Max) . ■ Furthermore, the average value of fMOD equals the typical value of the electrical characteristics. t fMOD (Min) f MOD (Max) t Modulation wave form Clock count nMOD (Max) fout (Output frequency) Clock count nMOD (Min)

Document Number: 002-08308 Rev. *B Page 15 of 24 MB88152A 11. Output Clock Duty Cycle (tDCC = tb/ta) 12. Input Frequency (fin = 1/tin) 13. Output Slew Rate (SR) 14. Cycle-cycle Jitter (tJC = | tn − tn + 1 |) CKOUT 1.5 V ta tb

0.8 VDD

2.4 V 0.4 V tftr CKOUT Note: SR = (2.4−0.4) /tr, SR = (2.4−0.4) /tf tn+1tn CKOUT Note: Cycle-cycle jitter is defined the difference between a certain cycle and immediately after (or, immediately before) .

Document Number: 002-08308 Rev. *B Page 16 of 24 MB88152A 15. Modulation Waveform fMOD − 1.0 % − 0.5 % fMOD − 1.5 % + 1.5 % ±1.5% modulation rate, Example of center spread −1.0% modulation rate, Example of down spread CKOUT output frequency CKOUT output frequency Frequency at modulation OFF Frequency at modulation OFF Time Time

Document Number: 002-08308 Rev. *B Page 17 of 24 MB88152A 16. Lock-up Time If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time “tLK”). For the input clock stabilization time, check the characteristics of the resonator or oscillator used. For modulation enable control using the XENS pin during normal operation, the set clock signal is output from CKOUT pin at most the lock-up time (tLK) after the level at the XENS pin is determined. Note: When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal becomes stable, the output frequency, output clock duty cycle, modulation period, and cycle-cycle jitter cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time.

3.0 VVDD

(lock-up time ) VIH VIL XIN XENS CKOUT tLK (lock-up time ) tLK (lock-up time )

Document Number: 002-08308 Rev. *B Page 18 of 24 MB88152A 17. Oscillation Circuit The left side of figures below shows the connection example about general resonator. The oscillation circuit has the built-in feedback resistance (Rf). The value of capacity (C1 and C2) is required adjusting to the most suitable value of an individual resonator. The right side of figures below shows the example of connecting for the 3rd over-tone resonator. The value of capacity (C1, C2 and C3) and inductance (L1) is needed adjusting to the most suitable value of an individual resonator. The most suitable value is different by individual resonator. Please refer to the resonator manufacturer which you use for the most suitable value. When an external clock is used (the resonator is not used), input the clock to XIN pin and do not connect anything with XOUT pin. XIN Pin When using an external clock Note: A jitter characteristic of an input clock may cause an affect to a cycle-cycle jitter characteristic. When using the resonator Rf (1 MΩ) C2 C1 Rf (1 MΩ) XOUT Pin MB88152A Internal MB88152A External Fundamental resonator 3rd over tone resonator XOUT PinXIN Pin OPEN Rf (1 MΩ) MB88152A LSI Internal External clock MB88152A LSI External XIN Pin XOUT PinXIN Pin

Document Number: 002-08308 Rev. *B Page 19 of 24 MB88152A 18. Interconnection Circuit Example MB88152A C

1 C2 C4 C3

C1, C2 : Oscillation stabilization capacitance (refer to "Oscillation Circuit”.) C3 : Capacitor of 10 μF or higher C4 : Capacitor about 0.01 μF (connect a capacitor of good high frequency property (ex. laminated ceramic capacitor) to close to this device.) R1 : Impedance matching resistor for board pattern SEL FREQ/FREQ0 XENS/FREQ1

Document Number: 002-08308 Rev. *B Page 20 of 24 MB88152A 19. Example Characteristics The condition of the examples of the characteristics is shown as follows : Input frequency = 20 MHz (Output frequency = 20 MHz : Use for MB88152A-111) Power-supply voltage = 3.3 V, None load capacity, Modulation rate = ±1.5% (center spread) . Spectrum analyzer HP4396B is connected with CKOUT. The result of the measurement with, RBW = 1 kHz (ATT use for −6 dB) . CH B Spectrum 10 dB /REF 0 dBm Avg RBW# 1 kHZ VBW 1 kHZ ATT 6 dB CENTER 20 MHZ SWP 2.505 s SPAN 4 MH Z No modulation −7.44 dBm ±1.5% modulation −25.75 dBm

Document Number: 002-08308 Rev. *B Page 21 of 24 MB88152A 20. Ordering Information Part Number Input/Output Frequency Modulation Type Modulation Enable pin Package Remarks MB88152APNF-G-100-JNE1 16.6 MHz to 134 MHz Down spread No 8-pin plastic SOP (SOB008) MB88152APNF-G-101-JNE1 16.6 MHz to 67 MHz Down spread Yes MB88152APNF-G-111-JNE1 16.6 MHz to 67 MHz Center spread Yes MB88152APNF-G-112-JNE1 40 MHz to 134 MHz Center spread Yes MB88152APNF-G-100-JNEFE1 16.6 MHz to 134 MHz Down spread No 8-pin plastic SOP (SOB008) Emboss taping (EF type) MB88152APNF-G-101-JNEFE1 16.6 MHz to 67 MHz Down spread Yes MB88152APNF-G-111-JNEFE1 16.6 MHz to 67 MHz Center spread Yes MB88152APNF-G-112-JNEFE1 40 MHz to 134 MHz Center spread Yes MB88152APNF-G-100-JNERE1 16.6 MHz to 134 MHz Down spread No 8-pin plastic SOP (SOB008) Emboss taping (ER type) MB88152APNF-G-101-JNERE1 16.6 MHz to 67 MHz Down spread Yes MB88152APNF-G-111-JNERE1 16.6 MHz to 67 MHz Center spread Yes MB88152APNF-G-112-JNERE1 40 MHz to 134 MHz Center spread Yes

Document Number: 002-08308 Rev. *B Page 22 of 24 MB88152A 21. Package Dimension $7 '$780 + 127(6 L 1 1.05 REF L c 0.45 0.15 0.60 0.75 0.25 NOM.MIN. 6.00 BSC. E D A 1.30 5.05 BSC. 1.40 0.05 SYMBOL MAX. 1.50 1.75 0.25 ș E1 3.90 BSC b 0.36 0.44 0.52 e 1.27 BSC. DIMENSIONS L 2 0.25 BSC h 0.40 BSC. 11. JEDEC SPECIFICATION NO. REF : N/A D E1 E

0.20 C A-B D

e 0.10 C SEATING PLANE b 0.13 C A-B D SIDE VIEW TOP VIEW b SECTION A-A' c L GAUGE PLANE DETAIL A L2ș A

0.25 H D;

0.25 H D

㻭 㻰 㻯 INDEX AREA h 45° SIDE VIEW BOTTOM VIEW 㻮 002-15856 Rev.**

Document Number: 002-08308 Rev. *B Page 23 of 24 MB88152A Document History Document Title: MB88152A Spread Spectrum Clock Generator Document Number: 002-08308 Revision ECN Orig. of Change Submission Date Description of Change ** – TAOA 06/29/2009 Initial release. *A 5560671 TAOA 12/28/2016 Migrated Spansion datasheet “DS04-29125-3E” into Cypress Template. *B 6003426 TAOA 12/25/2017 Deleated EOL part number: MB88152A-102/110 Updated Package Dimensions: Updated to Cypress format Changed the package name from FPT-8P-M02 to SOB008

Document Number: 002-08308 Rev. *B Revi sed December 25, 2017 Page 24 of 24 © Cypress Semiconductor Corporation, 2006-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Softwa re provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypr ess reserves the right to make changes to this document without further notice. Cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whol e or in part, and you s hall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unin tended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. MB88152A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Arm® Cortex® Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless PSoC® Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support