MACH220-10JC

MACH220-10 AMD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 33

Technical content

Publication# 14130 Rev. I Amendment /0 Issue Date: May 1995 Advanced Micro Devices MACH220-10/12/15/20 High-Density EE CMOS Programmable Logic FINAL COM’L: -10/12/15/20 IND: -14/18/24 DISTINCTIVE CHARACTERISTICS

68 Pins

96 Macrocells

100 MHz fCNT

56 Inputs with pull-up resistors

48 Outputs

96 Flip-flops; 4 clock choices

8 “PAL26V12” blocks with buried macrocells Pin-compatible with MACH120 and MACH221 GENERAL DESCRIPTION The MACH220 is a member of AMD’s high-performance EE CMOS MACH 2 device family. This device has approximately nine times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH220 consists of eight PAL blocks intercon- nected by a programmable switch matrix. The eight PAL blocks are essentially “PAL26V12” structures complete with product-term arrays, and programmable macro- cells, including buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH220 has two kinds of macrocell: output and buried. The output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH220 has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers for use in synchronizing signals and reducing setup time requirements. BLOCK DIAGRAM If you would like to view Block Diagram in full size, please click on the box.

I/O42 – I/O47I/O36 – I/O41I/O30 – I/O35I/O24 – I/O29 I/O18– I/O23 I/O6 – I/O11 I/O Cells Macrocells Macrocells I/O Cells Macrocells Macrocells I/O Cells Macrocells Macrocells 52 x 52 AND Logic Array and Logic Allocator CLK0/I0, CLK1/I1 CLK2/I4 , CLK3/I5 I2 – I3, I6 – I7 I/O0 – I/O5 Macrocells Macrocells 6 6 6 I/O Cells Macrocells Macrocells 6 6 6 I/O Cells Macrocells Macrocells 6 6 6 I/O Cells I/O Cells Macrocells Macrocells Switch Matrix Macrocells Macrocells 6 6 6 I/O Cells 6 666 6 66 I/O12 – I/O17 26262626 52 x 52 AND Logic Array and Logic Allocator OEOE OE OE OEOE OE OE 14130I-1

CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage I/O7 I/O8 I/O9 I/O10 I/O12 I/O14 I/O15 I/O17 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 GND I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 GND I/O30 I/O6 I/O I/O4 I/O3 I/O2 I/O0 GND VCC I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 GND I/O1 GND 9 8 7 6 5 4 3 2 1 6 86 76 66 56 46 36 26 1 CLK 0/I0 GND I/O13 I/O16 I/O41 I/O40 I/O39 I/O38 I/O36 GND VCC CLK 3/I5 CLK 2/I4 I/O35 I/O34 I/O33 I/O32 I/O3144 CLK 1/I1 VCC I/O11 I/O37 14130D-001A14130I-2 Note: Pin-compatible with MACH120 and MACH221.

4 MACH220-10/12/15/20 (Com’l)

ORDERING INFORMATION

AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: OPERATING CONDITIONS C = Commercial (0°C to +70°C) FAMILY TYPE MACH = Macro Array CMOS High-Speed SPEED -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD MACH220-10 MACH220-12 MACH220-15 MACH220-20 MACH -10 J C Valid Combinations OPTIONAL PROCESSING Blank = Standard Processing 220 DEVICE NUMBER 220 = 96 Macrocells, 68 Pins PACKAGE TYPE J = 68-Pin Plastic Leaded Chip Carrier (PL 068) JC Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.

5MACH220-14/18/24 (Ind) The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AMD programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: OPERATING CONDITIONS I = Industrial (–40°C to +85°C) FAMILY TYPE MACH = Macro Array CMOS High-Speed SPEED -14 = 14.5 ns tPD -18 = 18 ns tPD -24 = 24 ns tPD MACH220-14 MACH220-18 MACH220-24 MACH -14 J I Valid Combinations OPTIONAL PROCESSING Blank = Standard Processing 220 DEVICE NUMBER 220 = 96 Macrocells, 68 Pins PACKAGE TYPE J = 68-Pin Plastic Leaded Chip Carrier (PL 068) JI

6 MACH220-10/12/15/20

also be used as dedicated inputs. All inputs and I/O pins have built-in pull-up resistors. ent “PAL26V12” with 6 buried macrocells. and an asynchronous preset product term are provided. within the PAL block are initialized together. when fitting a design into the device. Figure 1 for cluster and macrocell numbers. Table 1. Logic Allocation T-type, allowing for product-term optimization. clock/gate pins, which are also available as data inputs. nous reset and preset product terms. available are common to all I/O cells in a PAL block. output for use in driving a bus.

Figure 1. MACH220 PAL Block

MACH220-10 (Com’l)8 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (TA) Operating Supply Voltage (VCC ) with Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 16 mA, VCC = Min 0.5 V VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 2) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –100 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –130 mA ICC Supply Current (Typical) V CC = 5 V, TA = 25°C, f = 25 MHz 205 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH ). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. (Note 4)

MACH220-10 (Com’l) 9 CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output 10 ns D-type 6.5 ns T-type 7.5 ns t H Register Data Hold Time 0 ns tCO Clock to Output 6.0 ns tWL Clock LOW 4 ns tWH Width HIGH 4 ns D-type 80 MHz T-type 74 MHz fMAX D-type 100 MHz T-type 91 MHz

125 MHz

tSL Setup Time from Input, I/O, or Feedback to Gate 7 ns tHL Latch Data Hold Time 0 ns tGO Gate to Output 7.5 ns tGWL Gate Width LOW 4 ns tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 14 ns tSIR Input Register Setup Time 2 ns tHIR Input Register Hold Time 2 ns tICO Input Register Clock to Combinatorial Output 15 ns tICS Input Register Clock to Output Register Setup D-type 11 ns T-type 12 ns tWICL Input Register LOW 4 ns tWICH Clock Width HIGH 4 ns fMAXIR Maximum Input Register Frequency 125 MHz tSIL Input Latch Setup Time 2 ns tHIL Input Latch Hold Time 2 ns tIGO Input Latch Gate to Combinatorial Output 17 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 18 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 10 ns tIGS Input Latch Gate to Output Latch Setup 11 ns Maximum Frequency (Note 1) Setup Time from Input, I/O, or Feedback to Clock External Feedback Internal Feedback (fCNT ) -10 tS No Feedback

MACH220-10 (Com’l)10 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description Min Max Unit tWIGL Input Latch Gate Width LOW 4 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 16 ns tAR Asynchronous Reset to Registered or Latched Output 15 ns tARW Asynchronous Reset Width (Note 1) 10 ns tARR Asynchronous Reset Recovery Time (Note 1) 8 ns tAP Asynchronous Preset to Registered or Latched Output 15 ns tAPW Asynchronous Preset Width (Note 1) 10 ns tAPR Asynchronous Preset Recovery Time (Note 1) 8 ns tEA Input, I/O, or Feedback to Output Enable 10 ns tER Input, I/O, or Feedback to Output Disable 10 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. -10

11MACH220-12/15/20 (Com’l) ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or Latchup Current Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (TA) Operating Supply Voltage (VCC ) with Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 16 mA, VCC = Min 0.5 V VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current V IN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –100 µA Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 2) Off-State Output Leakage V OUT = 0 V, VCC = Max –100 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) –30 –130 mA ICC Supply Current (Typical) V CC = 5 V, TA = 25°C, f = 25 MHz (Note 4) 205 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH ). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. IOZH IOZL

12 MACH220-12/15/20 (Com’l)

CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 12 15 20 ns 7 10 13 ns 81 1 1 4 n s tH Register Data Hold Time 0 0 0 ns tCO Clock to Output (Note 3) 8 10 12 ns tWL 668 n s tWH 668 n s 66.7 50 40 MHz 62.5 47.6 38.5 MHz fMAX 83.3 66.6 50 MHz 76.9 62.5 47.6 MHz 83.3 83.3 62.5 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 7 10 13 ns tHL Latch Data Hold Time 0 0 0 ns tGO Gate to Output (Note 3) 10 11 12 ns tGWL Gate Width LOW 6 6 8 ns tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 14 17 22 ns tSIR Input Register Setup Time 2 2 2 ns tHIR Input Register Hold Time 2 2.5 3 ns tICO Input Register Clock to Combinatorial Output 15 18 23 ns tICS Input Register Clock to Output Register Setup 12 15 20 ns 13 16 21 ns tWICL 668 n s tWICH 668 n s fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH ) 83.3 83.3 62.5 MHz tSIL Input Latch Setup Time 2 2 2 ns tHIL Input Latch Hold Time 2 2.5 3 ns tIGO Input Latch Gate to Combinatorial Output 17 20 25 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 19 22 27 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 9 12 15 ns tIGS Input Latch Gate to Output Latch Setup 13 16 21 ns -15-12 -20 Maximum Frequency (Note 1) tS Setup Time from Input, I/O, or Feedback to Clock 1/(tS + tCO ) Internal Feedback (fCNT ) No Feedback 1/(tWL + tWH ) External Feedback Clock Width D-type T-type D-type T-type D-type T-type D-type T-type LOW HIGH LOW HIGH Input Register Clock Width

13MACH220-12/15/20 (Com’l) SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) -15 Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tWIGL Input Latch Gate Width LOW 6 6 8 ns tPDLL Input, I/O, or Feedback to Output Through Transparent 16 19 24 ns Input and Output Latches tAR Asynchronous Reset to Registered or Latched Output 16 20 25 ns tARW Asynchronous Reset Width (Note 1) 12 15 20 ns tARR Asynchronous Reset Recovery Time (Note 1) 8 10 15 ns tAP Asynchronous Preset to Registered or Latched Output 16 20 25 ns tAPW Asynchronous Preset Width (Note 1) 12 15 20 ns tAPR Asynchronous Preset Recovery Time (Note 1) 8 10 15 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 12 15 20 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 12 15 20 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit for test conditions. 3. Parameters measured with 24 outputs switching. -20-12

14 MACH220-14/18/24 (Ind)

Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. INDUSTRIAL OPERATING RANGES Ambient Temperature (TA) Supply Voltage (VCC) with Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 16 mA, VCC = Min 0.5 V VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current V IN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 2) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –100 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) –30 –130 mA ICC Supply Current (Typical) V CC = 5 V, TA = 25°C, f = 25 MHz (Note 4) 205 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 12-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.

15MACH220-14/18/24 (Ind) CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) -14 -24Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 14.5 18 24 ns 8.5 12 16 ns 10 13.5 17 ns tH Register Data Hold Time 0 0 0 ns tCO Clock to Output (Note 3) 10 12 14.5 ns tWL 7.5 7.5 10 ns tWH 7.5 7.5 10 ns 53 40 32 MHz 50 38 30.5 MHz fMAX 61.5 53 38 MHz 57 44 34.5 MHz 66.5 66.5 50 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 8.5 12 16 ns tHL Latch Data Hold Time 0 0 0 ns tGO Gate to Output (Note 3) 12 13.5 14.5 ns tGWL Gate Width LOW 7.5 7.5 10 ns tPDL Input, I/O, or Feedback to Output Through Transparent 17 20.5 26.5 ns Input or Output Latch tSIR Input Register Setup Time 2.5 2.5 2.5 ns tHIR Input Register Hold Time 3 3.5 4 ns tICO Input Register Clock to Combinatorial Output 18 22 28 ns tICS Input Register Clock to Output Register Setup 14.5 18 24 ns 16 19.5 25.5 ns tWICL 7.5 7.5 10 ns tWICH 7.5 7.5 10 ns fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 66.5 66.5 50 MHz tSIL Input Latch Setup Time 2.5 2.5 2.5 ns tHIL Input Latch Hold Time 3 3.5 4 ns tIGO Input Latch Gate to Combinatorial Output 20.5 24 30 ns tIGOL Input Latch Gate to Output Through Transparent 23 26.5 32.5 ns Output Latch tSLL Setup Time from Input, I/O, or Feedback Through 11 14.5 18 ns Transparent Input Latch to Output Latch Gate tIGS Input Latch Gate to Output Latch Setup 16 19.5 25.5 ns tWIGL Input Latch Gate Width LOW 7.5 7.5 10 ns tPDLL Input, I/O, or Feedback to Output Through Transparent 19.5 23 29 ns Input and Output Latches -18 Maximum Frequency (Note 1) tS Setup Time from Input, I/O, or Feedback to Clock 1/(tS + tCO) Internal Feedback (fCNT) No Feedback 1/(tWL + tWH) External Feedback Clock Width D-type T-type D-type T-type D-type T-type D-type T-type LOW HIGH LOW HIGH Input Register Clock Width

16 MACH220-14/18/24 (Ind)

SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tAR Asynchronous Reset to Registered or Latched Output 19.5 24 30 ns tARW Asynchronous Reset Width (Note 1) 14.5 18 24 ns tARR Asynchronous Reset Recovery Time (Note 1) 10 12 18 ns tAP Asynchronous Preset to Registered or Latched Output 19.5 24 30 ns tAPW Asynchronous Preset Width (Note 1) 14.5 18 24 ns tAPR Asynchronous Preset Recovery Time (Note 1) 10 12 18 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 14.5 18 24 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 14.5 18 24 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. Parameters measured with 24 outputs switching. -24-18-14

TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS VCC = 5.0 V, TA = 25°C Input –40 –60 –80 –2 –1 123 Output, HIGH II (mA) VI (V) –20 IOH (mA) VOH (V) –50 –75 –100 –3 –2 –1 123 –25 –125 –150 –100 Output, LOW .4 .6 1.0.8 –20 –40 –60 –80 IOL (mA) VOL (V) 14130I-4 14130I-5 14130I-6

18 MACH220-10/12/15/20

TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C 14130I-7 275 250 225 200 175 150 125 100 0 1 02 03 04 0 5 0 6 0 7 08 09 0 MACH220 ICC (mA) Frequency (MHz) The selected “typical” pattern is a 12-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register.

TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Parameter Description PLCC Units θjc Thermal impedance, junction to case 10 °C/W θja Thermal impedance, junction to ambient 33 °C/W θjma Thermal impedance, junction to 200 lfpm air 29 °C/W 400 lfpm air 27 °C/W 600 lfpm air 24 °C/W 800 lfpm air 23 °C/W Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. Typ ambient with air flow

20 MACH220-10/12/15/20

Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. tPD Input, I/O, or Feedback Combinatorial Output VT VT Combinatorial Output VT Input, I/O, or Feed- back Registered Output Registered Output tS tCO VT tH VTClock tWH Clock Clock Width tWL VT Combinatorial Output Registered Input (MACH 2 and 4) tSIR tICO VT tHIR VT Input Register Clock Registered Input Latched Output (MACH 2, 3, and 4) Gate Gate Width (MACH 2, 3, and 4) tGWS VT VT VT VT tICS Input Register to Output Register Setup (MACH 2 and 4) Output Register Clock Input Register Clock Registered Input tPDL Input, I/O, or Feedback Latched Out Gate VT tHLtSL tGO VT VT 14130I-8 14130I-9 14130I-10 14130I-11 14130I-12 14130I-13 14130I-14

Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. Latched Input (MACH 2 and 4) Latched Input and Output (MACH 2, 3, and 4) Latched In Output Latch Gate Latched Out tSLL Combinatorial Output Gate tHILtSIL tIGO Latched In tPDLL tIGOL tIGS Input Latch Gate VT VT VT VT VT VT 14130I-15 14130I-16

22 MACH220-10/12/15/20

Input Register Clock Width (MACH 2 and 4) VT tWICL VT VT tARW VT tAR Asynchronous Reset Input, I/O, or Feedback Registered Output Clock tARR Asynchronous Preset Registered Output Clock VT VTOutputs Output Disable/Enable tER tEA VOH - 0.5V VOL + 0.5V Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. Input, I/O, or Feedback VT VT Input, I/O, or Feedback tAPW VT tAP tAPR Input Latch Gate Input Latch Gate Width (MACH 2 and 4) tWIGL VT 14130I-17 14130I-18 14130I-19 14130I-20 14130I-21

KEY TO SWITCHING WAVEFORMS KS000010-PAL Must be Steady May Change from H to L May Change from L to H Does Not Apply Don’t Care, Any Change Permitted Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is High- Impedance “Off” State WAVEFORM INPUTS OUTPUTS SWITCHING TEST CIRCUIT Measured Specification S 1 C L R 1 R 2 Output Value tPD , tCO Closed 1.5 V tEA Z → H: Open 35 pF 1.5 V Z → L: Closed 300 Ω 390 Ω tER H → Z: Open 5 pF H → Z: VOH – 0.5 V L → Z: Closed L → Z: VOL + 0.5 V Commercial 14130I-22 C L Output R 1 R 2 Test Point 5 V *Switching several outputs simultaneously should be avoided for accurate measurement.

24 MACH220-10/12/15/20

The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexi- bility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the in- put setup time for the external signals (t S + tCO ). The re- ciprocal, fMAX , is the maximum frequency with external feedback or in conjunction with an equivalent speed de- vice. This fMAX is designated “fMAX external.” The second type of design is a single-chip state ma- chine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop out- puts. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the inter- nal feedback and logic to the flip-flop inputs. This f MAX is designated “fMAX internal”. A simple internal counter is a good example of this type of design; therefore, this pa- rameter is sometimes called “fCNT.” The third type of design is a simple data path applica- tion. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (t S + tH ). However, a lower limit for the period of each fMAX type is the mini- mum clock period (tWH + tWL ). Usually, this minimum clock period determines the period for the third fMAX , des- ignated “fMAX no feedback.” For devices with input registers, one additional fMAX pa- rameter is specified: fMAXIR . Because this involves no feedback, it is calculated the same way as fMAX no feed- back. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH ). The clock widths are nor- mally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH ). Note that if both input and output reg- isters are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is meas- ured directly. tHIRtSIR LOGIC REGISTER tt CLK (SECOND CHIP) SC O tS fMAX External; 1/(tS + tCO ) LOGIC REGISTER CLK fMAX Internal (fCNT ) LOGIC REGISTER t CLK S fMAX No Feedback; 1/(tS + tH ) or 1/(tWH + tWL ) 14130I-23 LOGICREGISTER CLK fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH )

The MACH families are manufactured using AMD’s advanced Electrically Erasable process. This technol- ogy uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics Parameter Symbol Parameter Description Min Units Test Conditions

10 Years Max Storage

20 Years Max Operating

N Max Reprogramming Cycles 100 Cycles Normal Programming Conditions tDR Min Pattern Data Retention Time

26 MACH220-10/12/15/20

INPUT/OUTPUT EQUIVALENT SCHEMATICS Input I/O Preload Circuitry ESD Protection Feedback Input VCC VCC 1 kΩ 100 kΩ VCC VCC 100 kΩ 1 kΩ 14130I-24

The MACH devices have been designed with the capa- bility to reset during system power-up. Following power- up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing dia- gram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways V CC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Descriptions Max Unit tPR Power-Up Reset Time 10 µs tS Input or Feedback Setup Time tWL Clock Width LOW See Switching Characteristics tPR tWL tS 4 V VCC Power Registered Output Clock 14130I-25 Power-Up Reset Waveform

28 MACH220-10/12/15/20

incorporate register preload and observability. since it is easier to reach the state of interest. impossible for any designs with buried registers. instances to insure valid testing. feedback to hold the correct value, as shown in Figure 3. sequence, but should first be restored to a known state. Figure 2. Preload/Reset Conflict Figure 3. Combinatorial Latch

DEVELOPMENT SYSTEMS (subject to change) For more information on the products listed below, please consult the AMD FusionPLD Catalog. MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Cadence Design Systems

555 River Oaks Pkwy

San Jose, CA 95134 (408) 943-1234 Capilano Computing 960 Quayside Dr., Suite 406 New Westminster, B.C. Canada V3M 6G2 (800) 444-9064 or (604) 552-6200 CINA, Inc. P.O. Box 4872 Mountain View, CA 94040 (415) 940-1723 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (89) 857-6667 ISDATA GmbH Daimlerstr. 51 D7500 Karlsruhe 21 Germany Germany: 0721/75 10 87 Logic Modeling 19500 NW Gibbs Dr. P.O. Box 310 Beaverton, OR 97075 (503) 690-6900 Logical Devices, Inc. 692 S. Military Trail Deerfield Beach, FL 33442 (800) 331-7766 or (305) 428-6868 MACHXL  Software Ver. 2.0 ComposerPIC TM Designer (Requires MACH Fitter) Verilog, LeapFrog, RapidSim Simulators (Models also available from Logic Modeling) Ver. 3.3 LOG/iCTM Software (Requires MACH Fitter) ABEL TM -5 Software (Requires MACH Fitter) SynarioTM Software MacABEL TM Software (Requires SmartPart MACH Fitter) AMD-ABEL Software Data I/O MACH Fitters PROdeveloper/AMD Software PROsynthesis/AMD Software Design Center/AMD Software SmartModel Library SmartCAT Circuit Analyzer PLDSim 90 CUPL TM Software

30 MACH220-10/12/15/20

MANUFACTURER TEST GENERATION SYSTEM Acugen Software, Inc. 427-3 Amherst St., Suite 391 Nashua, NH 03063 (603) 891-1995 iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (87) 857-6667 DEVELOPMENT SYSTEMS (subject to change) (continued) Advanced Micro Devices is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by AMD of these products. ATGEN TM Test Generation Software MultiSIM Interactive Simulator LASAR PLDCheck 90 MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS Mentor Graphics Corp. 8005 S.W. Boeckman Rd. Wilsonville, OR 97070-7777 (800) 547-3000 or (503) 685-7000 MicroSim Corp.

20 Fairbanks

Irvine, CA 92718 (714) 770-3022 MINC Incorporated

6755 Earl Drive, Suite 200

Colorado Springs, CO 80918 (800) 755-FPGA or (719) 590-1155 OrCAD 3175 N.W. Aloclek Dr. Hillsboro, OR 97124 (503) 690-9881 SUSIE–CAD

10000 Nevada Highway, Suite 201

Boulder City, NV 89005 (702) 293-2271 Teradyne EDA 321 Harrison Ave. Boston, MA 02118 (800) 777-2432 or (617) 422-2793 Viewlogic Systems, Inc.

293 Boston Post Road West

Marlboro, MA 01752 (800) 442-4660 or (508) 480-0881 Programmable Logic Design Tools 386+ Schematic Design Tool 386+ Digital Simulation Tools ViewPLD or PROPLD (Requires PROSim Simulator MACH Fitter) ViewSim Simulator (Models for ViewSim also available from Logic Modeling) PLDesigner TM -XL Software (Requires MACH Fitter) PLDSynthesisTM (Requires MACH Fitter) QuickSim Simulator (Models also available from Logic Modeling) Design Center Software (Requires MACH Fitter) SUSIE TM Simulator

APPROVED PROGRAMMERS (subject to change) For more information on the products listed below, please consult the AMD FusionPLD Catalog. MANUFACTURER PROGRAMMER CONFIGURATION Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, CA 94086 (408) 243-7000 BP Microsystems 100 N. Post Oak Rd. Houston, TX 77055-7237 (800) 225-2102 or (713) 688-4600 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 Logical Devices Inc./Digelec 692 S. Military Trail Deerfield Beach, FL 33442 (800) 331-7766 or (305) 428-6868 SMS North America, Inc.

16522 NE 135th Place

Redmond, WA 98052 (800) 722-4122 or SMS lm Grund 15 D-7988 Vangen Im Allgau, Germany 07522-5018 Stag Microsystems Inc. 1600 Wyatt Dr. Suite 3 Santa Clara, CA 95054 (408) 988-1118 or Stag House Martinfield, Welwyn Garden City Herfordshire UK AL7 1JT 707-332148 System General 510 S. Park Victoria Dr. Milpitas, CA 95035 (408) 263-6667 or 3F, No. 1, Alley 8, Lane 45 Bao Shing Rd., Shin Diau Taipei, Taiwan 2-917-3005 BP1200 Pilot U84 Model 3900 Turpro-1 UniSiteTM AutoSite Stag Quazar Sprint/Expert ALLPRO TM –88 MANUFACTURER PROGRAMMER CONFIGURATION Corelis, Inc.

12607 Hidden Creek Way, Suite H

Cerritos, California 70703 (310) 926-6727 Advanced Micro Devices P.O. Box 3453, MS-1028 Sunnyvale, CA 94088-3453 (800) 222-9323 MACHpro JTAG PROG APPROVED ON-BOARD PROGRAMMERS

32 MACH220-10/12/15/20

PROGRAMMER SOCKET ADAPTERS (subject to change) MANUFACTURER PART NUMBER EDI Corporation P.O. Box 366 Patterson, CA 95363 (209) 892-3270 Emulation Technology 2344 Walsh Ave., Bldg. F Santa Clara, CA 95051 (408) 982-0660 Logical Systems Corp. P.O. Box 6184 Syracuse, NY 13217-6184 (315) 478-0722 Procon Technologies, Inc.

1333 Lawrence Expwy, Suite 207

Santa Clara, CA 95051 (408) 246-4456 Contact Manufacturer Contact Manufacturer Contact Manufacturer Contact Manufacturer

PHYSICAL DIMENSIONS* PL 068 68-Pin Plastic Leaded Chip Carrier (measured in inches) TOP VIEW SEATING PLANE .985 .995 .950 .956 Pin 1 I.D. .985 .995 .950 .956 .026 .032 .050 REF .042 .056 .062 .083 .013 .021 .890 .930 .800 REF .007 .013 .165 .180 .090 .130 16-038-SQ PL 068 DA78 6-28-94 ae SIDE VIEW *For reference only. BSC is an ANSI standard for Basic Space Centering. Trademarks Copyright  1995 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.