MACH210A-14JI

MACH210A-7 AMD | Alldatasheet

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Publication# 14128 Rev. I Amendment /0 Issue Date: May 1995 Advanced Micro Devices MACH210A-7/10/12 MACH210-12/15/20 MACH210AQ-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS

44 Pins

64 Macrocells

7.5 ns tPD Commercial 12 ns tPD Industrial

133 MHz fCNT

38 Inputs; 210A Inputs have built-in pull-up

Peripheral Component Interconnect (PCI) compliant

32 Outputs

64 Flip-flops; 2 clock choices

4 “PAL22V16” blocks with buried macrocells Pin-compatible with MACH110, MACH111, MACH211, and MACH215 GENERAL DESCRIPTION The MACH210 is a member of AMD’s high-performance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH210 consists of four PAL blocks intercon- nected by a programmable switch matrix. The four PAL blocks are essentially “PAL22V16” structures complete with product-term arrays and programmable macro- cells, including additional buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH210 has two kinds of macrocell: output and buried. The MACH210 output macrocell provides regis- tered, latched, or combinatorial outputs with program- mable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH210 has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time require- ments.

I/O0–I/O7 Macrocells I/O Cells Macrocells 8 88 I0–I1, I3–I4I/O8–I/O15 I/O16–I/O23 CLK 0/I2, CLK 1/I5 I/O24–I/O31 14128I-1 44 x 68 AND Logic Array and Logic Allocator 22 22 22 22 44 x 68 AND Logic Array and Logic Allocator 44 x 68 AND Logic Array and Logic Allocator 44 x 68 AND Logic Array and Logic Allocator OE Macrocells Macrocells Macrocells OE OE OE

Note: Pin-compatible with MACH110, MACH111, MACH211, and MACH215.

14128I-3Note: Pin-compatible with MACH111 and MACH211. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output VCC = Supply Voltage

ORDERING INFORMATION

AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: OPERATING CONDITIONS C = Commercial (0°C to +70°C) FAMILY TYPE MACH = Macro Array CMOS High-Speed SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD MACH210A-7 MACH210A-10 MACH210A-12 MACH210-12 MACH210-15 MACH210-20 MACH210AQ-12 MACH210AQ-15 MACH210AQ-20 MACH -7 J C Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- sult the local AMD sales office to confirm availability of specific valid combinations or to check on newly re- leased combinations. Valid Combinations OPTIONAL PROCESSING Blank = Standard Processing 210A DEVICE NUMBER 210 = 64 Macrocells, 44 Pins 210A = 64 Macrocells, 44 Pins, Input Pull-Up Resistors 210AQ = 64 Macrocells, 44 Pins, Input Pull-Up Resistors, Quarter Power PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) V = 44-Pin Thin Quad Flat Pack (PQT044) JC JC, VC

6 MACH210-12/14/18/24 (Ind)

AMD programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: OPERATING CONDITIONS I = Industrial (–40°C to +85°C) FAMILY TYPE MACH = Macro Array CMOS High-Speed SPEED -12 = 12 ns tPD -14 = 14.5 ns tPD -18 = 18 ns tPD -24 = 24 ns tPD MACH210A-12 MACH210A-14 MACH210-14 MACH210-18 MACH210-24 MACH -12 J I Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- sult the local AMD sales office to confirm availability of specific valid combinations or to check on newly re- leased combinations. Valid Combinations OPTIONAL PROCESSING Blank = Standard Processing 210A DEVICE NUMBER 210 = 64 Macrocells, 44 Pins 210A = 64 Macrocells, 44 Pins, Input Pull-Up Resistors PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) JI

can also be used as dedicated inputs. ent “PAL22V16” with 8 buried macrocells. and an asynchronous preset product term are provided. within the PAL block are initialized together. when fitting a design into the device. Figure 1 for cluster and macrocell numbers. Table 1. Logic Allocation T-type, allowing for product-term optimization.

The I/O cell in the MACH210 consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. PCI Compliance The MACH210A-7/10 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The MACH210A-7/10’s predictable timing ensures compliance with the PCI AC specifica- tions independent of the design. On the other hand, in CPLD and FPGA architectures without predictable timing, PCI compliance is dependent upon routing and product term distribution.

Figure 1. MACH210 PAL Block

10 MACH210A-7 (Com’l)

Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Pro- gramming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (TA) Operating Supply Voltage (VCC ) with Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 16 mA, VCC = Min 0.5 V VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current V IN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 2) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –100 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA ICC Supply Current V IN = 0 V, Outputs Open (IOUT = 0 mA) 130 mA VCC = 5.0 V, f = 25 MHz, TA = 25°C (Note 4) Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH ). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and capable of being loaded, enabled, and reset.

11MACH210A-7 (Com’l) CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges Parameter Symbol Parameter Description Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output 7.5 ns tS Setup Time from Input, I/O or Feedback to Clock D-Type 5.5 ns T-Type 6.5 ns tH Register Data Hold Time 0 ns tCO Clock to Output 5n s tWL Clock Width LOW 3 ns tWH HIGH 3 ns D-Type 100 MHz T-Type 91 MHz fMAX D-Type 133 MHz T-Type 125 MHz

166.7 MHz

tSL Setup Time from Input, I/O, or Feedback to Gate 5.5 ns tHL Latch Data Hold Time 0 ns tGO Gate to Output 6n s tGWL Gate Width LOW 3 ns tPDL Input, I/O, or Feedback to Output Through 9.5 ns Transparent Input or Output Latch tSIR Input Register Setup Time 2 ns tHIR Input Register Hold Time 2 ns tICO Input Register Clock to Combinatorial Output 11 ns tICS Input Register Clock to Output Register Setup D-Type 9 ns T-Type 10 ns tWICL Input Register Clock Width LOW 3 ns tWICH HIGH 3 ns fMAXIR Maximum Input Register Frequency 166.7 MHz tSIL Input Latch Setup Time 2 ns tHIL Input Latch Hold Time 2 ns tIGO Input Latch Gate to Combinatorial Output 12 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 14 ns tSLL Setup Time from Input, I/O, or Feedback Through 7.5 ns Transparent Input Latch to Output Latch Gate Maximum Frequency External Feedback Internal Feedback (fCNT ) No Feedback

12 MACH210A-7 (Com’l)

SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (continued) Parameter Symbol Parameter Description Min Max Unit tIGS Input Latch Gate to Output Latch Setup 10 ns tWIGL Input Latch Gate Width LOW 3 ns tPDLL Input, I/O, or Feedback to Output Through Transparent 11.5 ns Input and Output Latches tAR Asynchronous Reset to Registered or Latched Output 12 ns tARW Asynchronous Reset Width 8 ns tARR Asynchronous Reset Recovery Time 8 ns tAP Asynchronous Preset to Registered or Latched Output 12 ns tAPW Asynchronous Preset Width 8 ns tAPR Asynchronous Preset Recovery Time 8 ns tEA Input, I/O, or Feedback to Output Enable 7.5 ns tER Input, I/O, or Feedback to Output Disable 7.5 ns Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.

13MACH210A-10/12 (Com’l) ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (TA) Operating Supply Voltage (VCC ) with Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit V OH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 16 mA, VCC = Min 0.5 V VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 2) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –100 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA ICC Supply Current (Typical) V CC = 5V, TA = 25°C, f = 25 MHz 135 mA (Note 4) Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH ). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.

MACH210A-10/12 (Com’l)14 CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 10 12 ns D-Type 6.5 7 ns T-Type 7.5 8 ns tH Register Data Hold Time 0 0 ns tCO Clock to Output (Note 3) 6 8 ns tWL Clock LOW 5 6 ns tWH Width HIGH 5 6 ns D-Type 80 66.7 MHz T-Type 74 62.5 MHz fMAX D-Type 100 83.3 MHz T-Type 91 76.9 MHz 100 83.3 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 6.5 7 ns tHL Latch Data Hold Time 0 0 ns tGO Gate to Output (Note 3) 7 10 ns tGWL Gate Width LOW 5 6 ns tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 12 14 ns tSIR Input Register Setup Time 2 2 ns tHIR Input Register Hold Time 2 2 ns tICO Input Register Clock to Combinatorial Output 13 15 ns tICS Input Register Clock to Output Register Setup D-Type 10 12 ns T-Type 11 13 ns tWICL Input Register LOW 5 6 ns tWICH Clock Width HIGH 5 6 ns fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH ) 100 83.3 MHz tSIL Input Latch Setup Time 2 2 ns tHIL Input Latch Hold Time 2 2 ns tIGO Input Latch Gate to Combinatorial Output 14 17 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 16 19 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 8.5 9 ns tIGS Input Latch Gate to Output Latch Setup 11 13 ns Maximum Frequency (Note 1) Setup Time from Input, I/O, or Feedback to Clock External Feedback 1/(tS + tCO ) Internal Feedback (fCNT ) No Feedback 1/(tS + tH ) -10 -12 tS

15MACH210A-10/12 (Com’l) SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description Min Max Min Max Unit tWIGL Input Latch Gate Width LOW 5 6 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 14 16 ns tAR Asynchronous Reset to Registered or Latched Output 25 16 ns tARW Asynchronous Reset Width (Note 1) 10 12 ns tARR Asynchronous Reset Recovery Time (Note 1) 10 8 ns tAP Asynchronous Preset to Registered or Latched Output 15 16 ns tAPW Asynchronous Preset Width (Note 1) 10 12 ns tAPR Asynchronous Preset Recovery Time (Note 1) 10 8 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 10 12 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 10 12 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. -10 -12

MACH210A-12/14 (Ind)16 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. INDUSTRIAL OPERATING RANGES Temperature (TA) Operating Supply Voltage (VCC ) with Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit V OH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 16 mA, VCC = Min 0.5 V VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 2) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –100 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA ICC Supply Current (Typical) V CC = 5V, TA = 25°C, f = 25 MHz 135 mA (Note 4) Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH ). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.

17MACH210A-12/14 (Ind) CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 12 14.5 ns D-Type 8 8.5 ns T-Type 9 10 ns tH Register Data Hold Time 0 0 ns tCO Clock to Output (Note 3) 7.5 10 ns tWL Clock LOW 6 7.5 ns tWH Width HIGH 6 7.5 ns D-Type 64 53 MHz T-Type 59 50 MHz fMAX D-Type 80 61.5 MHz T-Type 72.5 57 MHz 80 66.5 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 8 8.5 ns tHL Latch Data Hold Time 0 0 ns tGO Gate to Output (Note 3) 8.5 12 ns tGWL Gate Width LOW 6 7.5 ns tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 14.5 17 ns tSIR Input Register Setup Time 2.5 2.5 ns tHIR Input Register Hold Time 3 3 ns tICO Input Register Clock to Combinatorial Output 16 18 ns tICS Input Register Clock to Output Register Setup D-Type 12 14.5 ns T-Type 13 16 ns tWICL Input Register LOW 6 7.5 ns tWICH Clock Width HIGH 6 7.5 ns fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH ) 80 66.5 MHz tSIL Input Latch Setup Time 2.5 2.5 ns tHIL Input Latch Hold Time 3 3 ns tIGO Input Latch Gate to Combinatorial Output 17 20.5 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 19.5 23 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 10.5 11 ns tIGS Input Latch Gate to Output Latch Setup 13.5 16 ns Maximum Frequency (Note 1) Setup Time from Input, I/O, or Feedback to Clock External Feedback 1/(tS + tCO ) Internal Feedback (fCNT ) No Feedback 1/(tS + tH ) -12 -14 tS

MACH210A-12/14 (Ind)18 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description Min Max Min Max Unit tWIGL Input Latch Gate Width LOW 6 7.5 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 17 19.5 ns tAR Asynchronous Reset to Registered or Latched Output 19.5 19.5 ns tARW Asynchronous Reset Width (Note 1) 12 14.5 ns tARR Asynchronous Reset Recovery Time (Note 1) 12 10 ns tAP Asynchronous Preset to Registered or Latched Output 18 19.5 ns tAPW Asynchronous Preset Width (Note 1) 12 14.5 ns tAPR Asynchronous Preset Recovery Time (Note 1) 12 10 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 12 14.5 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 12 14.5 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. -12 -14

19MACH210-12/15/20 (Com’l) ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (TA) Operating Supply Voltage (VCC ) with Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit V OH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 16 mA, VCC = Min 0.5 V VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –10 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 2) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –10 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA ICC Supply Current (Typical) V CC = 5V, TA = 25°C, f = 25 MHz 120 mA (Note 4) Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH ). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.

MACH210-12/15/20 (Com’l)20 CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 12 15 20 ns D-type 7 10 13 ns T-type 8 11 14 ns tH Register Data Hold Time 0 0 0 ns tCO Clock to Output (Note 3) 8 10 12 ns tWL Clock LOW 6 6 8 ns tWH Width HIGH 6 6 8 ns D-type 66.7 50 40 MHz T-type 62.5 47.6 38.5 MHz fMAX D-type 83.3 66.6 50 MHz T-type 76.9 62.5 47.6 MHz 83.3 83.3 62.5 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 7 10 13 ns tHL Latch Data Hold Time 0 0 0 ns tGO Gate to Output (Note 3) 10 11 12 ns tGWL Gate Width LOW 6 6 8 ns tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 14 17 22 ns tSIR Input Register Setup Time 2 2 2 ns tHIR Input Register Hold Time 2 2.5 3 ns tICO Input Register Clock to Combinatorial Output 15 18 23 ns tICS Input Register Clock to Output Register Setup 12 15 20 ns 13 16 21 ns tWICL Input Register LOW 6 6 8 ns tWICH Clock Width HIGH 6 6 8 ns fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH ) 83.3 83.3 62.5 MHz tSIL Input Latch Setup Time 2 2 2 ns tHIL Input Latch Hold Time 2 2.5 3 ns tIGO Input Latch Gate to Combinatorial Output 17 20 25 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 19 22 27 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 9 12 15 ns tIGS Input Latch Gate to Output Latch Setup 13 16 21 ns Maximum Frequency (Note 1) Setup Time from Input, I/O, or Feedback to Clock External Feedback 1/(tS + tCO ) Internal Feedback (fCNT ) No Feedback 1/(tWL + tWH ) -15 -20 D-type T-type tS -12

21MACH210-12/15/20 (Com’l) SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tWIGL Input Latch Gate Width LOW 6 6 8 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 16 19 24 ns tAR Asynchronous Reset to Registered or Latched Output 16 20 25 ns tARW Asynchronous Reset Width (Note 1) 12 15 20 ns tARR Asynchronous Reset Recovery Time (Note 1) 8 10 15 ns tAP Asynchronous Preset to Registered or Latched Output 16 20 25 ns tAPW Asynchronous Preset Width (Note 1) 12 15 20 ns tAPR Asynchronous Preset Recovery Time (Note 1) 8 10 15 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 12 15 20 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 12 15 20 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. -15 -20-12

MACH210-14/18/24 (Ind)22 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or I/O Latchup Current Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. INDUSTRIAL OPERATING RANGES Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 16 mA, VCC = Min 0.5 V VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current V IN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –10 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 2) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –10 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA Supply Current (Typical) V CC = 5 V, TA = 25°C, f = 25 MHz (Note 4) 120 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. ICC

23MACH210-14/18/24 (Ind) CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output 14.5 18 24 ns (Note 3) D-type 8.5 12 16 ns T-type 10 13.5 17 ns tH Register Data Hold Time 0 0 0 ns tCO Clock to Output (Note 3) 10 12 14.5 ns tWL Clock LOW 7.5 7.5 10 ns tWH Width HIGH 7.5 7.5 10 ns D-type 53 40 32 MHz T-type 50 38 30.5 MHz fMAX D-type 61.5 53 38 MHz T-type 57 44 34.5 MHz 66.5 66.5 50 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 8.5 12 16 ns tHL Latch Data Hold Time 0 0 0 ns tGO Gate to Output (Note 3) 12 13.5 14.5 ns tGWL Gate Width LOW 7.5 7.5 10 ns tPDL Input, I/O, or Feedback to Output Through 17 20.5 26.5 ns Transparent Input or Output Latch tSIR Input Register Setup Time 2.5 2.5 2.5 ns tHIR Input Register Hold Time 3 3.5 4 ns tICO Input Register Clock to Combinatorial Output 18 22 28 ns tICS Input Register Clock to Output Register Setup 14.5 18 24 ns 16 19.5 25.5 ns tWICL Input Register LOW 7.5 7.5 10 ns tWICH Clock Width HIGH 7.5 7.5 10 ns fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 66.5 66.5 50 MHz tSIL Input Latch Setup Time 2.5 2.5 2.5 ns tHIL Input Latch Hold Time 3 3.5 4 ns tIGO Input Latch Gate to Combinatorial Output 20.5 24 30 ns tIGOL Input Latch Gate to Output Through Transparent 23 26.5 32.5 ns Output Latch tSLL Setup Time from Input, I/O, or Feedback Through 11 14.5 18 ns Transparent Input Latch to Output Latch Gate tIGS Input Latch Gate to Output Latch Setup 16 19.5 25.5 ns tWIGL Input Latch Gate Width LOW 7.5 7.5 10 ns tPDLL Input, I/O, or Feedback to Output Through Transparent 19.5 23 29 ns Input and Output Latches Maximum Frequency (Note 1) Setup Time from Input, I/O, or Feedback to Clock External Feedback 1/(tS + tCO) Internal Feedback (fCNT) No Feedback 1/(tWL + tWH) -18 -24 D-type T-type tS -14

MACH210-14/18/24 (Ind)24 SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description Min Max Min Max Min Max Unit tAR Asynchronous Reset to Registered or Latched Output 19.5 24 30 ns tARW Asynchronous Reset Width (Note 1) 14.5 18 24 ns tARR Asynchronous Reset Recovery Time (Note 1) 10 12 18 ns tAP Asynchronous Preset to Registered or Latched Output 19.5 24 30 ns tAPW Asynchronous Preset Width (Note 1) 14.5 18 24 ns tAPR Asynchronous Preset Recovery Time (Note 1) 10 12 18 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 14.5 18 24 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 14.5 18 24 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. -18 -24-14

25MACH210AQ-12 (Com’l) ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (TA) Operating Supply Voltage (VCC ) with Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 16 mA, VCC = Min 0.5 V VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 2) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –100 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA ICC Supply Current (Typical) V CC = 5 V, TA = 25°C, f = 25 MHz 45 mA (Note 4) Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH ). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.

MACH210AQ-12 (Com’l)26 CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output 12 ns D-type 12 ns T-type 13 ns t H Register Data Hold Time 0 ns tCO Clock to Output 6n s tWL Clock LOW 6 ns tWH Width HIGH 6 ns D-type 55.6 MHz T-type 52.6 MHz fMAX D-type 83.3 MHz T-type 76.9 MHz

83.3 MHz

tSL Setup Time from Input, I/O, or Feedback to Gate 12 ns tHL Latch Data Hold Time 0 ns tGO Gate to Output 7n s tGWL Gate Width LOW 6 ns tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 14 ns tSIR Input Register Setup Time 2 ns tHIR Input Register Hold Time 2.5 ns tICO Input Register Clock to Combinatorial Output 17 ns tICS Input Register Clock to Output Register Setup D-type 15 ns T-type 16 ns tWICL Input Register LOW 6 ns tWICH Clock Width HIGH 6 ns fMAXIR Maximum Input Register Frequency 83.3 MHz tSIL Input Latch Setup Time 2 ns tHIL Input Latch Hold Time 2.5 ns tIGO Input Latch Gate to Combinatorial Output 19 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 20 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 13 ns tIGS Input Latch Gate to Output Latch Setup 16 ns Maximum Frequency (Note 1) Setup Time from Input, I/O, or Feedback to Clock External Feedback Internal Feedback (fCNT ) -12 tS No Feedback

27MACH210AQ-12 (Com’l) SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description Min Max Unit tWIGL Input Latch Gate Width LOW 6 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 18 ns tAR Asynchronous Reset to Registered or Latched Output 24 ns tARW Asynchronous Reset Width (Note 1) 19 ns tARR Asynchronous Reset Recovery Time (Note 1) 19 ns tAP Asynchronous Preset to Registered or Latched Output 24 ns tAPW Asynchronous Preset Width (Note 1) 19 ns tAPR Asynchronous Preset Recovery Time (Note 1) 19 ns tEA Input, I/O, or Feedback to Output Enable 12 ns tER Input, I/O, or Feedback to Output Disable 12 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. -12

MACH210AQ-15/20 (Com’l)28 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Temperature (TA) Operating Supply Voltage (VCC ) with Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit V OH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 16 mA, VCC = Min 0.5 V VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 2) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –100 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA ICC Supply Current (Typical) V CC = 5V, TA = 25°C, f = 25 MHz 45 mA (Note 4) Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH ). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.

29MACH210AQ-15/20 (Com’l) CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) 15 20 ns D-type 13 17 ns T-type 14 18 ns tH Register Data Hold Time 0 0 ns tCO Clock to Output (Note 3) 7 8 ns tWL Clock LOW 6 8 ns tWH Width HIGH 6 8 ns D-type 50 40 MHz T-type 47.6 38.4 MHz fMAX D-type 58.8 45.4 MHz T-type 55.5 43.4 MHz D-type 76.9 58.8 MHz T-type 71.4 55.5 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 13 17 ns tHL Latch Data Hold Time 0 0 ns tGO Gate to Output (Note 3) 8 8 ns tGWL Gate Width LOW 6 8 ns tPDL Input, I/O, or Feedback to Output Through Transparent Input or Output Latch 17 22 ns tSIR Input Register Setup Time 2 2 ns tHIR Input Register Hold Time 2.5 3 ns tICO Input Register Clock to Combinatorial Output 18 23 ns tICS Input Register Clock to Output Register Setup 17 22 ns 18 23 ns tWICL Input Register LOW 6 8 ns tWICH Clock Width HIGH 6 8 ns fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH ) 83.3 62.5 MHz tSIL Input Latch Setup Time 2 2 ns tHIL Input Latch Hold Time 2.5 3 ns tIGO Input Latch Gate to Combinatorial Output 20 25 ns tIGOL Input Latch Gate to Output Through Transparent Output Latch 22 27 ns tSLL Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 15 19 ns tIGS Input Latch Gate to Output Latch Setup 18 23 ns Maximum Frequency (Note 1) Setup Time from Input, I/O, or Feedback to Clock External Feedback 1/(tS + tCO ) Internal Feedback (fCNT ) No Feedback 1/(tS + tH ) -15 -20 D-type T-type tS

MACH210AQ-15/20 (Com’l)30 SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description Min Max Min Max Unit tWIGL Input Latch Gate Width LOW 6 8 ns tPDLL Input, I/O, or Feedback to Output Through Transparent Input and Output Latches 19 24 ns tAR Asynchronous Reset to Registered or Latched Output 25 30 ns tARW Asynchronous Reset Width (Note 1) 20 25 ns tARR Asynchronous Reset Recovery Time (Note 1) 20 25 ns tAP Asynchronous Preset to Registered or Latched Output 25 30 ns tAPW Asynchronous Preset Width (Note 1) 20 25 ns tAPR Asynchronous Preset Recovery Time (Note 1) 20 25 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 15 20 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 15 20 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. -15 -20

31MACH210AQ-18/24 (Ind) ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or I/O Latchup Current Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. INDUSTRIAL OPERATING RANGES Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges define those limits between which the func- tionality of the device is guaranteed. DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage I OH = –3.2 mA, VCC = Min 2.4 V VIN = VIH or VIL VOL Output LOW Voltage I OL = 16 mA, VCC = Min 0.5 V VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 V Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW 0.8 V Voltage for all Inputs (Note 1) IIH Input HIGH Leakage Current V IN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current V IN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage V OUT = 5.25 V, VCC = Max 10 µA Current HIGH V IN = VIH or VIL (Note 2) IOZL Off-State Output Leakage V OUT = 0 V, VCC = Max –100 µA Current LOW V IN = VIH or VIL (Note 2) ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA ICC Supply Current (Typical) V CC = 5 V, TA = 25°C, f = 25 MHz (Note 4) 45 mA Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset.

MACH210AQ-18/24 (Ind)32 CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = 2.0 V V CC = 5.0 V, TA = 25°C, 6 pF C OUT Output Capacitance V OUT = 2.0 V f = 1 MHz 8 pF SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min Max Min Max Unit tPD Input, I/O, or Feedback to Combinatorial Output 18 24 ns (Note 3) D-type 16 20.5 ns T-type 17 22 ns tH Register Data Hold Time 0 0 ns tCO Clock to Output (Note 3) 8.5 10 ns tWL Clock LOW 7.5 10 ns tWH Width HIGH 7.5 10 ns D-type 40 32 MHz T-type 38 30.5 MHz fMAX D-type 47 36 MHz T-type 44 34.5 MHz D-type 61.5 47 MHz T-type 57 47 MHz tSL Setup Time from Input, I/O, or Feedback to Gate 16 20.5 ns tHL Latch Data Hold Time 0 0 ns tGO Gate to Output (Note 3) 10 10 ns tGWL Gate Width LOW 7.5 10 ns tPDL Input, I/O, or Feedback to Output Through 20.5 26.5 ns Transparent Input or Output Latch tSIR Input Register Setup Time 2.5 2.5 ns tHIR Input Register Hold Time 3.5 4 ns tICO Input Register Clock to Combinatorial Output 22 28 ns tICS Input Register Clock to Output Register Setup 20.5 26.5 ns 22 28 ns tWICL Input Register LOW 7.5 10 ns tWICH Clock Width HIGH 7.5 10 ns fMAXIR Maximum Input Register Frequency 1/(tWICL + tWICH) 66.5 50 MHz tSIL Input Latch Setup Time 2.5 2.5 ns tHIL Input Latch Hold Time 3.5 4 ns tIGO Input Latch Gate to Combinatorial Output 24 30 ns tIGOL Input Latch Gate to Output Through Transparent 26.5 32.5 ns Output Latch tSLL Setup Time from Input, I/O, or Feedback Through 18 23 ns Transparent Input Latch to Output Latch Gate tIGS Input Latch Gate to Output Latch Setup 22 28 ns tWIGL Input Latch Gate Width LOW 7.5 10 ns tPDLL Input, I/O, or Feedback to Output Through Transparent 23 29 ns Input and Output Latches Maximum Frequency (Note 1) Setup Time from Input, I/O, or Feedback to Clock External Feedback 1/(tS + tCO) Internal Feedback (fCNT) No Feedback 1/(tS + tH) -18 -24 D-type T-type tS

33MACH210AQ-18/24 (Ind) SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description Min Max Min Max Unit tAR Asynchronous Reset to Registered or Latched Output 30 36 ns tARW Asynchronous Reset Width (Note 1) 24 30 ns tARR Asynchronous Reset Recovery Time (Note 1) 24 30 ns tAP Asynchronous Preset to Registered or Latched Output 30 36 ns tAPW Asynchronous Preset Width (Note 1) 24 30 ns tAPR Asynchronous Preset Recovery Time (Note 1) 24 30 ns tEA Input, I/O, or Feedback to Output Enable (Note 3) 18 24 ns tER Input, I/O, or Feedback to Output Disable (Note 3) 18 24 ns Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. -18 -24

34 MACH210-7/10/12/15/20, Q-12/15/20

TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS VCC = 5.0 V, TA = 25°C Input 14128I-6 –40 –60 –80 –2 –1 123 Output, HIGH II (mA) VI (V) –20 14128I-5 IOH (mA) VOH (V) –50 –75 –100 –3 –2 –1 123 –25 –125 –150 –100 Output, LOW .4 .6 1.0.8 –20 –40 –60 –80 IOL (mA) VOL (V) 14128I-7

MACH210-7/10/12/15/20, Q-12/15/20 35 TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C 14128I-8 150 125 100 0 1 02 03 04 0 5 06 07 0 8 09 0 1 0 0 MACH210A MACH210 MACH210AQ ICC (mA) Frequency (MHz) The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register.

36 MACH210-7/10/12/15/20, Q-12/15/20

TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Parameter Description TQFP PLCC Unit θjc Thermal impedance, junction to case 11.3 15 °C/W θja Thermal impedance, junction to ambient 41 40 °C/W θjma Thermal impedance, junction to 200 lfpm air 35 36 °C/W 400 lfpm air 33.7 33 °C/W 600 lfpm air 32.6 31 °C/W 800 lfpm air 32 29 °C/W Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. Typ ambient with air flow

Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. tPD Input, I/O, or Feedback Combinatorial Output VT VT Combinatorial Output VT Input, I/O, or Feed- back Registered Output Registered Output tS tCO VT tH VTClock tWH Clock Clock Width tWL VT Combinatorial Output Registered Input (MACH 2 and 4) tSIR tICO VT tHIR VT Input Register Clock Registered Input Latched Output (MACH 2, 3, and 4) Gate Gate Width (MACH 2, 3, and 4) tGWS VT VT VT VT tICS Input Register to Output Register Setup (MACH 2 and 4) Output Register Clock Input Register Clock Registered Input tPDL Input, I/O, or Feedback Latched Out Gate VT tHLtSL tGO VT VT 14128I-9 14128I-10 14128I-11 14128I-12 14128I-13 14128I-14 14128I-15

Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. Latched Input (MACH 2 and 4) Latched Input and Output (MACH 2, 3, and 4) Latched In Output Latch Gate Latched Out tSLL Combinatorial Output Gate tHILtSIL tIGO Latched In tPDLL tIGOL tIGS Input Latch Gate VT VT VT VT VT VT 14128I-16 14128I-17

Input Register Clock Width (MACH 2 and 4) VT tWICL VT VT tARW VT tAR Asynchronous Reset Input, I/O, or Feedback Registered Output Clock tARR Asynchronous Preset Registered Output Clock VT VTOutputs Output Disable/Enable tER tEA VOH - 0.5V VOL + 0.5V Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. Input, I/O, or Feedback VT VT Input, I/O, or Feedback tAPW VT tAP tAPR Input Latch Gate Input Latch Gate Width (MACH 2 and 4) tWIGL VT 14128I-18 14128I-19 14128I-20 14128I-21 14128I-22

KEY TO SWITCHING WAVEFORMS KS000010-PAL Must be Steady May Change from H to L May Change from L to H Does Not Apply Don’t Care, Any Change Permitted Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is High- Impedance “Off” State WAVEFORM INPUTS OUTPUTS SWITCHING TEST CIRCUIT Measured Specification S 1 C L R 1 R 2 Output Value tPD , tCO Closed 1.5 V tEA Z → H: Open 35 pF 1.5 V Z → L: Closed 300 Ω 390 Ω tER H → Z: Open 5 pF H → Z: VOH – 0.5 V L → Z: Closed L → Z: VOL + 0.5 V Commercial 14128I-23 C L Output R 1 R 2 Test Point 5 V *Switching several outputs simultaneously should be avoided for accurate measurement.

The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexi- bility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the in- put setup time for the external signals (t S + tCO ). The re- ciprocal, fMAX , is the maximum frequency with external feedback or in conjunction with an equivalent speed de- vice. This fMAX is designated “fMAX external.” The second type of design is a single-chip state ma- chine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop out- puts. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the inter- nal feedback and logic to the flip-flop inputs. This f MAX is designated “fMAX internal”. A simple internal counter is a good example of this type of design; therefore, this pa- rameter is sometimes called “fCNT.” The third type of design is a simple data path applica- tion. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (t S + tH ). However, a lower limit for the period of each fMAX type is the mini- mum clock period (tWH + tWL ). Usually, this minimum clock period determines the period for the third fMAX , des- ignated “fMAX no feedback.” For devices with input registers, one additional fMAX pa- rameter is specified: fMAXIR . Because this involves no feedback, it is calculated the same way as fMAX no feed- back. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + tWICH ). The clock widths are nor- mally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH ). Note that if both input and output reg- isters are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is meas- ured directly. tHIRtSIR LOGIC REGISTER tt CLK (SECOND CHIP) SC O tS fMAX External; 1/(tS + tCO ) LOGIC REGISTER CLK fMAX Internal (fCNT ) LOGIC REGISTER t CLK S fMAX No Feedback; 1/(tS + tH ) or 1/(tWH + tWL ) 14128I-24 LOGICREGISTER CLK fMAXIR ; 1/(tSIR + tHIR) or 1/(tWICL + tWICH )

The MACH families are manufactured using AMD’s advanced Electrically Erasable process. This technol- ogy uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics Parameter Symbol Parameter Description Min Units Test Conditions

10 Years Max Storage

20 Years Max Operating

N Max Reprogramming Cycles 100 Cycles Normal Programming Conditions tDR Min Pattern Data Retention Time

INPUT/OUTPUT EQUIVALENT SCHEMATICS Input I/O Preload Circuitry ESD Protection Feedback Input VCC VCC 1 kΩ 100 kΩ VCC VCC 100 kΩ 1 kΩ 14128I-25

The MACH devices have been designed with the capa- bility to reset during system power-up. Following power- up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing dia- gram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways V CC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Descriptions Max Unit tPR Power-Up Reset Time 10 µs tS Input or Feedback Setup Time tWL Clock Width LOW See Switching Characteristics tPR tWL tS 4 V VCC Power Registered Output Clock 14128I-26 Power-Up Reset Waveform

DEVELOPMENT SYSTEMS (subject to change) For more information on the products listed below, please consult the AMD FusionPLD Catalog. MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Cadence Design Systems

555 River Oaks Pkwy

San Jose, CA 95134 (408) 943-1234 Capilano Computing 960 Quayside Dr., Suite 406 New Westminster, B.C. Canada V3M 6G2 (800) 444-9064 or (604) 552-6200 CINA, Inc. P.O. Box 4872 Mountain View, CA 94040 (415) 940-1723 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (89) 857-6667 ISDATA GmbH Daimlerstr. 51 D7500 Karlsruhe 21 Germany Germany: 0721/75 10 87 Logic Modeling 19500 NW Gibbs Dr. P.O. Box 310 Beaverton, OR 97075 (503) 690-6900 Logical Devices, Inc. 692 S. Military Trail Deerfield Beach, FL 33442 (800) 331-7766 or (305) 428-6868 MACHXL  Software Ver. 2.0 ComposerPIC TM Designer (Requires MACH Fitter) Verilog, LeapFrog, RapidSim Simulators (Models also available from Logic Modeling) Ver. 3.3 LOG/iCTM Software (Requires MACH Fitter) ABEL TM -5 Software (Requires MACH Fitter) SynarioTM Software MacABEL TM Software (Requires SmartPart MACH Fitter) AMD-ABEL Software Data I/O MACH Fitters PROdeveloper/AMD Software PROsynthesis/AMD Software Design Center/AMD Software SmartModel Library SmartCAT Circuit Analyzer PLDSim 90 CUPL TM Software

MANUFACTURER TEST GENERATION SYSTEM Acugen Software, Inc. 427-3 Amherst St., Suite 391 Nashua, NH 03063 (603) 891-1995 iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (87) 857-6667 DEVELOPMENT SYSTEMS (subject to change) (continued) Advanced Micro Devices is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by AMD of these products. ATGEN TM Test Generation Software MultiSIM Interactive Simulator LASAR PLDCheck 90 MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS Mentor Graphics Corp. 8005 S.W. Boeckman Rd. Wilsonville, OR 97070-7777 (800) 547-3000 or (503) 685-7000 MicroSim Corp.

20 Fairbanks

Irvine, CA 92718 (714) 770-3022 MINC Incorporated

6755 Earl Drive, Suite 200

Colorado Springs, CO 80918 (800) 755-FPGA or (719) 590-1155 OrCAD 3175 N.W. Aloclek Dr. Hillsboro, OR 97124 (503) 690-9881 SUSIE–CAD

10000 Nevada Highway, Suite 201

Boulder City, NV 89005 (702) 293-2271 Teradyne EDA 321 Harrison Ave. Boston, MA 02118 (800) 777-2432 or (617) 422-2793 Viewlogic Systems, Inc.

293 Boston Post Road West

Marlboro, MA 01752 (800) 442-4660 or (508) 480-0881 Programmable Logic Design Tools 386+ Schematic Design Tool 386+ Digital Simulation Tools ViewPLD or PROPLD (Requires PROSim Simulator MACH Fitter) ViewSim Simulator (Models for ViewSim also available from Logic Modeling) PLDesigner TM -XL Software (Requires MACH Fitter) PLDSynthesisTM (Requires MACH Fitter) QuickSim Simulator (Models also available from Logic Modeling) Design Center Software (Requires MACH Fitter) SUSIE TM Simulator

APPROVED PROGRAMMERS (subject to change) For more information on the products listed below, please consult the AMD FusionPLD Catalog. MANUFACTURER PROGRAMMER CONFIGURATION Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, CA 94086 (408) 243-7000 BP Microsystems 100 N. Post Oak Rd. Houston, TX 77055-7237 (800) 225-2102 or (713) 688-4600 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 Logical Devices Inc./Digelec 692 S. Military Trail Deerfield Beach, FL 33442 (800) 331-7766 or (305) 428-6868 SMS North America, Inc.

16522 NE 135th Place

Redmond, WA 98052 (800) 722-4122 or SMS lm Grund 15 D-7988 Vangen Im Allgau, Germany 07522-5018 Stag Microsystems Inc. 1600 Wyatt Dr. Suite 3 Santa Clara, CA 95054 (408) 988-1118 or Stag House Martinfield, Welwyn Garden City Herfordshire UK AL7 1JT 707-332148 System General 510 S. Park Victoria Dr. Milpitas, CA 95035 (408) 263-6667 or 3F, No. 1, Alley 8, Lane 45 Bao Shing Rd., Shin Diau Taipei, Taiwan 2-917-3005 BP1200 Pilot U84 Model 3900 Turpro-1 UniSiteTM AutoSite Stag Quazar Sprint/Expert ALLPRO TM –88 MANUFACTURER PROGRAMMER CONFIGURATION Corelis, Inc.

12607 Hidden Creek Way, Suite H

Cerritos, California 70703 (310) 926-6727 Advanced Micro Devices P.O. Box 3453, MS-1028 Sunnyvale, CA 94088-3453 (800) 222-9323 MACHpro JTAG PROG APPROVED ON-BOARD PROGRAMMERS

PROGRAMMER SOCKET ADAPTERS (subject to change) MANUFACTURER PART NUMBER EDI Corporation P.O. Box 366 Patterson, CA 95363 (209) 892-3270 Emulation Technology 2344 Walsh Ave., Bldg. F Santa Clara, CA 95051 (408) 982-0660 Logical Systems Corp. P.O. Box 6184 Syracuse, NY 13217-6184 (315) 478-0722 Procon Technologies, Inc.

1333 Lawrence Expwy, Suite 207

Santa Clara, CA 95051 (408) 246-4456 Contact Manufacturer Contact Manufacturer Contact Manufacturer Contact Manufacturer

PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches) TOP VIEW SEATING PLANE .685 .695 .650 .656 Pin 1 I.D. .685 .695 .650 .656 .026 .032 .050 REF .042 .056 .062 .083 .013 .021 .590 .630 .500 REF .009 .015 .165 .180 .090 .120 16-038-SQ PL 044 DA78 6-28-94 ae SIDE VIEW

PHYSICAL DIMENSIONS* PQT044 44-Pin Thin Quad Flat Pack (measured in millimeters) 1.00 REF.

1.20 MAX

11° – 13° 11° – 13°

0.80 BSC

0.95 1.05 0.30 0.45 11.80 12.20 9.80 10.20 11.80 12.20 9.80 10.20 16-038-PQT-2_AH PQT 44 5-4-95 ae *For reference only. BSC is an ANSI standard for Basic Space Centering. Trademarks Copyright  1995 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.