Logic IC

MACH111-5

Advanced Micro Devices

High-Performance EE CMOS Programmable Logic

Manufacturer: Advanced Micro Devices

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Publication# 20420 Rev: B Amendment/+1 Issue Date: June 1998 MACH 111-5/7/10/12/15 High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS u

44 Pins in PLCC and TQFP

32 Macrocells

u 5 ns t PD Commercial, 7.5 ns t PD Industrial u

182 MHz f

32 I/Os; 4 dedicated inputs/clocks; 2 dedicated inputs

32 Flip-ﬂops; 4 clock choices

u 2 “PALCE26V16” blocks u SpeedLocking™ for guaranteed ﬁxed timing u Bus-Friendly™ Inputs and I/Os u Peripheral Component Interconnect (PCI) compliant (-5/-7/-10/-12) u Programmable power-down mode u Safe for mixed supply voltage system designs u Pin-compatible with the MACH211 GENERAL DESCRIPTION The MACH111 is a member of Vantis’ high-performance EE CMOS MACH 1 & 2 families. This device has approximately three times the logic macrocell capability of the popular PALCE22V10 without loss of speed. The MACH111 consists of two PAL blocks interconnected by a programmable switch matrix. The two PAL blocks are essentially “PALCE26V16” structures complete with product-term arrays and programmable macrocells, which can be programmed as high speed or low power. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully connected PAL blocks. This allows designs to be placed and routed efﬁciently. The MACH111 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered conﬁguration is chosen, the register can be conﬁgured as D-type or T- type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. Vantis offers software design support for MACH devices through its own development system and device ﬁtters integrated into third-party CAE tools. Platform support extends across PCs, Sun and HP workstations under advanced operating systems such as Windows 3.1, Windows 95 and NT, SunOS and Solaris, and HPUX.

2 MACH111-5/7/10/12/15

software is a complete development system for the PC, supporting Vantis' MACH devices. It supports design entry with Boolean and behavioral syntax, state machine syntax and truth tables. Functional simulation and static timing analysis are also included in this easy-to- use system. This development system includes high-performance device ﬁtters for all MACH devices. The same ﬁtter technology included in MACHXL software is seamlessly incorporated into third-party tools from leading CAE vendors such as Synario, Viewlogic, Mentor Graphics, Cadence and MINC. Interface kits and MACHXL conﬁgurations are also available to support design entry and veriﬁcation with other leading vendors such as Synopsys, Exemplar, OrCAD, Synplicity and Model Technology. These MACHXL conﬁgurations and interfaces accept EDIF 2.0.0 netlists, generate JEDEC ﬁles for MACH devices, and create industry-standard SDF, VITAL-compliant VHDL and Verilog output ﬁles for design simulation. Vantis offers in-system programming support for MACH devices through its MACHPRO software enabling MACH device programmability through JTAG compliant ports and easy-to-use PC interface. Additionally, MACHPRO generated vectors work seamlessly with HP3070, GenRad and Teradyne testers to program MACH devices or test them for connectivity. All MACH devices are supported by industry standard programmers available from a number of vendors. These programmer vendors include Advin Systems, BP Microsystems, Data I/O Corporation, Hi-Lo Systems, SMS GmbH, Stag House, and System General.

I/O0 – I/O15 I/O Cells Macrocells Switch Matrix OE 20420B-1 52 x 70 AND Logic Array and Logic Allocator I/O16 – I/O31 CLK 3/I5 CLK 1/I2 I/O Cells Macrocells OE 1616 I0-I1/CLK0 I3-I4/CLK2 Block A Block B

4 MACH111-5/7/10/12/15

Note: Pin-compatible with the MACH211SP and MACH211. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage Block A Block B 1 44 43 425 4 3 264 1 40 23 24 25 2619 20 21 2218 27 28 I/O5 I/O6 I/O7 CLK0/I1 GND CLK1/I2 I/O8 I/O9 I/O10 I/O11 I/O27 I/O26 I/O25 I/O24 CLK3/I5 GND CLK2/I4 I/O23 I/O22 I/O21 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 20420B-2

Note: Pin-compatible with the MACH211SP. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V CC = Supply Voltage Block B Block A I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 CLK3/I5 GND CLK2/I4 I/O23 I/O22 I/O21 I/O5 I/O6 I/O7 CLK0/I1 GND CLK1/I2 I/O8 I/O9 I/O10 I/O11 20420B-3

6 MACH111-5/7/10/12/15 (Com’l)

ORDERING INFORMATION

Vantis programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: Valid Combinations The Valid Combinations table lists conﬁgurations planned to be supported in volume for this device. Consult the local Vantis sales ofﬁce to conﬁrm availability of speciﬁc valid combinations and to check on newly released combinations. FAMILY TYPE MACH = Macro Array CMOS High-Speed MACH 111 -5 J C DEVICE NUMBER 111 = 32 Macrocells, 44 Pins, Power-Down option, Bus-Friendly Inputs OPERATING CONDITIONS C = Commercial (0°C to +70°C) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) V = 44-Pin Thin Quad Flat Pack (PQT044) SPEED -5 = 5 ns t PD -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD Valid Combinations MACH111-5 JC, VC MACH111-7 MACH111-10 MACH111-12 MACH111-15

MACH111-7/10/12/14/18 (Ind) 7 Vantis programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: Valid Combinations The Valid Combinations table lists conﬁgurations planned to be supported in volume for this device. Consult the local Vantis sales ofﬁce to conﬁrm availability of speciﬁc valid combinations and to check on newly released combinations. DEVICE NUMBER 111 = 32 Macrocells, 44 Pins, Power-Down option, Bus-Friendly Inputs FAMILY TYPE MACH = Macro Array CMOS High-Speed MACH 111 -7 J I OPERATING CONDITIONS I = Industrial (–40 °C to +85°C) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -14 = 14 ns tPD -18 = 18 ns tPD Valid Combinations MACH111-7 JI MACH111-10 MACH111-12 MACH111-14 MACH111-18

8 MACH111-5/7/10/12/15

allocator, 16 macrocells, and 16 I/O cells. The switch matrix feeds each PAL block with 26 inputs. the output enable product terms. ﬂip-ﬂop initialization. All ﬂip-ﬂops within the PAL block are initialized together. two control the last eight macrocells. software automatically conﬁgures the logic allocator when ﬁtting the design into the device. block. Refer to Figure 1 for cluster and macrocell numbers. Table 1. Logic Allocation

The MACH111 macrocells can be conﬁgured as either registered or combinatorial, with programmable polarity. The macrocell provides internal feedback whether conﬁgured as registered or combinatorial. The ﬂip-ﬂops can be conﬁgured as D-type or T-type, allowing for product-term optimization. The ﬂip-ﬂops can individually select one of four clock pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The ﬂip-ﬂops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The I/O Cell The I/O cell in the MACH111 consists of a three-state output buffer. The three-state buffer can be conﬁgured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to eight I/O cells. Within each PAL block, two product terms are available for selection by the ﬁrst eight three-state outputs; two other product terms are available for selection by the last eight three-state outputs. SpeedLocking for Guaranteed Fixed Timing The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in both raw speed, but even more importantly, guaranteed ﬁxed speed. Using the design of the central switch matrix, the MACH111 product offers the SpeedLocking feature, which allows a stable ﬁxed pin-to-pin delay, independent of logic paths, routing resources and design reﬁts for up to 12 product terms per output. Other non-Vantis CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product-term limits. Speed and SpeedLocking combine for continuous, high performance required in today's demanding designs. Bus-Friendly Inputs and I/Os The MACH111 inputs and I/Os include two inverters in series which loop back to the input. This double inversion reinforces the state of the input and pulls the voltage away from the input threshold voltage. Unlike a pull-up, this conﬁguration cannot cause contention on a bus. For an illustration of this conﬁguration, please turn to the Input/Output Equivalent Schematics section. PCI Compliant The MACH111-5/7/10/12 is fully compliant with the PCI Local Bus Speciﬁcation published by the PCI Special Interest Group. The MACH111-5/7/10/12’s predictable timing ensures compliance with the PCI AC speciﬁcations independent of the design. Power-Down Mode The MACH111 features a programmable low-power mode in which individual signal paths can be programmed as low power. These low-power speed paths will be slightly slower than the non-low-power paths. This feature allows speed critical paths to run at maximum frequency while the rest of the paths operate in the low-power mode, resulting in power savings of up to 50%. Safe for Mixed Supply Voltage System Designs The MACH111 is safe for mixed supply voltage system designs. The 5-V device will not overdrive 3.3-V devices above the output voltage of 3.3 V, while it accepts inputs from other 3.3-V devices. Thus, the MACH111 provides easy-to-use mixed-voltage design compatibility.

10 MACH111-5/7/10/12/15

Figure 1. MACH111 PAL Block

MACH111-5/7/10/12/15 (Com’l) 11 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage with DC Output or Latchup Current (T Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Supply Voltage (VCC) Operating ranges deﬁne those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL operating ranges Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of I IL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter program in low-power mode. This pattern is programmed in each PAL block and is capable of being enabled and reset. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage I OH = –3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V VOL Output LOW Voltage I OL = 16 mA, VCC = Min, VIN = VIH or VIL 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Current V IN = 5.25 V, VCC = Max (Note 2) 10 mA IIL Input LOW Current V IN = 0 V, VCC = Max (Note 2) –10 mA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 mA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –10 mA ISC Output Short-Circuit Current V OUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA ICC Supply Current (Static) V CC = 5 V, TA = 25°C, f = 0 MHz (Note 4) 40 mA Supply Current (Active) V CC = 5 V, TA = 25°C, f = 1 MHz (Note 4) 45 mA

12 MACH111-5/7/10/12/15 (Com’l)

CAPACITANCE (Note 1) SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiﬁed where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = VCC –0.5 V VCC = 5.0 V, TA = 25°C f = 1 MHz 6p F COUT Output Capacitance V OUT = 2.0 V 8 pF Paramete r Symbol Parameter Description -5 -7 -10 -12 -15 UnitMin Max Min Max Min Max Min Max Min Max tPD Input, I/O, or Feedback to Combinatorial Output 5 7.5 10 12 15 ns tS Setup Time from Input, I/O, or Feedback to Clock D-type 3.5 5.5 6.5 7 10 ns T-type 4 6.5 7.5 8 11 ns tH Register Data Hold Time 0 0 0 0 0 ns tCO Clock to Output 3.5 5 6 8 10 ns tWL Clock Width LOW 2.5 3 5 6 6 ns tWH HIGH 2.5 3 5 6 6 ns fMAX Maximum Frequency (Note 1) External Feedback 1/(t S + tCO) D-type 143 95 80 66.7 50 MHz T-type 133 87 74 62.5 47.6 MHz Internal Feedback (fCNT) D-type 182 133 100 76.9 66.6 MHz T-type 167 125 91 71.4 55.5 MHz No Feedback 1/(tWL + tWH) 200 166.7 100 83.3 83.3 MHz tAR Asynchronous Reset to Registered Output 7.5 9.5 11 16 20 ns tARW Asynchronous Reset Width (Note 1) 4.5 5 7.5 12 15 ns tARR Asynchronous Reset Recovery Time 4.5 5 7.5 8 10 ns tAP Asynchronous Preset to Registered Output 7.5 9.5 11 16 20 ns tAPW Asynchronous Preset Width (Note 1) 4.5 5 7.5 12 15 ns tAPR Asynchronous Preset Recovery Time (Note 1) 4.5 5 7.5 8 10 ns tEA Input, I/O, or Feedback to Output Enable 7.5 9.5 10 12 15 ns tER Input, I/O, or Feedback to Output Disable 7.5 9.5 10 12 15 ns tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 3) 77 77 7 n s tLPCO tCO Increase for Powered-down Macrocell (Note 3) 33 33 3 n s tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 ns

MACH111-7/10/12/14/18 (Ind) 13 ABSOLUTE MAXIMUM RATINGS Ambient Temperature Supply Voltage DC Output Latchup Current (T Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device r eliability. OPERATING RANGES Industrial (I) Devices Temperature (TA) Supply Voltage (VCC) Operating ranges deﬁne those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over INDUSTRIAL operating ranges Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of I IL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. Measured with a 16-bit up/down counter program in low-power mode. This pattern is programmed in each PAL block and is capable of being enabled and reset. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit VOH Output HIGH Voltage I OH = –3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V VOL Output LOW Voltage I OL = 16 mA, VCC = Min, VIN = VIH or VIL 0.5 V VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) 2.0 V VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Current V IN = 5.25 V, VCC = Max (Note 2) 10 mA IIL Input LOW Current V IN = 0 V, VCC = Max (Note 2) –10 mA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 mA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –10 mA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –30 –160 mA ICC Supply Current (Static) V CC = 5 V, TA = 25°C, f = 0 MHz (Note 4) 40 mA Supply Current (Active) V CC = 5 V, TA = 25°C, f = 1 MHz (Note 4) 45 mA

14 MACH111-7/10/12/14/18 (Ind)

CAPACITANCE (Note 1) SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modiﬁed where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter. Parameter Symbol Parameter Description Test Conditions Typ Unit C IN Input Capacitance V IN = VCC –0.5 V VCC = 5.0 V, TA = 25°C f = 1 MHz 6p F COUT Output Capacitance V OUT = 2.0 V 8 pF Parameter Symbol Parameter Description -7 -10 -12 -14 -18 UnitMin Max Min Max Min Max Min Max Min Max tPD Input, I/O, or Feedback to Combinatorial Output 7.5 10 12 14 18 ns tS Setup Time from Input, I/O, or Feedback to Clock D-type 5.5 6.5 7 8.5 12 ns T-type 6.5 7.5 8 10 13.5 ns tH Register Data Hold Time 0 0 0 0 0 ns tCO Clock to Output 5 6 8 10 12 ns tWL Clock Width LOW 3 5 6 6 7.5 ns tWH HIGH 3 5 6 6 7.5 ns fMAX Maximum Frequency (Note 1) External Feedback 1/(t S + tCO) D-type 95 80 66.7 54 40 MHz T-type 87 74 62.5 50 38 MHz Internal Feedback (fCNT) D-type 133 100 76.9 61.5 53 MHz T-type 125 91 71.4 57 44 MHz No Feedback 1/(tWL + tWH) 166.7 100 83.3 83.3 61.5 MHz tAR Asynchronous Reset to Registered Output 9.5 11 16 19.5 24 ns tARW Asynchronous Reset Width (Note 1) 5 7.5 12 14.5 18 ns tARR Asynchronous Reset Recovery Time 5 7.5 8 10 12 ns tAP Asynchronous Preset to Registered Output 9.5 11 16 19.5 24 ns tAPW Asynchronous Preset Width (Note 1) 5 7.5 12 14.5 18 ns tAPR Asynchronous Preset Recovery Time 5 7.5 8 10 12 ns tEA Input, I/O, or Feedback to Output Enable (Note 1) 9.5 10 12 14.5 18 ns tER Input, I/O, or Feedback to Output Disable (Note 1) 9.5 10 12 14.5 18 ns tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 ns tLPS tS Increase for Powered-down Macrocell (Note 3) 77777 n s tLPCO tCO Increase for Powered-down Macrocell (Note 3) 33333 n s tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 ns

TYPICAL CURRENT vs. VOLTAGE (I-V) CHARACTERISTICS VCC = 5.0 V, TA = 25°C -20 -40 -60 -80 20420B-5Output, LOW VOL (V) IOL (mA) 20420B-7Input II (mA) VI (V) -40 -60 -80 -2 -1 123 -20 -100 20420B-6 IOH (mA) VOH (V) -50 -75 -100 -3 -2 -1 123 -25 -125 -150 Output, HIGH

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TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. High Speed 150 125 100 0 1 02 03 04 05 06 07 08 09 0 ICC (mA) Frequency (MHz) Low Power 100 110 120 130 140 150 20420B-6

TYPICAL THERMAL CHARACTERISTICS Measured at 25°C ambient. These parameters are not tested. Plastic qjc Considerations The data listed for plastic qjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-ﬂow paths in plastic-encapsulated devices are complex, making the qjc measurement relative to a speciﬁc location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, qjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. The thermal measurements are taken with components on a six-layer printed circuit board. SWITCHING WAVEFORMS Notes: 1. V T = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. Parameter Symbol Parameter Description Typ UnitTQFP PLCC q jc Thermal impedance, junction to case 11 15 °C/W qja Thermal impedance, junction to ambient 40 24 °C/W qjma Thermal impedance, junction to ambient with air ﬂow 200 lfpm air 35 18 °C/W 400 lfpm air 33 17 °C/W 600 lfpm air 32 16 °C/W 800 lfpm air 31 15 °C/W 20420B-7 Combinatorial Output tPD Input, I/O, or Feedback Combinatorial Output VT VT 20420B-8 20420B-9 Registered Output Clock Width VT Input, I/O, or Feedback Registered Output tS tCO VT tH VTClock tWH Clock tWL

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Notes: 1. V T = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns–4 ns typical. VT VT tARW VT tAR Input, I/O, or Feedback Registered Output Clock tARR 20420B-10 Asynchronous Reset Input, I/O, or Feedback VT VT tAPW VT tAP tAPR Registered Output Clock 20420B-11 Asynchronous Preset 20420B-12 Output Disable/Enable VT VTOutputs tER tEA VOH – 0.5 V VOL + 0.5 V Input, I/O, or Feedback

KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUIT* * Switching several outputs simultaneously should be avoided for accurate measurement. Speciﬁcation S 1 C L Commercial Measured Output ValueR 1 R 2 tPD, tCO Closed 35 pF

300 W 390 W

1.5 V tEA Z ﬁ H: Open Z ﬁ L: Closed tER H ﬁ Z: Open L ﬁ Z: Closed 5 pF H ﬁ Z: VOH – 0.5 V L ﬁ Z: VOL + 0.5 V Must be Steady May Change from H to L May Change from L to H Does Not Apply Don’t Care, Any Change Permitted Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is High- Impedance “Off” State WAVEFORM INPUTS OUTPUTS KS000010-PAL 20420B-13 C L Output R 1 R 2 Test Point 5 V

20 MACH111-5/7/10/12/15

The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the ﬂexibility inherent in programmable logic devices offers a choice of clocked ﬂip-ﬂop designs, f MAX is speciﬁed for three types of synchronous designs. The ﬁrst type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path deﬁning the period is the sum of the clock-to-output time and the input setup time for the external signals (t S + tCO). The reciprocal, f MAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This f MAX is designated “fMAX external.” The second type of design is a single-chip state machine with internal feedback only. In this case, ﬂip-ﬂop inputs are deﬁned by the device inputs and ﬂip-ﬂop outputs. Under these conditions, the period is limited by the internal delay from the ﬂip-ﬂop outputs through the internal feedback and logic to the ﬂip-ﬂop inputs. This f MAX is designated “fMAX internal”. A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called “f CNT.” The third type of design is a simple data path application. In this case, input data is presented to the ﬂip-ﬂop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (t S + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated “fMAX no feedback.” All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly. LOGIC REGISTER CLK LOGIC REGISTER CLK tCOtS tS fMAX Internal (fCNT ) fMAX External 1/(ts + tCO ) tS LOGIC REGISTER CLK fMAX No Feedback; 1/(ts + tH ) or 1/(tWH + tWL ) (SECOND CHIP) 20420B-14

The MACH families are manufactured using Vantis’ advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Endurance Characteristics INPUT/OUTPUT EQUIVALENT SCHEMATICS Parameter Symbol Parameter Description Units Test Conditions tDR Min Pattern Data Retention Time

10 Years Max Storage Temperature

20 Years Max Operating Temperature

N Max Reprogramming Cycles 100 Cycles Normal Programming Conditions VCC ESD Protection 1 kW Input VCC 100 kW Preload Circuitry Feedback Input I/O VCCVCC 100 kW 1 kW 20420B-15

22 MACH111-5/7/10/12/15

The MACH devices have been designed with the capability to reset during system power-up. Following power-up, all ﬂip-ﬂops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra ﬂexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways V CC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Descriptions Max Unit tPR Power-Up Reset Time 10 ms tS Input or Feedback Setup Time See Switching Characteristics tWL Clock Width LOW 20420B-16 Power-Up Reset Waveform tPR tWL tS 4 V VCC Power Registered Output Clock

DEVELOPMENT SYSTEMS (subject to change) For more information on the products listed below, please consult the local Vantis sales ofﬁce. MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS Vantis Corporation P.O. Box 3755

920 DeGuigne Drive

Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com MACHXL Software Vantis-ABEL Software Vantis-Synario Software Aldec, Inc.

3 Sunset Way, Suite F

Henderson, NV 89014 (702) 456-1222 or (800) 487-8743 ACTIVE-CAD Cadence Design Systems

555 River Oaks Pkwy

San Jose, CA 95134 (408) 943-1234 or (800) 746-6223 PIC Designer Concept/Composer Synergy Leapfrog/Verilog-XL Exemplar Logic, Inc.

815 Atlantic Avenue, Suite 105

Alameda, CA 94501 (510) 337-3700 Leonardo™ Galileo™ Logic Modeling 19500 NW Gibbs Dr. P.O. Box 310 Beaverton, OR 97075 (800) 346-6335 SmartModel ® Library Mentor Graphics Corp. 8005 S.W. Boeckman Rd. Wilsonville, OR 97070-7777 (800) 547-3000 or (503) 685-7000 Design Architect, PLDSynthesis™ II Autologic II Synthesizer, QuickSim Simulator, QuickHDL Simulator MicroSim Corp.

20 Fairbanks

Irvine, CA 92718 (714) 770-3022 MicroSim Design Lab PLogic, PLSyn MINC Inc.

6755 Earl Drive, Suite 200

Colorado Springs, CO 80918 (800) 755-FPGA or (719) 590-1155 PLDesigner-XL™ Software Model Technology 8905 S.W. Nimbus Avenue, Suite 150 Beaverton, OR 97008 (503) 641-1340 V-System/VHDL OrCAD, Inc. 9300 S.W. Nimbus Avenue Beaverton, OR 97008 (503) 671-9500 or (800) 671-9505 OrCAD Express Synario ® Design Automation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 ABEL™ Synario™ Software

24 MACH111-5/7/10/12/15

Vantis is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by Vantis of these products. Synopsys 700 E. Middleﬁeld Rd. Mountain View, CA 94040 (415) 962-5000 or (800) 388-9125 FPGA or Design Compiler (Requires MINC PLDesigner-XL™) VSS Simulator Synplicity, Inc. 624 East Evelyn Ave. Sunnyvale, CA 94086 (408) 617-6000 Synplify Teradyne EDA 321 Harrison Ave. Boston, MA 02118 (800) 777-2432 or (617) 422-2793 MultiSIM Interactive Simulator LASAR VeriBest, Inc.

6101 Lookout Road, Suite A

Boulder, CO 80301 (800) 837-4237 VeriBest PLD Viewlogic Systems, Inc.

293 Boston Post Road West

Marlboro, MA 01752 (800) 873-8439 or (508) 480-0881 Viewdraw, ViewPLD, Viewsynthesis Speedwave Simulator, ViewSim Simulator, VCS Simulator MANUFACTURER TEST GENERATION SYSTEM Acugen Software, Inc. 427-3 Amherst St., Suite 391 Nashua, NH 03063 (603) 881-8821 ATGEN™ Test Generation Software iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (87) 857-6667 PLDCheck 90 MANUFACTURER SOFTWARE DEVELOPMENT SYSTEMS

APPROVED PROGRAMMERS (SUBJECT TO CHANGE) For more information on the products listed below, please consult the local Vantis sales ofﬁce. MANUFACTURER PROGRAMMER CONFIGURATION Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, CA 940 86 (408) 243-7000 or (800) 627-2456 BBS (408) 737-9200 Fax (408) 736-2503 Pilot-U40 Pilot-U84 MVP BP Microsystems 1000 N. Post Oak Rd., Suite 225 Houston, TX 77055-7237 (800) 225-2102 or (713) 688-4600 BBS (713) 688-9283 Fax (713) 688-0920 BP1200 BP1400 BP2100 BP2200 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 426-1045 or (206) 881-6444 BBS (206) 882-3211 Fax (206) 882-1043 UniSite™ Model 2900 Model 3900 AutoSite Hi-Lo Systems 4F, No. 2, Sec. 5, Ming Shoh E. Road Taipei, Taiwan (886) 2-764-0215 Fax (886) 2-756-6403 or Tribal Microsystems / Hi-Lo Systems 44388 South Grimmer Blvd. Fremont, CA 94538 (510) 623-8859 BBS (510) 623-0430 Fax (510) 623-9925 ALL-07 FLEX-700 SMS GmbH Im Grund 15

88239 Wangen

(49) 7522-97280 Fax (49) 7522-972850 or SMS USA 544 Weddell Dr. Suite 12 Sunnyvale, CA 94089 (408) 542-0388 Sprint Expert Sprint Optima Multisite Stag House Silver Court Watchmead, Welwyn Garden City Herfordshire UK AL7 1LT 44-1-707-332148 Fax 44-1-707-371503 Stag Quazar

26 MACH111-5/7/10/12/15

APPROVED ADAPTER MANUFACTURERS APPROVED ON-BOARD ISP PROGRAMMING TOOLS System General 1603A South Main Street Milpitas, CA 95035 (408) 263-6667 BBS (408) 262-6438 Fax (408) 262-9220 or 3F, No. 1, Alley 8, Lane 45 Bao Shing Road, Shin Diau Taipei, Taiwan (886) 2-917-3005 Fax (886) 2-911-1283 Turpro-1 Turpro-1/FX Turpro-1/TX MANUFACTURER PROGRAMMER CONFIGURATION California Integration Coordinators, Inc.

656 Main Street

Placerville, CA 95667 (916) 626-6168 Fax (916) 626-7740 MACH/PAL Programming Adapters Emulation Technology, Inc. 2344 Walsh Ave., Bldg. F Santa Clara, CA 95051 (408) 982-0660 Fax (408) 982-0664 Adapt-A-Socket Programming Adapters MANUFACTURER PROGRAMMER CONFIGURATION Corelis, Inc.

12607 Hidden Creek Way, Suite H

Cerritos, California 70703 (310) 926-6727 JTAGPROG™ Vantis Corporation P.O. Box 3755 Sunnyvale, CA 94088 (408) 732-0555 or 1(888) 826-8472 (VANTIS2) http://www.vantis.com MACHPRO MANUFACTURER PROGRAMMER CONFIGURATION

44-Pin Plastic Leaded Chip Carrier (measured in inches) TOP VIEW SEATING PLANE .685 .695 .650 .656Pin 1 I.D. .685 .695 .650 .656 .026 .032 .050 REF .042 .056 .062 .083 .013 .021 .590 .630 .500 REF .009 .015 .165 .180 .090 .120 16-038-SQ PL 044 DA78 6-28-94 ae SIDE VIEW

28 MACH111-5/7/10/12/15

44-Pin Thin Quad Flat Pack (measured in millimeters) Trademarks Copyright ª 1998 Vantis Corporation. All rights reserved. AMD is a registered trademark of Advanced Micro Devices, Inc. Vantis, the Vantis logo and combinations thereof, SpeedLocking and Bus-Friendly are trademarks, and MACH, MACHXL, MACHPRO and PAL are registered trademarks of Vantis Corporation. Other product names used in this publication are for identiﬁcation purposes only and may be trademarks of their respective comp anies. 1.00 REF.

1.20 MAX

11° – 13° 11° – 13°

0.80 BSC

0.95 1.05 11.80 12.20 9.80 10.20 11.80 12.20 9.80 10.20 0.30 0.45 16-038-PQT-2 PQT 44 7-11-95 ae

Product Information

MACH111-5 specifications and overview.

Summary

High-Performance EE CMOS Programmable Logic

Description

High-Performance EE CMOS Programmable Logic

Source title MACH111-5 Datasheet(PDF) - Advanced Micro Devices

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