M80C85

MSM80C85AHRS OKI | Alldatasheet

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Technical content

¡ Semiconductor MSM80C85AHRS/GS/JS GENRAL DESCRIPTION The MSM80C85AH is a complete 8-bit parallel; central processor implemented in silicon gate C-MOS technology and compatible with MSM80C85A. It is designed with higher processing speed (max.5 MHz) and lower power consumption compared with MSM80C85A and power down mode is provided, thereby offering a high level of system integration. The MSM80C85AH uses a multiplexed address/data bus. The address is split between the 8- bit address bus and the 8-bit data bus. The on-chip address latch : of a MSM81C55-5 memory product allows a direct interface with the MSM80C85AH.

FEATURES

• Power down mode (HALT-HOLD)
• Low Power Dissipation: 50mW(Typ)
• Single + 3 to + 6 V Power Supply
• –40 to + 85°C, Operating Temperature
• Compatible with MSM80C85A
• 0.8 ms instruction Cycle (V CC = 5V)
• On-Chip Clock Generator (with External Crystal)
• On-Chip System Controller; Advanced Cycle Status Information Available for Large System Control
• Bug operation in MSM80C85AH is fixed
• Four Vectored interrupt (One is non-maskable) Plus the 8080A-compatible interrupt.
• Serial, In/Serial Out Port
• Decimal, Binary and Double Precision Arithmetic
• Addressing Capability to 64K Bytes of Memory
• TTL Compatible
• 40-pin Plastic DIP(DIP40-P-600-2.54): (Product name: MSM80C85AHRS)
• 44-pin Plastic QFJ(QFJ44-P-S650-1.27): (Product name: MSM80C85AHJS)
• 44-pin Plastic QFP(QFP44-P-910-0.80-2K): (Product name: MSM80C85AHGS-2K) ¡ Semiconductor MSM80C85AHRS/GS/JS 8-Bit CMOS MICROPROCESSOR E2O0009-27-X2 This version: Jan. 1998 Previous version: Aug. 1996

¡ Semiconductor MSM80C85AHRS/GS/JS FUNCTIONAL BLOCK DIAGRAM INTR INTA 5.5 6.5 7.5 TRAP SID SOD RST Power Down Temporary Register (8) Arithmetic Logic Unit ALU(8) Instruction Register (8) Instruction Decoder And Machine Cycle Encoding Flag (5) Flip Flops CLK GEN Timing And Control Control Status DMA Reset Address Buffer (8) Data/Address Buffer (8) Stack Pointer (16) Program Counter (16) Register Array Incrementer/Decrementer Address Latch (16) H REG (8) D REG (8) B REG (8) C REG (8) E REG (8) C REG (8) 8-Bit Internal Data Bus CLK OUT READY RD WR ALE S0 S1 IO / M HOLD HLDA RESET IN RESET OUT A15 - A8 Address Bus AD7 - AD0 Address/Data Bus Interrupt Control Serial I/O Control Accumulator (8) Power Supply +5V GND

¡ Semiconductor MSM80C85AHRS/GS/JS PIN CONFIGURATION (TOP VIEW) 40 pin Plastic DIP X GND HOLD HLDA CLK(OUT) RESET IN READY IO/M S RD WR ALE S A15 A14 A13 A12 A11 A10 V CC AD5 AD6 AD7 RST7.5 RST6.5 RST5.5 INTR INTA AD AD1 AD2 AD3 AD4 RESET OUT SOD SID TRAP 44 pin Plastic QFP READY IO/M S RD WR NC ALE TRAP RST7.5 RST6.5 RST5.5 INTR NC INTA AD NC AD5 AD6 AD7 GND SID SOD RESET OUT X NC S A15 A14 AD0 AD1 AD2 AD3 17 A VCC A A10 A11 A12 HOLD HLDA CLK(OUT) RESET IN 44 pin Plastic QFJ READY IO/M S RD WR ALE S TRAP RST7.5 RST6.5 RST5.5 INTR INTA AD AD AD5 AD6 AD7 GND VCC SID SOD RESET OUT X NC A A14 A13 AD1 AD2 AD3 NC 11 A VCC A A10 A11 NC HOLD HLDA CLK(OUT) RESET IN

¡ Semiconductor MSM80C85AHRS/GS/JS MSM80C85AH FUNCTIONAL PIN DEFINITION The following describes the function of each pin: A0 - A7 (Input/Output) 3-state A8 - A15 (Output, 3-state) Multiplexed Address/Data Bus: Lower 8-bits of the memory address (or I/O address) appear on the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second and third clock cycles. Address Bus: The most significant 8-bits of the memory address or the 8-bits of the I/O address, 3-stated during Hold and Halt modes and during RESET. Symbol Function ALE (Output) Address Latch Enable: It occurs during the first clock state of a machine cycle and enables address to get latched into the on-chip latch peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. The falling edge ALE can also be used to strobe the status information ALE is never 3-state. S 0 , S1 , IO/M (Output) Machine cycle status: IO/M S1 S0 States S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of these lines. RD (Output, 3-state) READ control: A low level on RD indicates the selected memory or I/O device is to be read that the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RESET. WR (Output, 3-state) WRITE control: A low level on WR indicates the data on the Data Bus is to be written into the selected memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and Halt modes and during RESET. READY (Input) If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If READY is low, the cpu will wait an integral number of clock cycles for READY to go high before completing the read or write cycle READY must conform to specified setup and hold times. HOLD (Input) HLDA (Output) HOLD ACKNOWLEDGE: Indicates that the cpu has received the HOLD request and that it will relinquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The cpu takes the bus one half clock cycle after HLDA goes low. HOLD indicates that another master is requesting the use of the address and data buses. The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus transfer. Internal processing can continue. The processor can regain the bus only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3-stated. And status of power down is controlled by HOLD. INTR (Output) INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled on during the next to the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted. Power down mode is reset by INTR. INTA (Output) INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as) RD during the instruction cycle after an INTR is accepted. RST 5.5 RST 6.5 RST 7.5 (Input) RESTART INTERRUPTS: These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted. The priority of these interrupts is ordered as shown in Table 1. These interrupts have a higher priority than INTR. In addition, they may be individually masked out using the SIM instruction. Power down mode is reset by these interrupts. TRAP (Input) Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same timing as INTR or RST 5.5 - 7.5. It is unaffected by any mask or Interrupt Disable. It has the highest priority of any interrupt. (See Table 1.) Power down mode is reset by input of TRAP. Memory write Memory read I/O write I/O read Opcode fetch IO/M S

1 S0 States

• /CR
• /CR Interrupt Acknowledge Halt = 3-state Hold (high impedance) Reset · = unspecified

¡ Semiconductor MSM80C85AHRS/GS/JS Name Address Branched To (1) When Interrupt Occurs Type Trigger RST 7.5 3CH 34H Rising edge (latched). High level unitl sampled.RST 6.5 RST 5.5 2CH (2) High level until sampled. High level until sampled.INTR TRAP Priority 1 24H Rising edge and high level unit sampled. Table 1 Interrupt Priority, Restart Address, and Sensitivity Notes: (1) The processor pushes the PC on the stack before branching to the indicated address. (2) The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged. RESET IN (Input) Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops and release power down mode. The data and address buses and the control lines are 3-stated during RESET and because of the asynchronous nature of RESET IN, the processor's internal registers and flags may be altered by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connection to an R-C network for power-on RESET delay. The cpu is held in the reset condition as long as RESET IN is applied. Symbol Function RESET OUT (Output) Indicated cpu is being reset. Can be used as a system reset. The signal is synchronized to the processor clock and lasts an integral number of clock periods. X1, X2 (Input) X1 and X2 are connected to a crystal to drive the internal clock generator. X1 can also be an external clock input from a logic gate. The input frequency is divided by 2 to give the processor's internal operating frequency. SID (Input) Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. SOD (Output) Serial output data line. The output SOD is set or reset as specified by the SIM instruction. V CC + 5 Volt supply GND Ground Reference. CLK (Output) Clock Output for use as a system clock. The period of CLK is twice the X1, X2 input period.

¡ Semiconductor MSM80C85AHRS/GS/JS FUNCTIONAL DESCRIPTION The MSM80C85AH is a complete 8-bit parallel central processor. It is designed with silicon gate C-MOS technology and requires a single +5 volt supply. Its basic clock speed is 5 MHz, thus improving on the present MSM80C85A's performance with higher system speed and power down mode. Also it is designed to fit into a minimum system of two IC's: The CPU (MSM80C85AH), and a RAM/IO (MSM81C55-5) The MSM80C85AH has twelve addressable 8-bit register pairs. Six others can be used interchangeably as 8-bit registers or 16-bit register pairs. The MSM80C85AH register set is as follows: PC 16-bit address 8-bit · 6 or 16-bits · 3BC, DE, HL SP 16-bit address 5 flags (8-bit space)Flags or F Program Counter ACC or A 8-bitsAccumulator Mnemonic ContentsRegister General-Purpose Registers; data pointer (HL) Stack Pointer Flag Register The MSM80C85AH uses a multiplexed Data Bus. The address is spilt between the higher 8-bit Address Bus and the lower 8-bit Address/Data Bus. During the first T state (clock cycle) of a machine cycle the low order address is sent out on the Address/Data Bus. These lower 8-bits may be latched externally by the Address Latch Enable signal (ALE). During the rest of the machine cycle the data bus is used for mamory or I/O data. The MSM80C85AH provides RD, WR, S 0, S1, and IO/M signals for bus control. An Interrupt Acknowledge signal (INTA) is also provided. Hold and all Interrupts are synchronized with the processor's internal clock. The MSM80C85AH also provides Serial Input Data (SID) and Serial Output Data (SOD) lines for a simple serial interface. In addition to these features, the MSM80C85AH has three maskable, vector interrupt pins, one nonmaskable TRAP interrupt and power down mode with HALT and HOLD. INTERRUPT AND SERIAL I/O The MSM80C85AH has 5 interrupt inputs: INTR, RST 5.5 RST 6.5, RST 7.5, and TRAP. INTR is identical in function to the 8080A INT. Each of the three RESTART inputs, 5.5, 6.5, and 7.5, has a programmable mask. TRAP is also a RESTART interrupt but it is nonmaskable. The three maskable interrupts cause the internal execution of RESTART ( saving the program counter in the stack branching to the RESTART address) it the interrupts are enable and if the interrupt mask is not set. The nonmaskable TRAP causes the internal execution of a RESTART vector independent of the state of the interrupt enable or masks. (See Table 1.) There are two different types of inputs in the restart interrupt. RST 5.5 and RST 6.5 are high level-sensitive like INTR (and INT on the 8080A) and are recognized with the same timing as INTR. RST 7.5 is rising edge-sensitive.

¡ Semiconductor MSM80C85AHRS/GS/JS For RST 7.5, only a pulse is required to set an internal flip-flop which generates the internal interrupt request. The RST 7.5 request flip-flop remains set until the request is serviced. Then it is reset automatically, This flip-flop may also be reset by using the SIM instruction or by issuing a RESET␣ IN to the MSM80C85AH. The RST 7.5 internal flip-flop will be set by a pulse on the RST 7.5 pin even when the RST 7.5 interrupt is masked out. The interrupts are arranged in a flixed priority that determines which interrupt is to be recognized if more than one is pending, as follows: TRAP-highest priority, RST 7.5, RST 6.5, RST 5.5, INTR-lowest priority. This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt an RST 7.5 routine if the interrupt are re-enabled before the end of the RST 7.5 routine. The TRAP interrupt is useful for catastrophic evens such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive. The TRAP input must go high and remain high until it is acknowledged. It will not be recognized again until it goes low, then high again. This avoids any false triggering due to noise or logic glitches. Figure 3 illustrates the TRAP interrupt request circuitry within the MSM80C85AH. Note that the servicing of any interrupt (TRAP, RST 7.5, RST 6.5, RST 5.5,INTR) disables all future interrupts (except TRAPs) until an El instruction is executed. The TRAP interrupt is special in that it disables interrupts, but preserves the previous interrupt enable status. Performing the first RIM instruction following a TRAP interrupt allows you to determine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM instructions provide current interrupt enable status. Performing a RIM instruction following INTR or RST 5.5-7.5 will provide current interrupt Enable status, revealing that Interrupts are disabled. The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM, and SIM sets the SOD data. Inside the MSM80C85AHExternal TRAP Interrupt Request TRAP Schmitt Trigger RESET IN RESET TRAP Interrupt Request +5 V D CLK D Q F/F Clear TRAP F.FInternal TRAP Acknowledge Figure 3 Trap and RESET IN Circuit

¡ Semiconductor MSM80C85AHRS/GS/JS BASIC SYSTEM TIMING The MSM80C85AH has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8-bits of address on the Data Bus. Figure 5 shows an instruction fetch, memory read and I/O write cycle (as would occur during processing of the OUT instruction). Note that during the I/ O write and read cycle that the I/O port address is copied on both the upper and lower half of the address. There are seven possible types of machine cycles. Which of these seven takes place is defined by the status of the three status lines (IO/M, S 1, S0) and the three control signals (RD, WR,and INTA). (See Table 2.) The status line can be used as advanced controls (for device selection, for example), since they become active at the T1 state, at the outset of each machine cycle. Control lines RD and WR become active later, at the time when the transfer of data is to take place, so are used as command lines. A machine cycle normally consists of three T states, with the exception of OPCODE FETCH, which normally has either four or six T states (unless WAIT or HOLD states are forced by the receipt of READY or HOLD inputs). Any T state must be one of ten possible states, shown in Table 3. Memory Read O OMemory Write I/O Read 1 1I/O Write (MR) Opcode Fetch 0(OF) (MW) (IOR) Acknowledge of INTR 1(INA) (IOW) Bus Idle 0 TS O O O O TS TS IO/M S1 S0 RD WR INTA Machine Cycle Status Control (BI): DAD ACK. OF RST, TRAP HALT Table 2 MSM80C85AH Machine Cycle Chart

¡ Semiconductor MSM80C85AHRS/GS/JS T2 ·

• TWAIT T3 · T1 · T5 · TS TS 1 (1) A8 – A15 AD0 – AD7 RD, WR INTA ALE Machine State Status & Buses Control
• T6 TRESET TS TSTHALT THOLD TS TS TS TS TS TS TS TS 0 (2) 0 (2) S1, S0 IO/M 0 (2) TS TS TS Table 3 MSM80C85AH Machine State Chart 0 = Logic "0" 1 = Logic "1" TS = High Impedance
• = Unspecified Notes: (1) ALE not generated during 2nd and 3rd machine cycles of DAD instruction. (2) IO/M = 1 during T4 - T6 of INA machine cycle. PCH (High Order Address) (PC+1) H A8-15 T2 T3 T4 T1 T2 T3 T1 T2 M3M2M1 T3 T AD0-7 ALE CLK RD WR STATUS IO/M IO Port IO PortPCL S1S0(Fetch) 10 (Read) 01 Write 11 (Low Order Address) Data from Memory (Instruction) Data from Memory (I/O Port Address) Data to Memory or Peripheral (PC+1)L1 Figure 5 MSM80C85AH Basic System Timing

¡ Semiconductor MSM80C85AHRS/GS/JS POWER DOWN Mode The MSM80C85AH is compatible with the MSM80C85A in function and POWER DOWN mode. This reduces power consumption further. There are two methods available for starting this POWER DOWN mode. One is through software control by using the HALT command and the other is under hardware control by using the pin HOLD. This mode is released by the HOLD, RESET, and interrupt pins (TRAP, RST7.5, RST6.5 RST5.5, or INTR). (See Table 4.) Since the sequence of HALT, HOLD, RESET, and INTERRUPT is compatible with MSM80C85A, every the POWER DOWN mode can be used with no special attention. Start by means of Halt command Start by means of HOLD pin Released by using pins RESET and INTERRUPT (not by pin HOLD) Released by using RESET and HOLD pins (not by interrupt pins) Table 4 POWER DOWN Mode Releasing Method (1) Start by means of HALT command (See Figures 6 and 7.) The POWER DOWN mode can be started by executing the HALT command. At this time, the system is put into the HOLD status and therefore the POWER DOWN mode cannot be released even when the HOLD is released later. In this case, the POWER DOWN mode can be released by means of the RESET or interrupt. (2) Start by means of HOLD pin (See Figure 8.) During the execution of commands other than the HALT, the POWER DOWN mode is started when the system is put into HOLD status by means of the HOLD pin. Since no interrupt works during the execution of the HOLD, the POWER DOWN mode cannot be released by means of interrupt pins. In this case, the POWER DOWN mode can be released either by means of the RESET pin or by releasing the HOLD status by means of HOLD pin.

¡ Semiconductor MSM80C85AHRS/GS/JS ABSOLUTE MAXIMUM RATINGS –55 - +150 MSM80C85AHRS Power Supply Voltage VCC –0.5 - 7 V Input Voltage VIN –0.5 - VCC +0.5 V Output Voltage VOUT –0.5 - VCC +0.5 V Storage Temperature TSTG °C Power Dissipation PD 0.7 W Parameter UnitsSymbol With respect to GND Ta = 25°C Condition Limits MSM80C85AHGS MSM80C85AHJS 1.01.0 OPERATING RANGE Limits Power Supply Voltage VCC 3 - 6 V Operating Temperature TOP –40 - +85 °C Parameter UnitSymbol RECOMMENDED OPERATING CONDITIONS DC CHARACTERISTICS "L" VILR —–0.3 +0.8 Typ. Power Supply Voltage VCC 5V TOP +25 "L" Input Voltage V IL — "H" Output Voltage VIH — Min. 4.5 –40 –0.3 2.2 Max. 5.5 +85 +0.8 VCC +0.3 Parameter UnitSymbol V V Operating Temperature V VIHR —3.0 V CC +0.3 V RESET IN Input Voltage "H" RESET IN Input Voltage Typ. Max. "L" Output Voltage VOL — 0.4 V "H" Output Voltage V OH —— V —— V Parameter UnitSymbol Min. 3.0 VCC - 0.4 IOL = 2.5 mA IOH = –2.5 mA IOH = –100 mA Conditions VCC = 4.5 V - 5.5 V Ta = –40°C - +85°C Input Leak Current ILI —1 0 mA Output Leak Current ILO —1 0 mA –10 –10 0 £ VIN £ VCC 0 £ VOUT £ VCC Tcyc = 200 ns CL = 0 pF at resetOperating Supply Current I CC 10 20 mA 51 0 m A Tcyc = 200 ns CL = 0 pF at power down mode

¡ Semiconductor MSM80C85AHRS/GS/JS AC CHARACTERISTICS Parameter Symbol Condition Min. Max. Unit CLY Cycle Period t CYC tCYC=200 ns CL=150 pF 200 2000 ns CLY Low Time t 1 40 — ns CLY High Time t 2 70 — ns CLY Rise and Fall Time t r, tf —3 0n s X1 Rising to CLK Rising t XKR 25 120 ns X1 Rising to CKK Falling t XKF 30 150 ns A8~15 Valid to Leading Edge of Control (1) t AC 115 — ns AD0~7 Valid to Leading Edge of Control t ACL 115 — ns AD0~15 Valid Data in t AD — 350 ns Address Float After Leading Edge of RD INTA tAFR —0n s A8~15 Valid Before Trailing Edge of ALE (1) t AL 50 — ns AD0~7 Valid Before Trailing Edge of ALE t ALL 50 — ns READY Valid from Address Valid t ARY — 100 ns Address (A8~15) Valid After Control t CA 60 — ns Width of Control Law (RD, WR, INTA)t CC 230 — ns Trailing Edge of Control to Leading Edges of ALE t CL 25 — ns Data Valid to Trailing Edge of WR tDW 230 — ns HLDA to Bus Enable t HABE — 150 ns Bus Float After HLDA t HABF — 150 ns HLDA Valid to Trailing Edge of CLK t HACK 40 — ns HOLD Hold Time t HDH 0— n s HOLD Step Up Time to Trailing Edge of CLK t HDS 120 — ns INTR Hold Time t INH 0— n s INTR, RST and TRAP Setup Time to Falling Edge of CLK t INS 150 — ns Address Hold Time After ALE t LA 50 — ns Trailing Edge of ALE to Leading Edge of Control t LC 60 — ns ALE Low During CLK High t LCK 50 — ns ALE to Valid Data During Read t LDR — 270 ns ALE to Valid Data During Write t LDW — 140 ns ALE Width t LL 80 — ns ALE to READY Stable t LRY —3 0n s Trailing Edge of RD to Re-enabling of Address t RAE 90 — ns RD (or INTA) to Valid Data t RD — 150 ns Control Trailing Edge to Leading Edge of Next Control t RV 220 — ns Data Hold Time After RD INTA (7) t RDH 0— n s READY Hold Time t RYH 0— n s READY Setup Time to Leading Edge of CLK t RYS 100 — ns Data Valid After Trailing Edge of WR tWD 60 — ns LEADING Edge of WR to Data Vaild t WDL —2 0n s

¡ Semiconductor MSM80C85AHRS/GS/JS Notes: (1) A 8 - A15 address Specs apply to IO/ M, S0 and S1. (2) Test condition: t CYC=200 ns CL=150 pF (3) For all output timing where CL=150 pF use the following correction factors: 25 pF £ CL < 150 pF : –0.10ns/pF 150 pF < CL £ 200 pF : +0.30ns/pF (4) Output timings are measured with purely capacitive load. (5) All timings are measured to output voltage VL=0.8 V, VH=2.2 V, and 1.5 V with 10 ns rise and fall time on inputs. (6) To calculate timing specifications at other values of t CYC use Table 7. (7) Data hold time is guaranteed under all loading conditions. 2.4 Test Points 2.2 2.2 0.8 0.80.45 Input Waveform for A.C. Tests: (1/2)T - 50tAL Min (1/2)T - 50tLA Min (1/2)T - 20tLL Min (1/2)T - 50tLCK Min (1/2)T - 40tLC Min (5/2+N)T - 150tAD Max (3/2+N)T - 150tRD Max (1/2)T - 10tRAE Min (1/2)T - 40tCA Min (3/2+N)T -70tDW Min (1/2)T - 40tWD Min (3/2+N)T - 70tCC Min (1/2)T - 75tCL Min (3/2)T - 200tARY Max (1/2)T - 60tHACK Min (1/2)T + 50tHABF Max (1/2)T + 50 (2/2)T - 85 tHABE Max tAC Min (1/2)T - 60t1 Min (1/2)T - 30t2 Min (3/2)T - 80tRV Min tLDR Max MSM80C85AH Table 7 Bus Timing Specification as a TCYC Dependent Note: N is equal to the total WAIT states. T = tCYC (2+N)T -130

¡ Semiconductor MSM80C85AHRS/GS/JS X1 INPUT CLK OUTPUT tXKR t1 tXKF tCYC tr t2 tf Figure 6 Clock Timing Waveform READ OPERATION CLK A8-A15 AD0-AD7 ALE RD / INTA T1 T2 T3 T1 tLCK tLL tAL Address tAFR tLC tAC Address tLA tAD tLDR tRD tCC tCA tRAEtRDH tCL Data In WRITE OPERATION CLK tLDW Address tWDL Data Out A8-A15 AD0-AD7 ALE WR T2 T3 T1 Address tLCK tLA tLC tLL tAL tAC tDW tCC tWD tCL tCA

¡ Semiconductor MSM80C85AHRS/GS/JS Call Inst A8-15 tINS T2 T4 T5 T6 THOLD T1 T2 AD0-7 ALE RD INTA HOLD HLDA INTR Bus Floating (1) tINH tHDS tHDH tHACK tHABF tHABE NOTE: (1) IO/M is also floating during this time. Figure 9 MSM80C85AH Interrupt and Hold Timing

¡ Semiconductor MSM80C85AHRS/GS/JS MOVE, LOAD, AND STORE MOVr1 r2 MOV M r MOV r M MVI r MVI M LXI B LXI D LXI H LXI SP STAX B STAX D LDAX B LDAX D STA LDA SHLD LHLD XCHG Mnemonic Description Instruction Code (1) Clock (2) Cycles D D D D D D D D D S S S S S S D

7 D6 D5 D4 D3 D2 D1 D0

Load immediate register Pair B & C Load immediate register Pair D & E Load immediate register Pair H & L Load immediate stack pointer Store A indirect Store A indirect Load A indirect Load A indirect Store A direct Load A direct Store H & L direct Load H & L direct Exchange D & E H & L registers STACK OPS PUSH B PUSH D PUSH H PUSH PSW POP B POP D POP H POP PSW XTHL SPHL Push register Pair B & C on stack Push register Pair D & E on stack Push register Pair H & L on stack Push A and Flags on stack Pop register Pair B & C off stack Pop register Pair D & E off stack Pop register Pair H & L off stack Pop A and Flags off stack Exchange top of stack H & L H & L to stack pointer JUMP JMP JC JNC JZ JNZ JP JM JPE JPO PCHL Jump unconditional Jump on carry Jump on no carry Jump on zero Jump on no zero Jump on positive Jump on minus Jump on parity even Jump on parity odd H & L to program counter CALL CALL CC CNC CZ CNZ CP CM CPE CPO Call unconditional Call on carry Call on no carry Call on zero Call on no zero Call on positive Call on minus Call on parity even Call on parity odd Table 8 Instruction Set Summary

¡ Semiconductor MSM80C85AHRS/GS/JS RETURN RET RC RNC RZ RNZ RP RM RPE RPO Mnemonic Description Instruction Code (1) Clock (2) Cycles D D D D D D D Increment register Decrement register Increment memory Decrement memory Increment B & C registers Increment D & E registers Increment H & L registers Increment stack pointer Decrement B & C Decrement D & E Decrement H & L Decrement stack pointer ADD ADD r ADC r ADD M ADC M ADI ACI DAD B DAD D DAD H DAD SP S S S S S S Add register to A Add register to A with carry Add memory to A Add memory to A with carry Add immediate to A Add immediate to A with carry Add B & C to H & L Add D & E to H & L Add H & L to H & L Add stack pointer to H & L SUBTRACT SUB r SBB r SUB M SBB M SUI SBI S S S S S S Subtract register from A Subtract register from A with borrow Subtract memory from A Subtract memory from A with borrow Subtract immediate from A Subtract immediate from A with borrow Table 8 Instruction Set Summary cont'd

¡ Semiconductor MSM80C85AHRS/GS/JS LOGICAL ANA r XRA r ORA r CMP r ANA M XRA M ORA M CMP M ANI XRI ORI CPI Mnemonic Description Instruction Code (1) Clock (2) Cycles S S S S S S S S S S S S D Exclusive Or register with A Or register with A Compare register with A And memory with A Exclusive Or Memory with A Or memory with A Compare memory with A And immediate with A Exclusive Or immediate with A Or immediate with A Compare immediate with A ROTATE RLC RRC RAL RAR Rotate A left Rotate A right Rotate A left through carry Rotate A right through carry SPECIALS CMA STC CMC DAA Complement A Set carry Complement carry Decimal adjust A CONTROL EI DI NOP HLT RIM SIM Enable Interrupts Disable Interrupts No-operation Halt (Power down) Read Interrupt Mask Set Interrupt Mask Table 8 Instruction Set Summary cont'd (2) Two possible cycle times, (6/12) indicate instruction cycles dependent on condition flags. Precautions for operation (1) When the oscillation circuit is to be used, keep the RES input low until the oscillation is sufficiently stabilized after power is turned on. (2) When power is turned on, the output level (SOD etc.) is unknown before the equipment is reset. (3) Bug of MSM80C85A–2 at power down has fixed. (4) Because Spike Noise would be output on HLDA, RESET OUT and CLK pins, depending on the customers condition of usage; please take into account this issue at System Board design.

¡ Semiconductor MSM80C85AHRS/GS/JS SUPPLEMENTARY EXPLANATION (1) SIM instruction: The execution of the SIM instruction uses the contents of the accumulator to mask MSM80C85AH’S interrupts. Accumulator Setting Value R7.5 (Reset interrupt 7.5 Flip-flop): When this bit is set to 1, the edge detecting flip-flop of RST 7.5 interrupt is reset. MSE (Mask Set Enable): When this bit is set to 1, the interrupt mask bits are valid. M7.5 (Mask RST7.5): When this bit is set to 1 and MSE bit is set to 1, RST7.5 interrupt is masked. M6.5 (Mask RST6.5): When this bit is set to 1 and MSE bit is set to 1, RST6.5 interrupt is masked. M5.5 (Mask RST5.5): When this bit is set to 1 and MSE bit is set to 1, RST 5.5 interrupt is masked. Bit 7 R7.5 MSE M7.5 M6.5 M5.5 (2) RIM instruction: When the contents of the accumulator are read out after RIM instruction has been executed, MSM80C85AH interrupt status can be known. Accumulator Reading Value Bit 7 17.5 16.5 15.5 IE M7.5 M6.5 M5.5 17.5 (Pending RST7.5): When RST7.5 interrupt is pending, "1" is read out. 16.5 (Pending RST6.5): When RST6.5 interrupt is pending, "1" is read out. 15.5 (Pending RST5.5): When RST5.5 interrupt is pending, "1" is read out. IE (Interrupt Enable Flag): When interrupt is Enable, "1" is read out. M7.5 (Mask RST7.5): When RST7.5 interrupt is masked, "1" is read out. M6.5 (Mask RST6.5): When RST6.5 interrupt is masked, "1" is read out. M5.5 (Mask RST5.5): When RST5.5 interrupt is masked ,"1" is read out.

¡ Semiconductor MSM80C85AHRS/GS/JS NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. High-speed device (New) Low-speed device (Old) Remarks M80C85AH M80C85A/M80C85A-2 8bit MPU M80C86A-10 M80C86A/M80C86A-2 16bit MPU M80C88A-10 M80C88A/M80C88A-2 8bit MPU M82C84A-2 M82C84A/M82C84A-5 Clock generator M81C55-5 M81C55 RAM.I/O, timer M82C37B-5 M82C37A/M82C37A-5 DMA controller M82C51A-2 M82C51A USART M82C53-2 M82C53-5 Timer M82C55A-2 M82C55A-5 PPI

¡ Semiconductor MSM80C85AHRS/GS/JS Differences between MSM80C85AH and MSM80C85A/MSM80C85A-2 1) Manufacturing Process 2) Functions 3) Electrical Characteristics 3-1) Operating Conditions 3-2) DC Characteristics Item MSM80C85A MSM80C85A-2 MSM80C85AH Manufacturing Process 3mSi-CMOS 2.5mSi-CMOS 2 mSi-CMOS Notes: "at RES'' means ''at reset time'' and ''in PD'' means ''in power down mode''. As shown above, the V OL and VOH ranges the MSM80C85AH contain those of the MSM80C85A/ MSM80C85A-2. Although the supply current range (at a power failure) of the MSM80C85AH does not contain that of the MSM80C85A-2, this does not affect the actual use of the MSM80C85AH. 3-3) AC Characteristics The AC characteristics (5 MHz) of the MSM80C85AH satisfy that (3 MHz) of the MSM80C85A. The MSM80C85AH also satisfies that (5MHz) of the MSM80C85A. Parameter MSM80C85A MSM80C85A-2 MSM80C85AH Power Supply Voltage 4 to 6 V 3 to 6 V 3 to 6 V Symbol VCC Item MSM80C85A MSM80C85A-2 MSM80C85AH Power-down Function Not provided Provided (but may malfunction when HOLD is used) Provided (The malfunction has been removed.) Address output during T4 to T6 cycles Undefined (compatible with Intel devices) Not fixed The contents of data in T3 cycle are retained (for low power consumption). Parameter MSM80C85A MSM80C85A-2 MSM80C85AH ''L''Level Output Voltage

0.45 V maximum

(+2 mA) (+2 mA)

0.40 V maximum

(+2.5 mA) Symbol VOL ''H''Level Output Voltage

2.4 V minimum

(-400 mA) (-400 mA)

3.0 V maximum

(-2.5 mA)VOH ''H''Level Output Voltage

4.2 V minimum

(-40 mA) (-40 mA) VCC-0.2 V minimum (-100 mA)VOH Supply Current (at RES) 22 mA maximum (@3 MHz) 20 mA maximum (@5 MHz) 20 mA maximum (@5 MHz)ICC Supply Current (in PD) None 7 mA maximum (@5 MHz) 10 mA maximum (@5 MHz)ICC

¡ Semiconductor MSM80C85AHRS/GS/JS AC Charasteristics Notes: The italicized or underlined values indicate that they are different from those of the MSM80C85AH. MSM80C85ASymbol MSM80C85A-2 MSM80C85AH 320 nstCYC 200 ns 200 ns 80 nst1 40 ns 40 ns 120 nst2 70 ns 70 ns 30 nstXKR 25 ns 25 ns 270 nstAC 115 ns 115 ns 240 nstACL 115 ns 115 ns 575 nstAD 350 ns 115 nstAL 50 ns 50 ns 90 nstALL 50 ns 50 ns 220 nstARY 100 ns 100 ns 120 nstCA 60 ns 60 ns 400 nstCC 230 ns 230 ns 50 nstCL 25 ns 25 ns 420 nstDW 230 ns 230 ns 210 nstHABE 150 ns 150 ns 210 nstHABF 150 ns 150 ns 110 nstHACK 40 ns 40 ns 170 nstHDS 120 ns 120 ns 160 nstINS 150 ns 150 ns 100 nstLA 50 ns 50 ns 130 nstLC 60 ns 60 ns 100 nstLCK 50 ns 50 ns 460 nstLDR 270 ns 200 nstLDW 140 ns 140 ns 140 nstLL 80 ns 80 ns 110 nstLRY 30 ns 30 ns 150 nstRAE 90 ns 90 ns 300 nstRD 150 ns 150 ns 400 nstRV 220 ns 220 ns 100 nstWD 60 ns 60 ns 40 nstWDL 20 ns 20 ns Min Min Min Min Max Min Max Min Min Max Min Min Min Min Min Max Min Min Min Min Min Min Max Max Min Max Min Max Min Max Min 330 ns 250 ns

¡ Semiconductor MSM80C85AHRS/GS/JS 4) Other notes 1) As the MSM80C85AH employs the 2 m process, its noise characteristics may be a little different from those of the MSM80C85A. When devices are replaced for upgrading, it is recommended to perform noise evaluation. Especially, HLDA, RESOUT, and CLKOUT pins must be evaluated. 2) The MSM80C85AH basically satisfies the characteristics of the MSM80C85A-2 and the MSM80C85A, but their timings are a little different, Therefore, when critical timing is required in designing, it is recommended to evaluate operating margins at various temperatures and voltages.

¡ Semiconductor MSM80C85AHRS/GS/JS (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). DIP40-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP.

¡ Semiconductor MSM80C85AHRS/GS/JS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFJ44-P-S650-1.27 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP. Mirror finish

¡ Semiconductor MSM80C85AHRS/GS/JS (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP. QFP44-P-910-0.80-2K Mirror finish