M80C51

MSM80C31F OKI | Alldatasheet

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Technical content

¡ Semiconductor MSM80C31F/80C51F ¡ Semiconductor MSM80C31F/MSM80C51F CMOS 8-Bit Microcontroller GENERAL DESCRIPTION The OKI MSM80C31F/MSM80C51F microcontroller is a low-power, 8-bit device implemented in OKI's silicon-gate complementary metal-oxide semiconductor process technology. The device includes 4K bytes of mask programmable ROM (MSM80C51F only), 128 bytes of data RAM, 32 I/O lines, two 16-bit timer/counters, a five-source two-level interrupt structure, a full duplex serial port, and an oscillator and clock circuitry. In addition, the device has two software selectable modes for further power reduction — Idle and Power Down. Idle mode freezes the CPU's in-struction execution while maintaining RAM and allowing the timers, serial port and interrupt system to continue functions. Power Down mode saves the RAM contents but freezes the oscillator causing all other device functions to be inoperative.

FEATURES

• Low power consumption by 2 mm silicon gate CMOS process technology
• Fully static circuit
• Internal program memory : 4K bytes (MSM80C51F)
• External program memory space : 64K bytes
• Internal data memory (RAM) : 128 bytes
• External data memory (RAM) space : 64K bytes
• I/O ports : 8-bit ´ 4 ports
• Two 16-bit timer/counters
• Multifunctional serial port (UART)
• Five interrupt sources (Priority can be set)
• Four sets of working registers (R0-7 ´ 4)
• Stack : Internal data memory (RAM) 128-byte area can be used arbitrarily (by SP specified)
• Two CPU power-down modes (1) Idle mode : CPU stopped while oscillation continued. (Software setting) (2) PD mode : CPU and oscillation all stopped. (Software setting) (Setting I/O ports to floating status possible)
• Operating temperature : –40 to +85 °C (@ 12 MHz, V CC = 5 V –20%) –20 to +70°C (@ 16 MHz, VCC = 5 V –5%)
• 2-byte 1-machine cycle instructions : 1 msec. @ 12 MHz 0.75 msec. @ 16 MHz
• Multiplication/division instructions : 4 msec. @ 12 MHz 3 msec. @ 16 MHz
• Instruction code addressing method Byte specification : Data addressing (direct) Bit specification : Bit addressing E2E1037-19-41 This version: Mar. 1995

¡ Semiconductor MSM80C31F/80C51F

• Package options 40-pin plastic DIP (DIP40-P-600-2.54) : (MSM80C31F- ´´´RS) (MSM80C51F-´´´RS) 44-pin plastic QFP (QFP44-P-910-0.80-2K) : (M SM80C31F-´´´GS) (MSM80C51F-´´´GS) 44-pin plastic QFJ (PLCC) (QFJ44-P-S650-1.27) : (MSM80C31F-´´´JS) (MSM80C51F-´´´JS) ´´´ indicates the code number. DIFFERENCES BETWEEN MSM80C31F/MSM80C51F AND MSM80C31/MSM80C51
• Operating frequency
• External clock input terminal
• Emulation mode Output impedance of ALE and PSEN pins becomes about 20 kW while CPU is being reset in MSM80C31F/MSM80C51F. Any other functions and electrical characteristics of MSM80C31F/MSM80C51F except for above three differences are the same as those of MSM80C31/MSM80C51.

¡ Semiconductor MSM80C31F/80C51F BLOCK DIAGRAM PCH CONTROL SIGNALS SPECIAL FUNCTION REGISTER ADDRESS DECODER PLA IR AIR C-ROM TR1TR2ACC ALU BRPSW RAMDP R/W AMP

128 WORDS

´ 8 BITS DPLDPH PCL ROM

4096 WORDS

´ 8 BITS SENSE AMP PCLLPCHL PORT 2 PORT 0 PCON OSC AND TIMING PORT 1 PORT 3 XTAL1 XTAL2 ALE RESET PSEN EA TH1 TL1 TH0 TL0 TMOD TCON IE IP SBUF(T) SBUF(R) INTERRUPTTIMER/COUNTER SERIAL IO SCON SIGNALSR/W SP ADDRESS DECODER ADDRESS DECODER P2.0 to P2.7 P0.0 to P0.7 P1.0 to P1.7 P3.0 to P3.7

¡ Semiconductor MSM80C31F/80C51F CLOCK WAVEFORMS Basic Timing Chart ACC & RAM S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 PCL PCL PCL PCL PCH PCH PCH PCHPCHDPH & PORT DATAPCH PORT NEW DATA PC+1 TM+1 PC+1 TM+1TM+1TM+1 PC+1PC+1PC+1 CYCLE STEP XTAL1 ALE RD/WR PORT-0 PORT-2 CPU¬PORT PORT¬CPU PCH PCL DPL&Rr DATA STABLE PORT OLD DATA DATA STABLE PSEN PCL Instruction decoding Instruction execution Instruction decoding Instruction execution Instruction decoding Instruction execution Port output/input Instruction execution Port output/input Instruction execution execution External data memory instruction

¡ Semiconductor MSM80C31F/80C51F PIN CONFIGURATION (TOP VIEW) V SS P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET RXD/P3.0 TXD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 P2.0 V CC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA ALE PSEN P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 40-Pin Plastic DIP

¡ Semiconductor MSM80C31F/80C51F PIN CONFIGURATION (TOP VIEW) (continued) 44-Pin Plastic QFP P1.5 P1.6 P1.7 RESET P3.0/RXD NC P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1/HPDI P0.4 P0.5 P0.6 P0.7 EA NC ALE PSEN P2.7 P2.6 P2.5 /,/#01 P1.4 P1.3 P1.2 P1.1 P1.0 NC V CC P0.0 P0.1 P0.2 P0.3 P3.6/WR P3.7/RD XTAL2 XTAL1 V SS VSS P2.0 P2.1 P2.2 P2.3 P2.4

¡ Semiconductor MSM80C31F/80C51F PIN CONFIGURATION (TOP VIEW) (continued) 44-Pin Plastic QFJ (PLCC) P0.3 P0.2 P0.1 P0.0 V CC NC P1.0 P1.1 P1.2 P1.3 P1.4 P2.3 P2.2 P2.1 P2.0 NC V SS XTAL1 XTAL2 P3.7/RD P3.6/WR P1.5 P1.6 P1.7 RESET P3.0/RXD NC P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P0.5 P0.6 P0.7 EA NC ALE PSEN P2.7 P2.6 P2.5 P0.4 P2.4 P3.5/T1 /#06

¡ Semiconductor MSM80C31F/80C51F PIN DESCRIPTION Symbol Description VSS VCC Ground potential Supply voltage during Normal, Idle and Power Down operation Port 0 is an 8-bit open-drain bidirectional I/O port. It is also the mutiplexed low-order address and data bus during accesses to external memory. Port 0.0 - 0.7 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. It can drive CMOS inputs without external pull-ups. Port 1.0 - 1.7 Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. It outputs the high-order address byte during accesses to external memory. It can drive CMOS inputs without external pull-ups. Port 2.0 - 2.7 Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. It also provides various special features, as shown below: Port 3.0 - 3.7 Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Port 3 can drive CMOS inputs without external pull-ups. Alternate Function RXD TXD INT0 INT1 WR RD (serial input port) (serial output port) (external interrupt) (external interrupt) (Timer 0 external input) (Timer 1 external input) (external data memory write strobe) (external data memory read strobe) Reset input pin. A reset is accomplished by holding the RESET pin high for at least 1ms. even if the oscillator has been stopped. The CPU responds by executing an internal reset. An internal pull-down resistor permits Power-On reset using only a capacitor connected to V CC. This pin does not receive the power down voltage since the function has been transferred to the V CC pin. Address Latch Enable. This output latches for latching the low byte of the address during accesses to external memory. For this purpose, ALE is activated twice every machine cycle or at a constant rate of 1/6th the oscillator frequency, except during an external memory access at which time one ALE pulse is skipped. ALE can drive CMOS inputs without an external pull-up. Program Store Enable output. This output is the read strobe to external program memory. For this purpose, PSEN is activated twice every machine cycle. (However, when executing out of external program memory, two activations of PSEN are skipped during each access to external data memory.) PSEN is not activated during fetches from internal program memory. It can drive CMOS inputs without an external pull-up. External Access input pin. When EA is held high, the CPU executes out of internal program memory (unless the program counter exceeds 0FFFH). When EA is held low, the CPU executes only out of external program memory. EA must not be floated. Crystal 1 pin. It is an input to the inverting amplifier which forms the internal oscillator. Crystal 2 pin. It is an output of the inverting amplifier that forms the internal oscillator. RESET ALE PSEN EA XTAL1 XTAL2

¡ Semiconductor MSM80C31F/80C51F DATA MEMORY AND SPECIAL FUNCTION REGISTER LAYOUT DIAGRAM B ACC PSW IP IE SBUF SCON TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP USER RAM 80W ´ 8 bits ADDRESSABLE RAM BANK 3 BANK 2 BANK 1 BANK 0 SPECIAL FUNCTION REGISTERS BIT ADDRESSING DATA ADDRESSING BIT DATA RAM 0F0H 0E0H 0D0H 0B8H 0B0H 0A8H 0A0H 99H 98H 90H 8DH 8CH 8BH 8AH 89H 88H 87H 83H 82H 81H 80H

¡ Semiconductor MSM80C31F/80C51F DETAILED DIAGRAM OF DATA MEMORY (RAM) Bank 2 Bank 1 Bank 0 Bank 3 127 08H 2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 30H 7FH 1FH 18H 17H 10H 0FH 07H 00H INDIRECT ADDRESSING BIT ADDRESSING DATA ADDRESSING REGISTER ADDRESSING USER DATA RAM

¡ Semiconductor MSM80C31F/80C51F DETAILED DIAGRAM OF SPECIAL FUNCITON REGISTERS F7 F6 F5 F4 F3 F2 F1 F0 Data Address Special Function Register Symbol(MSB) Bit Address (LSB) 0F0H B E7 E6 E5 E4 E3 E2 E1 E00E0H ACC D7 D6 D5 D4 D3 D2 D1 D00D0H PSW — — — BC BB BA B9 B80B8H IP B7 B6 B5 B4 B3 B2 B1 B00B0H P3 AF — — AC AB AA A9 A80A8H IE A7 A6 A5 A4 A3 A2 A1 A00A0H P2 Not Bit Addressable99H SBUF 9F 9E 9D 9C 9B 9A 99 9898H SCON 97 96 95 94 93 92 91 9090H P1 Not Bit Addressable8DH TH1 Not Bit Addressable8CH TH0 Not Bit Addressable8BH TL1 Not Bit Addressable8AH TL0 Not Bit Addressable89H TMOD 8F 8E 8D 8C 8B 8A 89 8888H TCON Not Bit Addressable87H PCON Not Bit Addressable83H DPH Not Bit Addressable82H DPL Not Bit Addressable81H SP 87 86 85 84 83 82 81 8080H P0 CY AC F0 RS1 RS0 OV F1 P PS PT1 PX1 PT0 PX0 EA ES ET1 EX1 ET0 EX0 SM0 SM1 SM2 REN TB8 RB8 TI RI TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

¡ Semiconductor MSM80C31F/80C51F INSTRUCTION LIST List of Instruction Symbols A : Accumulator AB : Register pair AC : Auxiliary carry flag B : Arithmetic operation register C : Carry flag DPTR : Data pointer PC : Program counter Rr : Register indicator (r = 0 to 7) SP : Stack pointer AND : Logical product OR : Logical sum XOR : Exclusive-OR + : Addition – : Subtraction X : Multiplication / : Division (X) : Denotes the contents of X ((X)) : Denotes the contents of address determined by the contents of X # : Denotes the immediate data @ : Denotes the indirect address = : Equality Þ : Non-equality ¬ : Substitution ® : Substitution — : Negation < : Smaller than > : Larger than bit address : RAM and the special function register bit specifier address (b 0 to b7) code address : Absolute address (A 0 to A15) data : Immediate data (I 0 to I7) relative offset : Relative jump address offset value (R 0 to R7) direct address : RAM and the special function register byte specifier address (a 0 to a7)

¡ Semiconductor MSM80C31F/80C51F MSM80C31F/MSM80C51F Instruction Codes 0000 L H 0001 0010 0011 0100 0101 0110 0111 NOP AJMP address 11 (Page 0) LJMP address 16 RR A INC A INC direct INC @R0 INC @R10 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 JBC bit, rel ACALL address 11 (Page 0) LCALL adress 16 RRC A DEC A DEC direct DEC @R0 DEC @R1 JB bit, rel AJMP address 11 (Page 1) RET RL A ADD A, #data ADD A, direct ADD A, @R0 ADD A, @R1 JNB bit, rel ACALL address 11 (Page 1) RETI RLC A ADDC A, #data ADDC A, direct ADDC A, @R0 ADDC A, @R1 JC rel AJMP address 11 (Page 2) ORL direct, A ORL direct, #data ORL A, #data ORL A, direct ORL A, @R0 ORL A, @R1 JNC rel ACALL address 11 (Page 2) ANL direct, A ANL direct, #data ANL A, #data ANL A, direct ANL A, @R0 ANL A, @R1 JZ rel AJMP address 11 (Page 3) XRL direct, A XRL direct, #data XRL A, #data XRL A, direct XRL A, @R0 XRL A, @R1 JNZ rel ACALL address 11 (Page 3) ORL C, bit JMP @A+DPTR MOV A, #data MOV direct #data MOV @R0, #data MOV @R1, #data SJMP rel AJMP address 11 (Page 4) ANL C, bit MOVC A, @A+PC DIV AB MOV direct1, direct2 MOV direct, @R0 MOV direct, @R1 MOV DPTR, #data 16 ACALL address 11 (Page 4) MOV bit, C MOVC A, @A+DPTR SUBB A, #data SUBB A, direct SUBB A, @R0 SUBB A, direct ORL C, /bit AJMP address 11 (Page 5) MOV C, bit INC DPTR MUL AB MOV @R0, direct MOV @R1, direct ANL C, /bit ACALL address 11 (Page 5) CPL bit CPL C CJNE A, #data rel CJNE A, direct, rel CJNE @R0 #data, rel CJNE @R1, #data, rel PUSH direct AJMP address 11 (Page 6) CLR bit CLR C SWAP A XCH A, direct XCH A, @R0 XCH A, @R1 POP direct ACALL address 11 (Page 6) SETB bit SETB C DA A DJNZ direct, rel XCHD A, @R0 XCHD A, @R1 MOVX A, @DPTR AJMP address 11 (Page 7) MOVX A, @R0 MOVX A, @R1 CLR A MOV A, direct MOV A, @R0 MOV A, @R1 MOVX @DPTR, A ACALL address 11 (Page 7) MOVX @R0, A MOVX @R1, A CPL A MOV direct, A MOV @R0, A MOV @R1, A 2BYTES 2CYCLES 3BYTES 4CYCLES MNEMONIC

¡ Semiconductor MSM80C31F/80C51F 1000 INC R0 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7 DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 ADD A, R0 ADD A, R1 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7 ADDC A, R0 ADDC A, R1 ADDC A, R2 ADDC A, R3 ADDC A, R4 ADDC A, R5 ADDC A, R6 ADDC A, R7 ORL A, R0 ORL A, R1 ORL A, R2 ORL A, R3 ORL A, R4 ORL A, R5 ORL A, R6 ORL A, R7 ANL A, R0 ANL A, R1 ANL A, R2 ANL A, R3 ANL A, R4 ANL A, R5 ANL A, R6 ANL A, R7 XRL A, R0 XRL A, R1 XRL A, R2 XRL A, R3 XRL A, R4 XRL A, R5 XRL A, R6 XRL A, R7 MOV R0, #data MOV R1, #data MOV R2, #data MOV R3, #data MOV R4, #data MOV R5, #data MOV R6, #data MOV R7, #data MOV direct, MOV direct, MOV direct, MOV direct, MOV direct, MOV direct, MOV direct, MOV direct, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A, SUBB A, MOV R0, direct MOV R1, direct MOV R2, direct MOV R3, direct MOV R4, direct MOV R5, direct MOV R6, direct MOV R7, direct CJNE R0, #data rel CJNE R1, #data rel CJNE R2, #data rel CJNE R3, #data rel CJNE R4, #data rel CJNE R5, #data rel CJNE R6, #data rel CJNE R7, #data rel XCH A, XCH A, XCH A, XCH A, XCH A, XCH A, XCH A, XCH A, DJNZ R0, rel DJNZ R1, rel DJNZ R2, rel DJNZ R3, rel DJNZ R4, rel DJNE R5, rel DJNE R6, rel DJNE R7, rel MOV A, R0 MOV A, R1 MOV A, R2 MOV A, R3 MOV A, R4 MOV A, R5 MOV A, R6 MOV A, R7 MOV R0, A MOV R1, A MOV R2, A MOV R3, A MOV R4, A MOV R5, A MOV R6, A MOV R7, A 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 L H MSM80C31F/MSM80C51F Instruction Codes (continued)

¡ Semiconductor MSM80C31F/80C51F Instruction Set Details D6 D 5 D 4 D 3 D 1 BytesCyclesType Mnemonic Instruction code

Description

11100100CLR A 11 (A) ¬ 0 00101 r 2 r1 r0ADD A, Rr 11 (AC), (0V), (C), (A) ¬ (A)+(Rr) 11110100CPL A 11 (A) ¬ (A) 00100011PL A 11 Accumulator Airthmetic operation instructions C Accumulation operation instructions D2 D 0 00100101ADD A, direct 21 (AC), (0V), (C), (A) ¬ (A)+(direct address) 0010011r 0ADD A, @Rr 11 (AC), (0V), (C), (A) ¬ (A)+((Rr)) a7 a6 a5 a4 a3 a2 a1 a0 00100100ADD A, #data 21 (AC), (0V), (C), (A) ¬ (A)+#data 00111 r 2 r1 r0ADDC A, Rr 11 (AC), (0V), (C), (A) ¬ (A)+(C)+(Rr) I7 I6 I5 I4 I3 I2 I1 I0 00110101ADDC A, direct 21 (AC), (0V), (C), (A) ¬ (A)+(C)+ (direct address) 0011011r 0ADDC A, @Rr 11 (AC), (0V), (C), (A) ¬ (A)+(C)+((Rr)) a7 a6 a5 a4 a3 a2 a1 a0 00110100ADDC A, #data 21 (AC), (0V), (C), (A) ¬ (A)+(C)+#data 10011 r 2 r1 r0SUBB A, Rr 11 (AC), (0V), (C), (A) ¬ (A)–((C))+((Rr)) I7 I6 I5 I4 I3 I2 I1 I0 10010101SUBB A, direct 21 (AC), (0V), (C), (A) ¬ (A)–((C)+ (direct address)) 1001011r 0SUBB A, @Rr 11 (AC), (0V), (C), (A) ¬ (A)–((C)+((Rr)) a7 a6 a5 a4 a3 a2 a1 a0 10010100SUBB A, #data 21 (AC), (0V), (C), (A) ¬ (A)–((C)+ #data) 10100100MUL AB 14 (AB) ¬ (A) x (B) I7 I6 I5 I4 I3 I2 I1 I0 10000100DIV AB 14 (A)quotient, (B) remainder 11010100DA A 11 When the contents of accumulator bits 0 thru 3 are greater than 9, or when auxiliary carry (AC) is 1, 6 is added to bits 0 thru 3. Bits 4 thru 7 are then examined, and when bits 4thru 7 follwoing compensation of lower bits 0 thru 3 is greater than 9, or when carry (C) is 1, 6 is added to bits 4 thru 7. As a result, the cary flag can be set, but cannot be cleared. ¬ (A)/(B) 00110011PL C 11 Accumulator C

¡ Semiconductor MSM80C31F/80C51F Instruction Set Details (continued) D6 D 5 D 4 D 3 D 1 BytesCyclesType Mnemonic Instruction code DescriptionD7 00000011RR A 11 Accumulator Increment/decrement C Accumulation operation instructions D2 D 0 11000100SWAP A 11 (A4 -7) « (A0 -3) 00000101INC direct 21 (direct address) ¬ (direct address)+1 0000011r 0INC @Rr 11 ((Rr)) ¬ ((Rr))+1 a7 a6 a5 a4 a3 a2 a1 a0 01010100ANL A, #data 21 (A) ¬ (A) AND #data I7 I6 I5 I4 I3 I2 I1 I0 01010010ANL direct, A 21 (direct address) ¬ (direct address) AND (A) 0100011r 0ORL A, @Rr 11 (A) ¬ (A) OR ((Rr)) a7 a6 a5 a4 a3 a2 a1 a0 01000100ORL A, #data 21 (A) ¬ (A) OR #data I7 I6 I5 I4 I3 I2 I1 I0 00010011RRC A 11 Accumulator C 00001 r 2 r1 r0INC Rr 11 (Rr) ¬ (Rr)+1 00000100INC A 11 (A) ¬ (A)+1 10100011INC DPTR 12 (DPTR) ¬ (DPTR)+1 00010100DEC A 11 (A) ¬ (A)–1 00010101DEC direct 21 (direct address) ¬ (direct address)–1 a7 a6 a5 a4 a3 a2 a1 a0 00011 r 2 r1 r0DEC Rr 11 (Rr) ¬ (Rr)–1 0001011r 0DEC @Rr 11 ((Rr)) ¬ ((Rr))–1 01010101ANL A, direct 21 (A) ¬ (A) AND (direct address) a7 a6 a5 a4 a3 a2 a1 a0 01011 r 2 r1 r0ANL A, Rr 11 (A) ¬ (A) AND (Rr) 0101011r 0ANL A, @Rr 11 (A) ¬ (A) AND ((Rr)) 01010011ANL direct, #data 32 (direct address) ¬ (direct address) AND #dataa7 a6 a5 a4 a3 a2 a1 a0 I7 I6 I5 I4 I3 I2 I1 I0 01001 r 2 r1 r0ORL A, Rr 11 (A) ¬ (A) OR (Rr) 01000101ORL A, direct 21 (A) ¬ (A) OR (direct address) a7 a6 a5 a4 a3 a2 a1 a0 01000010ORL direct, A 21 (direct address) ¬ (direct address) OR (A)a7 a6 a5 a4 a3 a2 a1 a0 Logical operation instructions

¡ Semiconductor MSM80C31F/80C51F Instruction Set Details (continued) D6 D 5 D 4 D 3 D 1 BytesCyclesType Mnemonic Instruction code DescriptionD7 Immediate data setting instructions D2 D 0 10110000ANL C,/bit 22 (C) ¬ (C) AND (bit address) b7 b6 b5 b4 b3 b2 b1 b0 01110010ORL C, bit 22 (C) ¬ (C) OR (bit address) 0110011r 0XRL A, @Rr 11 (A) ¬ (A) XOR ((Rr)) b7 b6 b5 b4 b3 b2 b1 b0 01100100XRL A, #data 21 (A) ¬ (A) XOR #data I7 I6 I5 I4 I3 I2 I1 I0 10000010ANL C, bit 22 (C) ¬ (C) AND (bit address) b7 b6 b5 b4 b3 b2 b1 b0 11000011CLR C 11 (C) ¬ 0 01101 r 2 r1 r0XRL A, Rr 11 (A) ¬ (A) XOR (Rr) 01100010XRL direct, A 21 (direct address) ¬ (direct address) XOR (A)a7 a6 a5 a4 a3 a2 a1 a0 Carry flag operation instructions 01000011ORL direct, #data 32 (direct address) ¬ (direct address) OR #dataa7 a6 a5 a4 a3 a2 a1 a0 I7 I6 I5 I4 I3 I2 I1 I0 01100011XRL direct, #data 32 (direct address) ¬ (direct address) XOR #dataa7 a6 a5 a4 a3 a2 a1 a0 I7 I6 I5 I4 I3 I2 I1 I0 Logical operation instructions 01110100MOV A, #data 21 (A) ¬ #data I7 I6 I5 I4 I3 I2 I1 I0 01111 r 2 r1 r0MOV Rr, #data 21 (Rr) ¬ #data I7 I6 I5 I4 I3 I2 I1 I0 0111011r 0MOV @Rr, #data 21 (Rr)) ¬ #data I7 I6 I5 I4 I3 I2 I1 I0 01110101MOV direct, #data 32 (direct address) ¬ #data a7 a6 a5 a4 a3 a2 a1 a0 I7 I6 I5 I4 I3 I2 I1 I0 10010000MOV DPTR, #data 16 32 (DPTR) ¬ #data 16 I7 I6 I5 I4 I3 I2 I1 I0 11010011SETB C 11 (C) ¬ 1 10110011CPL C 11 (C) ¬ (C) 10100000ORL C,/bit 22 (C) ¬ (C) OR (bit address) b7 b6 b5 b4 b3 b2 b1 b0 01100101XRL A, direct 21 (A) ¬ (A) XOR (direct address) a7 a6 a5 a4 a3 a2 a1 a0 I15 I14 I13 I12 I11 I10 I9 I8

¡ Semiconductor MSM80C31F/80C51F Instruction Set Details (continued) D6 D5 D 4 D 3 D 1 BytesCyclesType Mnemonic Instruction code DescriptionD7 D 2 D 0 1110011r 0MOV A, @Rr 11 (A) ¬ ((Rr)) 11111MOV Rr, A 11 (Rr) ¬ (A) 11000101XCH A, direct 22 (A) « (direct address) a7 a6 a5 a4 a3 a2 a1 a0 11001XCH A, Rr 11 (A) « (Rr) 11101 r 2 r1 r0MOV A, Rr 11 (A) ¬ (Rr) 10101MOV Rr, direct 22 (Rr) ¬ (direct address) a7 a6 a5 a4 a3 a2 a1 a0 MOV direct, A 21 (direct address) ¬ (A) Data transfer instructions 10010011MOVC A, @A+DPTR 12 (A) ¬ ((A)+(DPTR)) 10000011MOVC A, @A+PC 12 (PC) ¬ (PC+1) (A) ¬ ((A)+(PC)) 11100101MOV A, direct 21 (A) ¬ (direct address) a7 a6 a5 a4 a3 a2 a1 a0 10100010MOV C, bit 21 (C) ¬ (bit address) b7 b6 b5 b4 b3 b2 b1 b0 10010010MOV bit, C 22 (bit address) ¬ (C) b7 b6 b5 b4 b3 b2 b1 b0 Carry flag operation instructions 11010010SETB bit 21 (bit address) ¬ 1 b7 b6 b5 b4 b3 b2 b1 b0 11000010CLR bit 21 (bit address) ¬ 0 b7 b6 b5 b4 b3 b2 b1 b0 10110010CPL bit 21 (bit address) ¬ (bit address) b7 b6 b5 b4 b3 b2 b1 b0 Bit operation instructions r2 r1 r0 r2 r1 r0 11110101 a7 a6 a5 a4 a3 a2 a1 a0 10001MOV direct, Rr 22 (direct address) ¬ (Rr) a7 a6 a5 a4 a3 a2 a1 a0 r2 r1 r0 10000MOV direct 1, direct 2 32 (direct address 1) ¬ (direct address 2) a7 a6 a5 a4 a3 a2 a1 a0 11r 0 10100MOV @Rr, direct 22 ((Rr)) ¬ (direct address) a7 a6 a5 a4 a3 a2 a1 a0 11r 0 1111011r 0MOV @Rr, A 11 ((Rr)) ¬ (A) Constant code instructions r2 r1 r0 11000XCH A, @Rr 11 (A) « ((Rr))11r 0 11010XCHD A, @Rr 11 (A0 - 3) « ((Rr0 - 3))11r 0 Data exchange instructions a7 a6 a5 a4 a3 a2 a1 a0 22222222 11111111

¡ Semiconductor MSM80C31F/80C51F Instruction Set Details (continued) D6 D 5 D 4 D 3 D 1 BytesCyclesType Mnemonic Instruction code DescriptionD7 D 2 D 0 Subroutine instructions 11000000PUSH direct 22 (SP) ¬ (SP)+1 ((SP)) ¬ (direct address) 11010000POP direct 22 (direct address) ¬ ((SP)) (SP) ¬ (SP)–1 10 001ACALL addr 22 (PC) ¬ (PC)+2 (SP) ¬ (SP)+1 ((SP)) ¬ (PC0 - 7) (SP) ¬ (SP)+1 (PC0 - 10) ¬ A0 - 10 A7 A6 A5 A4 A3 A2 A1 A0 00010010LCALL addr 32 (PC) ¬ (PC)+3 (SP) ¬ (SP)+1 ((SP)) ¬ (PC0 - 7) (SP) ¬ (SP)+1 (PC0 - 10) ¬ A0 - 10 00100010RET 12 (PC8 - 15) ¬ ((SP)) (SP) ¬ (SP)–1 (PC0 - 7) ¬ ((SP)) (SP) ¬ (SP)–1 a7 a6 a5 a4 a3 a2 a1 a0 a7 a6 a5 a4 a3 a2 a1 a0 00110010RETI 12 (PC8 - 15) ¬ ((SP)) (SP) ¬ (SP)–1 (PC0 - 7) ¬ ((SP)) (SP) ¬ (SP)–1 A10 A9 A8 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 00 001AJMP addr 11 22 (PC) ¬ (PC)+2 (PC0 - 10) ¬ A0 - 10A7 A6 A5 A4 A3 A2 A1 A0 A10 A9 A8 00000010LJMP addr 16 32 (PC0 - 15) ¬ A0 - 15 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 10000000SJMP rel 22 (PC) ¬ (PC)+3 (SP) ¬ (SP)+1 01110011JMP @A+ DPTR 12 (PC) ¬ (A)+(DPTR) Jump instructions R7 R6 R5 R4 R3 R2 R1 R0

¡ Semiconductor MSM80C31F/80C51F Instruction Set Details (continued) D6 D 5 D 4 D 3 D 1 BytesCyclesType Mnemonic Instruction code DescriptionD7 D 2 D 0 Branch instructions 10110101CJNE A, direct, rel 32 (PC) ¬ (PC)+3 IF (A)¹(direct address) THEN (PC) ¬ (PC)+relative offset IF (A)<(direct address) THEN (C) ¬ 1 ELSE (C) ¬ 0 a7 a6 a5 a4 a3 a2 a1 a0 R7 R6 R5 R4 R3 R2 R1 R0 10110100CJNE A, #data, rel 32 (PC) ¬ (PC)+3 IF (A)¹ #data THEN (PC) ¬ (PC)+relative offset IF (A)< #data THEN (C) ¬ 1 ELSE (C) ¬ 0 I

7 I6 I5 I4 I3 I2 I1 I0

10111 r 2 r1 r0CJNE Rr, #data, rel 32 (PC) ¬ (PC)+3 IF ((Rr))¹ #data THEN (PC) ¬ (PC)+relative offset IF (Rr))< #data THEN (C) ¬ 1 ELSE (C) ¬ 0 I 1011011r 0CJNE @Rr, #data, rel 32 (PC) ¬ (PC)+3 IF ((Rr))¹ #data THEN (PC) ¬ (PC)+relative offset IF ((Rr))< #data THEN (C) ¬ 1 ELSE (C) ¬ 0 I 11011 r 2 r1 r0DJNZ Rr, rel 22 (PC) ¬ (PC)+2 (Rr) ¬ (Rr)–1 IF (Rr)< 0 THEN (PC) ¬ (PC)+relative offset R

7 R6 R5 R4 R3 R2 R1 R0

11010101DJNZ direct, rel 32 (PC) ¬ (PC)+3 (direct address) ¬ (direct address)–1 IF (direct address)¹ 0 THEN (PC) ¬ (PC)+relative offset a 7 a6 a5 a4 a3 a2 a1 a0 R7 R6 R5 R4 R3 R2 R1 R0

¡ Semiconductor MSM80C31F/80C51F Instruction Set Details (continued) D6 D 5 D 4 D 3 D 1 BytesCyclesType Mnemonic Instruction code DescriptionD7 D 2 D 0 Branch instructions 01100000JZ rel 22 (PC) ¬ (PC)+2 IF (A) = 0 THEN (PC) ¬ (PC)+relative offset R7 R6 R5 R4 R3 R2 R1 R0 00000000NOP 11 (PC) ¬ (PC)+1 01110000JNZ rel 22 (PC) ¬ (PC)+2 IF (A) ¹ 0 THEN (PC) ¬ (PC)+relative offset R7 R6 R5 R4 R3 R2 R1 R0 01000000JC rel 22 (PC) ¬ (PC)+2 IF (C) = 1 THEN (PC) ¬ (PC)+relative offset R 01010000JNC rel 22 (PC) ¬ (PC)+2 IF (C) = 0 THEN (PC) ¬ (PC)+relative offset R 00100000JB bit, rel 32 (PC) ¬ (PC)+3 IF (bit address) = 1 THEN (PC) ¬ (PC)+relative offset b 7 b6 b5 b4 b3 b2 b1 b0 R7 R6 R5 R4 R3 R2 R1 R0 00110000JNB bit, rel 32 (PC) ¬ (PC)+3 IF (bit address) = 0 THEN (PC) ¬ (PC)+relative offset b 7 b6 b5 b4 b3 b2 b1 b0 R7 R6 R5 R4 R3 R2 R1 R0 00010000JBC bit, rel 32 (PC) ¬ (PC)+3 IF (bit address) = 1 THEN (bit address) ¬ 0 (PC) ¬ (PC)+relative offset b 7 b6 b5 b4 b3 b2 b1 b0 R7 R6 R5 R4 R3 R2 R1 R0 1110000r 0MOVX A, @Rr 12 (A) ¬ ((Rr)) EXTERNAL RAM 11100000MOVX A, @DPTR 12 (A) ¬ ((DPTR)) EXTERNAL RAM 1111001r 0MOVX @Rr, A 12 (Rr) ¬ (A) EXTERNAL RAM 11110000MOVX @DPTR, A 12 ((DPTP)) ¬ (A) EXTERNAL RAM External memory instructions Other instructions

¡ Semiconductor MSM80C31F/80C51F ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Supply Voltage V CC –0.5 to +7.0 V Voltage from Any Pin to VSS VI –0.5 to VCC +7.0 V Storage Temperature T STG –55 to +150 °C Ta = 25°C Ta = 25°C OPERATING RANGE Parameter Symbol Condition Range Unit Supply Voltage V CC 2.5 to 6 V Oscillation Frequency f OSC DC to 16 Ambient Temperature Ta –40 to +85 °C MHzSee figure below MSM80C31F/51F See figure below Memory Retention Voltage V CC 2 to 6 VfOSC = Oscillation stop –20 to +70MSM80C31F-1 *1 DC & AC characteristics in the range of 2.5 V £ VCC < 4 V will be specified by DC & AC Characteristics 2. *2 Specify MSM80C31F-1 when using MSM80C31F at 12 MHz to 16 MHz. GUARANTEED OPERATING RANGE 0.75 23 4 5 6 [ms] 1.2 Ta = –40 to +85°C (MSM80C31F/80C51F) Ta = –20 to +70°C (MSM80C31F-1) Operating Range MSM80C31/51 MSM80C31F/51F MSM80C31F-1 Cycle Time (tcy) Oscillation Frequency (fOSC) Supply Voltage (VCC) [V]

¡ Semiconductor MSM80C31F/80C51F

ELECTRICAL CHARACTERISTICS

0.2 VCC – 0.1 Parameter Symbol Condition Min. Typ. Max. Unit Low Input Voltage V IL — –0.5 — V VCC + 0.5High Input Voltage V IH Except XTAL1, RESET 0.2 VCC + 0.9 — Vand EA VCC + 0.5High Input Voltage V IH1 XTAL1, RESET and EA 0.7 VCC —V 0.45 Low Output Voltage VOL IOL = 1.6 mA — — V(Port 1, 2 and 3) 0.45 Low Output Voltage VOL1 IOL = 3.2 mA — — V(Port 0, ALE and PSEN) —High Output Voltage VOH IOH = –60 mA 2.4 — V (Port 1, 2 and 3) VCC = 5 V ±10% —IOH = –30 mA 0.75 V CC —V —IOH = –10 mA 0.9 V CC —V —High Output Voltage VOH1 IOH = –400 mA 2.4 — V (Port 0, ALE and PSEN) VCC = 5 V ±10% —IOH = –150 mA 0.75 V CC —V —IOH = –40 mA 0.9 V CC —V –200 Output Current at Low Input/ High Output Power Supply IIL / IOH VI = 0.45 V –10 — mAVO = 0.45 V –500ITL VIL = 2.0 V — — mA 125RESET Pull-down Resistor R RST —2 0 4 0 k W 10Input Pin Capacitor C IO Ta = 25°C, f = 1 MHz —— p F5 V (except XTAL1) 50Power Down Current I PD VCC = 2 V — 1 mA 3±10 Input Leakage Current ILI VSS < VI < VCC —— mA(Floating Port 0 and EA) Output Current (Port 1, 2 and 3) at transition from H to L MSM80C31F/51F V CC = 5 V ±20%, VSS = 0 V, Ta = –40°C to +85°C MSM80C31F-1/51F-1 VCC = 5 V ±5%, VSS = 0 V, Ta = –20°C to +70°C

¡ Semiconductor MSM80C31F/80C51F DC Characteristics 2 Meas- uring circuit 0.25VCC – 0.1 Parameter Symbol Condition Min. Typ. Max. Unit Low Input Voltage V IL — –0.5 — V VCC + 0.5High Input Voltage V IH Except XTAL1, RESET 0.25VCC + 0.9 — Vand EA VCC + 0.5High Input Voltage V IH1 XTAL1, RESET and EA 0.6VCC + 0.6 — V 0.1 Low Output Voltage VOL IOL = 10 mA— — V(Port 1, 2 and 3) 0.1 Low Output Voltage VOL1 IOL = 20 mA— — V(Port 0, ALE and PSEN) High Output Voltage VOH —V(Port 1, 2 and 3) IOH = –5 mA 0.75 V CC High Output Voltage VOH1 —V(Port 0, ALE and PSEN) IOH = –20 mA 0.75 V CC –100 Output Current at Low Input/ High Output Power Supply IIL / IOH VI = 0.1 V —— mAVO = 0.1 V –300ITL VIL = 1.9 V — — mA 125RESET Pull-down Resistor R RST —2 0 4 0 k W 10Input Pin Capacitor C IO Ta = 25°C, f = 1 MHz —— p F5 V (except XTAL1) 10Power Down Current I PD —— 1 mA 3±10 Input Leakage Current ILI VSS < VI < VCC —— mA(Floating Port 0 and EA) Output Current (Port 1, 2 and 3) at transition from H to L CC = 2.5 to 4.0 V, VSS = 0 V, Ta = –40 to +85°C)

¡ Semiconductor MSM80C31F/80C51F Maximum operating power supply I CC [mA] VCC 2.5 V 3.0 V 4.0 V Freq 0.7 0.9 1.60.5 MHz 1.9 2.4 4.33.0 MHz — — 8.38 MHz — — 12.012 MHz VCC 2.5 V 3.0 V 4.0 V Freq 0.3 0.4 0.60.5 MHz 0.6 0.8 1.23.0 MHz — — 2.28 MHz — — 3.112 MHz Maximum IDLE power supply I CC [mA]

¡ Semiconductor MSM80C31F/80C51F Measuring Circuit VCC VSS INPUT OUTPUT VIH VIL (*2) V A IO VCC VSS INPUT OUTPUT (*1) V VCC VSS INPUT OUTPUT VIH VIL (*2) V A VCC VSS INPUT OUTPUT VIH VIL A A (*3) (*3) (*3) *1 Repeated for specified input pin. *2 Repeated for specified output pin. *3 Logic input for specified condition.

¡ Semiconductor MSM80C31F/80C51F External Program Memory Access AC Characteristics 1 (VCC = 5 V –20%, VSS = 0 V, Ta = –40°C to +85°C; Load Capacitance for Port 0, ALE, and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF) Parameter Symbol Min. Max. Unit XTAL1, XTAL2 Oscillation Cycle tCLCL —— n s ALE Signal Width t LHLL 126 — ns Adderss Setup Time (to ALE Falling Edge) tAVLL 43 — ns Max. Min. 83.3 CLCL – 40 1tCLCL – 40 Adderss Hold Time (from ALE Falling Edge) tLLAX 48 — ns —1 t CLCL – 35 Instruction Data Read Time (from ALE Falling Edge) tLLIV —4 t CLCL – 100 ns233 — From ALE Falling Edge to PSEN Falling Edge tLLPL 58 — ns —1 t CLCL – 25 PSEN Signal Width t PLPH 215 — ns —3 t CLCL – 35 Instruction Data Read Time (from PSEN Falling Edge) tPLIV —3 t CLCL – 105 ns145 — Instruction Data Hold Time (from PSEN Rising Edge) tPXIX 0— n s —0 Bus Floating Time after Instruction Data Read (from PSEN Rising Edge) tPXIZ —1 t CLCL – 20 ns63 — Address Output Time from PSEN Rising Edge tPXAV 75 — ns —1 t CLCL – 8 Instruction Data Read Time (from Address Output) tAVIV —5 t CLCL – 105 ns312 — Bus Floating Time (Address Float from PSEN Falling Edge) tPLAZ —0 n s 0—

12 MHz Clock

¡ Semiconductor MSM80C31F/80C51F External Program Memory Access AC Characteristics 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –40°C to +85°C; Load Capacitance for Port 0, ALE, and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF) Parameter Symbol Min. Max. Unit XTAL1, XTAL2 Oscillation Cycle tCLCL —— n s ALE Signal Width t LHLL 126 — ns Adderss Setup Time (to ALE Falling Edge) tAVLL 43 — ns Max. Min. 83.3 CLCL – 40 1tCLCL – 40 Adderss Hold Time (from ALE Falling Edge) tLLAX 48 — ns —1 t CLCL – 35 Instruction Data Read Time (from ALE Falling Edge) tLLIV —4 t CLCL – 100 ns233 — From ALE Falling Edge to PSEN Falling Edge tLLPL 58 — ns —1 t CLCL – 25 PSEN Signal Width t PLPH 215 — ns —3 t CLCL – 35 Instruction Data Read Time (from PSEN Falling Edge) tPLIV —3 t CLCL – 105 ns145 — Instruction Data Hold Time (from PSEN Rising Edge) tPXIX 0— n s —0 Bus Floating Time after Instruction Data Read (from PSEN Rising Edge) tPXIZ —1 t CLCL – 20 ns63 — Address Output Time from PSEN Rising Edge tPXAV 75 — ns —1 t CLCL – 8 Instruction Data Read Time (from Address Output) tAVIV —5 t CLCL – 105 ns312 — Bus Floating Time (Address Float from PSEN Falling Edge) tPLAZ —0 n s 0—

¡ Semiconductor MSM80C31F/80C51F External Program Memory Read Cycle tLHLL tAVLL tLLPL tPLPH tLLIV tPLIV tPXAV tPXIZ tLLAX tPLAZ tAVIV tPXIX A0~A7 INSTR IN A0~A7PORT0 PORT2 A8~A15 A8~A15 A8~A15 PSEN ALE

¡ Semiconductor MSM80C31F/80C51F External Data Memory Access AC Characteristics 1 (VCC = 5 V –20%, VSS = 0 V, Ta = –40°C to +85°C; load capacitance for Port 0, ALE, and PSEN = 100 pF ; load capacitance for all other outputs = 80 pF) Parameter Symbol Min. Max. Unit XTAL1, XTAL2 Oscillation Cycle tCLCL —— n s ALE Single Width t LHLL 126 — ns Adderss Setup Time (to ALE Falling Edge) tAVLL 43 — ns Max. Min. 62.5 CLCL – 40 1tCLCL – 40 Adderss Hold Time (from ALE Falling Edge) tLLAX 48 — ns —1 t CLCL – 35 RD Single Width t RLRH 400 — ns —6 t CLCL – 100 WR Single Width t WLWH 400 — ns —6 t CLCL – 100 RAM Data Read Time (from RD Single Falling Edge) tRLDV —5 t CLCL – 165 ns251 — RAM Data Read Hold Time (from RD Single Rising Edge) tRHDX 0— n s —0 Data Bus Floating Time (from RD Single Rising Edge) tRHDZ —2 t CLCL – 70 ns96 — RAM Data Read Time (from ALE Single Falling Edge) tLLDV —8 t CLCL – 150 ns516 — RAM Data Read Time (from Address Output) tAVDV —9 t CLCL – 165 ns585 — RD/WR Output Time from ALE Falling Edge tLLWL 200 3t CLCL + 50 ns300 3t CLCL – 50 RD/WR Output Time from Address Output tAVWL 203 — ns —4 t CLCL – 130 RD Output Time from Data Output tQVWX 23 — ns —1 t CLCL – 60 Time from Data Output to WR Rising Edge tQVWH 433 — ns —7 t CLCL – 150 Data Hold Time (WR Rising Edge) tWHQX 33 — ns —1 t CLCL – 50 Time from RD Output to Address Float tRLAZ —0 n s 0— Time from RD/WR Rising Edge to ALE Rising Edge tWHLH 43 1t CLCL + 50 ns133 1t CLCL – 40 See Guaranteed Operating Range

¡ Semiconductor MSM80C31F/80C51F External Data Memory Access AC Characteristics 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –40°C to +85°C; load capacitance for Port 0, ALE, and PSEN = 100 pF ; load capacitance for all other outputs = 80 pF) Parameter Symbol Min. Max. Unit XTAL1, XTAL2 Oscillation Cycle tCLCL —— n s ALE Single Width t LHLL 126 — ns Adderss Setup Time (to ALE Falling Edge) tAVLL 43 — ns Max. Min. 62.5 CLCL – 40 1tCLCL – 40 Adderss Hold Time (from ALE Falling Edge) tLLAX 48 — ns —1 t CLCL – 35 RD Single Width t RLRH 400 — ns —6 t CLCL – 100 WR Single Width t WLWH 400 — ns —6 t CLCL – 100 RAM Data Read Time (from RD Single Falling Edge) tRLDV —5 t CLCL – 165 ns251 — RAM Data Read Hold Time (from RD Single Rising Edge) tRHDX 0— n s —0 Data Bus Floating Time (from RD Single Rising Edge) tRHDZ —2 t CLCL – 70 ns96 — RAM Data Read Time (from ALE Single Falling Edge) tLLDV —8 t CLCL – 150 ns516 — RAM Data Read Time (from Address Output) tAVDV —9 t CLCL – 165 ns585 — RD/WR Output Time from ALE Falling Edge tLLWL 150 3t CLCL + 50 ns300 3t CLCL – 100 RD/WR Output Time from Address Output tAVWL 203 — ns —4 t CLCL – 130 RD Output Time from Data Output tQVWX 23 — ns —1 t CLCL – 60 Time from Data Output to WR Rising Edge tQVWH 433 — ns —7 t CLCL – 150 Data Hold Time (WR Rising Edge) tWHQX 33 — ns —1 t CLCL – 50 Time from RD Output to Address Float tRLAZ —0 n s 0— Time from RD/WR Rising Edge to ALE Rising Edge tWHLH 43 1t CLCL + 100 ns183 1t CLCL – 40 See Guaranteed Operating Range

¡ Semiconductor MSM80C31F/80C51F External Data Memory Read Cycle tLHLL tWHLH tLLDV tLLWL tRLRH tAVLL tLLAX tRLAZ tRLDV tRHDX tRHDZ tAVWL tAVDV PCH A8~A15 PCH P2.0~P2.7 DATA A8~A15 DPH or A8~A15 PCH A0~A7 PCL A0~A7 Rr or DPL A0~A7 PCL INSTR IN ALE PSEN RD PORT 0 PORT 2 External Data Memory Write Cycle tLHLL tWHLH tLLWL tWLWH tAVLL tLLAX tQVWX tQVWH tWHQX tAVWL A8~A15 PCH P2.0~P2.7 DATA A8~A15 DPHor A8~A15 PCH A0~A7 PCL A0~A7 Rr or DPL A0~A7 PCL INSTR IN ALE PSEN WR PORT 0 PORT 2 DATA (ACC) A8~A15 PCH

¡ Semiconductor MSM80C31F/80C51F Serial Port Timing (I/O Expansion Mode) AC Characteristics 1 tXLXL MACHINE CYCLE ALE SHIFT CLOCK OUTPUT DATA INPUT DATA tQVXH tXHQX tXHDV tXHDX VALID VALID VALID VALID VALID VALID VALID VALID 01234567 123456780 SymbolParameter Min. Max. Unit tXLXL 12tCLCL — ns tQVXH 10tCLCL – 133 — ns tXHQX 2tCLCL – 117 — ns tXHDX 0 — ns tXHDV — 10tCLCL – 133 ns (Ta = –40°C to +85°C ; V CC = 5 V ±20% ; VSS = 0 V) Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid

¡ Semiconductor MSM80C31F/80C51F Serial Port Timing (I/O Expansion Mode) AC Characteristics 2 SymbolParameter Min. Max. Unit tXLXL 12tCLCL — ns tQVXH 10tCLCL – 133 — ns tXHQX 2tCLCL – 117 — ns tXHDX 0 — ns tXHDV — 10tCLCL – 133 ns (Ta = –40°C to +85°C ; V C C =2.5 to 4.0 V ; VSS = 0 V) Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid tXLXL MACHINE CYCLE ALE SHIFT CLOCK OUTPUT DATA INPUT DATA tQVXH tXHQX tXHDV tXHDX VALID VALID VALID VALID VALID VALID VALID VALID 01234567 123456780

¡ Semiconductor MSM80C31F/80C51F AC Characteristics Measuring Conditions Input/output signal VOH VOL VIH VIL VIH VIL TEST POINT VOH VOL * The input signals in AC test mode are either V OH (logic "1") or VOL (logic "0") input signals where logic "1" corresponds to a CPU output signal waveform measuring point in excess of V IH, and logic "0" to a point below V IL. Floating * The port 0 floating interval is measured from the time the port 0 pin voltage drops below VIH after sinking to GND at 2.4 mA when switching to floating status from a "1" output, and from the time the port 0 pin voltage exceeds V IL after connecting to a 400 mA source when switching to floating status from a "0" output. VOH VOL VIH VIL VIH VIL Floating VOH VOL XTAL1 External Clock Input Waveform Conditions Parameter Min. Max. Unit Symbol Variable Clock See Guaranteed Operating Range External Clock Frequency 1/t CLCL DC 16 MHz High Time t CHCX 20 — ns Low Time t CLCX 20 — ns Rise Time t CLCH —2 0n s Fall Time t CHCL —2 0n s External clock waveform 0.7VCC 0.2VCC – 0.10.45 V VCC – 0.5 tCHCL tCLCH tCLCX tCLCL tCHCX

¡ Semiconductor MSM80C31F/80C51F (Unit : mm) PACKAGE DIMENSIONS DIP40-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP.

¡ Semiconductor MSM80C31F/80C51F (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP. QFP44-P-910-0.80-2K Mirror finish

¡ Semiconductor MSM80C31F/80C51F (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). QFJ44-P-S650-1.27 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP. Mirror finish

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