MSM7705-01 OKI | Alldatasheet

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¡ Semiconductor MSM7705-01/02/03 ¡ Semiconductor MSM7705-01/02/03 4ch Single Rail CODEC GENERAL DESCRIPTION The MSM7705-01/02/03 are four-channel CODEC CMOS ICs for voice signals ranging from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion. Designed especially for a single-power supply and low-power applications, these devices contain four-channel A/D and D/A converters in a single chip and achieve a reduced footprint and a reduced number of external components. The MSM7705-01/02/03 are best suited for digital telephone terminals, digital PABXs, and push- button phones.

FEATURES

  • Single power supply: +5 V
  • Power consumption Operating mode: 70 mW Typ. 140 mW Max. Power-saving mode: 14 mW Typ. 32 mW Max. Power-down mode: 0.05 mW Typ. 0.3 mW Max.
  • Conforms to ITU-T Companding law MSM7705-01: m/A-law pin-selectable MSM7705-02: m-law MSM7705-03: A-law
  • Built-in PLL eliminates a master clock
  • The PCM interface can be switched between 4 channel serial/parallel
  • Transmission clock: 64/128/256/512/1024/2048 kHz 96/192/384/768/1536/1544 kHz (During 4 channel serial mode, the 64, 96, 128, and 192 kHz clocks are disabled)
  • Transmit gain adjustable for each channel
  • Built-in reference voltage supply
  • Analog output can directly drive a 600 W line transformer
  • Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name : MSM7705-01GS-2K) (Product name : MSM7705-02GS-2K) (Product name : MSM7705-03GS-2K) E2U0042-28-81 This version: Aug. 1998 Previous version: Nov. 1996

¡ Semiconductor MSM7705-01/02/03 BLOCK DIAGRAM AIN1 GSX1 AIN2 GSX2 AOUT1 AOUT2 SGC XSYNC DOUT1 DOUT2 BCLK RSYNC (ALAW) DIN1 DIN2 PDN VDD AG DG RC LPF 8th BPF RC LPF 8th BPF 5th LPF S&H 5th LPF S&H SG GEN VR GEN AD CONV. TCONT AUTO ZERO DA CONV. PLL RTIM RCONT PWD Logic AIN3 GSX3 AIN4 GSX4 RC LPF 8th BPF RC LPF 8th BPF AD CONV. AUTO ZERO AOUT3 AOUT4 5th LPF S&H 5th LPF S&H DA CONV. DOUT3 DOUT4 CHPS DIN3 DIN4

¡ Semiconductor MSM7705-01/02/03 PIN CONFIGURATION (TOP VIEW) VDD, DG, and AG have two pins each. Each of these pairs are internally connected with each other. * The ALAW pin is only supported by MSM7705-01GS-2K. 11 23 /#04 NC NC NC V DD VDD NC NC DIN4 DIN3 DIN2 DIN1 RSYNC XSYNC BCLK NC DG DG NC DOUT4 DOUT3 DOUT2 DOUT1 CHPS PDN (ALAW)* NC NC NC NC AIN1 GSX1 GSX2 AIN2 AIN3 GSX3 GSX4 AIN4 SGC AG AG AOUT1 AOUT2 AOUT3 AOUT4 NC : No connect pin ( ( 44-Pin Plastic QFP

¡ Semiconductor MSM7705-01/02/03 PIN AND FUNCTIONAL DESCRIPTIONS AIN1, AIN2, AIN3, AIN4, GSX1, GSX2, GSX3, GSX4 AIN1, AIN2, AIN3, and AIN4 are the transmit analog inputs for channels 1, 2, 3 and 4 respectively. GSX1, GSX2, GSX3, and GSX4 are the transmit level adjustments for channels 1, 2, 3 and 4 respectively. AIN1, AIN2, AIN3, and AIN4 are connected to the inverting inputs for the op-amps. GSX1, GSX2, GSX3, and GSX4 are connected to the outputs for the op-amps. They are used to adjust levels as shown below, and are connected to the outputs of the op-amps. During power saving mode and power down mode, the GSX1, GSX2, GSX3, and GSX4 outputs are at 0 V. When these pins are not used, connect AIN1 to GSX1, AIN2 to GSX2, AIN3 to GSX3, and AIN4 to GSX4. CHn Analog Input + –AINnC1n R1n R2n GSXn CHn Gain Gain = R2n/R1n £ 10 R1n: Variable R2n > 20 kW AOUT1, AOUT2, AOUT3, AOUT4 AOUT1, AOUT2, AOUT3, and AOUT4 are the receive filter outputs for channels 1, 2, 3, and 4 respectively. When the digital signal of +3 dBm0 is input to DIN1, DIN2, DIN3, and DIN4, the output signal has an amplitude of 3.4 V PP above and below the signal ground voltage (SG : 1/2 V DD). The output can drive a load of 600 W or more. During power saving or power down mode, these outputs are at the voltage level of SG with a high impedance.

¡ Semiconductor MSM7705-01/02/03 DIN1, DIN2, DIN3 PCM signal inputs for channels 1, 2, and 3 when the parallel mode is selected. D/A conversion is performed by the serial PCM signals to these pins, the RSYNC signals synchronous with the serial PCM signals, and the BCLK signal. Then the analog signals are output from AOUT1, AOUT2, and AOUT3 pins, respectively. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is not used and should be connected to GND (0 V). DIN4 PCM signal input for channel 4 when the parallel mode is selected. D/A conversion is performed by the serial PCM signal to this pin, the RSYNC signal synchronous with the serial PCM signal, and the BCLK signal. Then the analog signal is output from AOUT4 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSD) is identified at the rising edge of RSYNC. When the serial mode is selected, this pin is used for the 4ch multiplexed PCM signal input. BCLK Shift clock signal input for DIN1, DIN2, DIN3, DIN4, DOUT1, DOUT2, DOUT3, and DOUT4. The frequency is equal to the data rate. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving state. RSYNC Receive synchronizing signal input. Eight bits of PCM data required are selected from a series of PCM signal to the DIN1, DIN2, DIN3, and DIN4 pins by the receive synchronizing signal. All timing signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK (generated from the same clock source as BCLK). The frequency should be 8 kHz –50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the receive section. However, this device operates in the range of 6 kHz to 10 kHz unless the frequency characteristics of the system used are strictly specified, but the electrical characteristics specified in the data sheet are not guaranteed.

¡ Semiconductor MSM7705-01/02/03 XSYNC Transmit synchronizing signal input. PCM output signal from the DOUT1, DOUT2, DOUT3, and DOUT4 pins is output in synchronization with this transmit synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. This synchronizing signal must be synchronized in phase with BCLK. The frequency should be 8 kHz –50 ppm to guarantee the AC characteristics which are mainly the frequency characteristics of the transmit section. However, this device can be operated in the range of 6 kHz to 10 kHz unless the frequency characteristics of the system used are strictly specified, but the electrical characteristics are not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to power saving state. DOUT1 PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is configured to be the output of serial multiplexed 4ch PCM signal. A pull-up resistor must be connected to this pin because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7705-03 (A-law) outputs the character signal, inverting the even bits. Input/Output Level +Full scale –Full scale PCMIN/PCMOUT MSM7705-02 (m-law) MSD 1000 0000 1111 1111 0111 1111 0000 0000 MSM7705-03 (A-law) MSD 1010 1010 1101 0101 0101 0101 0010 1010

¡ Semiconductor MSM7705-01/02/03 DOUT2, DOUT3, DOUT4 PCM signal outputs for channels 2, 3, and 4 when parallel mode is selected. The PCM output signal is output from MSD in a sequential order, synchronizing with the rising edge of the BCLK signal. MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK and XSYNC. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down state. When the serial mode is selected, this pin is unconnected. A pull-up resistor must be connected to each of these pins because it is an open drain output. This device is compatible with the ITU-T recommendation on coding law and output coding format. The MSM7705-03 (A-law) outputs the character signal inverting the even bits. CHPS Control signal input for the mode selection of PCM input and output. When this signal is at a logic "1" level, the PCM input and output are in parallel mode. The PCM data of CH1, CH2, CH3, and CH4 is input to DIN1, DIN2, DIN3, and DIN4 outputs from DOUT1, DOUT2, DOUT3, and DOUT4 with the same timing. When this signal is at logic "0" level, the PCM input and output are in serial mode. The PCM data of CH1 to CH4 is input from DIN4 and output from DOUT1 as time division multiplexed data. PDN Power down control signal. When PDN is at a logic "0" level, both transmit and receive circuits are in power down state. V DD Power supply for +5 V. A power supply for an analog circuit in the system to which the device is applied should be used. A bypass capacitor of 0.1 mF to 1 mF with excellent high-frequency characteristics and a capacitor of 10 mF to 20 mF should be connected between this pin and the AG pin if needed. AG Analog signal ground. DG Ground for digital signal circuits. This ground is separate from the analog signal ground. The DG pin must be connected to the AG pin on the printed circuit board to make a common analog ground.

¡ Semiconductor MSM7705-01/02/03 SGC Used to generate the signal ground voltage level by connecting a bypass capacitor. Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. ALAW Control signal input of the companding law selection. Only the MSM7705-01GS-2K has this pin. The CODEC will operate in the m-law when this pin is at a logic "0" level and will operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is left open, since this pin is internally pulled down.

¡ Semiconductor MSM7705-01/02/03 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition Rating 0 to 7.0 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –55 to +150 Unit V V V Parameter Power Supply Voltage Operating Temperature Analog Input Voltage High Level Input Voltage Low Level Input Voltage Clock Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time Sync Pulse Width DIN Setup Time DIN Hold Time Digital Output Load Analog Input Allowable DC Offset Allowable Jitter Width Symbol VDD Ta VAIN VIH VIL FC FS DC tIr tIf tXS tSX tRS tSR tWS tDS tDH RDL CDL Voff Condition Voltage must be fixed Gain = 1 XSYNC, RSYNC, BCLK, DIN1, DIN2, DIN3, DIN4, PDN, CHPS, ALAW BCLK = (When in 4ch serial mode, 64, 96, 128, 192 kHz are not used) XSYNC, RSYNC BCLK XSYNC, RSYNC, BCLK, DIN1, DIN2, DIN3, DIN4, PDN, CHPS BCLK®XSYNC, See Fig. 1 BCLK®RSYNC, See Fig. 1 XSYNC, RSYNC DIN1, DIN2, DIN3, DIN4 DIN1, DIN2, DIN3, DIN4 DOUT1, DOUT2, Transmit gain stage, Gain = 1 XSYNC, RSYNC XSYNC®BCLK, See Fig. 1 RSYNC®BCLK, See Fig. 1 Transmit gain stage, Gain = 10 DOUT3, DOUT4 Pull-up resistor Min. 4.75 –30 2.2 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544 6.0 100 100 100 100

1 BCLK

0.5 VDD/2 –100 VDD/2 –10 Typ. 5.0 +25 8.0 Max. 5.25 +85 3.4 V DD 0.8 10.0 100 100 VDD/2 +100 500 VDD/2 +10 Unit V VPP V V kHz ns ns ns ns ns ns ms ns ns kW pF mV ns mV kHz

¡ Semiconductor MSM7705-01/02/03

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics Transmit Analog Interface Characteristics Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage R INX RLGX CLGX VOGX VOSGX AIN1, AIN2, AIN3, AIN4 Gain = 1 –1.7 –20 +1.7 +20 MW kW pF V mV GSX1, GSX2, GSX3, GSX4 with respect to SG Parameter Symbol Condition Min. Typ. Max. Unit (VDD = +5 V ± 5%, Ta = –30°C to +85°C) Receive Analog Interface Characteristics Output Load Resistance Output Load Capacitance RLAO CLAO 0.6 kW pF Output Amplitude Offset Voltage VOAO VOSAO –1.7 –100 +1.7 +100 V mV AOUT1 AOUT2 AOUT3 AOUT4 Parameter Symbol Condition Min. Typ. Max. Unit (VDD = +5 V ±5%, Ta = –30°C to +85°C) Each output; with respect to SG RL = 0.6 kW; with respect to SG Parameter Power Supply Current High Level Input Voltage Low Level Input Voltage High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance Symbol IDD1 IDD2 IDD3 VIH VIL IIH IIL VOL IO Condition Operating mode, No signal Power-save mode, PDN = 1, XSYNC or BCLK OFF Power-down mode, PDN = 0 BCLK OFF Pull-up resistor > 500 W Min. 0.0 0.0 Typ. 14.0 2.6 0.01 0.2 Max. 28.0 6.0 0.05 V DD 2.0 0.5 0.4 Unit mA mA mA V V mA mA V mA CIN — —5— p F (VDD = +5 V ±5%, Ta = –30°C to +85°C) 2.2 0.8

¡ Semiconductor MSM7705-01/02/03 AC Characteristics Condition (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Symbol Min. Typ. Max. Unit Transmit Frequency Response Loss T1 Level (dBm0) 60 20 26 — Freq. (Hz) Loss T2 300 –0.15 +0.07 +0.20 Loss T3 1020 Reference dB0Loss T4 2020 –0.15 –0.04 +0.20 Loss T5 3000 –0.15 +0.03 +0.20 Loss T6 3400 0 0.40 0.80 Receive Frequency Response Loss R1 300 –0.15 –0.03 +0.20 Loss R2 1020 Reference Loss R3 2020 –0.15 +0.04 +0.20 dB0 Loss R4 3000 –0.15 +0.11 +0.20 Loss R5 3400 0.0 0.47 0.80 SD T1 35 43 — 3 SD T2 35 41 — 0 SD T3 35 38 — –30Transmit Signal to Distortion Ratio 1020 dB SD T4 29 31.5 — –40 SD T5 24 27 — –45 SD R1 36 43 — 3 SD R2 36 41 — 0 SD R3 36 40 — –30Receive Signal to Distortion Ratio 1020 dB SD R4 30 33.5 — –40 SD R5 25 30 — –45 Transmit Gain Tracking GT T2 Reference GT T3 1020 –0.3 +0.04 +0.3 dB–40 –10 –50 –55 Receive Gain Tracking GT R2 Reference GT R3 1020 –0.3 +0.04 +0.3 dB –40 –10 –50 –55 *1 Psophometric filter is used

¡ Semiconductor MSM7705-01/02/03 AC Characteristics (Continued) *1 Psophometric filter is used *2 Upper columns are specified for the m-law, lower for the A-law *3 Input "0" code to PCMIN *4 Minimum value of the group delay distortion Absolute Level (Initial Difference) Nidle T — — –73.5 –71.5 –70 –68 dBm0p Nidle R — –78 AV T 0.821 0.850 0.880 AV R 0.821 0.850 0.880 Vrms 1020 Absolute Delay AV Rt –0.2 — +0.2 tD 1020 — — 0.60 ms0 A to A BCLK = 64 kHz Transmit Group Delay tGD T1 — 0.19 0.75 tGD T2 — 0.11 0.35 tGD T3 — 0.02 0.125 0 tGD T4 — 0.05 0.125 ms*4 0.07tGD T5 — 0.75 Receive Group Delay — 0.00 0.75 0.00 — 0.00 0.125 ms0 — 0.09 0.125 — 0.12 0.75 — –75 Idle Channel Noise — AIN = SG *1 *3 *1 *2 dB dB VDD = 5.0 V Ta = 25°C VDD = 5 V ±5% Ta = –30 to +85°C Absolute Level (Deviation of Temperature and Power) 500 600 1000 2600 2800 Crosstalk Attenuation C R T 7 58 0— CR R 76 1020 dB 0 TRANS ® RECV RECV ® TRANS tGD R1 tGD R2 tGD R3 tGD R4 tGD R5 500 600 1000 2600 2800 70 — — 0.35 Condition (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Symbol Min. Typ. Max. UnitLevel (dBm0) Freq. (Hz) CR CH 80 CH to CH 75 —

¡ Semiconductor MSM7705-01/02/03 AC Characteristics (Continued) *5 Measurement performed under idle channel noise DIS 4.6 kHz to 30 32 — dB Digital Output Delay Time tSD 20 — 200 tXD1 20 — 200 tXD2 20 — 200 tXD3 20 — 200 ns Discrimination 0 0 to 4000 Hz CL = 100 pF + 1 LSTTL S 300 to — –37.5 –35 dBm0Out-of-band Spurious 0 4.6 kHz to IMD fa = 470 — –52 –35 dBm0Intermodulation Distortion –4 2fa – fd PSR T 0 to —3 0— d BPower Supply Noise Rejection Ratio 50 mV PP *5PSR R 72 kHz 3400 fd = 320 50 kHz 100 kHz Condition (VDD = +5 V ±5%, Ta = –30°C to +85°C) Parameter Symbol Min. Typ. Max. UnitLevel (dBm0) Freq. (Hz)

¡ Semiconductor MSM7705-01/02/03 APPLICATION CIRCUIT Example of Basic Connection (PCM Serial Mode Operation) CH1 Analog Input CH1 Analog Output CH2 Analog Input CH2 Analog Output 0 V +5 V 0.1 mF 10 mF1 mF+ AIN1 4ch Multiplex PCM Signal OutputGSX1 AOUT1 AIN2 GSX2 AOUT2 SGC AG DG DOUT1 DOUT2 DIN4 BCLK XSYNC PDN DIN1 RSYNC CHPS V DD +5 V 1 kW (Open) 4ch Multiplex PCM Signal Input 0 V Bit Clock Input Sync Pulse Input Power Down Control Input 1 : Operation 0 : Power Down 0 V MSM7705-01 CH3 Analog Input CH3 Analog Output CH4 Analog Input CH4 Analog Output AIN3 GSX3 AOUT3 AIN4 GSX4 AOUT4 DOUT3 (Open) DOUT4 (Open) DIN2 DIN3 VDD AG DG ALAW Companding Law Control Input 1 : A-law 0 : m-law 1 mF 20 k W 20 kW 1 mF 20 k W 20 kW 1 mF 20 k W 20 kW 1 mF 20 k W 20 kW 1 mF 1 mF 1 mF 1 mF 0 to 20 W

¡ Semiconductor MSM7705-01/02/03

APPLICATION INFORMATION

A value of the pull-up resistor for the DOUT pin should be determined depending on frequencies of BCLK and load capacitance. If a smaller value is used, there may be some degradation in noise performance, resulting in an increase in supply current. Equation to give pull-up resistor – 50 ns CL where fBCLK = CL = 50 ns = Frequency of BCLK Load capacitance of the PCMOUT pin (approximately 20 pF for a CMOS or TTL load) Internal delay of the MSM7705 Condition for Calculation If data is turned back from DOUT to DIN under the condition the SYNC signal and BCLK signal rise simultaneously, the data can normally be transferred. T = Rpull ´ CL X, RSYNC BCLK DOUT T

¡ Semiconductor MSM7705-01/02/03 BCLK (kHz) 128 256 512 1024 1544 2048 385.6 190.3 92.7 43.8 19.4 11.2 7.2 C L = 10 pF 192.8 95.2 46.3 21.9 9.7 5.6 3.6 C L = 20 pF 77.1 38.1 18.5 8.8 3.9 2.2 1.4 C L = 50 pF 38.6 19.0 9.3 4.4 1.9 1.1 0.7 C L = 100 pF Rpull (kW) Choice of Actual Resistor Value If the calculated value is more than or equal to 100 kW, 100 kW should be employed. +10% of the calculated value is within a tolerance, thus, for example, the value of 10 kW can be used for the calculated value of 9.3 kW in the above examples. Channel Crosstalk The MSM7705 contains the 4-channel CODEC. The circuit and trace design and pin layout are made to minimize crosstalk between channels inside the LSI device provided the following should be taken into consideration. Transmit side The GSX1 – AIN2, AIN3, and AIN4 traces should not be kept closer. The GSX2 – AIN1, AIN3, and AIN4 traces should not be kept closer. The GSX3 – AIN1, AIN2, and AIN4 traces should not be kept closer. The GSX4 – AIN1, AIN2, and AIN3 traces should not be kept closer. AIN1, AIN2, AIN3, and AIN4, which are op-amp inverting input pins, have higher resistance, therefore proximity of these lines to signal lines of other channels may cause crosstalk. Receive side The channel outputs AOUT1, AOUT2, AOUT3, and AOUT4 of the receive side are amplifier outputs with lower resistance, thus crosstalk due to PCB traces is smaller. Nevertheless, the PCB traces should not be run closer together and in parallel wherever possible. Calculation Example for Typical Values

¡ Semiconductor MSM7705-01/02/03 How to Avoid Transmit Side Amplifier Oscillation Due to PCB Layout R F AINn GSXn MSM7705 The trace length (illustrated by the bold line in the above drawing) should be kept as short as possible in order to avoid oscillation. The length of less than 2 cm or 3 cm is permissible, though it depends on PCB layout. It is recommended to connect a capacitor of 20 pF to 50 pF across the feedback resistor R F, if the oscillation occurs.

¡ Semiconductor MSM7705-01/02/03 NOTES ON USED

  • To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins.
  • Connect the AG pin and the DG pin as close as possible. Connect to the system ground with low impedance.
  • Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the use of IC socket is unavoidable, use the short lead type socket.
  • When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave sources such as power supply transformers surround the device.
  • Keep the voltage on the V DD pin not lower than –0.3 V even instantaneously to avoid latch- up that may otherwise occur when power is turned on.
  • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of these devices.

¡ Semiconductor MSM7705-01/02/03 (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP. QFP44-P-910-0.80-2K Mirror finish