M67620 | DigiCamel IC Datasheet

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MSM67P620 OKI | Alldatasheet

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OKI'S ORIGINAL nX HIGH PERFORMANCE CMOS 16-BIT SINGLE CHIP MICROCONTROLLER a GENERAL DESCRIPTION MSM67620 is a high-performance 16-bit single-chip microcontroller that employs Oki’s original nX-16 CPU core, and integrates memory as well as peripheral functions on-chip. With a minimum instruction execution time of 200 ns (10MHz clock), the MSM67620 is capable of high-speed Processing, and includes 16 K words (16 x 16 K) of program memory, 256 words (16 x 256) of data memory, 8-bit timers, 16-bit timers, capture input/compare output, a serial port, and other functions on chip. Also available is the MSM67P620, which replaces the on-chip program memory with one-time PROM.

FEATURES

© 16-bit CPU using Oki original architecture @ 3external interrupts (NMI, INTO, INT1) @ General Register Machine ® 10internal interrupt factors Four banks of eight 16-bit registers © 4 priority level settings ® Data Types Bit*, byte (8 bits), word (16 bits), double += On-Chip Memory word (32 u instrueti © 256 words data memory bh ration instructions Multipicationiivsion instructions * Y6K words program memory © High-Speed Data Processing (10 MHz Clock) One-time PROM --- MSM67P620 16-bit addition and subtraction 200 ns 16-bit multiplication 2.3 ps Power Down Modes 32 + 16 bit division 2.3 ps © Haltmode © 3-Words Instruction Queve Terminates instruction execution but ® Highly Orthogonal Instruction Set peripheral functions keep operating ® Bit Operation Instructions © Stop mode @ Easy-To-Use I/O Access Instruction Stop system clock oscillation e r apres Memory: 64 K words Packages . Data Memory: 64K bytes © 64 pin plastic shrink DIP (SD1P64-P-750) © 64pin plastic QFP(T.B.D) Peripheral Functions © 68 pin PLCC (QFJ68-P-S950) © 8-bit auto reload timer x2 @ 16-bit auto reload timer x3 @ = 4-channel capture input/compare output © Serial port with 8-bit baud rate generator Asynchronous mode/Synchronous mode © = &bit parallel port x7 Bit-by-bit Input/Output specification

= Tod_,o,_ | e msme7620/67P620 6 PIN DESCRIPTIONS Type PinName | 0 Description 70.0~P0.7 8:bit bidirectional port that allows bit-by-bit (porta) VO | specification for VO. Secondary function of port 0is Pe external program memory address/data but. P1.0~P1.7 8:bit bidirectional port that allows bit-by-bit tor) VO | specification for VO. Secondary function of port 1 is Por external program memory address/data bus. 72.0~P2.7 8-bit bidirectional port that allows bit-by-bit tbo) VO | specification for VO. Secondary function of port 2is por external data memory address/data bus. 73.0~P3.7 B-bit bidirectional port that allows bit-by-bit (pore) VO | specification for VO. Secondary function of port 3 is Port por external data memory address/data bus. p4.0~P47 8:bit bidirectional port that allows bit-by-bit tore) VO _ | specification for /O. Secondary functions of port 4 Pp are external address/data bus control signal I/O pins. 8-bit bidirectional port that allows bit-by-bit P5.0~P5.7 | 14 | specification for VO. Secondary functions of port (port 5) are on-chip timer clock input pins, serial port /O pins; external interrupt input pins. 76.0~P6.7 8-bit bidirectional port that allows bit-by-bit (oort6) YO | specification for /O. Secondary function of port 6 pe are capture input/compare output I/O pins. a System reset input pin. “L" level input performs system reset; pulled up to Vcc by resistance. _ Program memory select input pin. “L” level input for tA Input | external program memory; “H” level input for system internal program memory. High impedance input. Control System clock input pin. Quartz oscillator or ceramic XTAL oscillator is connected between XTALI and XTAL2 For external clock, input at XTAL1, leaving XTAL2 open. MAG Syren dock up Interrupt [nm | tout | Non-maskable interrupt input pin. High impedance Power Supply 619

SECONDARY FUNCTIONS OF PORTS type | finame | vo Description Lower 8 bits of external program memory ADO~AD7 | VO | address/data bus. Port 0 secondary function (P0.0 to P0.7). Upper 8 bits of external program memory AD8~AD15. ie} address/data bus. Port 1 secondary function (P1.0 to P1.7). Output External program memory read strobe output pin; low active output. P4.0 secondary function. External program memory address latch signal Ale output | Putin. ALE latches address from multiplexed address/data bus ADO through AD15. P4.1 secondary function. Lower 8 bits of external data memory address/data BADO~BAD7 ie} bus. Port 2 secondary function (P2.0 to P2.7). saos-sapis | vo |UPPerBbitsof external data memory addressidata bus. Port 3 secondary function (3.0 to P3.7). Bus and Bus External data memory address latch signal output Control BALE Output pin. BALE latches address from multiplexed address/data bus BADO through BAD15. P4.4 secondary function. Output External data memory read strobe output pin; low active output. P4.5 secondary function. External data memory lower byte write strobe WAL Output | output pin; low active output. Secondary function of P46, External data memory upper byte write strobe WRH Output | output pin; low active output. Secondary function of P47. Bus request input pin. “H” level input opens BREQ Input | address/data bus to external device. P4.2 secondary function. Bus acknowledge output pin. High active output BACK Output | that indicates address/data bus is open to external device. P4.3 secondary function. 620

Type Pin Name vo Description into External interrupt 0 input pin. P5.0 secondary function. Interrupt int External interrupt 1 input pin. P5.1 secondary function. Timer 0 external clock input pin. P5.2 secondary function. Timer 1 external clock input pin. P5.3 secondary Timer Wt input | 17" Inpures y function. 1c inpur_ | CaP*ure timer external clock input pin. P6.4 secondary function. KU Serial port data transmit pin. P5.4 secondary function. Serial Port aXcK output Serial port receive synchronizing clock output pin. P5.6 secondary function. | lock in. IXCK Output Serial port transmit synchronizing clock output pin. PS.7 secondary function, Capture input/compare output channel 0 input/output pin. Capture trigger input pin in CAPO/CMPO | VO | capture input mode, output pin when compare match is generated in compare output mode. P6.0 secondary function. Capture input/compare output channel 1 input/output pin. Capture trigger input pin in capiycmPt | 0 | capture input mode, output pin when compare match is generated in compare output mode. P6.1 Capture Input secondary function. / Compare Output Capture input/compare output channel 2 inpuvoutput pin. Capture trigger input pin in cap2/cMP2 | VO | capture input mode, output pin when compare match is generated in compare output mode. P6.2 secondary function. Capture input/compare output channel 3 input/output pin. Capture trigger input pin in CAP3/CMP3 capture input mode, output pin when compare match is generated in compare output mode. P6.3 secondary function. 621

© MSM67620/62P620 © AAA @ i i i REGISTERS © General Purpose Registers (used as data registers and address registers) Four banks, each with eight 16-bit registers w nL af ef rl sf os © Special Purpose Registers Pe (Program Counter) (Stack Pointer) rm (Program Status Word) 622

© PSW Configuration 15 0 L- [= [= [= - T= [e+ [so] Tr [ro Tac] w Tov[ Tz] Zero flag Carry flag Overflow flag Negative flag Half-carry flag User flags Master interrupt enable flag Register bank select flags MEMORY MAP Data Memory Space Program Memory Space 64Kbytes (8 x 64K) 64kwords (16 x 64K) a : 80H Zero Page orn Vector Table Area OOH Pr-n---n--n--o === Internal Internal Data Memory Program Memory Program Memory 280H 4000H External Data Memory External Program Memory OFFFFH OFFFFH 623

0000 _|roto CTP sede 9001 oon oor front srt 0003 [port 1 directionregister | PR 00H ooo rota seseoed 9005 00H 000s rota etre 0007 [ron 3 directionregister | PDR oH 0008 [rota OFXH

9009 OFOH

0008 [Pores directionregister SIR oH oooc_|poné CC seine 9000 0H

008 OF3H

0020 OFOH

0022 OOH

0023 OFOH

RW; Read/write WIB ; Word/byte access R ; Readonly Wj Write access only W Word only B ;_ Byteaccess only 624

OCS A MSM E7E20/67PE20 © (HEX) Write| Byte o0za OE2H

0025 OE2H

0026 OOH

0028 OOH

0030 OOH

0031 OFOH

0032 OFEH

0034 OFEH

0035 OFeH

0066 w [0000+ 0070 0000H 0072 09008 oo7a 0000H 0076 aw 0000H 0078 oon 0979 00H 007A oH

0078 OOH

gore | w | 00008 oo7e 0000H 625

‘© MSM67620/67P620 ¢@ AAA AAA ADDRESSING MODES {MSM67620's instruction set allows use of eight addressing modes. 1. Register Direct Addressing Rm Example General Purpose Registers pam BL [no 2. immediate Addressing #n Example MOV RO, #1234H 3. Direct Addressing adrs Example Data Memory mov RO,1234H 1234h 4. Indirect Addressing [Rm] Example mov RO, " Data Memory — — — 626

CP MSM 67620/67P620 © 5. Pre-Decrement Addressing [- Rm] Example MOV RO, [- R2) Data Memory | R2€(R2)-2 /}—2—| 6. Post-Increment Addressing [Rm +] Example Mov RO, [R2 + Data Memory {2} | R2 —(R2)+2 7. Index Addressing adrs [Rm] Example Mov RO, 1234H [R2] ® — 8. PC Relative Addressing adrs Example | Program Memory | ® — 627

© MSM67620/62P620 <= AMAA aii INSTRUCTION TABLE ® Arithmetic Operations [enone | etn ADD ADDB Data addition ADDS ADDSB Short data addition (#1 to #8 addition) ADC ADCB Data addition with carry sus suBB Data subtraction suBs suBsB Short data subtraction (#1 to #8 subtraction) Bc sBcB Data subtraction with carry MUL MULB Multiplication piv pive Division DIVQ Word quick division (16-bit quotient) NEG NEGB Two's complement DAA Register decimal adjust after addition DAS Register decimal adjust after subtraction cup cups Comparison TST TSTB Test (comparison with zero) EXTS Signed word extension EXTU Unsigned word extension © Logical Operations Fineness] AND ANDB Logical AND ANDZ ANDZB Zero page area immediate logical AND OR ORB Logical OR ORZ ORZB Zero page area immediate logical OR XOR XORB Exclusive OR XORZ XORZB Zero page area immediate exclusive OR NOT NOTB Data complement 628

sing ggg MIS ME 7620/67 PEO © © Data Transfer Instructions MOV MOVB Data transfer MOVs MOVSB Short immediate transfer (#1 to #8 transfer) MOVZ Rm MOVZB Rm Zero page area data transfer MOvz #n MOV2B #n Immediate data transfer to zero page area MOvR Data transfer between register banks MOVC Code data transfer XCH Data swap SWAP High byte and low byte swap CLR CLRB Clear © Rotate and Shift ee ROL ROLB Register rotate left ROR RORB Register rotate right RLC RLCB Register and carry flag rotate left RRC RRCB Register and carry flag rotate right SUL SLLB Register shift left SRL SRLB Register shift right SRA SRAB Register shift right arithmetic © Bit Operations BSET Bit set BCLR Bit clear BNOT Bit complement BIST Bit test BAND Carry and bit logical AND BOR Carry and bit logical OR BXOR Carry and bit exclusive OR BMOV Carry and bit transfer sc Carry flag set RC Carry flag reset NC Carry flag complement 629

MSNEE20/62P620 ©$AAAADBaO<$ © Jumps J Jump SJ Short jump. J Rm) Indirect jump Jee Conditional jump B NB ition; } } Zero page area bit condition jump DINZ Decrement register, and jump if not 0 © Subroutines a PUSH Rm Register push PUSH PSW PSW push POP Rm Register pop POP PSW PSW pop CAL Subroutine call SCAL Subroutine short call CAL [Rm] Indirect call according to register Rm contents RET Return from subroutine RET! Return from interrupt RETNMI Return from NMI © CPU Control Et Interrupt enable DI Interrupt disable HALT Halt (instruction execution halt) STOP Stop (clock oscillation stop) BRK System reset by software 630

Product Information

M67620 specifications and overview.

Summary

HIGH PERFORMANCE CMOS 16-BIT SINGLE CHIP MICROCONTROLLER

Description

HIGH PERFORMANCE CMOS 16-BIT SINGLE CHIP MICROCONTROLLER

Source title M67620 Datasheet(PDF) - OKI electronic componets

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