M655 | DigiCamel IC Datasheet

Online Datasheet

Read M655 online.

MSM65511 OKI | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 25

Technical content

Oki Original High Performance CMOS 8 Bit 1 Chip Microcontroller nee GENERAL DESCRIPTION MSM65511 is a high-performance 8-bit single-chip controller that employs Oki’s original nX-8/50 CPU core. With a minimum instruction execution time of 400 ns (10MHz clock), MSM65511 is capable of high-speed processing, and includes 4 Kbytes of program memory, 128 bytes of data memory, timers and serial ports on chip. Program and system evaluation can be performed using MSM65P512, which as a version of MSM65512 that replaces program memory with one-time PROM. MSM65512 shares upward compatibility with MSM65511. OPERATING RANGE | @ Operating Frequency : OC~ 10MHz | © Operating Voltage : 45~5.5V _ @ Operating Temperature : -40~85°C | FEATURES \\ @ MemorySpace : 8 Kbytes @ Timers i 8-bit auto-reload timer x 2 i On-Chip Program Memory : 4 Kbytes Watchdog timer x 1 | On-Chip Data Memory : 128 bytes j © Counters | © Minimum instruction Execution Cycle: Time base counter x 1 ' 400nS @ 10 MHz | @ Serial ports © Powerful instruction set: Shift register x 1 \\ 81 basic instructions | 8/16-bit operation instructions @ Externalinterrupts: 2 ; Bit manipulation instructions i Compound function instructions © Interruptfactors: 6 @ Abundant addressing modes © Package: 40-pin plastic DIP @ WOports: 8bitx4 44-pin plastic QFP 44-pin PLCC * Specifications are subject to change without notice. | 1

| aebe ff eee 990 < 2 09009 bE yg a 8 3 Is H Te 7 | 2 A Ken 5 g 3 Ke 1 - Ho) KO [TENSES AL Lie~ 21%] [5] [5] 8 3 = q | 3¥|| 32 KY § = Ly PEE +-O0zZ0 $95 +0O>00 2 o Per o28 bE

System clock input pin. Quartz oscillator or ceramic oscillator Oscitla- Osco Input is connected between OSCO and OSCT. For external clock, tion input at OSCO, leaving OSC1 open. osc1 System clock output pin RESET System reset input (program starts from address 0040H); i internal pull-up resistance i Control , | Program memory select input pin. | “L* level input for external program memory; “H” level input | for internal program memory. | | 5 output | Read strobe signal during external memory access : Address latch signal during external memory access &bit /O port PORTO vo During external memory access, becomes address/data bus for address output, instruction fetch or data read/write along with ALE, RD and WR pins Port PORT 8-bit VO port Address bus during external memory access PORT2 8-bit VO port x2. Secondary functions shown in following table are added for ports 2 and 3. PORT 3

~ Pin Name Description INTO P2.2 secondary function. External interrupt 0 input pin. i INTI/GATE P2.3 secondary functions. \\ External interrupt 1 input pin. Also used as input pin for gate H signal for timer 0 count enable /disable. | TOCK P2.4 secondary function | Timer 0 external clock input pin. | HSTOP P2.5 secondary function. Hard stop mode input pin; stops system clock oscillation with “L* level input. WR Output | P2.6 secondary function. Write strobe signal output pin during external data memory access. TIOUT P2.7 secondary function. Output pin for signal that 2-divided timer 1 overflow. ~ SFTO Output | P3.5 secondary function. Shift register data output pin. SFTI P3.6 secondary function. ! Shift register data input signal. ' SFTCK P3.7 secondary function. i Shift register synchronizing clock input/output signal.

MSM65511 ELECTRICAL CHARACTERISTICS @ ABSOLUTE MAXIMUM RATINGS Input voltage Mv -0.3~Vpp + 0.3 7 Output voltage Vo Ta = 25°C - 0.3~Vpp + 0.3 Analog reference voltage -0.3~Vop + 0.3 Analog input voltage = 0.3~Vop +0.3 Power dissipation Pp Ta = 25°C (per package) | 400 mw @ OPERATING CONDITIONS Supply voltage Voo fosc S 10MHz 4.5~5.5 v Memory hold voltage Voomu fosc =OHz 2~5.5 Operating frequency fosc Vop = 5V410% } _o~0 | MHz Operating temperature Top -40~ +85 (MSM65511) Cc

@ AC CHARACTERISTICS @ External Memory Control Voo =5V+10%, GND=0V Ta= -40~ +85°C: MSM65511 Parameter Symbol [ condition [ min | MAX | Unit Clock period te | wo | - | “L" clock pulse width tccw | «3 [| - | | “H" clock pulse width tcHw fo | - | | ALE pulse width taw ficrtexw-20] = | “RD pulse width trw lice tonw- 20] - | "RD pulse delay time tro | WR pulse width tww fice tcnw-40] = | “WR pulse delay time two “s “L" address set up time tras } w-4 | - | : “H" address set up time [| «-4 | - | t “L" address hold time C= 100pF | taw-20 | - | : Bus float time taz | - | 2» | "H” address hold time | «-2 | - | i “H" address hold time tHaHw tc - 20 ; - | \\ Read data access time Read data access time [ - | tw 10 | Read data hold time po | - | Write data set up time fice tow- 40] - | Write data hold time | taw-20 | - |

~ © CPU Control Vpp = 5V410%, GND=O0V Ta= -40~ + 85°C: MSM65511 | *1 Excluding power ON, stop mode and hard stop mode i *2 In power ON, stop mode and hard stop mode | *3 Oscillation stabilization time depends on resonator t i | e Peripheral Control 1 (if applicable) = Vop=5V+410%, GND=0V Ta= —40~ +85°C: MSM65511 t EXI | External interrupt pulse | External clock pulse To |wiatn poe | | T2 | External clock pulse | *1 Excluding PO, P2.6 _ *2 PO,P2.6 *3 trocix: Timer 0 count clock period selected by TOCON

@ Peripheral Control 2 (if applicable) Vop=5Vt10%, GND=O0V Ta= -40~ +85°C: MSM65511 a SFTCK “L* pulse width | tseccw | atc-20 | — | get [SFTCK"H" pulse width | tsecuw | atc-20 | — | SFTO set up time tseos | tsrcow-t00 | — | SFTO hold time tstou | tsecuw-100 | — | Synchronous clock Cu= 100pF poe | = | period SIC ¢ i mode) \\ Output data set up time | étc-100 | — | | Outputdataholdtime | tsion ae-100 | | Input data set up time a Input data hold time | tsim | fo | - | | 10

@ €&xternal Memory Control | ' i CHW. te osco FUAD.PPYN taw ALE Ro SS tras 4 ah “aot PO b+ INST or |

5 Pet an DATA IN

: two tww t twos ‘WOH tHaHw. Pl PCH i | "1

@ Operation Registers i (Accumulator) (BR) * For 16-bit operation instruction, A register holds low byte data and the B register holds high byte data. e@ Special Purpose Registers (SP) word (PSW) Carry flag Zero flag Half-carry flag Parity flag Master interrupt enable flag Do not write “1” here Register set select flag Register set select flag (PC)

ERT 9 fronnoor etter en neo nn nee R10 RQ ERO 4 prococennnenm neem nnnnn n= I *1 4 banks of local registers are mapped in local memory space data memory. *2. Registers R8 to R11 can be used as 16-bit registers, ERO and ER1. i | 15

: Vector Call Table Area Internal Data Memory Memory 80H 40H Local Register Set 3 Program Memory 30H Local Register Set 2 40H | 20H Local Register Set 1 20H interrupt Vector Table Area 10H Local Register Set 0 0 Vector Call Table Area

| 17

i MSM6S511 has 256 bytes of local memory space and 8 Kbytes of general memory space. A variety | of addressing modes are available for accessing these spaces. 1. Register Direct Addressing @ A,B. SP, PSW e BA i Example DAA A 2. Local Register Direct Addressing @ Rn (n= 0~15) @ ERn (n=0, 1) Example Local Registers ‘ a eee 3. Local Memory Direct Addressing © ¥ adrs Example Local Memory L A, ¥S6H

General Memory Direct Addressing i e@ adrs Example General Memory LG A, QABCH | 5. Local Memory - Register Indirect Addressing | Example ~ b A, {RO} Local Memory |_f0__] Wud 6. General Memory - Register indirect Addressing © [eR] (n= 0,1) H e [BA] Example \\ \\lG A, a General Memory

Local Memory Index Addressing @ disp (Rn) (n=1,9) Example LA, SHIR Lt Local Memory 8. General Memory index Addressing © disp [ER1} Example le A, scsi [-----er1-----] General Memory © WM 9. Immediate Addressing e #n Example LA, #255 | 20

PC Relative Addressing ~ @ adrs Example IZ adrs : = i | General Memory

| © Data Transfer Instructions oy | L obj1, obj2 Local memory load LG obj 1, obj2 General memory load | ST obj1, obj2 Store into local memory | STG bjt, obj2 Store into general memory Mov PSW, #n Immediate data transfer to PSW MOV Obj1, obj2 Data transfer H MOVG obj1, obj2 General memory data transfer | MOVW obj1, obj2 16-bit data transfer | XCH CP Carry and parity exchange XCH obj1, obj2 Data exchange SWAP obj Upper nibble and lower nibble swap | @ Increment and Decrement i INC obj Data increment INCG obj General memory increment INCW obj 16-bit data increment i DEC obj Data decrement DEC6E obj General memory decrement DECW obj 16-bit data decrement @ Arithmetic Operations i a ADD obj1, obj2 Data add ADOW obj, obj2 16-bit data add ADC obj!, obj2 Data add with carry ADCG obj, obj2 General memory data add with carry i SUB obj1, obj2 Data subtract | SUBW obj1, obj2 16-bit data subtract | sBc obj1, obj2 Data subtract with carry | SBCG obj1, obj2 General memory data subtract with carry i 22

@ Comparisons cMP obj1, obj2 Data compare cCMPW objt, obj2 16-bit data compare ®@ Logical Operations ee AND PSW, #n PSW and immediate data logical AND AND obj1, obj2 Data logical AND OR PSW, #n PSW and immediate data logical OR OR obj, obj2 Data logical OR XOR obj!, obj2 Data exclusive OR © Bit Operations ~ [Teed SB obj.n Bit set SB obj PSW bit set RB obj.n Bit reset RB obj PSW bit reset CPL Cc Carry complement L C, obj Bit transfer to carry st C, obj Bit transfer from carry © Rotate and Shift a ROL obj Rotate left ROR obj Rotate right

1 SLL obj Shift left

_ SRL obj Shift right © Decimal Adjust ee | DAA obj Decimal adjust after add | OAS obj Decimal adjust after subtract | 23

: @ Conditional Jumps a | JZ adrs Jump if zero flag is set JNZ adrs Jump if zero flag is not set | Jc adrs Jump if carry is set | INC adrs Jump if carry is not set | JZ Rn, adrs Decrement register, and jump if zero | DJNZ Rn, adrs Decrement register, and jump if not zero | JBS obj.n, adrs Jump if bit is set | JBR obj..n, adrs Jump, if bitis reset JBSC obj.n, adrs Jump and clear bit if bit is set Ge C, P, adrs Compare carry and parity; jump if equal CONE C, P, adrs Compare carry and parity; jump if not equal GE obj1, obj2, adrs Compare; jump if equal CJNE objt, obj2, adrs Compare; jump if not equal CEG obj1, obj2, adrs Compare with general memory data; jump if equal CINEG obj1, obj2, adrs Compare with general memory data; jump if not equal | © Jumps J adrs Jump SJ adrs Short jump J [BA} Indirect jump i 24

® Subroutines a a a PUSH obj Data push POP obj Data pop CAL adrs Subroutine call | CALZ adrs Call subroutine if zero flag is set | CALC adrs Call subroutine if carry flag is set | VCAL n Vector call | VCALZ n Vector call if zero flag is set | VCALC n Vector call if carry flag is set RT Return from subroutine RTZ Return from subroutine if zero flag is set RTC Return from subroutine if carry flag is set © Other Instructions i : CLR obj Clear CLRW BA 16-bit data clear | CPL obj Data complement | cPLW BA 16-bit data complement | NOP No operation | CHK obj Parity check ' DLY a Program execution delay i

Product Information

M655 specifications and overview.

Summary

Oki Original High Performance CMOS 8 Bit 1 Chip Microcontroller

Description

Oki Original High Performance CMOS 8 Bit 1 Chip Microcontroller

Source title M655 Datasheet(PDF) - OKI electronic componets

Related Parts

More parts from the same family.

Browse manufacturer