MSM5840 OKI | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 11
Technical content
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER OO GENERAL DESCRIPTION The OK| MSM5840 microcontroller is a low-power, high-performance single chip device imple- mented in complementary metal oxide semiconductor technology. Integrated within this one chip are 46K bits of mask program ROM, 512 bits of data RAM, 30 Input/Output tines, a programmable timer/counter, and oscillator. Program memory is byte wide and data-paths are organized in 4 bit nib- bles. RAM and I/O fines are bit addressable. Up to 4K of external ROM interfaces to the 8 bit bidirec- tional bus. 98 instructions include binary, BCD, logical operations; bit set, reset, test, 8 bit I/O; relative jumps; multifunctional instructions (increment, modify, skip); 8 bit wide table output; subroutine call and return. 94% of instructions are single byte, single cycle operations.
FEATURES
@ Low Power Consumption —8mW Typical ® Expandable Memory and I/O © 100% Static Logic — 50x.W Standby, Typical © 2 Interrupt Levels ® 2K X 8 Internal ROM @ 4 Stack Levels @ Upto 4K x 8 External ROM @ Operating Temperature @ 128 X 4Internal RAM —40° to +85°C @ 301/0 Lines incl. 8 Bit Data Bus @ 3V to 6V Operating Vpop @ Programmable 8 Bit Timer/Counter © Battery Powered or Battery Backup ®@ Self-contained Oscillator @ TTL Compatible (with pullups) ®@ 98 Instructions © 7.6us Cycle Time @4,2MHz (Vpp 5V+ 10%) FUNCTIONAL BLOCK DIAGRAM Lx] ‘ [owe | = a ra Ae “ PH] fT --- J s. > we Te 2 [re] OA ee lt ~~ ae pam ee tof fd ooo | | \\ beteesd 7, CT | dy GO lo co 208% 3221032103210 32103210 i ie mr 3210321 OROWRIFCIN wv pg Yep op Le eK “L pa Lee L bd PF also «1098 76643710 sync abe ‘open drain 4 —o— bmatrucion
© MSM§840 AA PIN CONFIGURATION (Top View)
42 PIN PLASTIC DIP (RS) 44 Pin Plastic Fiat Package
» of 3 00 nasaaaione Paes conn RARE sq fos, seme CH Ba» woo 5 a =a f mee ce mi ‘woot CH] ae som Cr] Fao ow ox, GH Bc. oe D ro. xcs Oa ED o, ose, CE 0 w= Ol BD o wee 7) eo ® BD <, © 96: « GH BB a . @& Dr | fae) °F « G ff ~« C34 [25 Pr. o@ fo > Ce za . @ ia © on: Gd Fan) or . & EB « ® gl oe apo
28 B BEEGIIEGKIE
6 | PIN DESCRIPTION Designation | Pino. | Function GND | 21 __[ CircultGNo potential Vop [42 _ | Main powersource (+5V) OSCo [10 _| Crystal OSCinput, external clock input Osc: |__| Crystal OSC input, external clock output (not TTL compatible) PA,PB 1to4 Pseudo-bidirectional ports for 4-bit parallel I/O. Used as a pair for 8-bit 1/0. Used 381041 to output 8 LSBs of address in external ROM mode. Used to read external instruction during IF. PD, PE, 17 to20 Output ports for 4-bit parallel output and bit set/reset. Specified by internal PE,PG 23 to34 port pointer, Bit position specified by set/reset instruction. PD also used for instruction address MSBs in external ROM mode during IF. PK 13016 4-bit parallel or bit test input port (unlatched) PH 36 and 37 | 2-bit input port with latched memory (negative level sensitive) RESET 7 RESET has priority over every other signal. (see MSM5840 user's manual for initialization sequence) MODE Used toenable external ROM mode during RESET and alsoto enable STOP mode during execution (for stepping program) iNT Negative edge sensitive external interrupt signal associated with El and DI instructions. Vectors to location 20H. cn Negative edge sensitive external input for counter associated with ECT and DCT instructions. Vectors to location 100H. (same as timer) SYNC General purpose synchronizing signal output at the beginning of each machine cycle. Used for address strobe during external ROM mode. RO [12 __| Read strobe pulse occuring when port A or Bis read (1A, 1B, 1AB) WR [11 | Write strobe pulse occurring when port A or Bis written (OA, OB, OAB, OBS, OTD) ia |__22 _| Read strobe pulse occurring duringan instruction fetch from external ROM.
ee * MSM5840 FUNCTIONAL DESCRIPTION Program ROM Timer/Counter The MSM5840 will address up to 4K bytes of The timer/counter is an 8-bit counter whose program ROM and can have 2K bytes of internal input is selected under program control to be masked ROM, or all ROM may be located exter- either an external signal (CIN) or an internal nally. External EPROM may be used for program square wave of 1/128 the frequency of the OSCo development with conversion to internal ROM oc- input (2 MHz/128 = 15.625 kHz). The curring after program debug and system check- _ timer/counter can be enabled or disabled under cout and verification. All instructions are byte program control as can be associated internal in- wide. Only three of the 98 instructions require _terrupt which vectors to location 100H and has two bytes of program code. The instructions are _ higher priority than the external interrupt. routed to a programmed logic array which gener- ates the necessary internal control signals Stack The stack is an LIFO queue for storing return- Data RAM from-interrupt and return-from-subroutine ad- Data is organized in 4 bit nibbles. Internal dress information. It is eleven bits wide and 4 data RAM consists of 128 nibbles, 8 nibbles of _ levels deep. which are dedicated registers accessible directly under program control. These are the general ProgramCounter (PC) oo purpose registers, W, X, Y and Z, and the 4 save The program counter is 11 bits wide and (exchange) registers, CH, A, L, and AX. All other !oaded under program control. DATA RAM must be addressed indirectly through the DP (data po.nter) registers, a seven Aecumulator ter i bit pointer (directly accessible by numerous in- ;,,27@ accumulator register is the data path structions) consisting of 4 bit DPL register and a _f0Cal point of the CPU. Approximately one-half of 3 bit DP} register. Any nibble of internal data ‘he instructions involve the accumulator. Its con- RAM cartbe accessed through the DP registers. tents are the source and destination for many Some instructions automatically change the con- ALU operations and port operations. CASE state- tents of the DP registers allowing efficient array ents (computed GOTOs) are possible by using processing the Jump with Accumulator (JA) instruction. 6 Flay Input Output Ports se two ports are pseudo- ‘The MSMS840 is endowed with the following bidirectional ports which can be used as simple Set Of flags. ; V/O lines or used as either a 4-bit or 8-bit parallel 2 ~ 2r0 flag i Indicates that the result bus. An instruction fetches the external ROM of the previous operation data through these ports by outputting the 8 low was zero order bits of address during SYNC followed by F ~allones : Indicates a carry from the an IF (instruction fetch) cycle. In addition, OP, register synchronized data transfers are possible © ~ allzeros Indicates @ borrow from through these ports with the I/O pin signals RD the DPL register and WR associated with certain input/output in-_ © — carry : Indicates a carry from the structions dedicated to these ports. In short, PA 7 previous operation and PB can be used as a multiplexed address/ 7 — timer : Indicates that the timer/ instruction/data bus. counter is specified as a PD, PE, PF, PG — These four output ports are imer - addressed indirectly through the TWO BIT port C7 ~ counter 1 Indicates that the timer/ pointer whose contents are changed through counter is specified as a certain instructions. These ports are bit " " (set/reset) addressable. PD is also used for the 'M—timertiag — : Indicates an overtiow of high order bits of address during an external in- the timer/counter register struction fetch. PF and PG are open drain out- 'NT—interrupt —: Latching memory flag for puts and PG is set high by a hardware RESET. the external interrupt PK is an input port without memory, ad- INTE — interrupt : Indicates that interrupts dressable either as a nibble or bit level input. enable have been enabled PH is a two-bit input port with memory, which He—Hememory — : Indicates that an input can be tested and reset under program control. eer detected on the External Interrupt Hi : same as Ho except Hi The INT pin can be tested under program input - control or enabled to cause a vectored interrupt + 0 indicates internal ROM, to location 200H. It is negative edge sensitive. 1 indicates external ROM. If all external ROM, 0 indicates first bank of 2K.
2 MS85 840,
CLA Clear Accumulator oo0oo010000 1 cL Clear DPL 00100000 1 cLH | ClearDPy 01100000 1 LAI Load Accumulator with Immediate 0001 tb kh bb 1 Lu Load DP,_ with Immediate 00108 kh te 1 LHI Load DP} with Immediate 01100 kN bo 1 L Load Accumulator with Memory 10010100 1 iM Load Accumulator with Memory then Modity DP} 100101h b 1 LAL Load Accumulator with DP o1010101 1 _ | LA Load DP, with Accumulator 01010100 1 8} Law | Load Accumulator with W Register 10000100 1 5 | LAX Load Accumulator with X Register 10000101 1 ? Lay Load Accumulator with Y Register 10000110 1 §) uaz Load Accumutator with Z Register 1ooo0o0111 1 Sis ‘Store Accumulator to Memory then Increment DP, 10010000 1 S| sm ‘Store Accumulator to Memory then Modify DP, 1001008 b 1 and Increment DP LWA Load W Register with Accumulator 1oooo000 0 1 LXA Load X Register with Accumulator 10000001 1 LYA Load Y Register with Accumulator 10000010 1 LZA Load Z Register with Accumulator 10000011 1 LPA Load Port Pointer with Accumulator o1011000 1 LT Load Timer with Immediate o1101000 2 ty le Is Ie Is kk by bo RTH Read Timer H o1101010 1 RTL Read timer L o1101011 1 XA Exchange Accumulator with Save Register A 01001001 1 XL Exchange DP, with Save Register L_ 01001010 1 &| xcu Exchange DP} and Carry with Save Register CH. 01001000 1 2 x Exchange Accumulator with Memory 10011000 1 i} xm Exchange Accumulator wth Memory then Modity 100110h b 1 XAX Exchange Accumulator with Save Register AX 01001011 1 =| INA Increment Accumulator oo000001 1 By iw Increment DPL_ o1ro0orordd) 1 8| wm Increment Memory o10111401 1 | inw Increment W Register Skip if Zero 10001000 1 8] nx Increment X Register 10001001 1 §] iny Increment Y Register 10001010 1 =| nz Increment Z Register 10001011 1
M840 ° INSTRUCTION SET (CONT.) DCA Decrement Accumulator ~ Skip if Not All Ones ooooi17d 1 § DCL Decrement DP,_ 01010110 1 5 | DCM Decrement Memory 01011100 1 &|ocw — | Decrement W Register Skipif AllOnes 10001100 1
2 Dox Decrement x Register 10001101 1
§| cy Decrement Y Register 100011710 1 2| cz —_| Decrement z Register rooortid 1 DCH Decrement DP} — Skip if All Ones and C = Zero o1077977 1 CAO Complement Accumulator of One 01010000 1 | AND ‘And Accumulator with Memory 01000100 1 Bor Or Accumulator with Memory 01000101 1 EOR Exclusive or Accumulator with Memory 01000110 1 RAL Rotate Accumulator Left through Carry o100017111 1 AC Add Memory to Accumulator with Carry 01001100 1 Acs | Add Memory to Accumulator with Carry, Skip o100t101 1 ifCarry AS Add Memory to Accumulator, Skip if Carry o100111 0 1 gas Add Immediate to Accumulator, Skip itCarry 0 00ObkN bb 1 GI — DAS Decimal adjust Accumulator in Subtraction 01011010 1 =| om ‘Compare Accumulator with Memory, Skipif Equal o1ro11t10 1 AWS Add W Register to Accumulator, Skip if Carry 10011100 1 AXS | Add X Registerto Accumulator, Skip if Carry 1oo1rri10?d 1 AYS And Y Register to Accumulator, Skip if Carry 10011110 1 AZS | Add Z Register to Accumulator, Skip if Carry toorrd_idg 1 SPB Set Port Bit 101 10048 Ie 1 RPB Reset Port Bit 1011 014 bt bo 1 SMB | SetMemory Bit 10111 0b bo 1 RMB Reset Memory Bit 101 14 1 Tb b 1 | tsa Test Accumulator Bit 1010001 bo 1 §| Ts | TestMemory sit ror oT 1 8) tke Test K Port Bit 10101 0h b 1 & THB Test H Port Bit ‘Skip ifOne 10101 1 0 bo 1 g|T Test Interrupt flag 1o1rortdd 1 T™ Test Time flag 10101110 1 Te Test Carry flag 01000010 1 sc Set Carry flag 01000000 1 RC Reset Carry flag o1000001 1
@ MSM5840 @— INSTRUCTION SET (CONT.) |! Jump 00110wtb el 2] 2 g ole Is le bs ke by bo 8) uc Jump in Current Page Vib bb kb bl) 1] 4 &| vA Jump with Accumulator o100001 1; 44 4 $| CAL | Call Subroutine 00111 lw bs} 2] 2 A bh bh hb ®| ar Return from Subroutine or1orroon}i|e2 ops — | Output Byte String o1i10000 2~17 OTD | Output Table Data o1110001 2 OA Output Accumulator to Port A 01110010 1 _| 8 Output Accumulator to Port B o1r1r1o0o018 1 8| op Output Accumulator to Port P designated Port o1110100 1
3 Pointer
| AB | OutputMemoryand AccumulatortoPortsAandB = fO 1 110101 1 =} OPM | Output Memory to Port P designated Port Pointer o11101410 1 ta Input Port A in Accumulator 01111010 1
8 Input Port B in Accumulator o1r1110114 1
ik Input PortK in Accumulator o1111100 1 i aa Input Ports A and B in Memory and Accumulator o1114101 1 el Enable interrupt o1o1rooind 1 oO Disable Interrupt 01010010 1 er Enable Timer o1101a01 1 3) OT Disable Timer 01101110 1 | ECT. | Enablecountor ortaaadg) 1 Oct | Disable Counter o11ri1110 1 HLT | Halt 01101101 1 EXP | Exchange Program 01101001 1 NoP__| NoOperation oo000000 1
Parameter [_Symbot[Conaitions J timite Unit Storage Temperature [tag sstortso se Note: Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage tothe device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING CONDITIONS Parameter Unit Vv Supply vol iF [etwiz [sts | = ween voleee °° v [cwostad [1s | Fan Out [Tit teee [| D.C. CHARACTERISTICS (Vpp = 5V+ 10%, Ta = —20° to +70°C) Parameter [_symbo_[ Conditions Twin. [ Tyo. [ Max unit High Input Voltage [ww [= se TT Figh Output Vatage a Low Outpt Vote [vor [io=rema [ff ow |v OSCoInput Leak Current |__| Vi=Vop/ov = HA | =25_| RESET, MODE Leak Current [im | Vi=Vpp/ov = MA | =60 | Input Leak Current(2) [m4 | Vi=Vpp/ov [+] BA [=| {= 1MH {= 1MHz. Current Consumption(3) mA f=4.2MHZ Notes: (1) Except PA, PB (see graphs) (2) Except OSCo, RESET, MODE (3) Typical Value of Vpp is 5V
A.C. CHARACTERISTICS (INTERNAL ROM MODE) (Vpp = 5V+10%, Ta = —40° to +85°C) a oo Seren ign a FOraeswan ———[ Ce oe Sree Leo | acca mesos WPuseweti [waa Sy 6 esteeF—[yanseyos| Ts we. PA,PB WArwnowonavars | teow | sor | || as * PD, PE, PF,PG Note: (1) The processor logic will ignore the following events: 1. An INT falling edge occurring during Ty of a 7} instruction. 2. APHoor PH : low level occurring only during Ti i of a Tyg instruction. 6 | TIMING CHARTS. . ES in nh 2 i aN INT wey. UN Note: (1) All ‘ONES’ must be output before reading port A or B.
Te MSM 840 © A.C. CHARACTERISTICS (EXTERNAL ROM MODE) (Vpp = 5V+10%, Ta = 40° to +85°C) Parameter | Symbor [Gonaons [win We [Mex [unt Gycle Time Toy | | 7 [ [jas ‘Sync Pulse Width [iw] +| os | | dt as TF Pulse Wiath Tw | | es fs se iF [vip | a= [aoe | ‘Address Low Delay [wan | c-sor | | | 8s fecresstowheid [tan || ey | towns Instruction Setup [ous | «| ietey [| os Instruction Hold [wm | | is Data Recovery [toa | =sorr | oo | | 08 | as ‘Address High Delay [tan | cumsor [| | 8s ‘Address High Hold [wa | | oe | os as SYNC ee tIW- _ ee IF we LL! Ly tH pa,PB DATA ADDRESS} YinstA)y DATA, iad =p on tHAH GycieopendentTmings [ae ‘se asicy+1 748 13/16ty +1 5ouS
SM 840 $A TYPICAL PERFORMANCE CURVES ‘Supply Current vs Supply Voltage ‘Supply Current vs Oscillator Frequency (Ta = 25°C, No Load) (Ta = 25°C, No Load) 10m 10m Vpp = 6V 1m 4 1m ‘av: | 4 2 : Q a 8 100 100 2 gs 104 — 10 10k 100K iM 10M J (OSC) (Hz) 6 | : | O.1u TEL ot 3 5 7 10 Vpo (v) Oscillator Frequency vs Supply Voltage Oscillator Frequency vs Temperature (Ta = 25°C, Cy = SOpF) (CL = 50pF) 10 10 8 8 z z S 5 8 8 = 4 24 2 2 o1 3 5 7 10 50 oO 50 100 Vop (v) Tac)
er MSM5840 © Low Current Out vs Voltage High Current Out vs Voltage (Ta = 25°C, Except PA, PB) . | 7X “ : Tan /| + Yop = 5V 3 Fa < < +4 E Vi —£ ly 5 10 / pp = 4V. FE DD. gy 9° = iZ “Te 5 f} Vop = 3V V7 bo. ol a DNA \\ o1 3 5 7 10 ot 3 5 7 10 Vo (v) Vo (v) Fall Time vs Load Rise Time vs Load (Ta = 25°C, PA, PB, PD, PE, RD, WR, IF, SYNC) (Ta = 25°C, PD, PE, RD, WR, IF, SYNC) 800 800 /| = 600 = 600 z | [7 Von = 8V © 400 © 100 y 4 Yop = 5V | “Cee CETTE TT ° -—+—T_| ° 10 20 50 100 200 500 1000 10 20 60 100 200 500 1000 Cy (oF) Cy (PF)