M541

MSM5412222 OKI | Alldatasheet

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¡ Semiconductor MSM5412222 ¡ Semiconductor MSM5412222 262,214-Word ´ 12-Bit Field Memory

DESCRIPTION

The OKI MSM5412222 is a high performance 3-Mbit, 256K ´ 12-bit, Field Memory. It is especially designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. MSM5412222 is a FRAM for wide or low end use in general commodity TVs and VTRs exclusively. MSM5412222 is not designed for high end use in medical systems, professional graphics systems which require long term picture storage, data storage systems and others. Two or more MSM5412222s can be cascaded directly without any delay devices between them. (Cascading provides larger storage depth or a longer delay). Each of the 12-bit planes has separate serial write and read ports. These employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams. The MSM5412222 provides high speed FIFO, First-In First-Out, operation without external refreshing: MSM5412222 refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MSM5412222’s function is simple, and similar to a digital delay device whose delay-bit- length is easily set by reset timing. The delay length, and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 256 ´ 12-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. Additionally, the MSM5412222 has a write mask function or input enable function (IE), and read- data skipping function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to MSM5412222. The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a “picture in picture” on a TV screen. The MSM5412222 is similar in operation and functionality to OKI 1-Mbit Field Memory MSM514222B and 2-Mbit Field Memory MSM518222. Three MSM514222Bs or one MSM514222B plus one MSM518222 can be replaced simply by one MSM5412222. Preliminary This version: Jan. 1998 Previous version: Dec. 1996 E2L0034-17-Y1

¡ Semiconductor MSM5412222

FEATURES

• Single power supply : 5 V –10%
• 512 Rows ´ 512 Columns ´ 12 bits
• Fast FIFO (First-In First-Out) operation
• High speed asynchronous serial access Read/write cycle time 25 ns/30 ns Access time 23 ns/25 ns
• Direct cascading capability
• Write mask function (Input enable control)
• Data skipping function (Output enable control)
• Self refresh (No refresh control is required)
• Package options: 44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM5412222-xxTS-K) 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM5412222-xxJS) xx indicates speed rank. PRODUCT FAMILY Family Cycle Time (Min.) Package MSM5412222-25TS-K MSM5412222-30TS-K MSM5412222-25JS MSM5412222-30JS 25 ns 30 ns 25 ns 30 ns 400 mil 44-pin TSOP (II) 400 mil 40-pin SOJ Access Time (Max.) 23 ns 25 ns 23 ns 25 ns

¡ Semiconductor MSM5412222 PIN CONFIGURATION (TOP VIEW) DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 DIN5 DIN4 IE NC VCC VSS DOUT11 DOUT10 DOUT9 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 SRCK RSTR RE OE V SS VCC DOUT8 DOUT7 DOUT6 DOUT5 VSS DIN3 DIN2 DIN1 WE RSTW SWCK DIN0 NCNC 39 40-Pin Plastic SOJ /#08 1VSS 44-Pin Plastic TSOP (II) (K Type) 22VCC 2DIN11 3DIN10 4NC 5DIN9 6DIN8 7DIN7 8DIN6 9NC 10DIN5 13DIN2 14NC 15DIN1 16DIN0 17SWCK 18RSTW 19NC 20WE 21IE

44 V SS

23 V CC

43 D OUT11

42 D OUT10

39 D OUT8

38 D OUT7

37 D OUT6

32 D OUT2

31 V SS

30 D OUT1

29 D OUT0

28 SRCK

27 RSTR

/#08 11DIN4 12DIN3

34 D OUT4

33 D OUT3

Power Supply (5 V) Ground (0 V) No Connection Function Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin.

¡ Semiconductor MSM5412222 BLOCK DIAGRAM DOUT (´ 12) Data-out Buffer (´ 12) OE RE RSTR SRCK Serial

512 Word Serial Read Register (´ 12)

Low-Half (´ 12) Read Line Buffer High-Half (´ 12) 256 (´ 12) 256K (´ 12) Memory Array X Decoder

71 Word

Sub-Register (´ 12) Read/Write and Refresh Controller Clock Oscillator Write Line Buffer Low-Half (´ 12) Write Line Buffer High-Half (´ 12)

512 Word Serial Write Register (´ 12)

Buffer (´ 12) D IN (´ 12) Serial IE WE RSTW SWCK Sub-Register (´ 12) 256 (´ 12) VBB Generator Read Controller Read Controller

¡ Semiconductor MSM5412222 OPERATION Write Operation The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW. Each write operation, which begins after RSTW, must contain at least 80 active write cycles, i.e. SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW operation is required after the last SWCK cycle. Note that every write timing of MSM5412222 is delayed by one clock compared with read timings for easy cascading without any interface delay devices. Write Reset : RSTW The first positive transition of SWCK after RSTW becomes high resets the write address counters to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states of WE and IE are ignored in the write reset cycle. Before RSTW may be brought high again for a further reset operation, it must be low for at least two SWCK cycles. Data Inputs : D IN0 - 11 Write Clock : SWCK The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK. Write Enable : WE WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high) restrictions, because the MSM5412222 is in fully static operation as long as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK. Input Enable : IE IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are referenced to the rising edge of SWCK.

¡ Semiconductor MSM5412222 Read Operation The read operation is controlled by three clocks, SRCK, RSTR, and RE. Read operation is accomplished by cycling SRCK, and holding RE high after the read address pointer reset operation or RSTR. Each read operation, which begins after RSTR, must contain at least 80 active read cycles, i.e. SRCK cycles while RE is high. Read Reset : RSTR The first positive transition of SRCK after RSTR becomes high resets the read address counters to zero. RSTR setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled by the SRCK rising edge after the high level of RSTR, the states of RE and OE are ignored in the read reset cycle. Before RSTR may be brought high again for a further reset operation, it must be low for at least *two SRCK cycles. Data Out : D OUT0 - 11 Read Clock : SRCK Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read operation. The SRCK input increments the internal read address pointer when RE is high. The three-state output buffer provides direct TTL compatibility ( no pullup resistor required). Data out is the same polarity as data in. The output becomes valid after the access time interval t AC that begins with the rising edge of SRCK. *There are no output valid time restriction on MSM5412222. Read Enable : RE The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE setup times (t RENS and tRDSS) and RE hold times (t RENH and tRDSH) are referenced to the rising edge of the SRCK clock. Output Enable : OE OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced to the rising edge of SRCK.

¡ Semiconductor MSM5412222 Power-up and Initialization On power-up, the device is designed to begin proper operation after at least 100 ms after VCC has stabilized to a value within the range of recommended operating conditions. After this 100 ms stabilization interval, the following initialization sequence must be performed. Because the read and write address counters are not valid after power-up, a minimum of 80 dummy write operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW operation and an RSTR operation, to properly initialize the write and the read address pointer. Dummy write cycles/RSTW and dummy read cycles/RSTR may occur simultaneously. If these dummy read and write operations start while V CC and/or the substrate voltage has not stabilized, it is necessary to perform an RSTR operation plus a minimum of 80 SRCK cycles plus another RSTR operation, and an RSTW operation plus a minimum of 80 SRCK cycles plus another RSTW operation to properly initialize read and write address pointers. Old/New Data Access There must be a minimum delay of 600 SWCK cycles between writing into memory and reading out from memory. If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the next RSTW operation), then the data just written will be read out. The start of reading out the first field of data may be delayed past the beginning of writing in the second field of data for as many as 70 SWCK cycles. If the RSTR operation for the first field read- out occurs less than 70 SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that the first field will still be read out. The first field of data that is read out while the second field of data is written is called “old data”. In order to read out “new data”, i.e., the second field written in, the delay between an RSTW operation and an RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR operations is more than 71 but less than 600 cycles, then the data read out will be undetermined. It may be “old data” or “new” data, or a combination of old and new data. Such a timing should be avoided. Cascade Operation The MSM5412222 is designed to allow easy cascading of multiple memory devices. This provides higher storage depth, or a longer delay than can be achieved with only one memory device.

¡ Semiconductor MSM5412222

ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition Rating Input Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature V T IOS PD Topr Tstg at Ta = 25°C, VSS Ta = 25°C Ta = 25°C –1.0 to 7.0 0 to 70 –55 to 150 Unit V mA W Recommended Operating Conditions Parameter Symbol Min. Unit Typ. Max. Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage V CC VSS VIH VIL V V V V 4.5 2.4 –1.0 5.0 V CC 5.5 VCC + 1 0.8 DC Characteristics Parameter Symbol Condition Min. Input Leakage Current Output Leakage Current Output "H" Level Voltage Output "L" Level Voltage Operating Current Standby Current I LI ILO VOH VOL ICC1 ICC2 Minimum Cycle Time, Output Open –10 –10 2.4 Max. Unit 0.4 100 mA mA V V mA mA -25 -30 0 < VI < VCC + 1, Other Pins Tested at V = 0 V 0 < VO < VCC IOH = –1 mA IOL = 2 mA Input Pin = VIH / VIL Capacitance Parameter Unit Input Capacitance (DIN, SWCK, SRCK, RSTW, RSTR, WE, RE, IE, OE) Output Capacitance (DOUT) pF pF CI CO Symbol Max. (Ta = 25°C, f = 1 MHz)

¡ Semiconductor MSM5412222 AC Characteristics Parameter Symbol Unit Access Time from SRCK D OUT Hold Time from SRCK DOUT Enable Time from SRCK SWCK "H" Pulse Width SWCK "L" Pulse Width Input Data Setup Time Input Data Hold Time WE Enable Setup Time WE Enable Hold Time WE Disable Setup Time WE Disable Hold Time IE Enable Setup Time IE Enable Hold Time IE Disable Setup Time IE Disable Hold Time WE "H" Pulse Width WE "L" Pulse Width IE "H" Pulse Width IE "L" Pulse Width RSTW Setup Time RSTW Hold Time SRCK "H" Pulse Width SRCK "L" Pulse Width RE Enable Setup Time RE Enable Hold Time RE Disable Setup Time RE Disable Hold Time OE Enable Setup Time OE Enable Hold Time OE Disable Setup Time OE Disable Hold Time Output Buffer Turn-off Delay Time from OE RE "H" Pulse Width RE "L" Pulse Width OE "H" Pulse Width OE "L" Pulse Width RSTR Setup Time RSTR Hold Time SWCK Cycle Time SRCK Cycle Time Transition Time (Rise and Fall) t AC tDDCK tDECK tWSWH tWSWL tDS tDH tWENS tWENH tWDSS tWDSH tIENS tIENH tIDSS tIDSH tWWEH tWWEL tWIEH tWIEL tRSTWS tRSTWH tWSRH tWSRL tRENS tRENH tRDSS tRDSH tOENS tOENH tODSS tODSH tOEZ tWREH tWREL tWOEH tWOEL tRSTRS tRSTRH tSWC tSRC tT Min. Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MSM5412222-25 MSM5412222-30 (VCC = 5 V ±10%, Ta = 0°C to 70°C) Min. Max.

¡ Semiconductor MSM5412222 Notes: 1. Input signal reference levels for the parameter measurement are V IH = 3.0 V and VIL = 0 V. The transition time tT is defined to be a transition time that signal transfers between VIH = 3.0 V and VIL = 0 V. 2. AC measurements assume t T = 3 ns. 3. Read address must have more than a 600 address delay than write address in every cycle when asynchronous read/write is performed. 4. Read must have more than a 600 address delay than write in order to read the data written in a current series of write cycles which has been started at last write reset cycle: this is called "new data read". When read has less than a 70 address delay than write, the read data are the data written in a previous series of write cycles which had been written before at last write reset cycle: this is called "old data read". 5. When the read address delay is between more than 71 and less than 599, read data will be undetermined. However, normal write is achieved in this address condition. 6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output reference levels are V OH = 2.0 V and VOL = 0.8 V.

¡ Semiconductor MSM5412222 SWCK RSTW DIN WE IE n - 1 n 01 2 n cycle 0 cycle 1 cycle 2 cycle tT tRSTWS tRSTWH tSWC tDS tDH tWSWH tWSWL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL TIMING WAVEFORM Write Cycle Timing (Write Reset) Write Cycle Timing (Write Enable) /,/#02 /#06/#08 /#01 /#07 /#02 /#08 SWCK WE DIN IE RSTW n - 1 n n+1 n cycle Disable cycle Disable cycle n+1 cycle /#06/#06/#07/#08 tWENH tWDSS tWENS tWWEL tWWEH tWDSH VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL

¡ Semiconductor MSM5412222 Write Cycle Timing (Input Enable) /#02 /#01 /#01/#02 SWCK IE DIN WE RSTW n - 1 n n+3 n cycle n+1 cycle n+2 cycle n+3 cycle tIENH tIDSH tIDSS tIENS tWIEL tWIEH VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL SRCK RSTR DOUT RE OE n - 1 n 0 1 2 n cycle 0 cycle 1 cycle 2 cycle tSRC tT tRSTRS tRSTRH tWSRL tWSRH tAC tDDCK VIH VIL VIH VIL VOH VOL VIH VIL VIH VIL Read Cycle Timing (Read Reset)

¡ Semiconductor MSM5412222 Read Cycle Timing (Read Enable) /,/#01 SRCK RE DOUT OE RSTR n - 1 n n+1 n cycle disable cycle disable cycle n+1 cycle tRENH tRENS tWREL tRDSH tRDSS tWREH VIH VIL VIH VIL VOH VOL VIH VIL VIH VIL /,/#01 SRCK OE DOUT RE RSTR n - 1 n n+3 n cycle n+1 cycle n+2 cycle n+3 cycle /#01/,/#02 Hi-Z tOENStOENH tODSH tODSS tWOEN tWOEH tDECK VIH VIL VIH VIL VOH VOL VIH VIL VIH VIL /,/#02/#03/#05 Read Cycle Timing (Output Enable)

¡ Semiconductor MSM5412222 (Unit : mm) PACKAGE DIMENSIONS Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.54 TYP. TSOPII44-P-400-0.80-K Mirror finish

¡ Semiconductor MSM5412222 (Unit : mm) Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). SOJ40-P-400-1.27 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP. Mirror finish