M420000023

AM42DL32X4G AMD | Alldatasheet

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 25822 Rev: B Amendment/ 0 Issue Date: May 19, 2003 Refer to AMD’s Website (www.amd.com) for the latest information. Am42DL32x4G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features ■ Power supply voltage of 2.7 to 3.3 volt ■ High performance — Flash Access time as fast as 70 ns — SRAM access time as fast as 55 ns ■ Package — 73-Ball FBGA ■ Operating Temperature — –40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations ■ Secured Silicon (SecSi) Sector: Extra 256 Byte sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. — Customer lockable: Sector is one-time programmable. Once locked, data cannot be changed ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero ■ Top or bottom boot block ■ Manufactured on 0.17 µm process technology ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS ■ High performance — Access time as fast as 70 ns — Program time: 4 µs/word typical utilizing Accelerate function ■ Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode ■ Minimum 1 million write cycles guaranteed per sector ■ 20 Year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES ■ Data Management Software (DMS) — AMD-supplied software manages data programming and erasing, enabling EEPROM emulation — Eases sector erase limitations ■ Supports Common Flash Memory Interface (CFI) ■ Erase Suspend/Erase Resume — Suspends erase operations to allow programming in same bank ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to reading array data ■ WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system SRAM Features ■ Power dissipation — Operating: 22 mA maximum for 70 ns, 30 mA maximum for 55 ns — Standby: 10 µA maximum ■ CE1s# and CE2s Chip Select ■ Power down features using CE1s# and CE2s ■ Data retention supply voltage: 1.5 to 3.3 volt ■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

2 Am42DL32x4G May 19, 2003

The Am29DL322G/323G/324G consists of 32 megabit, 3.0 volt-only flash memory devices, organized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed to be programmed in-system with the stan- dard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers. The devices are available with access times of 85 and 70 ns. The device is offered in a 73-ball FBGA pack- age. Standard control pins—chip enable (CE#f), write enable (WE#), and output enable (OE#)—control nor- mal read and write operations, and avoid bus contention issues. The devices requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and simultaneously read from the other bank, with zero la- tency. This releases the system from waiting for the completion of program or erase operations. The Am29DL32xG device family uses multiple bank architectures to provide flexibility for different applica- tions. Three devices are available with the following bank sizes: The Secured Silicon (SecSi) Sector is an extra 256 byte sector capable of being permanently locked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to re- place a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number). Customer Lockable devices are one-time programmable and one-time lockable. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes. Device Bank 1 Bank 2 DL322 4 28 DL323 8 24 DL324 16 16

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May 19, 2003 Am42DL32x4G 5 PRELIMINARY PRODUCT SELECTOR GUIDE MCP BLOCK DIAGRAM Part Number Am42DL32x4G Speed Options Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory SRAM 71 70 85 71 70 85 Max Access Time (ns) 70 70 85 55 70 85 CE# Access (ns) 70 70 85 55 70 85 OE# Access (ns) 30 30 40 25 35 35 VSS /VSSQVCC s/VCCQ RESET# WE# CE#f OE# CE1#s VSSVCC f RY/BY# LB#s UB#s CIOf WP#/ACC CE2s

4 M Bit

32 M Bit

A–1 A17 to A0

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FLASH MEMORY BLOCK DIAGRAM VCC VSS Upper Bank AddressA20–A0 RESET# WE# CE# CIOf DQ15–DQ0 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# CIOf DQ15–DQ0 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address OE# CIOf Status Control A20–A0 A20–A0 A20–A0A20–A0 DQ15–DQ0 DQ15–DQ0

May 19, 2003 Am42DL32x4G 7 PRELIMINARY CONNECTION DIAGRAM Special Handling Instructions for FBGA Package Special handling is required for Flash Memory prod- ucts in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A10 B10 F10 G10 L10 M10 NC NC NC NC NC NC NCNC NC CE#f CE1#s V SS OE# DQ0 DQ8 LB# UB# A18 A17 DQ1 DQ9 DQ10 DQ2 NC WP#/ACC RESET# RY/BY# DQ3 V CCf DQ11 NC WE# CE2s A20 DQ4 VCCs NC A19 A10 DQ6 DQ13 DQ12 DQ5 A11 A12 A13 A14 NC DQ15/A-1 DQ7 DQ14 A15 NC NC A16 CIOf V SS NC NC NC NC NC NC SRAM only Shared Flash only 73-Ball FBGA Top View

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A17–A0 = 18 Address Inputs (Common) A-1, A20–A18 = 4 Address Inputs (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) CIOf = I/O Configuration (Flash) CIOf = VIH = Word mode (x16), CIOf = VIL = Byte mode (x8) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCC f = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage sup- ply tolerances) V CC s = SRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ15–DQ0 A17–A0 CE#f OE# WE# RESET# UB#s RY/BY# WP#/ACC A-1, A20–A18 LB#s CIOf CE1#s CE2s

May 19, 2003 Am42DL32x4G 9 PRELIMINARY

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations Am42DL32x 4 G T 70 I T TAPE AND REEL T=7 i n c h e s TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector PROCESS TECHNOLOGY G = 0.17 µm SRAM DEVICE DENSITY 4= 4 M b i t s AMD DEVICE NUMBER/DESCRIPTION Am42DL32x4G Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL32xG 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (256 K x 16-Bit) Static RAM Valid Combinations Order Number Package Marking Am42DL3224GT71I Am42DL3224GB71I T M42000005W M42000005X Am42DL3234GT71I Am42DL3234GB71I M42000005Y M42000005Z Am42DL3244GT71I Am42DL3244GB71I M420000060 M420000061 Am42DL3224GT70I Am42DL3224GB70I M420000022 M420000023 Am42DL3224GT85I Am42DL3224GB85I M420000024 M420000025 Am42DL3234GT70I Am42DL3234GB70I M420000026 M420000027 Am42DL3234GT85I Am42DL3234GB85I M420000028 M420000029 Am42DL3244GT70I Am42DL3244GB70I M42000002A M42000002B Am42DL3244GT85I Am42DL3244GB85I M42000002C M42000002D

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This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state ma- chine. The state machine outputs dictate the function of the device. Tables 1 through 2 list the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections de- scribe each of these operations in further detail.

Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH

1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.

IL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

1. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.

0.3 V H High-Z High-Z

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Table 2. Device Bus Operations—Flash Byte Mode, CIOf = VSS

1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
3. Don’t care or open LB#s or UB#s.

IL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed. If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

1. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.

May 19, 2003 Am42DL32x4G 13 PRELIMINARY Word/Byte Configuration The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the device is in word configura- tion, DQ15–DQ0 are active and controlled by CE# and OE#. If the CIOf pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ7–DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to V IL. CE#f is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V IH. The CIOf pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Flash Read-Only Opera- tions table for timing specifications and to Figure 14 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to V IL, and OE# to VIH. For program operations, the CIOf pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facil- itate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on pro- gramming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 4–7 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 con- tains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank ad- dress” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively.

14 Am42DL32x4G May 19, 2003

state, independent of the OE# input. modes, before it is ready to read data. standby current specification. data is latched and always available to the system. automatic sleep mode current specification. the RESET# pin returns to VIH. rameters and to Figure 15 for the timing diagram. Table 3. Device Bank Division

64 Kbyte/32 Kword

Table 4. Top Boot Sector Addresses

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Am29DL322GT, A20 and A19 for Am29DL323GT, and A20 for Am29DL324GT. Table 5. Top Boot SecSi Sector Addresses Table 4. Top Boot Sector Addresses (Continued)

Table 6. Bottom Boot Sector Addresses

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are A20–A18 for Am29DL322GB, A20 and A19 for Am29DL323GB, and A20 for Am29DL324GB. Table 7. Bottom Boot SecSi Sector Addresses Table 6. Bottom Boot Sector Addresses (Continued)

quence section for more information. Table 8. Top Boot Sector/Sector Block Addresses

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Table 9. Bottom Boot Sector/Sector Block Sector/Sector Block Unprotect”. The device is shipped with all sectors unprotected. sectors were last set to be protected or unprotected. tor/Sector Block Protection and Unprotection”.

1. All protected sectors unprotected (If WP#/ACC = VIL,

outermost boot sectors will remain protected).

1. All previously protected sectors are protected once

Figure 1. Temporary Sector Unprotect Operation

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Note: The term “sector” in the figure applies to both sectors and sector blocks. Figure 1. In-System Sector/Sector Block Protect and Unprotect Algorithms

ing commands to the boot sectors. tected when the device is shipped from the factory. 000000h–0000FFh in byte mode). when programming the SecSi Sector. method is only applicable to the SecSi Sector. Sector, follow the algorithm shown in Figure 2.. Figure 2. SecSi Sector Protect Verify

24 Am42DL32x4G May 19, 2003

or WE# do not initiate a write cycle. cally reset to reading array data on power-up. interfaces for long-term compatibility. an Embedded Program or embedded erase algorithm. Table 10. CFI Query Identification String

Table 11. System Interface String Table 12. Device Geometry Definition

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Table 13. Primary Vendor-Specific Extended Query The number of sectors in Bank 2 is device dependent. Am29DL322 = 38h, Am29DL323 = 30h, Am29DL324 = 20h.

May 19, 2003 Am42DL32x4G 27 PRELIMINARY COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. Tables 14 and 16 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to read- ing array data. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever hap- pens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the “Device Bus Operations” section for more information. The Flash Read-Only Operations table provides the read parameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to read- ing array data (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Tables 14 and 16 show the address and data require- ments. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is ac- tively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autoselect mode. The system may read at any ad- dress within the same bank any number of times without initiating another autoselect command sequence: ■ A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. ■ A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. ■ A read cycle to an address containing a sector ad- dress (SA) within the same bank, and the address 02h on A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Ta- bles 4–7 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend).

28 Am42DL32x4G May 19, 2003

Enter SecSi Sector/Exit SecSi Sector Command Sequence The system can access the SecSi Sector region by is- suing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to nor- mal operation. Tables 14 and 16 show the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Mem- ory Region” for further information. Note that a hardware reset (RESET#=V IL) will reset the device to reading array data. Note that the ACC function and un- lock bypass modes are not available when the SecSi Sector is enabled. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the CIOf pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cy- cles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the pro- grammed cell margin. Tables 14 and 16 show the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and ad- dresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are un- available when a program operation is in progress. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Tables 14 and 16 show the re- quirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the reading array data. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Flash Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.

30 Am42DL32x4G May 19, 2003

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. mation on these status bits. reading array data, to ensure data integrity. period during the sector erase command sequence. imum of 20 µs to suspend the erase operation. if a sector is actively erasing or is erase-suspended. mation on these status bits. just as in the standard Byte Program operation. Figure 4. Erase Operation

1. See Tables 14 and 16 for erase command sequence.
2. See the section on DQ3 for information on the sector

Table 14. Command Definitions (Flash Word Mode) RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE#f pulse, whichever happens first. erased. Address bits A20–A12 uniquely select any sector. in bypass mode, or is being erased.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A20–A12 are don’t cares.
3. No unlock or command cycles required when bank is in read
4. The Reset command is required to return to reading array data

high (while the bank is providing status information).

1. The fourth cycle of the autoselect command sequence is a read
2. The data is 80h for factory locked and 00h for not factory locked.
3. The data is 00h for an unprotected sector/sector block and 01h

for a protected sector/sector block.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

1. Command is valid when device is ready to read array data or when

device is in autoselect mode. Table 15. Autoselect Device IDs (Word Mode)

32 Am42DL32x4G May 19, 2003

Table 16. Command Definitions (Flash Byte Mode) RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE#f pulse, whichever happens first. erased. Address bits A20–A12 uniquely select any sector. in bypass mode, or is being erased.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A20–A12 are don’t cares.
3. No unlock or command cycles required when bank is in read
4. The Reset command is required to return to reading array data

high (while the bank is providing status information).

1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

1. The data is 80h for factory locked and 00h for not factory locked.
2. The data is 00h for an unprotected sector/sector block and 01h

for a protected sector/sector block.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

1. Command is valid when device is ready to read array data or when

device is in autoselect mode. Table 17. Autoselect Device IDs (Byte Mode)

34 Am42DL32x4G May 19, 2003

Table 18 shows the outputs for RY/BY#. complete, DQ6 stops toggling. Table 18 shows the outputs for Toggle Bit I on DQ6. subsection on DQ2: Toggle Bit II. Figure 6. Toggle Bit Algorithm

36 Am42DL32x4G May 19, 2003

Table 18. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

38 Am42DL32x4G May 19, 2003

Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC , VCC = VCC max ±1.0 µA ILIT RESET# Input Load Current V CC = VCC max ; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC , VCC = VCC max ±1.0 µA ILIA ACC Input Leakage Current VCC = VCC max , WP#/ACC = V ACC max 35 µA ICC1 f Flash VCC Active Read Current (Notes 1, 2) CE#f = VIL, OE# = VIH, Byte Mode

5 MHz 10 16

CE#f = VIL, OE# = VIH, Word Mode

1 MHz 2 4

ICC2 f Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL 15 30 mA ICC3 fF l a s h VCC Standby Current (Note 2)VCC f = VCC max , CE#f, RESET#, WP#/ACC = V CC f ± 0.3 V 0.2 5 µA ICC4 fF l a s h VCC Reset Current (Note 2)VCC f = VCC max , RESET# = VSS ± 0.3 V, WP#/ACC = VCC f ± 0.3 V 0.2 5 µA ICC5 f Flash VCC Current Automatic Sleep Mode (Notes 2, 4) VCC f = VCC max , VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6 f Flash VCC Active Read-While-Program Current (Notes 1, 2) CE#f = V IL, OE# = VIH Byte 21 45 mAWord 21 45 ICC7 f Flash VCC Active Read-While-Erase Current (Notes 1, 2) CE#f = VIL, OE# = VIH Byte 21 45 mAWord 21 45 ICC8 f Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE#f = V IL, OE#f = VIH 17 35 mA VIL Input Low Voltage –0.2 0.6 V VIH Input High Voltage 2.4 V CC + 0.2 V VHH Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection 8.5 9.5 V VID Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect 11.5 12.5 V V OL Output Low Voltage IOL = 4.0 mA, VCC f = VCC s = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC f = VCC s = VCC min 0.85 x VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC –0.4 VLKO Flash Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

May 19, 2003 Am42DL32x4G 39 PRELIMINARY Notes: 1. Undershoot: –1.0V if pulse width ≤ 20 ns. 2. Overshoot: VCC +1.0V if pulse width ≤ 20 ns. SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V IN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC Operating Power Supply Current IIO = 0 mA, CE1#s = VIL, CE2s = WE# = VIH, VIN = VIH or VIL 55 5 mA 70 3 ICC1 s Average Operating Current Cycle time = 1 µs, 100% duty, IIO = 0 mA, CE1#s ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 55 30 mA 70 22 ICC2 s Average Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH 55 5 mA 70 3 VIL Input Low Voltage –0.2 (Note 1) 0.4 V VIH Input High Voltage 2.2 VCC +0.2 (Note 2) V VOL Output Low Voltage I OL = 2.1 mA 0.4 V VOH Output High Voltage I OH = –1.0 mA 2.4 V ISB Standby Current (TTL) CE1#s = VIH, CE2 = VIL, Other inputs = VIH or VIL 0.3 mA ISB1 Standby Current (CMOS) CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC –

0.2 V (CE1#s controlled) or CE2 ≤

0.2 V (CE2s controlled), CIOs =

VSS or VCC , Other input = 0 ~ VCC 10 µA

40 Am42DL32x4G May 19, 2003

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 10. Typical ICC1 vs. Frequency

42 Am42DL32x4G May 19, 2003

SRAM CE#s Timing Figure 13. Timing Diagram for Alternating Between SRAM to Flash

Description

Test Setup All Speeds Unit JEDEC Std —t CCR CE#s Recover Time — Min 0 ns CE#f tCCR tCCR CE1#s CE2s tCCR tCCR

May 19, 2003 Am42DL32x4G 43 PRELIMINARY AC CHARACTERISTICS Flash Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 11 and Table 19 for test specifications. Parameter JEDEC Std 70, 71 85 tAVAV tRC Read Cycle Time (Note 1) Min 70 85 ns tAVQV tACC Address to Output Delay CE#f, OE# = V IL Max 70 85 ns tELQV tCE Chip Enable to Output Delay OE# = V IL Max 70 85 ns tGLQV tOE Output Enable to Output Delay Max 30 40 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns tAXQX tOH Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First Min 0 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tOH tCE Outputs WE# Addresses CE#f OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH

0 VRY/BY#

RESET# tDF Figure 14. Read Operation Timings

44 Am42DL32x4G May 19, 2003

Figure 15. Reset Timings

46 Am42DL32x4G May 19, 2003

Flash Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed Options Unit JEDEC Std Description 70, 71 85 tAVAV tWC Write Cycle Time (Note 1) Min 70 85 ns tAVWL tAS Address Setup Time (WE# to Address) Min 0 ns tASO Address Setup Time to OE# or CE#f Low During Toggle Bit Polling Min 15 ns tWLAX tAH Address Hold Time (WE# to Address) Min 45 ns tAHT Address Hold Time From CE#f or OE# High During Toggle Bit Polling Min 0 ns tDVWH tDS Data Setup Time Min 35 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEH OE# Hold Time Read Min 0 ns Toggle and Data# Polling Min 10 ns tOEPH Output Enable High During Toggle Bit Polling Min 20 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to CE#f Low) Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time (CE#f to WE#) Min 0 ns tELWL tCS CE#f Setup Time (WE# to CE#f) Min 0 ns tEHWH tWH WE# Hold Time (CE#f to WE#) Min 0 ns tWHEH tCH CE#f Hold Time (CE#f to WE#) Min 0 ns tWLWH tWP Write Pulse Width Min 30 35 ns tELEH tCP CE#f Pulse Width Min 30 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec tVCS VCC f Setup Time (Note 1) Min 50 µs tRB Write Recovery Time From RY/BY# Min 0 ns tBUSY Program/Erase Valid To RY/BY# Delay Max 90 ns

48 Am42DL32x4G May 19, 2003

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

50 Am42DL32x4G May 19, 2003

Figure 23. Toggle Bit Timings (During Embedded Algorithms) Figure 24. DQ2 vs. DQ6

Figure 25. Temporary Sector/Sector Block Unprotect

52 Am42DL32x4G May 19, 2003

Figure 26. Sector/Sector Block Protect and Unprotect

May 19, 2003 Am42DL32x4G 53 PRELIMINARY AC CHARACTERISTICS Alternate CE#f Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed Options Unit JEDEC Std Description 70, 71 85 tAVAV tWC Write Cycle Time (Note 1) Min 70 85 ns tAVWL tAS Address Setup Time (WE# to Address) Min 0 ns tASO Address Setup Time to CE#f Low During Toggle Bit Polling Min 15 ns tELAX tAH Address Hold Time Min 45 ns tAHT Address Hold time from CE#f or OE# High During Toggle Bit Polling Min 0 ns tDVEH tDS Data Setup Time Min 35 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE#f Pulse Width Min 30 35 ns tEHEL tCPH CE#f Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.4 sec

54 Am42DL32x4G May 19, 2003

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

Figure 28. SRAM Read Cycle—Address Controlled

56 Am42DL32x4G May 19, 2003

Figure 29. SRAM Read Cycle

1. WE# = VIH. WE# remains high for the read cycle.
2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device

1. tCW is measured from CE1#s going low to the end of write.
2. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
3. tAS is measured from the address valid to the beginning of write.
4. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
5. If CE1# goes low (or CE2 goes high) at the same time or after WE# goes low, the outputs will remain at high impedance.
6. If CE1# goes high (or CE2 goes low) at the same time or before WE# goes high, the outputs will remain at high impedance.
7. If OE# is high during the write cycle, the outputs will remain at high impedance.
8. Output data may be present on the bus at this time; input signals should not be applied.

Figure 30. SRAM Write Cycle—WE# Control

58 Am42DL32x4G May 19, 2003

1. tCW is measured from CE1#s going low to the end of write.
2. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
3. tAS is measured from the address valid to the beginning of write.
4. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
5. Output data may be present on the bus at this time; input signals should not be applied.
6. If OE# is high during the write cycle, the outputs will remain at high impedance.

Figure 31. SRAM Write Cycle—CE1#s Control

1. UB#s and LB#s controlled.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
6. Output data may be present on the bus at this time; input signals should not be applied.
7. If OE# is high during the write cycle, the outputs will remain at high impedance.

Figure 32. SRAM Write Cycle—UB#s and LB#s Control

60 Am42DL32x4G May 19, 2003

Flash Erase And Programming Performance Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC , 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 14 and 16 or further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. FLASH LATCHUP CHARACTERISTICS Note:Includes all pins except VCC . Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Note: 7.Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.4 5 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 28 sec Byte Program Time 5 150 µs Excludes system level overhead (Note 5) Word Program Time 7 210 µs Accelerated Byte/Word Program Time 4 120 µs Chip Program Time (Note 3) Byte Mode 21 63 sec Word Mode 14 42 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Description Test Setup Typ Max Unit C IN Input Capacitance V IN = 0 11 14 pF C OUT Output Capacitance V OUT = 0 12 16 pF C IN2 Control Pin Capacitance V IN = 0 14 16 pF C IN3 WP#/ACC Pin Capacitance V IN = 0 17 20 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

62 Am42DL32x4G May 19, 2003

FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm

May 19, 2003 Am42DL32x4G 63 PRELIMINARY REVISION SUMMARY Revision A (January 9, 2002) Initial release. Revision A + 1 (September 30, 2002) Connection Diagram Changed H7 from NC to DQ13. Logic Symbol Changed from 19 to 18 address inputs for A17 to A0. Sector/Sector Block Protection and Unprotection Added bottom boot sector protection table. Common Flash Memory Interface (CFI) Changed third paragraph to indicate that the system must write reset command to return to reading array data, not the autoselect mode. Changed URL for CFI documents. DC Characteristics, CMOS Compatible Removed I ACC from table. SRAM DC and Operating Characteristics Added VIL and VIH to table. Revision A + 2 (February 5, 2003) Global Added the 75 speed option to Flash memory and SRAM throughout the datasheet. Removed the 85 ns speed option in SRAM. Added order numbers to reflect the new speed option. Common Flash Memory Interface (CFI) Changed CFI website address. Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. SecSi Sector Flash Memory Region, and Enter SecSi Sector/Exit SecSi Sector Command Sequence Noted that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled. Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Com- mand Sequence Noted that the SecSi Sector, autoselect, and CFI func- tions are unavailable when a program or erase operation is in progress. Revision A + 3 (February 7, 2003) Product Selector Guide Corrected typo in Speed Option. Revision A + 4 (March 14, 2003) Product Selector Guide Corrected typo in SRAM Speed Option and updated tables in datasheet to reflect correction. Revision B (May 19, 2003) Global Removed “Pseudo” from data sheet. Removed 75 ns speed option and added 71 ns speed option. Then, corrected ordering information to reflect change. Trademarks Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

©2003 Advanced Micro Devices, Inc. Printed in USA One AMD Place, P .O. Box 3453,Sunnyvale, CA 94088-3453 408-732-2400 TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics.The performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry. For specific testing details, contact your local AMD sales representative.The company assumes no responsibility for the use of any circuits described herein. © Advanced Micro Devices, Inc. All rights reser ved. AMD, the AMD Arrow logo and combination thereof, are trademarks of Advanced Micro Devices, Inc. Other product names are for informational purposes only and may be trademarks of their respective companies. North America CALIFORNIA, FLORIDA, ILLINOIS, NEW JERSEY, TEXAS, International CHINA, GERMANY, JAPAN, UNITED KINGDOM, Representatives in U.S. and Canada ARIZONA, CALIFORNIA, CANADA, COLORADO, FLORIDA, GEORGIA, ILLINOIS, INDIANA, IOWA, KANSAS, MASSACHUSETTS, MICHIGAN, MINNESOTA, MISSOURI, NEW JERSEY, NEW YORK, NORTH CAROLINA, OHIO, OREGON, UTAH, VIRGINIA, WASHINGTON, WISCONSIN, Representatives in Latin America ARGENTINA, CHILE, COLUMBIA, MEXICO, PUERTO RICO, Sales Offices and Representatives es