AM41PDS3224D AMD | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 59

Technical content

/G45/G88/G79/G92/G3/G21/G19/G19/G22 /G55/G75/G72/G3/G73/G82/G79/G79/G82/G90/G76/G81/G74/G3/G71/G82/G70/G88/G80/G72/G81/G87/G3/G86/G83/G72/G70/G76/G73/G76/G72/G86/G3/G54/G83/G68/G81/G86/G76/G82/G81/G3/G80/G72/G80/G82/G85/G92/G3/G83/G85/G82/G71/G88/G70/G87/G86/G3/G87/G75/G68/G87/G3/G68/G85/G72/G3/G81/G82/G90/G3/G82/G73/G73/G72/G85/G72/G71/G3/G69/G92/G3/G69/G82/G87/G75/G3/G36/G71/G89/G68/G81/G70/G72/G71 /G48/G76/G70/G85/G82/G3/G39/G72/G89/G76/G70/G72/G86/G3/G68/G81/G71/G3/G41/G88/G77/G76/G87/G86/G88/G17/G3/G36/G79/G87/G75/G82/G88/G74/G75/G3/G87/G75/G72/G3/G71/G82/G70/G88/G80/G72/G81/G87/G3/G76/G86/G3/G80/G68/G85/G78/G72/G71/G3/G90/G76/G87/G75/G3/G87/G75/G72/G3/G81/G68/G80/G72/G3/G82/G73/G3/G87/G75/G72/G3/G70/G82/G80/G83/G68/G81/G92/G3/G87/G75/G68/G87/G3/G82/G85/G76/G74/G16 /G76/G81/G68/G79/G79/G92/G3/G71/G72/G89/G72/G79/G82/G83/G72/G71/G3/G87/G75/G72/G3/G86/G83/G72/G70/G76/G73/G76/G70/G68/G87/G76/G82/G81/G15/G3/G87/G75/G72/G86/G72/G3/G83/G85/G82/G71/G88/G70/G87/G86/G3/G90/G76/G79/G79/G3/G69/G72/G3/G82/G73/G73/G72/G85/G72/G71/G3/G87/G82/G3/G70/G88/G86/G87/G82/G80/G72/G85/G86/G3/G82/G73/G3/G69/G82/G87/G75/G3/G36/G48/G39/G3/G68/G81/G71 /G41/G88/G77/G76/G87/G86/G88/G17 Continuity of Specifications /G55/G75/G72/G85/G72/G3/G76/G86/G3/G81/G82/G3/G70/G75/G68/G81/G74/G72/G3/G87/G82/G3/G87/G75/G76/G86/G3/G71/G68/G87/G68/G86/G75/G72/G72/G87/G3/G68/G86/G3/G68/G3/G85/G72/G86/G88/G79/G87/G3/G82/G73/G3/G82/G73/G73/G72/G85/G76/G81/G74/G3/G87/G75/G72/G3/G71/G72/G89/G76/G70/G72/G3/G68/G86/G3/G68/G3/G54/G83/G68/G81/G86/G76/G82/G81/G3/G83/G85/G82/G71/G88/G70/G87/G17/G3/G3/G36/G81/G92 /G70/G75/G68/G81/G74/G72/G86/G3/G87/G75/G68/G87/G3/G75/G68/G89/G72/G3/G69/G72/G72/G81/G3/G80/G68/G71/G72/G3/G68/G85/G72/G3/G87/G75/G72/G3/G85/G72/G86/G88/G79/G87/G3/G82/G73/G3/G81/G82/G85/G80/G68/G79/G3/G71/G68/G87/G68/G86/G75/G72/G72/G87/G3/G76/G80/G83/G85/G82/G89/G72/G80/G72/G81/G87/G3/G68/G81/G71/G3/G68/G85/G72/G3/G81/G82/G87/G72/G71/G3/G76/G81/G3/G87/G75/G72 /G71/G82/G70/G88/G80/G72/G81/G87/G3/G85/G72/G89/G76/G86/G76/G82/G81/G3/G86/G88/G80/G80/G68/G85/G92/G15/G3/G90/G75/G72/G85/G72/G3/G86/G88/G83/G83/G82/G85/G87/G72/G71/G17/G3/G3/G41/G88/G87/G88/G85/G72/G3/G85/G82/G88/G87/G76/G81/G72/G3/G85/G72/G89/G76/G86/G76/G82/G81/G86/G3/G90/G76/G79/G79/G3/G82/G70/G70/G88/G85/G3/G90/G75/G72/G81/G3/G68/G83/G83/G85/G82/G83/G85/G76/G68/G87/G72/G15 /G68/G81/G71/G3/G70/G75/G68/G81/G74/G72/G86/G3/G90/G76/G79/G79/G3/G69/G72/G3/G81/G82/G87/G72/G71/G3/G76/G81/G3/G68/G3/G85/G72/G89/G76/G86/G76/G82/G81/G3/G86/G88/G80/G80/G68/G85/G92/G17 Continuity of Ordering Part Numbers /G36/G48/G39/G3/G68/G81/G71/G3/G41/G88/G77/G76/G87/G86/G88/G3/G70/G82/G81/G87/G76/G81/G88/G72/G3/G87/G82/G3/G86/G88/G83/G83/G82/G85/G87/G3/G72/G91/G76/G86/G87/G76/G81/G74/G3/G83/G68/G85/G87/G3/G81/G88/G80/G69/G72/G85/G86/G3/G69/G72/G74/G76/G81/G81/G76/G81/G74/G3/G90/G76/G87/G75/G3/G179/G36/G80/G180/G3/G68/G81/G71/G3/G179/G48/G37/G48/G180/G17/G3/G55/G82/G3/G82/G85/G71/G72/G85 /G87/G75/G72/G86/G72/G3/G83/G85/G82/G71/G88/G70/G87/G86/G15/G3/G83/G79/G72/G68/G86/G72/G3/G88/G86/G72/G3/G82/G81/G79/G92/G3/G87/G75/G72/G3/G50/G85/G71/G72/G85/G76/G81/G74/G3/G51/G68/G85/G87/G3/G49/G88/G80/G69/G72/G85/G86/G3/G79/G76/G86/G87/G72/G71/G3/G76/G81/G3/G87/G75/G76/G86/G3/G71/G82/G70/G88/G80/G72/G81/G87/G17 For More Information /G51/G79/G72/G68/G86/G72/G3/G70/G82/G81/G87/G68/G70/G87/G3/G92/G82/G88/G85/G3/G79/G82/G70/G68/G79/G3/G36/G48/G39/G3/G82/G85/G3/G41/G88/G77/G76/G87/G86/G88/G3/G86/G68/G79/G72/G86/G3/G82/G73/G73/G76/G70/G72/G3/G73/G82/G85/G3/G68/G71/G71/G76/G87/G76/G82/G81/G68/G79/G3/G76/G81/G73/G82/G85/G80/G68/G87/G76/G82/G81/G3/G68/G69/G82/G88/G87/G3/G54/G83/G68/G81/G86/G76/G82/G81 /G80/G72/G80/G82/G85/G92/G3/G86/G82/G79/G88/G87/G76/G82/G81/G86/G17 Am41PDS3224D Data Sheet Publication Number 26085 Revision A Amendment +1 Issue Date May 13, 2003

This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 26085 Rev: A Amendment/+1 Issue Date: May 13, 2002 Refer to AMD’s Website (www.amd.com) for the latest information. Am41PDS3224D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features ■ Power supply voltage of 1.8 to 2.2 volt ■ High performance — Access time as fast as 100 ns flash, 70 ns SRAM ■ Package — 73-Ball FBGA ■ Operating Temperature — –40°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank. — Zero latency between read and write operations ■ Page Mode Operation — 4 word page allows fast asynchronous reads ■ Dual Bank architecture — One 4 Mbit bank and one 28 Mbit bank ■ SecSi (Secured Silicon) Sector: Extra 64 KByte sector — Factory locked and identifiable: 16 byte Electronic Serial Number available for factory secure, random ID; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed ■ Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. ■ Top or bottom boot block ■ Manufactured on 0.23 µm process technology ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS ■ High performance — Random access time of 100 ns at 1.8 V to 2.2 V VCC ■ Ultra low power consumption (typical values) — 2.5 mA active read current at 1 MHz for initial page read — 24 mA active read current at 10 MHz for initial page read — 0.5 mA active read current at 10 MHz for intra-page read — 1 mA active read current at 20 MHz for intra-page read — 200 nA in standby or automatic sleep mode ■ Minimum 1 million write cycles guaranteed per sector ■ 20 year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES ■ Data Management Software (DMS) — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations ■ Erase Suspend/Erase Resume ■ Data# Polling and Toggle Bits ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) ■ Hardware reset pin (RESET#) ■ WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system SRAM Features ■ Power dissipation — Operating: 2 mA typical — Standby: 0.5 µA typical ■ CE1s# and CE2s Chip Select ■ Power down features using CE1s# and CE2s ■ Data retention supply voltage: 1.0 to 2.2 volt ■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)

2 Am41PDS3224D May 13, 2002

The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash memory organized as 2,097,152 words of 16 bits each. The device is designed to be programmed in system with standard system 1.8 V V CC supply. This device can also be reprogrammed in standard EPROM programmers. The Am29PDS322D offers fast page access time of 40 ns with random access time of 100 ns (at 1.8 V to

2.2 V V

CC ), allowing operation of high-speed micropro- cessors without wait states. To eliminate bus conten- tion the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The page size is 4 words. The device requires only a single 1.8 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and si- multaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The device is divided as shown in the following table: Am29PDS322D Features The SecSi (Secured Silicon) Sector is an extra 64 KByte sector capable of being permanently locked by AMD or customers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, cus- tomer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and soft- ware integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via program- ming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes. Bank 1 Sectors Bank 2 Sectors Quantity Size Quantity Size 8 4 Kwords 56 32 Kwords 7 32 Kwords

4 Mbits total 28 Mbits total

4 Am41PDS3224D May 13, 2002

May 13, 2002 Am41PDS3224D 5 PRELIMINARY PRODUCT SELECTOR GUIDE MCP BLOCK DIAGRAM Part Number Am41PDS3224D Speed Options Standard Voltage Range: VCC = 1.8–2.2 V Flash Memory SRAM 10 11 10, 11 Max Access Time (ns) 100 110 70 CE# Access (ns) 100 110 70 OE# Access (ns) 35 40 35 Max Page Address Access Time (ns) 40 45 N/A VSS /VSSQVCC s/VCCQ RESET# WE# CE#f OE# CE1#s VSSVCC f RY/BY# LB#s UB#s WP#/ACC CE2s SA CIOs

4 M Bit

32 M Bit

6 Am41PDS3224D May 13, 2002

FLASH MEMORY BLOCK DIAGRAM VCC VSS Upper Bank AddressA20–A0 RESET# WE# CE# DQ15–DQ0 STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# DQ15–DQ0 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address OE# Status Control A20–A0 A20–A0 A20–A0A20–A0 DQ15–DQ0 DQ15–DQ0

May 13, 2002 Am41PDS3224D 7 PRELIMINARY CONNECTION DIAGRAM Special Package Handling Instructions Special handling is required for Flash Memory prod- ucts in molded packages (TSOP , BGA, PLCC, PDIP , SSOP). The package and/or data integrity may be compromised if the package body is exposed to tem- peratures above 150°C for prolonged periods of time. A10 B10 F10 G10 L10 M10 NC NC NC NC NC NC NCNC NC CE#f CE1#s V SS OE# DQ0 DQ8 LB# UB# A18 A17 DQ1 DQ9 DQ10 DQ2 NC WP#/ACC RESET# RY/BY# DQ3 V CC f DQ11 NC WE# CE2s A20 DQ4 VCC s CIOs A19 A10 DQ6 DQ13 DQ12 DQ5 A11 A12 A13 A14 SA DQ15 DQ7 DQ14 A15 NC NC A16 NC V SS NC NC NC NC NC NC SRAM only Shared Flash only 73-Ball FBGA Top View

8 Am41PDS3224D May 13, 2002

A17–A0 = 18 Address Inputs (Common) A20–A18 = 3 Address Inputs (Flash) SA = Highest Order Address Pin (SRAM) Byte mode DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE1#s = Chip Enable 1 (SRAM) CE2s = Chip Enable 2 (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output (Flash) UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) CIOs = I/O Configuration (SRAM) CIOs = VIH = Word mode (x16), CIOs = VIL = Byte mode (x8) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCC f = Flash 1.8 volt-only single power supply (see Product Selector Guide for speed options and voltage sup- ply tolerances) V CC s = SRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ15–DQ0 A17–A0 CE#f OE# WE# RESET# UB#s RY/BY# WP#/ACC SA A20–A18 LB#s CIOs CE1#s CE2s

May 13, 2002 Am41PDS3224D 9 PRELIMINARY

ORDERING INFORMATION

The order number (Valid Combination) is formed by the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations Am41PDS322 4 D T 10 I T TAPE AND REEL T = 7 inches S=1 3 i n c h e s TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) SPEED OPTION See “Product Selector Guide” on page 5 BOOT CODE SECTOR ARCHITECTURE T=T o p s e c t o r B=B o t t o m s e c t o r PROCESS TECHNOLOGY D = 0.23 µm SRAM DEVICE DENSITY 4= 4 M b i t s AMD DEVICE NUMBER/DESCRIPTION Am41PDS3224D Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM Valid Combinations Order Number Package Marking Am41PDS3224DT10I Am41PDS3224DB10I T, S M410000077 M410000078 Am41PDS3224DT11I Am41PDS3224DB11I M410000079 M41000007A

10 Am41PDS3224D May 13, 2002

scribe each of these operations in further detail. Table 1. Device Bus Operations—SRAM Word Mode, CIOs = VCC

  1. Other operations except for those indicated in this column are inhibited.
  2. Do not apply CE#f = VIL, CE1#s = VIL and CE2s = VIH at the same time.
  3. Don’t care or open LB#s or UB#s.
  4. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

  1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
  2. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends

WP#/ACC = V HH, all sectors will be unprotected.

0.3 V H High-Z High-Z

Table 2. Device Bus Operations—SRAM Byte Mode, CIOs = VSS

  1. Other operations except for those indicated in this column are inhibited.

IL, CE1#s = VIL and CE2s = VIH at the same time.

  1. Don’t care or open LB#s or UB#s.
  2. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

  1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector Block Protection
  2. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on

VHH, all sectors will be unprotected.

12 Am41PDS3224D May 13, 2002

mand is necessary in this mode to obtain array data. gate data to the output pins if the device is selected. croprocessor supplying the specific word location. Table 3. Page Word Mode and Unlock Bypass command sequences. space that each sector occupies. tables and timing diagrams for write operations.

May 13, 2002 Am41PDS3224D 13 PRELIMINARY and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC pin returns the device to normal op- eration. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 and ICC7 in the Flash DC Characteristics table represent the current specifications for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#f and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE#f and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The de- vice requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the Flash DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. Automatic sleep mode current is drawn when CE# = V SS ± 0.3 V and all inputs are held at VCC ± 0.3 V. If CE# and RESET# voltages are not held within these tolerances, the automatic sleep mode current will be greater. I CC5 f in the Flash DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS ± 0.3 V, the de- vice draws CMOS standby current (ICC3 f). If RESET# is held at VIL but not within VSS ± 0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not ex- ecuting (RY/BY# pin is “1”), the reset operation is com- pleted within a time of t READY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 17 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

14 Am41PDS3224D May 13, 2002

Table 4. Am29PDS322DT Top Boot Sector Addresses

Table 5. Am29PDS322DT Top Boot SecSi Sector Address Table 4. Am29PDS322DT Top Boot Sector Addresses (Continued) Table 6. Am29PDS322DB Bottom Boot Sector Addresses

16 Am41PDS3224D May 13, 2002

Table 6. Am29PDS322DB Bottom Boot Sector Addresses (Continued)

Table 7. Am29PDS322DB Bottom Boot SecSi Sector Address quence section for more information. Table 8. Top Boot Sector/Sector Block Addresses

18 Am41PDS3224D May 13, 2002

Table 9. Bottom Boot Sector/Sector Block The device is shipped with all sectors unprotected. AMD representative for details. sectors were last set to be protected or unprotected. tor/Sector Block Protection and Unprotection”.

Figure 1. Temporary Sector Unprotect Operation

  1. All protected sectors unprotected (If WP#/ACC = VIL,

outermost boot sectors will remain protected).

  1. All previously protected sectors are protected once

20 Am41PDS3224D May 13, 2002

Note: The term “sector” in the figure applies to both sectors and sector blocks. Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms

May 13, 2002 Am41PDS3224D 21 PRELIMINARY SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 KBytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the secu- rity of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable version is shipped with the SecSi Sec- tor unprotected, allowing customers to utilize that sector in any manner they choose. The customer-lock- able version also has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indi- cator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command se- quence, it may read the SecSi Sector by using the ad- dresses normally occupied by the first sector (SA0). This mode of operation continues until the system is- sues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors instead of the SecSi sector Factory Locked: SecSi Sector Programmed and Protected at the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with one of the following: ■ A random, secure ESN only ■ Customer code through the ExpressFlash service ■ Both a random, secure ESN and customer code through the ExpressFlash service. In devices that have an ESN, a Bottom Boot device will have the 16-byte ESN in the lowest addressable memory area at addresses 000000h–000007h. In the Top Boot device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at addresses 1F8000h–1F8007h. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the permanently locked. Contact an AMD representative for details on using AMD’s Express- Flash service. Customer Lockable: SecSi Sector NOT Programmed or Protected at the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array by 64 Kbytes. The SecSi Sector can be read, programmed, and erased as often as required. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either V IH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sec- tor/Sector Block Protection and Unprotection” sec- tion. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector protection must be used with cau- tion since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 10 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low V CC Write Inhibit When V CC is less than VLKO , the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subse- quent writes are ignored until V CC is greater than VLKO .

22 Am41PDS3224D May 13, 2002

The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO . Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE#f = VIH or WE# = VIH. To initiate a write cycle, CE#f and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE#f = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to reading array data on power-up. FLASH COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 10 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a pro- gramming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more infor- mation. See also Requirements for Reading Array Data in the MCP Device Bus Operations section for more informa- tion. The Read-Only Operations table provides the read parameters, and Figure 15 shows the timing dia- gram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 10 shows the address and data requirements. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing.

May 13, 2002 Am41PDS3224D 23 PRELIMINARY The autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read any number of autoselect codes without reinitiating the command sequence. Table 10 shows the address and data requirements for the command sequence. To determine sector protec- tion information, the system must write to the appropri- ate sector group address (SGA). Tables 4 and 6 show the address range associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 16-byte random Electronic Serial Num- ber (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the de- vice to normal operation. Table 10 shows the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Mem- ory Region” for further information. Note that a hard- ware reset (RESET#=V IL) will reset the device to reading array data. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 10 shows the address and data requirements for the program command se- quence. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Flash Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 10 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to reading array data. See Figure 3 for the unlock bypass algorithm.

24 Am41PDS3224D May 13, 2002

Figure 3. Unlock Bypass Algorithm parameters, and Figure 18 for timing diagrams. Note:See Table 10 for program command sequence. Figure 4. Program Operation

26 Am41PDS3224D May 13, 2002

Status section for information on these status bits. just as in the standard word program operation. can be written after the chip has resumed erasing.

  1. See Table 10 for erase command sequence.
  2. See the section on DQ3 for information on the sector

Figure 5. Erase Operation

Table 10. Am29PDS322D Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. or erased. Address bits A20–A12 uniquely select any sector.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except for the read cycle and the fourth and fifth cycle of the

autoselect command sequence, all bus cycles are write cycles.

  1. Data bits DQ15–DQ8 are don’t care in command sequences,
  2. Unless otherwise noted, address bits A20–A12 are don’t cares in
  3. No unlock or command cycles required when device is in read
  4. The Reset command is required to return to the read mode (or to

(while the device is providing status information).

  1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

  1. The device ID must be read across the fourth, fifth and sixth
  2. The data is 80h for factory locked and 00h for not factory locked.
  3. The data is 00h for an unprotected sector group and 01h for a
  4. The Unlock Bypass command is required prior to the Unlock
  5. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

  1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

  1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

28 Am41PDS3224D May 13, 2002

gram or erase operation is complete or in progress. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Table 11 shows the outputs for Data# Polling on DQ7. Data# Polling timing diagram. Figure 6. Data# Polling Algorithm

  1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

  1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

30 Am41PDS3224D May 13, 2002

DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE# to con- trol the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 11 to compare out- puts for DQ2 and DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 23 shows the toggle bit timing diagram. Figure 24 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 7 for the following discussion. When- ever the system initially begins reading toggle bit sta- tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the tog- gle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of Figure 7). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previ- ously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between addi- tional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the sys- tem software should check the status of DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 11 shows the status of DQ3 relative to the other status bits.

Table 11. Write Operation Status

  1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

  1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

32 Am41PDS3224D May 13, 2002

  1. Minimum DC voltage on input or I/O pins is –0.5 V.

SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V.

  1. Minimum DC input voltage on pins OE#, RESET#, and

overshoot to +12.0 V for periods up to 20 ns.

  1. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability. tionality of the device is guaranteed. Figure 8. Maximum Negative Figure 9. Maximum Positive

May 13, 2002 Am41PDS3224D 33 PRELIMINARY Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. FLASH DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current V IN = VSS to VCC , VCC = VCC max ±1.0 µA ILIT RESET# Input Load Current V CC = VCC max ; RESET# = 12.5 V 35 µA ILO Output Leakage Current V OUT = VSS to VCC , VCC = VCC max ±1.0 µA ILIA ACC Input Leakage Current V CC = VCC max , WP#/ACC = VACC max 35 µA ICC1 f Flash VCC Active Inter-Page Read Current (Notes 1, 2) CE#f = VIL, OE# = VIH, 1 MHz 2.5 3 mA

10 MHz 24 28

ICC2 fF l a s h VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH 15 30 mA ICC3 fF l a s h VCC Standby Current (Note 2) VCC f = VCC max , CE#f, RESET# = VCC ± 0.3 V 0.2 5 µA ICC4 fF l a s h VCC Reset Current (Note 2) VCC f = VCC max , WP#/ACC = VCC f ± 0.3 V, RESET# = VSS ± 0.3 V 0.1 5 µA ICC5 f Flash VCC Automatic Sleep Mode Current (Notes 2, 4) VCC f = VCC max , CE#f = VSS ± 0.3 V; RESET# = VCC ± 0.3 V, VIN = VCC ± 0.3 V or VSS ± 0.3 V 0.2 5 µA ICC6 f Flash VCC Active Read-While-Program Current (Notes 1, 2, 5) CE#f = VIL, OE# = VIH 30 55 mA ICC7 f Flash VCC Active Read-While-Erase Current (Notes 1, 2, 5) CE#f = VIL, OE# = VIH 30 55 mA ICC8 f Flash VCC Active Program-While-Erase-Suspended Current (Note 2) CE#f = VIL, OE# = VIH 17 35 mA ICC9 fF l a s h VCC Active Intra-Page Read Current CE#f = VIL, OE# = VIH 10 MHz 0.5 1 mA

20 MHz 1 2

IACC WP#/ACC Accelerated Program Current V CC = VCCMax , WP#/ACC = VACCMax 12 20 mA VIL Input Low Voltage –0.5 0.2 x V CC V VIH Input High Voltage 0.8 x V CC VCC + 0.3 V VACC /VHH Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection 8.5 9.5 V VID Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect 91 1 V VOL Output Low Voltage I OL = 4.0 mA, VCC f = VCC s = VCC min 0.1 V VOH1 Output High Voltage IOH = –2.0 mA, VCC f = VCC s = VCC min 0.85 x V CC V VOH2 IOH = –100 µA, VCC = VCC min VCC –0.1 VLKO Flash Low VCC Lock-Out Voltage (Note 5) 1.2 1.5 V

34 Am41PDS3224D May 13, 2002

Note:Typical values measured at VCC = 2.0 V, TA = 25°C. Not 100% tested. SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V IN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC Operating Power Supply Current IIO = 0 mA, CE1#s = VIL, CE2s = WE# = VIH, VIN = VIH or VIL 2m A ICC1 s Average Operating Current Cycle time = 1 µs, 100% duty, IIO = 0 mA, CE1#s ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 2m A ICC2 s Average Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH 17 mA VOL Output Low Voltage I OL = 2.1 mA 0.2 V VOH Output High Voltage I OH = –0.1 mA 1.4 V ISB1 Standby Current (CMOS) CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC –

0.2 V (CE1#s controlled) or CE2 ≤

0.2 V (CE2s controlled), CIOs =

V SS or VCC , Other input = 0 ~ VCC 0.5 8 µA

36 Am41PDS3224D May 13, 2002

Table 12. Test Specifications Figure 12. Test Setup Figure 13. Input Waveforms and Measurement Levels

May 13, 2002 Am41PDS3224D 37 PRELIMINARY AC CHARACTERISTICS SRAM CE#s Timing Figure 14. Timing Diagram for Alternating

Description

Test Setup All Speeds Unit JEDEC Std —t CCR CE#s Recover Time — Min 0 ns CE#f tCCR tCCR CE1#s CE2s tCCR tCCR

38 Am41PDS3224D May 13, 2002

  1. See Figure 12 and Table 12 for test specifications.
  2. Measurements performed by placing a 50Ω termination on the data pin with a bias of VCC /2. The time from OE# high to the

data bus driven to VCC /2 is taken as tDF AC Characteristics.

0 VRY/BY#

Figure 15. Conventional Read Operation Timings

Figure 16. Page Mode Read Timings

40 Am41PDS3224D May 13, 2002

Figure 17. Reset Timings

May 13, 2002 Am41PDS3224D 41 PRELIMINARY FLASH AC CHARACTERISTICS Flash Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed Options Unit JEDEC Std Description 10 11 tAVAV tWC Write Cycle Time (Note 1) Min 100 110 ns tAVWL tAS Address Setup Time (WE# to Address) Min 0 ns tASO Address Setup Time to OE# or CE#f Low During Toggle Bit Polling Min 15 ns tWLAX tAH Address Hold Time (WE# to Address) Min 60 ns tAHT Address Hold Time From CE#f or OE# High During Toggle Bit Polling Min 0 ns tDVWH tDS Data Setup Time Min 60 ns tWHDX tDH Data Hold Time Min 0 ns tOEH OE# Hold Time Read Min 0 ns Toggle and Data# Polling Min 20 ns tOEPH Output Enable High During Toggle Bit Polling Min 20 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to CE#f Low) Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time (CE#f to WE#) Min 0 ns tELWL tCS CE#f Setup Time (WE# to CE#f) Min 0 ns tEHWH tWH WE# Hold Time (CE#f to WE#) Min 0 ns tWHEH tCH CE#f Hold Time (CE#f to WE#) Min 0 ns tWLWH tWP Write Pulse Width Min 60 ns tELEH tCP CE#f Pulse Width Min 60 ns tWHDL tWPH Write Pulse Width High Min 60 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 11 µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 5 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec tVCS VCC f Setup Time (Note 1) Min 50 µs tRB Write Recovery Time From RY/BY# Min 0 ns tBUSY Program/Erase Valid To RY/BY# Delay Max 90 ns

42 Am41PDS3224D May 13, 2002

Figure 19. Accelerated Program Timing Diagram

  1. PA = program address, PD = program data, DOUT is the true data at the program address.

Figure 18. Program Operation Timings

  1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write Operation Status”).

Figure 20. Chip/Sector Erase Operation Timings

44 Am41PDS3224D May 13, 2002

Figure 21. Back-to-back Read/Write Cycle Timings Figure 22. Data# Polling Timings (During Embedded Algorithms)

46 Am41PDS3224D May 13, 2002

Figure 25. Temporary Sector/Sector Block Unprotect

Figure 26. Sector/Sector Block Protect and Unprotect

48 Am41PDS3224D May 13, 2002

Alternate CE#f Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter Speed Options Unit JEDEC Std Description 10 11 tAVAV tWC Write Cycle Time (Note 1) Min 100 110 ns tAVWL tAS Address Setup Time (WE# to Address) Min 0 ns tASO Address Setup Time to CE#f Low During Toggle Bit Polling Min 15 ns tELAX tAH Address Hold Time Min 60 ns tAHT Address Hold time from CE#f or OE# High During Toggle Bit Polling Min 0 ns tDVEH tDS Data Setup Time Min 60 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE#f Pulse Width Min 60 ns tEHEL tCPH CE#f Pulse Width High Min 60 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 16 µs tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 5 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

  1. Figure indicates last two bus cycles of a program or erase operation.
  2. PA = program address, SA = sector address, PD = program data.
  3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

50 Am41PDS3224D May 13, 2002

Figure 28. SRAM Read Cycle—Address Controlled

Figure 29. SRAM Read Cycle

  1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing.
  2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
  3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device

52 Am41PDS3224D May 13, 2002

  1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
  2. tCW is measured from CE1#s going low to the end of write.
  3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
  4. tAS is measured from the address valid to the beginning of write.
  5. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 30. SRAM Write Cycle—WE# Control

  1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.
  2. tCW is measured from CE1#s going low to the end of write.
  3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
  4. tAS is measured from the address valid to the beginning of write.
  5. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 31. SRAM Write Cycle—CE1#s Control

54 Am41PDS3224D May 13, 2002

  1. UB#s and LB#s controlled, CIOs must be high.
  2. tCW is measured from CE1#s going low to the end of write.
  3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
  4. tAS is measured from the address valid to the beginning of write.
  5. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 32. SRAM Write Cycle—UB#s and LB#s Control

May 13, 2002 Am41PDS3224D 55 PRELIMINARY FLASH ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 2.0 V VCC , 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. FLASH LATCHUP CHARACTERISTICS Note:Includes all pins except VCC . Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Note: 7.Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 1 10 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 93 sec Word Program Time 16 360 µs Excludes system level overhead (Note 5) Accelerated Byte/Word Program Time 5 µs Chip Program Time (Note 3) Word Mode 20 100 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Description Test Setup Typ Max Unit C IN Input Capacitance V IN = 0 1 11 4p F C OUT Output Capacitance V OUT = 0 1 21 6p F C IN2 Control Pin Capacitance V IN = 0 1 41 6p F C IN3 WP#/ACC Pin Capacitance V IN = 0 1 72 0p F Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Years 125°C 20 Years

56 Am41PDS3224D May 13, 2002

  1. Typical values are not 100% tested.

Figure 33. CE1#s Controlled Data Retention Mode Figure 34. CE2s Controlled Data Retention Mode

May 13, 2002 Am41PDS3224D 57 PRELIMINARY PHYSICAL DIMENSIONS FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm

58 Am41PDS3224D May 13, 2002

Revision A (February 18, 2002) Initial release. Revision A+1 (May 13, 2002) Distinctive Characteristics Modified text in “High Performance” bullet. Deleted reference to 48-ball FBGA package. Figure 30, SRAM Write Cycle—WE# Control Corrected tBW in Data Out waveform to tWHZ . Trademarks Copyright © 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.