M29LV800B

AM29LV800B AMD | Alldatasheet

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 21490 Rev: E Amendment/ +1 Issue Date: March 1998 Refer to AMD’s Website (www.amd.com) for the latest information. Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications — Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors ■ Manufactured on 0.35 µm process technology — Compatible with 0.5 µm Am29LV800 device ■ High performance — Full voltage range: access times as fast as 80 ns — Regulated voltage range: access times as fast as 70 ns ■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current — 200 nA standby mode current — 7 mA read current — 15 mA program/erase current ■ Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences ■ Top or bottom boot block configurations available ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Minimum 1,000,000 write cycle guarantee per sector ■ Package option — 48-ball FBGA — 48-pin TSOP — 44-pin SO ■ Compatibility with JEDEC standards — Pinout and software compatible with single- power supply Flash — Superior inadvertent write protection ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data

2 Am29LV800B

The Am29LV800B is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt V CC supply to perform read, program, and erase operations. A standard EPROM pro- grammer can also be used to program and erase the device. This device is manufactured using AMD’s 0.35 µm process technology, and offers all the features and benefits of the Am29LV800, which was manufactured using 0.5 µm process technology. In addition, the Am29LV800B features unlock bypass programming and in-system sector protection/unprotection. The standard device offers access times of 70, 80, 90 and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus conten- tion the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com- mands are written to the command register using standard microprocessor write timings. Register con- tents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algo- rithm—an internal algorithm that automatically prepro- grams the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via program- ming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode . Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tun- neling. The data is programmed using hot electron injection.

Note:See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part Number Am29LV800B Speed Options Regulated Voltage Range: VCC =3.0–3.6 V 70R Full Voltage Range: VCC = 2.7–3.6 V 80 90 120 Max access time, ns (tACC ) 70 80 90 120 Max CE# access time, ns (tCE ) 70 80 90 120 Max OE# access time, ns (tOE ) 30 30 35 50 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# BYTE# CE# OE# STB STB DQ0 –DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA0–A18 21490E-1

4 Am29LV800B

WE# RESET# NC NC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 A15 A18 A14 A13 A12 A11 A10 NC NC WE# RESET# NC NC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 21490E-2 Reverse TSOP Standard TSOP

RY/BY# A18 A17 CE# V SS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 RESET# WE# A10 A11 A12 A13 A14 A15 A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 V SSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5NCNCRESET#WE# DQ11 DQ3DQ10DQ2NCA18NCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# V SSCE#A0A1A2A4A3 SO 21490E-3 FBGA Bump Side (Bottom) View

6 Am29LV800B

Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. PIN CONFIGURATION A0–A18 = 19 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V SS = Device ground NC = Pin not connected internally LOGIC SYMBOL 21490E-4 16 or 8 DQ0–DQ15 (A-1) A0–A18 CE# OE# WE# RESET# BYTE# RY/BY#

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. DEVICE NUMBER/DESCRIPTION Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Blank = Standard Processing B = Burn-in (Contact an AMD representative for more information) TEMPERATURE RANGE C= Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) S = 44-Pin Small Outline Package (SO 044) WB = 48-ball Fine Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 9 mm package SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top Sector B = Bottom Sector Valid Combinations Am29LV800BT70R, Am29LV800BB70R EC, EI, FC, FI, SC, SI, WBC Am29LV800BT80, Am29LV800BB80 EC, EI, EE, FC, FI, FE, SC, SI, SE, WBC, WBI, WBE Am29LV800BT90, Am29LV800BB90 Am29LV800BT120, Am29LV800BB120

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does not occupy any addressable memory location. register serve as inputs to the internal state machine. these operations in further detail. Table 1. Am29LV800B Device Bus Operations

1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section. an input for the LSB (A-1) address function. data upon device power-up, or after a hardware reset. mand register contents are altered. rent specification for reading array data.

0.3 V XX VCC ±

0.3 V X High-Z High-Z High-Z

Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Un- lock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector ad- dress” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteris- tics” for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde- pendent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. In the DC Characteristics table, I CC3 and ICC4 repre- sents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of reset- ting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS ±0.3 V, the device draws CMOS standby current (ICC4 ). If RESET# is held at VIL but not within VSS ±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not ex- ecuting (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embed- ded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.

10 Am29LV800B

rameters and to Figure 14 for the timing diagram. Table 2. Am29LV800BT Top Boot Block Sector Address Table

Table 3. Am29LV800BB Bottom Boot Block Sector Address Table section for more information. through the command register. ID (11.5 V to 12.5 V) on address pin A9.

1. In addition, when verifying sector protection, the sec-

details on using the autoselect mode.

12 Am29LV800B

Table 4. Am29LV800B Autoselect Codes (High Voltage Method) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. The device is shipped with all sectors unprotected. AMD representative for details. or unprotected. See “Autoselect Mode” for details. ID on address pin A9 and OE#. an AMD representative to request a copy. Figure 22 shows the timing diagrams, for this feature. Figure 1. Temporary Sector Unprotect Operation

1. All protected sectors unprotected.
2. All previously protected sectors are protected once

Figure 2. In-System Sector Protect/Unprotect Algorithms

14 Am29LV800B

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 5 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low V CC Write Inhibit When V CC is less than VLKO , the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than VLKO . The system must provide the proper signals to the control pins to prevent uninten- tional writes when VCC is greater than VLKO . Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = V IL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 5 defines the valid register command sequences. Writing incorrect address and data val- ues or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Em- bedded Erase algorithm. After the device accepts an Erase Suspend com- mand, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming opera- tion in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode. The system must issue the reset command to re-ena- ble the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Com- mand” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame- ters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command to the device resets the de- vice to reading array data. Address bits are don’t care for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 5 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires V ID on address bit A9. The autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect com-

mand. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufac- turer code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) re- turns 01h if that sector is protected, or 00h if it is unpro- tected. Refer to Tables 2 and 3 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program com- mand sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or tim- ings. The device automatically provides internally gen- erated program pulses and verifies the programmed cell margin. Table 5 shows the address and data re- quirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program- ming operation. The program command sequence should be reinitiated once the device has reset to read- ing array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to the device faster than using the standard program command sequence. The unlock by- pass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The de- vice then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Table 5 shows the requirements for the com- mand sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data. Figure 3 illustrates the algorithm for the program oper- ation. See the Erase/Program Operations table in “AC Characteristics” for parameters, and to Figure 17 for timing diagrams.

16 Am29LV800B

Note: See Table 5 for program command sequence. Figure 3. Program Operation returned to reading array data, to ensure data integrity. addresses are no longer latched. quirements for the sector erase command sequence. ings during these operations. and any additional sector addresses and commands. edge of the final WE# pulse in the command sequence. array data, to ensure data integrity.

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Table 5. Am29LV800B Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A18–A12 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
4. Data bits DQ15–DQ8 are don’t cares for unlock and
5. Address bits A18–A11 are don’t cares for unlock and

command cycles, unless PA or SA required.

1. No unlock or command cycles required when reading array
2. The Reset command is required to return to reading array

high (while the device is providing status data).

1. The fourth cycle of the autoselect command sequence is a
2. The data is 00h for an unprotected sector and 01h for a
3. The Unlock Bypass command is required prior to the Unlock
4. The Unlock Bypass Reset command is required to return to
5. The system may read and program in non-erasing sectors, or
6. The Erase Resume command is valid only during the Erase

20 Am29LV800B

RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, sev- eral RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC . If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/BY#. Figures 13, 14, 17 and 18 shows RY/BY# for read, reset, program, and erase operations, respectively. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase op- eration), and during the sector erase time-out. During an Embedded Program or Erase algorithm op- eration, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sec- tors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Em- bedded Erase algorithm erases the unprotected sec- tors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to deter- mine whether a sector is actively erasing or is erase- suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro- gram algorithm is complete. Table 6 shows the outputs for Toggle Bit I on DQ6. Fig- ure 6 shows the toggle bit algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the subsec- tion on “DQ2: Toggle Bit II”. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for eras- ure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would com- pare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data.

the status of the operation (top of Figure 6). applies after each additional sector erase command. also the “Sector Erase Command Sequence” section. cepted. Table 6 shows the outputs for DQ3.

1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as DQ5

Figure 6. Toggle Bit Algorithm

22 Am29LV800B

Table 6. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

24 Am29LV800B

Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. ICC active while Embedded Erase or Embedded Program is in progress. 3. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. 4. Not 100% tested. Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC , VCC = VCC max ±1.0 µA ILIT A9 Input Load Current V CC = VCC max ; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC , VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Note 1) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 7 12

1 MHz 2 4

CE# = VIL, OE# = VIH, Word Mode (Notes 2 and 4) CE# = VIL, OE# = VIH 15 30 mA ICC3 VCC Standby Current VCC = VCC max ; CE#, RESET# = VCC ±0.3 V 0.2 5 µA ICC4 VCC Reset Current VCC = VCC max ; RESET# = V SS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (Note 3)VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x V CC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC –0.4 VLKO Low VCC Lock-Out Voltage (Note 4) 2.3 2.5 V

26 Am29LV800B

Table 7. Test Specifications Figure 11. Test Setup

120 Unit

Figure 12. Input Waveforms and Measurement Levels

Notes: 1. Not 100% tested. 2. See Figure 11 and Table 7 for test specifications. Parameter

Description

JEDEC Std Test Setup 70R 80 90 120 Unit tAVAV tRC Read Cycle Time (Note 1) Min 70 80 90 120 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 70 80 90 120 ns tELQV tCE Chip Enable to Output Delay OE# = V IL Max 70 80 90 120 ns tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 25 25 30 30 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 25 25 30 30 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tOE

0 VRY/BY#

RESET# tDF tOH 21490E-17 Figure 13. Read Operations Timings

28 Am29LV800B

Figure 14. RESET# Timings

30 Am29LV800B

Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter 70R 80 90 120JEDEC Std Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 45 45 45 50 ns tDVWH tDS Data Setup Time Min 35 35 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 35 35 50 ns tWHWL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 11 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

32 Am29LV800B

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

34 Am29LV800B

Figure 21. DQ2 vs. DQ6 Figure 22. Temporary Sector Unprotect Timing Diagram

Figure 23. Sector Protect/Unprotect Timing Diagram

36 Am29LV800B

Alternate CE# Controlled Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter 70R 80 90 120JEDEC Std Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 80 90 120 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 45 45 50 ns tDVEH tDS Data Setup Time Min 35 35 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 35 35 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 11 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

38 Am29LV800B

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC , 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Includes all pins except VCC . Test conditions: VCC = 3.0 V, one pin at a time. TSOP AND SO PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 15 s Excludes 00h programming prior to erasureChip Erase Time 14 s Byte Programming Time 9 300 µs Excludes system level overhead (Note 5) Word Programming Time 11 360 µs Chip Programming Time (Note 3) Byte Mode 9 27 s Word Mode 5.8 17 s Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit C IN Input Capacitance V IN = 0 6 7.5 pF C OUT Output Capacitance V OUT = 0 8.5 12 pF C IN2 Control Pin Capacitance V IN = 0 7.5 9 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Years 125°C 20 Years

PHYSICAL DIMENSIONS* TS 048—48-Pin Standard TSOP (measured in millimeters) * For reference only. BSC is an ANSI standard for Basic Space Centering. TSR048—48-Pin Reverse TSOP (measured in millimeters) * For reference only. BSC is an ANSI standard for Basic Space Centering. 18.30 18.50 19.80 20.20 11.90 12.10 0.05 0.15

0.50 BSC

0.95 1.05 16-038-TS48-2 TS 048 DT95 8-8-96 lv Pin 1 I.D. 1.20 MAX 0.50 0.70 0.10 0.21 0.25MM (0.0098") BSC 0.08 0.20 18.30 18.50 19.80 20.20 11.90 12.10 SEATING PLANE 0.05 0.15 0.95 1.05 16-038-TS48 TSR048 DT95 8-8-96 lv Pin 1 I.D. 1.20 MAX 0.50 0.70 0.10 0.21 0.25MM (0.0098") BSC 0.08 0.20

40 Am29LV800B

FGB—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm (measured in mm) 5.80 6.20 8.80 9.20 DATUM B DATUM A INDEX 0.025 CHAMFER

0.15 M Z B M

5.60 BSC 0.40 4.00 BSC

0.08 M ZA B

0.10 Z 0.25 0.45 0.80 DETAIL A 0.20 Z DETAIL A

1.20 MAX

SO 044—44-Pin Small Outline Package (measured in millimeters) 44 23 1 22 13.10 13.50 15.70 16.301.27 NOM. 28.00 28.40 2.17 2.45 0.35 0.50 0.10 0.35 2.80 MAX. SEATING PLANE 16-038-SO44-2 SO 044 DF83 8-8-96 lv 0.10 0.21 0.60 1.00 END VIEW SIDE VIEW TOP VIEW

42 Am29LV800B

REVISION SUMMARY FOR AM29LV800B Revision E Distinctive Characteristics Changed typical read and program/erase current spec- ifications. Device now has a guaranteed minimum endurance of 1,000,000 write cycles. Figure 1, In-System Sector Protect/Unprotect Algorithm Corrected A6 to 0, Changed wait specification to 150 µs on sector protect and 15 ms on sector unprotect. DC Characteristics Changed typical read and program/erase current spec- ifications. AC Characteristics Alternate CE# Controlled Erase/Program Operations: Changed tCP to 35 ns for 70R, 80, and 90 speed options. Erase and Programming Performance Device now has a guaranteed minimum endurance of 1,000,000 write cycles. Physical Dimensions Corrected dimensions for package length and width in FBGA illustration (standalone data sheet version). Revision E+1 Figure 2, In-System Sector Protect/Unprotect Algorithms In the sector protect algorithm, added a “Reset PLSCNT=1” box in the path from “Protect another sec- tor?” back to setting up the next sector address. DC Characteristics Changed Note 1 to indicate that OE# is at V IH for the listed current. AC Characteristics Erase/Program Operations; Alternate CE# Controlled Erase/Program Operations: Corrected the notes refer- ence for tWHWH1 and tWHWH2 . These parameters are 100% tested. Corrected the note reference for tVCS . This parameter is not 100% tested. Temporary Sector Unprotect Table Added note reference for tVIDR . This parameter is not 100% tested. Figure 23, Sector Protect/Unprotect Timing Diagram A valid address is not required for the first write cycle; only the data 60h. Erase and Programming Performance In Note 2, the worst case endurance is now 1 million cy- cles. Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.