LV065MU

AM29LV640MT AMD | Alldatasheet

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Publication Number 26190 Revision C Amendment 8 Issue Date February 1, 2007 This product has been retired and is not avai lable for designs. For new and current designs, S29GL064A supersedes Am29LV640MT/B and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this doc- ument is retained for reference and historical purposes only. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Am29LV640MT/B Data Sheet RETIRED PRODUCT

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Publication# 26190 Rev: C Amendment/8 Issue Date: February 1, 2007 DATA SHEET Am29LV640MT/B

64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™

3.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES „ Single power supply operation — 3 V for read, erase, and program operations „ Manufactured on 0.23 µm MirrorBit process technology „ Secured Silicon Sector region — 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence — Can be programmed and locked at the factory or by the customer „ Flexible sector architecture — One hundred twenty-seven 32 Kword/64-Kbyte sectors — Eight 4 Kword/8 Kbyte boot sectors „ Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection „ Minimum 100,000 erase cycle guarantee per sector „ 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS „ High performance — 90 ns access time — 25 ns page read times — 0.5 s typical sector erase time — 22 µs typical effective write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word/byte updates — 4-word/8-byte page read buffer — 16-word/32-byte write buffer „ Low power consumption (typical values at 3.0 V, 5 MHz) — 30 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current „ Package options — 48-pin TSOP — 63-ball Fine-pitch BGA — 64-ball Fortified BGA SOFTWARE & HARDWARE FEATURES „ Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices „ Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Unprotect: V ID-level method of changing code in locked sectors — WP#/ACC input: Write Protect input (WP#) protects top or bottom two sectors regardless of sector protection settings ACC (high voltage) accelerates programming time for higher throughput during system production — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) indicates program or erase cycle completion This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640M T/B and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

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The Am29LV640M is a 64 Mbit, 3.0 volt single power supply flash memory device organized as 4,194,304 words or 8,388,608 bytes. The device has an 8-bit/16-bit bus and can be programmed either in the host system or in standard EPROM programmers. An access time of 90, 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (V CC) and an I/O voltage range (VIO), as specified in Product Selector Guide on page 6 and Or- dering Information on page 10. The device is offered in a 48-pin TSOP , 63-ball Fine-pitch BGA or 64-ball Forti- fied BGA package. Each device has separate chip en- able (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (ACC) function provides shorter programming times through increased current on the WP#/ACC input. This feature is intended to facilitate factory throughput dur- ing system production, but can also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the device using standard microprocessor write timing. Write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase oper- ation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to deter- mine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This is achieved in-system or via programming equip- ment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Sus- pend/Program Resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operatio n. The RESET# pin can be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The Write Protect (WP#) feature protects the top or bottom two sectors by asserting a logic low on the WP#/ACC pin. The protected sector is still protected even during accelerated programming. The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.

February 1, 2007 26190C8 Am29LV640MT/B 3 DATA SHEET MIRRORBIT 64 MBIT DEVICE FAMILY RELATED DOCUMENTS To download related documents, click on the following links or go to www.amd.com→Flash Memory →Prod- uct Information→MirrorBit→Flash Information→Tech- nical Documentation. MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs AMD MirrorBit™ White Paper Device Bus Sector Architecture Packages V IO RY/BY# WP#, ACC WP# Protection LV065MU x8 Uniform (64 Kbyte) 48-pin TSOP (std. & rev. pinout), 63-ball FBGA Y es Y es ACC only No WP# LV640MT/B x8/x16 Boot (8 x 8 Kbyte at top & bottom) 48-pin TSOP , 63-ball Fine-pitch BGA, 64-ball Fortified BGA No Y es WP#/ACC pin 2 x 8 Kbyte top or bottom LV640MH/L x8/x16 Uniform (64 Kbyte) 56-pin TSOP (std. & rev. pinout), 64-ball Fortified BGA Y es Y es WP#/ACC pin 1 x 64 Kbyte high or low LV641MH/L x16 Uniform (32 Kword) 48-pin TSOP (std. & rev. pinout) Y es No Separate WP# and ACC pins 1 x 32 Kword top or bottom LV640MU x16 Uniform (32 Kword) 64-ball Fortified BGA, 63-ball Fine-pitch BGA Y es Y es ACC only No WP#

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Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 22 Figure 13. Input Waveforms and Figure 20. Data# Polling Timings (During Embedded Algorithms). 51 Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 53 Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 54 Figure 25. Alternate CE# Controlled Write (Erase/Program)

February 1, 2007 26190C8 Am29LV640MT/B 5 DATA SHEET

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Note: See AC Characteristics on page 45 for full specifications. BLOCK DIAGRAM Part Number Am29LV640M Speed Option VCC = 3.0–3.6 V 90R 100R 110R 120R VCC = 2.7–3.6 V 100 110 120 Max. Access Time (ns) 90 100 110 120 Max. CE# Access Time (ns) 90 100 110 120 Max. Page access time (t PACC) 2 53 03 04 0 3 0 4 0 Max. OE# Access Time (ns) 25 30 30 40 30 40 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# WP#/ACC BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA21–A0

February 1, 2007 26190C8 Am29LV640MT/B 7 DATA SHEET CONNECTION DIAGRAMS C2 D2 E2 F2 G2 H2 J2 K2 C3 D3 E3 F3 G3 H3 J3 K3 C4 D4 E4 F4 G4 H4 J4 K4 C5 D5 E5 F5 G5 H5 J5 K5 C6 D6 E6 F6 G6 H6 J6 K6 C7 D7A7 B7 A8 B8 A1 B1 E7 F7 G7 H7 J7 K7 L7 NC* NC*NC* NC* NC* NC* NC* NC* NC* NC* NC*NC NC NC NC DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19A21RESET#WE# DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 * Balls are shorted together via the substrate but not connected to the die. A15 A18 A14 A13 A12 A11 A10 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48-Pin Standard TSOP 63-ball Fine-pitch BGA (FBGA) Top View, Balls Facing Down

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Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/or data integrity can be compromised if the package body is exposed to temperatures above 150 °C for prolonged periods of time. B3 C3 D3 E3 F3 G3 H3 B4 C4 D4 E4 F4 G4 H4 B5 C5 D5 E5 F5 G5 H5 B6 C6 D6 E6 F6 G6 H6 B7 C7 D7 E7 F7 G7 H7 B8 C8 D8 E8 F8 G8 H8 NCNCNCVSSNCNCNC VSSDQ15/A-1BYTE#A16A15A14A12 DQ6DQ13DQ14DQ7A11A10A8 DQ4VCCDQ12DQ5A19A21RESET# DQ3DQ11DQ10DQ2A20A18WP#/ACC DQ1DQ9DQ8DQ0A5A6A17 NC A13 WE# RY/BY# B2 C2 D2 E2 F2 G2 H2 VSSOE#CE#A0A1A2A4 B1 C1 D1 E1 F1 G1 H1 NCNCNCNCNCNCNC NC 64-Ball Fortified BGA (fBGA) Top View, Balls Facing Down

February 1, 2007 26190C8 Am29LV640MT/B 9 DATA SHEET PIN DESCRIPTION A21–A0 = 22 Address inputs DQ14–DQ0 = 15 Data inputs/outputs DQ15/A-1 = DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode) CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP#/ACC = Hardware Write Protect input/Pro- gramming Acceleration input RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output BYTE# = Selects 8-bit or 16-bit mode V CC = 3.0 volt-only single power supply (See Product Selector Guide on page 6 for speed options and voltage supply tolerances.) VSS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ15–DQ0 (A-1) A21–A0 CE# OE# WE# RESET# RY/BY# WP#/ACC BYTE#

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Am29LV640M T 120R PC I TEMPERATURE RANGE F = Industrial (-40 °C to +85°C) with Pb-free Package I = Industrial (–40 °C to +85°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) PC = 64-Ball Fortified Ball Grid Array 1.0 mm pitch, 13 x 11 mm package (LAA064) WH = 63-Ball Fine Pitch Ball Grid Array 0.80 mm pitch, 12 x 11 mm package (FBE063) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = VIL) T = Top boot sector device, top two address sectors protected B = Bottom boot sector device, bottom two address sectors protected DEVICE NUMBER/DESCRIPTION Am29LV640M

64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™ Boot Sector Flash Memory

3.0 Volt-only Read, Program, and Erase

(ns) VCC Range Valid Combinations for BGA Packages Speed (ns) VCC RangeOrder Number Package Marking Order Number Package Marking Am29LV640MT90R, Am29LV640MB90R EI EF 90 3.0–

3.6 V Am29LV640MT90R WHI L640MT90RI Am29LV640MT90R WHF L640MT90RF

90 3.0– 3.6 V PCI L640MT90NI PCF L640MT90NF Am29LV640MT100, Am29LV640MB100 100 2.7– 3.6 V Am29LV640MB90R WHI L640MB90RI Am29LV640MB90R WHF L640MB90RF PCI L640MB90NI PCF L640MB90NF Am29LV640MT110, Am29LV640MB110 110 Am29LV640MT100 WHI L640MT10VI Am29LV640MT100 WHF L640MT10VF 100 2.7– 3.6 V PCI L640MT10PI PCF L640MT10PF Am29LV640MT120, Am29LV640MB120 120 Am29LV640MB100 WHI L640MB10VI Am29LV640MB100 WHF L640MB10VF PCI L640MB10PI PCF L640MB10PF Am29LV640MT100R, Am29LV640MB100R 100 3.0– 3.6 V Am29LV640MT110 WHI L640MT11VI Am29LV640MT110 WHF L640MT11VF 110PCI L640MT11PI PCF L640MT11PF Am29LV640MT110R, Am29LV640MB110R 110 Am29LV640MB110 WHI L640MB11VI Am29LV640MB110 WHF L640MB11VF PCI L640MB11PI PCF L640MB11PF Am29LV640MT120R, Am29LV640MB120R 120 Am29LV640MT120 WHI L640MT12VI Am29LV640MT120 WHF L640MT12VF 120PCI L640MT12PI PCF L640MT12PF Am29LV640MB120 WHI L640MB12VI Am29LV640MB120 WHF L640MB12VF Valid Combinations Valid Combinations list configura- tions planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availabil- ity of specific valid combinations and to check on newly released combina- tions. PCI L640MB12PI PCF L640MB12PF Am29LV640MT100R WHI L640MT10RI Am29LV640MT100R WHF L640MT10RF 100 3.0– 3.6 V PCI L640MT10NI PCF L640MT10NF Am29LV640MB100R WHI L640MB10RI Am29LV640MB100R WHF L640MB10RF PCI L640MB10NI PCF L640MB10NF Am29LV640MT110R WHI L640MT11RI Am29LV640MT110R WHF L640MT11RF 110PCI L640MT11NI PCF L640MT11NF Am29LV640MB110R WHI L640MB11RI Am29LV640MB110R WHF L640MB11RF PCI L640MB11NI PCF L640MB11NF Am29LV640MT120R WHI L640MT12RI Am29LV640MT120R WHF L640MT12RF 120PCI L640MT12NI PCF L640MT12NF Am29LV640MB120R WHI L640MB12RI Am29LV640MB120R WHF L640MB12RF PCI L640MB12NI PCF L640MB12NF

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Device Bus Operations

1. Addresses are A21:A0 in word mode; A21:A-1 in byte mode. Sector addresses are A21:A12 in both modes.
2. The sector protect and sector unprotect functions can also be implemented via programming equipment. See the See Sector

Group Protection and Unprotection on page 20.

1. D IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

used as an input for the LSB (A-1) address function.

0.3 V XX VCC ±

0.3 V XH X High-Z High-Z High-Z

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The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See See Reading Array Data on page 27 for more in- formation. See the table, Read-Only Operations on page 45 for timing specifications and to Figure 14 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Ad- dress bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to t ACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t PACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE. Fast page mode ac- cesses are obtained by keeping the “read-page ad- dresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The Word/Byte Program Command Sequence on page 29 has details on programming data to the device using both standard and Unlock Bypass command se- quences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 and Table 3 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. AC Character- istics on page 45 contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system to write a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See Write Buffer on page 12 for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated program- ming, or device damage can result. In addition, no ex- ternal pullup is necessary since the WP#/ACC pin has internal pullup to V CC. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. See Autoselect Mode on page 19 and Au- toselect Command Sequence on page 28 for more in- formation. Standby Mode When the system is not read ing or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires stan- dard access time (t CE) for read access when the de-

standby current specification. data is latched and always available to the system. sleep mode current specification. rameters and to Figure 16 for the timing diagram. Table 2. Am29LV640MT Top Boot Sector Architecture

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Table 2. Am29LV640MT Top Boot Sector Architecture (Continued)

16 Am29LV640MT/B 26190C8 February 1, 2007

Table 3. Am29LV640MB Bottom Boot Sector Architecture

Table 3. Am29LV640MB Bottom Boot Sector Architecture (Continued)

18 Am29LV640MT/B 26190C8 February 1, 2007

through the command register.

1. In addition, when verifying sector protection, the

shows the remaining address bits that are don’t care. sponding identifier code on DQ7–DQ0. command register, as shown in Table 12 and Table 13. Table 4. Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

20 Am29LV640MT/B 26190C8 February 1, 2007

can be implemented via two methods. the first sector group unprotect write cycle. tact an AMD representative for details. Table 5. Am29LV640MT Top Boot Table 6. Am29LV640MB Bottom Boot

scribed in Sector Group Protection and Unprotection . increased. See the table in DC Characteristics. Figure 1. Temporary Sector Group

1. All protected sector groups unprotected (If WP# = V IL,

the first or last sector remain protected).

1. All previously protected sector groups are protected

22 Am29LV640MT/B 26190C8 February 1, 2007

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

product is shipped to the field. vices that are factory locked. protected when the device is shipped from the factory. ble to the Secured Silicon Sector. Table 7. Secured Silicon Sector Contents

24 Am29LV640MT/B 26190C8 February 1, 2007

Figure 3. Secured Silicon Sector Protect Verify or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. 55h, any time the device is ready to read array data. the system must write the reset command. device to reading array data.

Table 8. CFI Query Identification String Table 9. System Interface String

26 Am29LV640MT/B 26190C8 February 1, 2007

Table 10. Device Geometry Definition

Table 11. Primary Vendor-Specific Extended Query

28 Am29LV640MT/B 26190C8 February 1, 2007

which the system can read data from any non-erase-suspended sector. After completing a pro- gramming operation in the Erase Suspend mode, the system can once again read array data with the same exception. See Erase Suspend/Erase Resume Com- mands on page 35 for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. See the next section, Reset Command , for more informa- tion. See also Requirements for Reading Array Data on page 11 in Device Bus Operations for more informa- tion. See the table, Read-Only Operations on page 45 for the read parameters, and Figure 14 for the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command can be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command can be written between the sequence cycles in a pr ogram command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command can be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Pro- gramming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific ad- dresses: Note: The device ID is read over three cycles. SA = Sector Address Tables 12 and 13 show the address and data require- ments. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence can be written to an address that is either in the read or erase-suspend-read mode. The autoselect command cannot be written while the de- vice is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system can read at any address any number of times without initiating another autoselect command sequence. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte random Elec- tronic Serial Number (ESN ). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Se- cured Silicon Sector region until the system issues the four-cycle Exit Secured S ilicon Sector command se- quence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. Ta- bles 12 and 13 show the address and data require- ments for both command sequences. See also Secured Silicon Sector Flash Memory Region for further infor- mation. Identifier Code A7:A0 (x16) A6:A-1 (x8) Manufacturer ID 00h 00h Device ID, Cycle 1 01h 02h Device ID, Cycle 2 0Eh 1Ch Device ID, Cycle 3 0Fh 1Eh Secured Silicon Sector Factory Protect 03h 06h Sector Protect Verify (SA)02h (SA)04h

February 1, 2007 26190C8 Am29LV640MT/B 29 DATA SHEET Word/Byte Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 12 and 13 show the address and data requirements for the word program command sequence. Note that the autoselect and CFI functions are unavailable when a program operation is in progress. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7 or DQ6. See Write Operation Status on page 38 for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so can cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Tables 12 and 13 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initi- ated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which pro- gramming occurs. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system pro- grams six unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is se- lected by address bits A MAX–A4. All subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations can be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be per- formed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be per- formed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation aborts. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is decre- mented for every data load operation. The host system must therefore account for loading a write-buffer loca- tion more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Also note, if an address location is loaded more than once into the buffer, the final data loaded for that address is programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Pro- gram Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into

30 Am29LV640MT/B 26190C8 February 1, 2007

the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load com- mand. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data load- ing stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the de- vice for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is re- quired when using Write-Buffer-Programming features in Unlock Bypass mode. Accelerated Program The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system can then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated programming, or device dam- age can result. In addition, no external pullup is neces- sary since the WP#/ACC pin has internal pullup to V CC. Figure 5 illustrates the algorithm for the program oper- ation. See the table, Erase and Program Operations on page 48 in AC Characteristics for parameters, and Figure 17 for timing diagrams.

Figure 4. Write Buffer Programming Operation

1. When Sector Address is specified, any address in
2. DQ7 can change simultaneously with DQ5.
3. If this flowchart location was reached because

command. if DQ5=1, write the Reset command.

1. See Table 13 for command sequences required for

32 Am29LV640MT/B 26190C8 February 1, 2007

Figure 5. Program Operation μs maximum (5 μs typical) and updates the status bits. to enter and exit this region. page 38 for more information. Note: See Table 13 for program command sequence.

34 Am29LV640MT/B 26190C8 February 1, 2007

on page 38 for information on these status bits. reading array data, to ensure data integrity. Figure 7. Erase Operation

1. See Table 12 and Table 13 for erase command
2. See DQ3: Sector Erase Timer on page 41 for

information on the sector erase timer.

February 1, 2007 26190C8 Am29LV640MT/B 35 DATA SHEET Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sec- tor erase operation, including the 50 µs time-out pe- riod during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a typi- cal of 5 µs (maximum of 20 µs) to suspend the erase operation. However, when the Erase Suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The sys- tem can read data from or program data to any sector not selected for erasure. (The device “erase sus- pends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors pro- duces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 38 for information on these status bits. After an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. See Write Operation Status on page 38 for more informa- tion. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. See Autose- lect Mode on page 19 and Autoselect Command Se- quence on page 28 for details. To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Note: During an erase operation, this flash device per- forms multiple internal operations which are invisible to the system. When an erase operation is suspended, any of the internal operations that were not fully com- pleted must be restarted. As such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress is impeded as a function of the number of suspends. The result is a longer cumulative erase time than without suspends. Note that the additional suspends do not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases, erase performance is not significantly im- pacted.

36 Am29LV640MT/B 26190C8 February 1, 2007

Table 12. Command Definitions (x16 Mode, BYTE# = V IH) RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. or CE# pulse, whichever happens later. WE# or CE# pulse, whichever happens first. erased. Address bits A21–A15 uniquely select any sector. WC = Word Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. During unlock cycles, when lower address bits are 555 or 2AAh

is required) and data bits higher than DQ7 are don’t cares.

1. No unlock or command cycles required when device is in read
2. The Reset command is required to return to the read mode (or to

while the device is providing status information.

1. The fourth cycle of the autoselect command sequence is a read
2. The device ID must be read in three cycles. The data is 2201h for

top boot and 2200h for bottom boot.

1. If WP# protects the top two address sectors, the data is 98h for
2. The data is 00h for an unprotected sector group and 01h for a
3. The total number of cycles in the command sequence is

including "Program Buffer to Flash" command.

1. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system can read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

Table 13. Command Definitions (x8 Mode, BYTE# = V IL) RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. or CE# pulse, whichever happens later. WE# or CE# pulse, whichever happens first. erased. Address bits A21–A15 uniquely select any sector. BC = Byte Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. During unlock cycles, when lower address bits are 555 or AAAh

is required) and data bits higher than DQ7 are don’t cares.

1. No unlock or command cycles required when device is in read
2. The Reset command is required to return to the read mode (or to

while the device is providing status information.

1. The fourth cycle of the autoselect command sequence is a read

Command Sequence on page 28 for more information.

1. The device ID must be read in three cycles. The data is 01h for
2. If WP# protects the top two address sectors, the data is 98h for
3. The data is 00h for an unprotected sector group and 01h for a
4. The total number of cycles in the command sequence is

including "Program Buffer to Flash" command.

1. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system can read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

38 Am29LV640MT/B 26190C8 February 1, 2007

in progress or has been completed. final WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status might not be valid. Table 14 shows the outputs for Data# Polling on DQ7. Figure 8. Data# Polling Algorithm

1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

1. Recheck DQ7 even if DQ5 = “1” because DQ7 can

change simultaneously with DQ5.

February 1, 2007 26190C8 Am29LV640MT/B 39 DATA SHEET RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, sev- eral RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. If the output is low (Busy), the device is actively eras- ing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 14 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or com- plete, or whether the device has entered the Erase Suspend mode. Toggle Bit I can be read at any ad- dress, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm op- eration, successive read c ycles to any address cause DQ6 to toggle. The system can use either OE# or CE# to control the read cycles. When the operation is com- plete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approxi- mately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the de- vice enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alterna- tively, the system can use DQ7. See DQ7: Data# Polling on page 38). If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro- gram algorithm is complete. Table 14 shows the outputs for Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 21 in AC Characteristics shows the toggle bit timing dia- grams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also DQ2: Toggle Bit II on page 40.

40 Am29LV640MT/B 26190C8 February 1, 2007

Figure 9. Toggle Bit Algorithm tem also should note whether the value of DQ5 is high.

termine the status of the operation (top of Figure 9). in the erase-suspend-program mode). mand might not have been accepted. Programming on page 29 for more details. Table 14. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. See DQ5: Exceeded Timing Limits for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
3. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

42 Am29LV640MT/B 26190C8 February 1, 2007

1. Minimum DC voltage on input or I/O pins is –0.5 V.

SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V. pins can overshoot to VCC +2.0 V for periods up to 20 ns.

1. Minimum DC input voltage on pins A9, OE#, ACC, and
2. No more than one output can be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods can affect device reliability. the functionality of the device is guaranteed. Figure 10. Maximum Negative Figure 11. Maximum Positive

February 1, 2007 26190C8 Am29LV640MT/B 43 DATA SHEET DC CHARACTERISTICS CMOS Compatible Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA. 2. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. Maximum I CC specifications are tested with VCC = VCCmax. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. 6. Not 100% tested. 7. Includes RY/BY# Parameter Symbol Parameter Description (Notes) Test Conditio ns Min Typ Max Unit ILI Input Load Current (1) VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, ACC Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILR Reset Leakage Current V CC = VCC max; RESET= 12.5 V 35 µA ICC1 VCC Active Read Current (2, 3) CE# = VIL, OE# = VIH,

5 MHz 15 20

1 MHz 15 20

ICC2 VCC Initial Page Read Current (2, 3)C E # = V IL, OE# = VIH 30 50 mA ICC3 VCC Intra-Page Read Current (2, 3)C E # = V IL, OE# = VIH 10 20 mA ICC4 VCC Active Write Current (3, 4)C E # = V IL, OE# = VIH 50 60 mA ICC5 VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V, WP# = VIH 15 µ A ICC6 VCC Reset Current (3) RESET# = V SS ± 0.3 V, WP# = VIH 15 µ A ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 15 µ A VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 1.9 V CC + 0.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.7 –3.6 V 11.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.15 x VCC V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC–0.4 V VLKO Low VCC Lock-Out Voltage (6)2 . 3 2 . 5 V

44 Am29LV640MT/B 26190C8 February 1, 2007

Table 15. Test Specifications Note: If VIO < VCC, the reference level is 0.5 VIO. Figure 12. Test Setup Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.

1. See Figure 12 and Table 15 for test specifications.

0 VRY/BY#

Figure 14. Read Operation Timings

46 Am29LV640MT/B 26190C8 February 1, 2007

• Figure shows word mode. Addresses are A1–A-1 for byte mode.

Figure 15. Page Read Timings

Description All Speed Options UnitJEDEC Std. Figure 16. Reset Timings

48 Am29LV640MT/B 26190C8 February 1, 2007

Erase and Program Operations Notes: 1. Not 100% tested. 2. See Erase And Programming Performance on page 57 for more information. 3. For 1–16 words/ 1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/ 32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter Speed Options JEDEC Std. Description 90R 100, 100R 112, 112R 120, 120R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 11 µs Per Word Typ 22 µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 8.8 µs Per Word Typ 17.6 µs Single Word/Byte Program Operation (Note 2, 5) Byte Typ 100 µs Word 100 Accelerated Single Word/Byte Programming Operation (Note 2, 5) Byte Typ µs Word 90 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tBUSY WE# High to RY/BY# Low Max 90 100 110 120 ns tPOLL Program Valid Before Status Polling (Note 6) Max 4 µs

50 Am29LV640MT/B 26190C8 February 1, 2007

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data. See Write Operation Status on page 38.
2. These waveforms are for the word mode.

Figure 19. Chip/Sector Erase Operation Timings

Figure 20. Data# Polling Timings (During Embedded Algorithms)

52 Am29LV640MT/B 26190C8 February 1, 2007

Figure 21. Toggle Bit Timings (During Embedded Algorithms) Figure 22. DQ2 vs. DQ6

Figure 23. Temporary Sector Group Unprotect Timing Diagram

54 Am29LV640MT/B 26190C8 February 1, 2007

• For sector group protect, A6–A0 = 0xx0010. For sector group unprotect, A6–A0 = 1xx0010.

Figure 24. Sector Group Protect and Unprotect Timing Diagram

February 1, 2007 26190C8 Am29LV640MT/B 55 DATA SHEET AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See Erase And Programming Performance on page 57 for more information. 3. For 1–16 words programmed/1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter

Description

JEDEC Std. 90R 100, 100R 112, 112R 120, 120R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 11 µs Per Word Typ 22 µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 8.8 µs Per Word Typ 17.6 µs Single Word/Byte Program Operation (Note 2) Byte Typ 100 µs Word 100 Accelerated Single Word/Byte Programming Operation (Note 2) Byte Typ µs Word 90 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tRH RESET High Time Before Write (Note 1) Min 50 ns tPOLL Program Valid Before Status Polling (Note 6) Max 4 µs

56 Am29LV640MT/B 26190C8 February 1, 2007

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D

OUT is the data written to the device.

1. Waveforms are for the word mode.

February 1, 2007 26190C8 Am29LV640MT/B 57 DATA SHEET ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times as sume the following conditions: 25°C, 3.0 V VCC. Programming specifications assume that all bits are programmed to 00h. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation. 5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Tables 12 and 13 for further information on command definitions. 8. The device has a minimum erase and program cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 15 sec Excludes 00h programming prior to erasure (Note 6)Chip Erase Time 64 128 sec Single Word/Byte Program Time (Note 3) Byte 100 800 µs Excludes system level overhead (Note 7) Word 100 800 µs Accelerated Single Word/Byte Program Time (Note 3) Byte 90 720 µs Word 90 720 µs Total Write Buffer Program Time (Note 4) 352 1800 µs Effective Write Buffer Program Time (Note 5) Per Byte 11 57 µs Per Word 22 113 µs Total Accelerated Write Buffer Program Time (Note 4) 282 1560 µs Effective Accelerated Write Buffer Program Time (Note 4) Per Byte 8.8 49 µs Per Word 17.6 98 µs Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA

58 Am29LV640MT/B 26190C8 February 1, 2007

TSOP PIN AND BGA PACKAGE CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 TSOP 6 7.5 pF Fine-pitch BGA 4.2 5.0 pF COUT Output Capacitance V OUT = 0 TSOP 8.5 12 pF Fine-pitch BGA 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 TSOP 7.5 9 pF Fine-pitch BGA 3.9 4.7 pF Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

February 1, 2007 26190C8 Am29LV640MT/B 59 DATA SHEET PHYSICAL DIMENSIONS TS 048—48-Pin Standard Pinout Thin Small Outline Package (TSOP) Dwg rev AA; 10/99

60 Am29LV640MT/B 26190C8 February 1, 2007

FBE063—63-Ball Fine-pitc h Ball Grid Array (FBGA) 12 x 11 mm Package Dwg rev AF; 10/99

February 1, 2007 26190C8 Am29LV640MT/B 61 DATA SHEET PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package

62 Am29LV640MT/B 26190C8 February 1, 2007

Revision A (April 26, 2002) Initial release. Revision B (May 23, 2002) Changed packaging from 64-ball FBGA to 64-ball For- tified BGA. Changed Block Diagram: Moved V IO from RY/BY# to Input/Output Buffers. Changed Note about WP#/ACC pin to indicate internal pullup to VCC. Revision B+1 (July 31, 2002) MIRRORBIT 64 MBIT Device Family Added 64 Fortified BGA to LV640MU device. Alternate CE# Controlled Erase and Program Operations Added tRH parameter to table. Erase and Program Operations Added tBUSY parameter to table. Figure 16. Program Operation Timings Added 100R, 110R, and 120R OPNs. Added 100R, 110R, and 120R OPNs. Modified the special handling wording. Deleted FI from Valid Combinations Table. Revision B+4 (October 15, 2002) Connection Diagrams Changed from 56-Pin Standard TSOP to 48-Pin Stan- dard TSOP . Product Selector Guide Added regulated OPNs. Revision C (December 5, 2002) Secured Silicon Sector Flash Memory Region, and Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence Noted that the A CC function and unlock bypass modes are not available when the Secured Silicon sector is en- abled. Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Com- mand Sequence Noted that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program or erase operation is in progress. Common Flash Memory Interface (CFI) Changed CFI website address. Command Definitions Changed wording in last sentence of first paragraph from, “...resets the device to reading array data.” to ...”may place the device to an unknown state. A reset command is then required to return the device to read- ing array data.” CMOS Compatible Added I LR parameter to table. Removed VIL, VIH, VOL, and VOH from table and added VIL1 , V IH1 , V IL2 , V IH2 , VOL, VOH1 , and V OH2 from the CMOS table in the Am29LV640MH/L datasheet. Changed VIH1 and VIH2 minimum to 1.9. Removed typos in notes. AC Characteristics and Read-Only Operations Changed the Chip Enable to Output High Z and Out- put Enable to Output High Z Speed Options from 30 ns to 16 ns.

February 1, 2007 26190C8 Am29LV640MT/B 63 DATA SHEET Word/Byte Configuration Changed BYTE# Switching Low to Output High Z Speed Options from 30 ns to 16 ns. Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the factory. Added second bullet, Secured Silicon sector-protect. Revision C+1 (February 16, 2003) Distinctive Characteristics Corrected performance characteristics. Product Selector Guide Added note 2. Connection Diagrams Changed pin F1 to NC. Corrected Valid Combinations table. Added Note. AC Characteristics Removed 93, 93R speed option. Added Note Input values in the t WHWH1 and tWHWH2 parameters in the Erase and Program Options table that were previ- ously TBD. Also, added note 5. Input values in the t WHWH1 and tWHWH2 parameters in the Alternate CE# Controlled Erase and Program Op- tions table that were previously TBD. Also, added note Erase and Programming Performance Input values into table that were previously TBD. Added note 3 and 4 Revision C+2 (June 12, 2003) Added 90R speed grade. Erase and Programming Performance Modified table and notes, inserted values for Typical. Revision C+3 (February 12, 2004) Erase Suspend/Erase Resume Commands Added note reference to erase operation. Table 12 & Table 13: Command Definitions Modified the Addr information for both Program/Erase Suspend and Program/Erase Resume from BA to XXX. AC Characteristics - Erase and Program Operations, and Alternate CE# Controlled Erase and Program Operations Added t POLL information. AC Characteristics Figures - Program Operation Timings, Data# Polling Timings (During Embedded Algorithms, and Alternate CE# Controlled Write (Erase/Program) Operation Timings Updated figures with t POLL information. Revision C+4 (August 19, 2004) Added Max programming specifications. Cover sheet and Title page Added notation referencing superseding documenta- tion. Revision C+5 (November5, 2004) Ordering Information and Valid Combinations Added Pb-Free options Revision C+6 (December 7, 2004) Coversheet and Title page Added notation referencing superseding documenta- tion. Revision C+7 (December 13, 2005) Global This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640MT/B and is the factory-rec- ommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Revision C8 (February 1, 2007) Global Changed SecSi Sector to Secured Silicon Sector. AC Characteristics Erase and Program Operations table: Changed t BUSY to a maximum specification.

64 Am29LV640MT/B 26190C8 February 1, 2007

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2002–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.