LV065MU

AM29LV641MH AMD | Alldatasheet

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Publication Number 25261 Revision B Amendment +10 Issue Date December 21, 2005 Am29LV641MH/L Data Sheet RETIRED PRODUCT This product has been retired and is not avai lable for designs. For new and current designs, S29GL064A supersedes Am29LV641M H/L and is th e factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. April 2005 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

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This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Refer to AMD’s Website (www.amd.com) for the latest information. Publication# 25261 Rev: B Amendment/+10 Issue Date: December 21, 2005 Am29LV641MH/L 64 Megabit (4 M x 16-Bit) MirrorBit™ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O™ Control DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES „ Single power supply operation — 3 V for read, erase, and program operations „ VersatileI/O™ control — Device generates data output voltages and tolerates data input voltages on CE# and the DQ inputs/outputs as determined by the voltage on the V IO pin; operates from 1.65 to 3.6 V „ Manufactured on 0.23 µm MirrorBit process technology „ SecSi™ (Secured Silicon) Sector region — 128-word sector for permanent, secure identification through an 8-word random Electronic Serial Number, accessible through a command sequence — May be programmed and locked at the factory or by the customer „ Flexible sector architecture — One hundred twenty-eight 32 Kword sectors „ Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection „ Minimum 100,000 erase cycle guarantee per sector „ 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS „ High performance — 90 ns access time — 25 ns page read times — 0.5 s typical sector erase time — 22 µs typical effective write buffer word programming time: 16-word write buffer reduces overall programming time for multiple-word updates — 4-word page read buffer — 16-word write buffer „ Low power consumption (typical values at 3.0 V, 5 MHz) — 30 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current „ Package options — 48-pin TSOP SOFTWARE & HARDWARE FEATURES „ Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resu me: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices „ Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Unprotect: V ID-level method of changing code in locked sectors — ACC (high voltage) input accelerates programming time for higher throughput during system production — Write Protect input (WP#) prot ects first or last sector regardless of sector protection settings — Hardware reset input (RESET#) resets device This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29L V641M H/L and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

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The Am29LV641MH/L is a 64 Mbit, 3.0 volt single power supply flash memory devices organized as 4,194,304 words. The devices have a 16-bit wide data bus, and can be programmed either in the host system or in standard EPROM programmers. An access time of 90, 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (V CC) and an I/O voltage range (VIO), as specified in the Product Selector Guide and the Order- ing Information sections. The device is offered in a 48-pin TSOP package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the device using standard microprocessor write timing. Write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase oper- ation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits to de- termine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/O™ (V IO) control allows the host sys- tem to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the V IO pin. Refer to the Ordering Information section for valid V IO options. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Sus- pend/Program Resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The SecSi ™ (Secured Silicon) Sector provides a 128-word area for code or data that can be perma- nently protected. Once this sector is protected, no fur- ther changes within the sector can occur. The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP# pin. The protected sector will still be protected even during accelerated programming. AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.

December 21, 2005 Am29LV641MH/L 3 DATASHEET MIRRORBIT 64 MBIT DEVICE FAMILY RELATED DOCUMENTS To download related documents, click on the following links or go to www.amd.com →Flash Memory →Prod- uct Information→MirrorBit→Flash Information→Tech- nical Documentation. MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices AMD MirrorBit™ White Paper Migrating from Single-byte to Three-byte Device IDs Device Bus Sector Architecture Packages V IO RY/BY# WP#, ACC WP# Protection LV065MU x8 Uniform (64K-byte) 48-pin TSOP (std. & rev. pinout), 63-ball FBGA Y es Y es ACC only No WP# LV640MT/B x8/x16 Boot (8x8K-byte @ top & bottom) 48-pin TSOP , 63-ball Fine-pitch BGA, 64-ball Fortified BGA No Y es WP#/ACC pin 2 x 8 Kbyte top or bottom LV640MH/L x8/x16 Uniform (64K-byte) 56-pin TSOP (std. & rev. pinout),

64 Fortified BGA Y es Y es WP#/ACC pin 1 x 64 Kbyte

LV641MH/L x16 Uniform (32K-word) 48-pin TSOP (std. & rev. pinout) Y es No Separate WP# and ACC pins 1 x 32 Kword top or bottom LV640MU x16 Uniform (32K-word) 63-ball Fine-pitch BGA,

64 Ball Fortified BGA Y es Y es ACC only No WP#

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Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 17 Figure 13. Input Waveforms and Figure 21. Data# Polling Timings Figure 22. Toggle Bit Timings Figure 24. Temporary Sector Group Unprotect Timing Diagram ... 48 Figure 25. Sector Group Protect and Unprotect Timing Diagram .. 49 Figure 26. Alternate CE# Controlled Write (Erase/Program)

December 21, 2005 Am29LV641MH/L 5 DATASHEET PRODUCT SELECTOR GUIDE Notes: 1. See “AC Characteristics” for full specifications. 2. For the Am29LV641MH/L device, the last numeric digit in the speed option (e.g. 101, 112, 120) is used for internal purposes only. Please use OPNs as listed when placing orders. BLOCK DIAGRAM Part Number Am29LV641MH/L Speed Option VCC = 3.0–3.6 V 90R (VIO = 3.0–3.6 V) 101R (VIO = 2.7–3.6 V) 112R (VIO = 1.65–3.6 V) 120R (VIO = 1.65–3.6 V) VCC = 2.7–3.6 V 101 (VIO = 2.7–3.6 V) 112 (VIO = 1.65–3.6 V) 120 (VIO = 1.65–3.6 V) Max. Access Time (ns) 90 100 110 120 Max. CE# Access Time (ns) 90 100 110 120 Max. Page access time PACC) 25 30 30 40 30 40 Max. OE# Access Time (ns) 25 30 30 40 30 40 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS VIO WE# WP# ACC CE# OE# STB STB DQ0–DQ15 Sector Switches RESET# Data Latch Y-Gating Cell Matrix Address LatchA21–A0

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WE# RESET# ACC WP# A19 A17 A16 DQ2 V IO VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48-Pin Standard TSOP A15 A18 A14 A13 A12 A11 A10 A21 A20 WE# RESET# ACC WP# A19 A17 A16 DQ2 V IO VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48-Pin Reverse TSOP

December 21, 2005 Am29LV641MH/L 7 DATASHEET PIN DESCRIPTION A21–A0 = 22 Address inputs DQ15–DQ0 = 16 Data inputs/outputs CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP# = Hardware Write Protect input ACC = Acceleration input RESET# = Hardware Reset Pin input V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V IO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL DQ15–DQ0 A21–A0 CE# OE# WE# RESET# ACC WP# VIO

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ORDERING INFORMATION

AMD standard products are available in several packages and o perating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. Note: For the Am29LV641MH/L device, the last numeric digit in the speed option (e.g. 101, 112, 120) is used for internal purposes only. Please use OPNs as listed when placing orders. Am29LV641M H 120R E I TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected DEVICE NUMBER/DESCRIPTION Am29LV641MH/L

64 Megabit (4 M x 16-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO™ Control

3.0 Volt-only Read, Program, and Erase

(ns) VIO Range VCC Range Am29LV641MH90R, Am29LV641ML90R EI, FI 90 3.0– 3.6 V 3.0– 3.6 V Am29LV641MH101, Am29LV641ML101 100 2.7–3.6 V 2.7– 3.6 V Am29LV641MH112, Am29LV641ML112 110 1.65–3.6 V Am29LV641MH120, Am29LV641ML120 120 1.65–3.6 V Am29LV641MH101R, Am29LV641ML101R 100 2.7–3.6 V 3.0– 3.6 V Am29LV641MH112R, Am29LV641ML112R 110 1.65–3.6 V Am29LV641MH120R, Am29LV641ML120R 120 1.65–3.6 V

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Device Bus Operations

1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

1. If WP# = V IL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as
2. D IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

tion” on page 8 for VIO options on this device. mand is necessary in this mode to obtain array data.

0.3 V XX VCC ±

0.3 V XH XH i g h - Z

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data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing speci- fications and to Figure 14 for the timing diagram. Refer to the DC Characteristics ta ble for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words. The appropriate page is se- lected by the higher address bits A(max)–A2. Address bits A1–A0 determine the specific word within a page. This is an asynchronous operation; the microproces- sor supplies the specific word location. The random or initial page access is equal to t ACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t PACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE. Fast page mode ac- cesses are obtained by keeping the “read-page ad- dresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Char- acteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system to write a maximum of 16 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. See “Write Buffer” for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily in- tended to allow faster manufacturing throughput dur- ing system production. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC pin returns the device to normal op- eration. Note that the ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V IO ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad-

December 21, 2005 Am29LV641MH/L 11 DATASHEET dresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for th e duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 17 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

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Table 2. Sector Address Table

Note: All sectors are 32 Kwords in size. Table 2. Sector Address Table (Continued)

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accessed in-system through the command register. A6, A3, A2, A1, and A0 must be as shown in Table 3. mand Sequence section for more information. Table 3. Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

implemented via two methods. the first sector group unprotect write cycle. tact an AMD representative for details. Table 4. Sector Group Protection/Unprotection Note: All sector groups are 128 Kwords in size.

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mode, the maximum input load current is increased. See the table in “DC Characteristics”. Figure 1. Temporary Sector Group

1. All protected sector gr oups unprotected (If WP# = VIL,

the first or last sector will remain protected).

1. All previously protected sector groups are protected

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

18 Am29LV641MH/L December 21, 2005

rity of the ESN once the product is shipped to the field. being used to replace devices that are factory locked. dresses normally occupied by the first sector (SA0). sending commands to sector SA0. gram and protect the 128-word SecSi sector. mand sequence. See Command Definitions. space can be modified in any way. without raising any device pin to a high voltage. Sector, follow the algorithm shown in Figure 3. writing within the remainder of the array. Table 5. SecSi Sector Contents

Figure 3. SecSi Sector Protect Verify and power-down transitions, or from system noise. or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. 55h, any time the device is ready to read array data. the system must write the reset command. device to reading array data.

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Table 6. CFI Query Identification String Table 7. System Interface String

Table 8. Device Geometry Definition

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Table 9. Primary Vendor-Specific Extended Query

December 21, 2005 Am29LV641MH/L 23 DATASHEET non-erase-suspended sector. After completing a pro- gramming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. See the next section, Reset Command , for more informa- tion. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Pro- gramming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific ad- dresses: Note: The device ID is read over three cycles. SA = Sector Address Table 10 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and re- quires V ID on address pin A9. The autoselect com- mand sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the de- vice is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-word random Electronic Serial Num- ber (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the de- vice to normal operation. Table 10 shows the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further information. Note that the ACC function and unlock bypass modes are not avail- able when the SecSi Sector is enabled. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further Identifier Code A7:A0 Manufacturer ID 00h Device ID, Cycle 1 01h Device ID, Cycle 2 0Eh Device ID, Cycle 3 0Fh SecSi Sector Factory Protect 03h Sector Protect Verify (SA)02h

24 Am29LV641MH/L December 21, 2005

controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 10 shows the address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status sec- tion for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Table 10 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load com- mand written at the Sector Address in which program- ming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is se- lected by address bits A MAX–A4. All subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be per- formed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be per- formed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the addre ss/data pair counter will be decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter dec- rements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Pro- gram Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming.

December 21, 2005 Am29LV641MH/L 25 DATASHEET The write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load com- mand. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data load- ing stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the de- vice for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is re- quired when using Write-Buffer-Programming features in Unlock Bypass mode. Accelerated Program The device offers accelerated program operations through the ACC pin. When the system asserts V HH on the ACC pin, the device automatically enters the Un- lock Bypass mode. The system may then write the two-cycle Unlock Bypass program command se- quence. The device uses the higher voltage on the ACC pin to accelerate the operation. Note that the ACC pin must not be at V HH for operations other than accelerated programming, or device damage may re- sult. Figure 5 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.

26 Am29LV641MH/L December 21, 2005

Figure 4. Write Buffer Programming Operation

1. When Sector Address is specified, any address in
2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

1. If this flowchart location was reached because

command. if DQ5=1, write the Reset command.

1. See Table 10 for command sequences required for

Figure 5. Program Operation program operation is in progress. Autoselect Command Sequence for more information. written after the device has resume programming. Note: See Table 10 for program command sequence.

28 Am29LV641MH/L December 21, 2005

Figure 6. Program Suspend/Program Resume of the erase operation by using DQ7, DQ6, or DQ2. mation on these status bits. available when an erase operation is in progress. and Figure 20 section for timing diagrams. ings during these operations. erase operation is in progress.

December 21, 2005 Am29LV641MH/L 29 DATASHEET The system can monitor DQ3 to determine if the sec- tor erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris- ing edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector. Refer to the Write Opera- tion Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- mands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 7 illustrates the algorithm for the erase opera- tion. Refer to the Erase and Program Operations ta- bles in the AC Characteristics section for parameters, and Figure 20 section for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sec- tor erase operation, including the 50 µs time-out pe- riod during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a typi- cal of 5 µs (maximum of 20 µs) to suspend the erase operation. However, when the Erase Suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The sys- tem can read data from or program data to any sector not selected for erasure. (The device “erase sus- pends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors pro- duces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for infor- mation on these status bits. After an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Note: During an erase operation, this flash device per- forms multiple internal operations which are invisible to the system. When an erase operation is suspended, any of the internal operations that were not fully com- pleted must be restarted. As such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress will be impeded as a function of the number of suspends. The result will be a longer cumulative erase time than without suspends. Note that the additional suspends do not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In this ex- ample, erase performance will not be significantly im- pacted.

30 Am29LV641MH/L December 21, 2005

Figure 7. Erase Operation

1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector

Table 10. Command Definitions RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. or CE# pulse, whichever happens later. WE# or CE# pulse, whichever happens first. erased. Address bits A21–A15 uniquely select any sector. WC = Word Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All other are write cycles.
4. During unlock and command cycles, when lower address bits are

data bits higher than DQ7 are don’t care.

1. No unlock or command cycles required when device is in read
2. The Reset command is required to return to the read mode (or to

while the device is providing status information.

1. The fourth cycle of the autoselect command sequence is a read

Command Sequence section for more information.

1. The device ID must be read in three cycles.
2. If WP# protects the highest address sector, the data is 98h for
3. The data is 00h for an unprotected sector group and 01h for a
4. The total number of cycles in the command sequence is

including "Program Buffer to Flash" command.

1. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

32 Am29LV641MH/L December 21, 2005

final WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Table 11 shows the outputs for Data# Polling on DQ7. Figure 8. Data# Polling Algorithm

1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

34 Am29LV641MH/L December 21, 2005

DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE# to con- trol the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 11 to compare out- puts for DQ2 and DQ6. Figure 9 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 22 shows the toggle bit timing diagram. Figure 23 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 9 for the following discussion. When- ever the system initially begins reading toggle bit sta- tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the tog- gle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of Figure 9). DQ5: Exceeded Timing Limits DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not suc- cessfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between addi- tional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the sys- tem software should check the status of DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 11 shows the status of DQ3 relative to the other status bits.

Programming section for more details. Table 11. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
3. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

36 Am29LV641MH/L December 21, 2005

1. Minimum DC voltage on input or I/O pins is –0.5 V.

overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V. CC +2.0 V for periods up to 20 ns.

1. Minimum DC input voltage on pins A9, OE#, ACC, and
2. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability.

1. Operating ranges define those limits between which the

functionality of the device is guaranteed.

1. See Ordering Information section for valid VCC/VIO range

Figure 10. Maximum Negative Figure 11. Maximum Positive

December 21, 2005 Am29LV641MH/L 37 DATASHEET DC CHARACTERISTICS CMOS Compatible Notes: 1. On the WP#/ACC pin only, the maxi mum input load current when WP# = VIL is ± 5.0 µA. 2. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. Maximum I CC specifications are tested with VCC = VCCmax. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. TIf VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH for these connections is VIO + 0.3 V 6. V CC voltage requirements. 7. V IO voltage requirements. 8. Not 100% tested. 9. Includes RY/BY# Parameter Symbol Parameter Description (Notes) Test Conditions Min Typ Max Unit I LI Input Load Current (1) VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, ACC Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILR Reset Leakage Current V CC = VCC max; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (2, 3) CE# = VIL, OE# = VIH,

5 MHz 15 20

1 MHz 15 20

ICC2 VCC Initial Page Read Current (2, 3) CE# = V IL, OE# = VIH 30 50 mA ICC3 VCC Intra-Page Read Current (2, 3) CE# = V IL, OE# = VIH 10 20 mA ICC4 VCC Active Write Current (3, 4) CE# = V IL, OE# = VIH 50 60 mA ICC5 VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V, WP# = VIH 15 µ A ICC6 VCC Reset Current (3) RESET# = V SS ± 0.3 V, WP# = VIH 15 µ A ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 15 µ A IACC ACC Accelerated Program Current (3) CE# = VIL, OE# = VIH ACC pin 10 20 mA VCC pin 30 60 mA VIL1 Input Low Voltage 1(5, 6) –0.5 0.8 V VIH1 Input High Voltage 1 (5, 6) 1.9 V CC + 0.5 V VIL2 Input Low Voltage 2 (5, 7) –0.5 0.3 x V IO V VIH2 Input High Voltage 2 (5, 7) 1.9 V IO + 0.5 V VHH Voltage for ACC Program Acceleration VCC = 2.7 –3.6 V 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.7 –3.6 V 11.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min = VIO 0.15 x VIO V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO V VOH2 IOH = –100 µA, VCC = VCC min = VIO VIO–0.4 V VLKO Low VCC Lock-Out Voltage (8) 2.3 2.5 V

38 Am29LV641MH/L December 21, 2005

Table 12. Test Specifications Note: If VIO < VCC, the reference level is 0.5 VIO. Figure 12. Test Setup Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.

1. See Figure 12 and Table 12 for test specifications.
2. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

Figure 14. Read Operation Timings

40 Am29LV641MH/L December 21, 2005

Figure 15. Page Read Timings

1. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

Description All Speed Options UnitJEDEC Std. Figure 16. Read Operation Timings

42 Am29LV641MH/L December 21, 2005

Figure 17. Reset Timings

December 21, 2005 Am29LV641MH/L 43 DATASHEET AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. For 1–16 words programmed. 4. Effective write buffer specification is based upon a 16-word write buffer operation. 5. Word programming specification is based upon a single word programming operation not utilizing the write buffer. 6. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. When using the program suspend/resume featur e, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter Speed Options JEDEC Std. Description 90R 101 112 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Effective Word Program Time, using the Write Buffer (Notes 2, 4) Typ 22 µs Effective Accelerated Word Program Time, using the Write Buffer (Notes 2, 4) Typ 17.6 µs Single Word Program Operation (Note 2, 5) Typ 100 µs Accelerated Single Word Programming Operation (Note 2, 5) Typ 90 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tPOLL Program Valid Before Status Polling (Note 7) Max 4 µs

44 Am29LV641MH/L December 21, 2005

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 18. Program Operation Timings Figure 19. Accelerated Program Timing Diagram

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

46 Am29LV641MH/L December 21, 2005

48 Am29LV641MH/L December 21, 2005

1. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

Figure 24. Temporary Sector Group Unprotect Timing Diagram

• For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.

Figure 25. Sector Group Protect and Unprotect Timing Diagram

50 Am29LV641MH/L December 21, 2005

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. For 1–16 words programmed. 4. Effective write buffer specification is based upon a 16-word write buffer operation. 5. Word programming specification is based upon a single word programming operation not utilizing the write buffer. 6. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. When using the program suspend/resume featur e, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter Speed Options JEDEC Std. Description 90R 101, 101R 112, 112R 120, 120R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Effective Word Program Time, using the Write Buffer (Notes 2, 4) Typ 22 µs Effective Accelerated Word Program Time, using the Write Buffer (Notes 2, 4) Typ 17.6 µs Single Word Program Operation (Note 2, 5) Typ 100 µs Accelerated Single Word Programming Operation (Note 2, 5) Typ 90 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tRH Reset High Time Before Write (Note 1) Min 50 ns tPOLL Program Valid Before Status Polling (Note 7) Max 4 µs

1. Figure indicates last two bus cycl es of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

52 Am29LV641MH/L December 21, 2005

ERASE AND PROGRAMMING PERFORMANCE 1. Typical program and erase times as sume the following conditions: 25°C, 3.0 V VCC. Programming specifications assume that all bits are programmed to 00h. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. For 1-16 words programmed in a single write buffer programming operation. 5. Effective write buffer specification is calculated on a per-word basis for a 16-word write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 10 for further information on command definitions. 8. The device has a minimum erase and program cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 15 sec Excludes 00h programming prior to erasure (Note 6)Chip Erase Time 64 128 sec Single Word Program Time (Note 3) 100 800 µs Excludes system level overhead (Note 7) Accelerated Single Word Program Time (Note 3) 90 720 µs Total Write Buffer Program Time (Note 4) 352 1800 µs Effective Word Program Time, using the Write Buffer (Note 5) 22 113 µs Total Accelerated Write Buffer Program Time (Note 4) 282 1560 µs Effective Accelerated Word Program Time, using the Write Buffer (Note 4) 17.6 98 µs Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA

December 21, 2005 Am29LV641MH/L 53 DATASHEET TSOP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 6 7.5 pF COUT Output Capacitance V OUT = 0 8.5 12 pF CIN2 Control Pin Capacitance V IN = 0 7.5 9 pF Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

54 Am29LV641MH/L December 21, 2005

TS 048—48-Pin Standard Thin Small Outline Package Dwg rev AA; 10/99

December 21, 2005 Am29LV641MH/L 55 DATASHEET PHYSICAL DIMENSIONS TSR048—48-Pin Reverse Thin Small Outline Package Dwg rev AA; 10/99

56 Am29LV641MH/L December 21, 2005

Revision A (August 3, 2001) Initial release as abbreviated Advance Information data sheet. Revision A+1 (October 3, 2001) Global Added 120 ns speed option. Changed operating voltage range for 90 ns device. Physical Dimensions Added section. Revision B (March 14, 2002) Global Expanded data sheet to full specification version. Revision B+1 (April 26, 2002) MirrorBit 64 Mbit Device Family Deleted Am29LV641MT/B. Figure 2, In-System Sector Group Protect/Unprotect Algorithms Added A3 and A2 address requirement. Sector Group Protection/Unprotection Deleted reference to alternate method of sector pro- tection. Autoselect Command Substituted text with ID code table for easier refer- ence. Table 10, Command Definitions Combined Notes 4 and 5 from Revision B. Corrected number of cycles indicated for Write-to-Buffer and Au- toselect Device ID command sequences. Figure 25, Sector Group Protect and Unprotect Timing Diagram In the note, added A3 and A2 address requirement. Revision B+2 (August 1, 2002) Mirrorbit 64 MBIT Device Family Added 64 Fortified BGA to table. Program Suspend/Program Resume Command Sequence Changed program operation wait time from 1ms to 15μs. Figure 5. Program Suspend/Program Resume Changed wait from 1ms to 15μs. Modified the special handling wording. Deleted the IACC specification row. Added Note 1. Sector Erase Command Sequence Deleted statement that describes the outcome of when the Embedded Erase operation is in progress. Revision B+4 (October 15, 2002) Erase and Programming Performance Changed values for typical and maximum times on word program time and write buffer program time to TBD. Inserted TBD for maximum chip erase time. Revision B+5 (November 26, 2002) Product Selector Guide and Read-Only Characteristics Added a 30 ns option to t PACC and tOE standard for the 112R and 120R speed options. Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. SecSi Sector Flash Memory Region, and Enter SecSi Sector/Exit SecSi Sector Command Sequence Noted that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled.

December 21, 2005 Am29LV641MH/L 57 DATASHEET Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Command Sequence Noted that the SecSi Sector, autoselect, and CFI func- tions are unavailable when a program or erase opera- tion is in progress. Common Flash Memory Interface (CFI) Changed CFI website address Changed VIH1 and VIH2 minimum to 1.9. Corrected performance characteristics. Corrected Valid Combination to reflect speed option changes. Added Note. AC Characteristics Removed 90, 90R speed option. Added Note Input values in the t WHWH1 and tWHWH2 parameters in the Erase and Program Options table that were previ- ously TBD. Also added notes 5 and 6. Input values in the t WHWH1 and tWHWH2 parameters in the Alternate CE# Controlled Erase and Program Op- tions table that were previously TBD. Also added notes Erase and Programming Performance Input values into table that were previously TBD. Added note 3 and 4. Revision B+7 (June 12, 2003) Added 90R speed grade, modified note. Erase and programming Performance Modified table, inserted values for Typical. Revision B+8 (February 13, 2004) Table 1 Device Bus Operations Modified ACC column, replaced instances of X to L/H. Word/Byte Program Command Sequence Removed reference to byte. Erase Suspend/Erase Resume Commands Added note on flash device performance during sus- pend/erase mode Table 10 Command Definitions Modified Program/Erase Suspend and Program/Erase Resume from BA to XXX (Don’t Care). AC Characteristics - Erase and Program Operations Added tPOLL information and note. AC Characteristics - Alternate CE# Controlled Erase and Program Operations Added tPOLL information and note. AC Characteristics Figures Added t POLL timing to Figure 18, Program Operation Timings ; Figure 21, Data# Polling Timings (During Embedded Algorithms); and Figure 26, Alternate CE# Controlled Write (Erase/Program) Operation Timings. Erase and Programming Performance Removed reference to byte. Trademarks Updated. Revision B+9 (August 23, 2004) Added Max programming specifications. Added notation referencing superseding documenta- tion. Revision B+10 (December 21, 2005) Global This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV641M H/L and is the factory-rec- ommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

58 Am29LV641MH/L December 21, 2005

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de- vices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2004-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.