LV033MU

AM29LV320MH AMD | Alldatasheet

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This product has been retired and is not ava ilable for designs. For new and current designs, S29GL032A supersedes Am29LV320MH/L and is th e factory-recommended migration path. Please refer to the S29GL032A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. The following document contains information on Spansion memory products. Although the docu- ment is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 26517 Revision B Amendment 4 Issue Date January 31, 2007

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Publication# 26517 Rev: B Amendment/4 Issue Date: January 31, 2007 DATA SHEET Am29LV320MH/L

32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit™

3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O™ Control

DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Single power supply operation — 3 V for read, erase, and program operations ■ VersatileI/O™ control — Device generates data output voltages and tolerates data input voltages on the DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V ■ Manufactured on 0.23 µm MirrorBit process technology ■ Secured Silicon Sector region — 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence — May be programmed and locked at the factory or by the customer ■ Flexible sector architecture — Sixty-four 32 Kword/64-Kbyte sectors ■ Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection ■ Minimum 100,000 erase cycle guarantee per sector ■ 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS ■ High performance — 90 ns access time — 25 ns page read times — 0.5 s typical sector erase time — 15 µs typical effective write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word/byte updates — 4-word/8-byte page read buffer — 16-word/32-byte write buffer ■ Low power consumption (typical values at 3.0 V, 5 MHz) — 13 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current ■ Package options — 56-pin TSOP — 64-ball Fortified BGA SOFTWARE & HARDWARE FEATURES ■ Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices ■ Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Unprotect: V ID-level method of changing code in locked sectors — WP#/ACC input: Write Protect input (WP#) protects first or last sector regardless of sector protection settings ACC (high voltage) accelerates programming time for higher throughput during system production — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) indicates program or erase cycle completion This product has been retired and is not available for designs. For new and current designs, S29GL032A supersedes Am29LV320M H/L and is the factory-recommended migration path. Please refer to the S29GL032A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

2 Am29LV320MH/L 26517B4 January 31, 2007

The Am29LV320MH/L is a 32 Mbit, 3.0 volt single power supply flash memory device organized as 2,097,152 words or 4,194,304 bytes. The device has an 8-bit/16-bit bus and can be programmed either in the host system or in standard EPROM programmers. An access time of 90, 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (V CC) and an I/O voltage range (VIO), as specified in the Product Selector Guide and the Order- ing Information sections. The device is offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (ACC) feature provides shorter programming times through increased current on the WP#/ACC input. This feature is intended to facilitate factory throughput dur- ing system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the device using standard microprocessor write timing. Write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase oper- ation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to deter- mine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/O™ (V IO) control allows the host sys- tem to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the V IO pin. Refer to the Ordering Information section for valid V IO options. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Sus- pend/Program Resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin. The protected sector will still be protected even during accelerated programming. The Secured Silicon Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.

January 31, 2007 26517B4 Am29LV320MH/L 3 DATA SHEET MIRRORBIT 32 MBIT DEVICE FAMILY RELATED DOCUMENTS To download related documents, click on the following links or go to www.amd.com →Flash Memory →Prod- uct Information→MirrorBit→Flash Information→Tech- nical Documentation. MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs AMD MirrorBit™ White Paper Device Bus Sector Architecture Packages V IO RY/BY# WP#, ACC WP# Protection LV033MU x8 Uniform (64 Kbyte) 40-pin TSOP (std. & rev. pinout), 48-ball FBGA Y es Y es ACC only No WP# LV320MT/B x8/x16 Boot (8 x 8 Kbyte at top & bottom) 48-pin TSOP , 48-ball Fine-pitch BGA, 64-ball Fortified BGA No Y es WP#/ACC pin 2 x 8 Kbyte top or bottom LV320MH/L x8/x16 Uniform (64 Kbyte) 56-pin TSOP (std. & rev. pinout),

64 Fortified BGA Y es Y es WP#/ACC pin 1 x 64 Kbyte

4 Am29LV320MH/L 26517B4 January 31, 2007

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...18 Figure 13. Input Waveforms and Figure 20. Data# Polling Timings (During Embedded Algorithms) . 46 Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 48 Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 49 Figure 25. Alternate CE# Controlled Write (Erase/Program)

January 31, 2007 26517B4 Am29LV320MH/L 5 DATA SHEET PRODUCT SELECTOR GUIDE Note: 1. See AC Characteristics for full specifications. 2. For the Am29LV320MH/L device, the last numeric digit in the speed option (e.g. 90R, 101, 112, 120) is used for internal purposes only. Please use OPNs as listed when placing orders. BLOCK DIAGRAM Part Number Am29LV320MH/L Speed Option VCC = 3.0–3.6 V 90R (VIO = 3.0–3.6 V) 101R (VIO = 2.7–3.6 V) 112R (VIO = 1.65–3.6 V) 120R (VIO = 1.65–3.6 V) VCC = 2.7–3.6 V 101 (VIO = 2.7–3.6 V) 112 (VIO = 1.65–3.6 V) 120 (VIO = 1.65–3.6 V) Max. Access Time (ns) 90 100 110 120 Max. CE# Access Time (ns) 90 100 110 120 Max. Page access Time (t PACC)2 5 3 0 3 0 4 0 3 0 4 0 Max. OE# Access Time (ns) 25 30 30 40 30 40 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# WP#/ACC BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA20–A0 VIO

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V IO A15 A18 A14 A13 A12 A11 A10 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# V SS CE# DQ5 DQ12 DQ4 V CC DQ11 DQ3 DQ10 NC NC A15 A14 A13 A12 A11 A10 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A18 A17 NC NC A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 NC NC OE# V SS CE# NC VIO 56-Pin Standard TSOP 56-Pin Reverse TSOP

January 31, 2007 26517B4 Am29LV320MH/L 7 DATA SHEET CONNECTION DIAGRAMS Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP , BGA, SSOP , PDIP , PLCC). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. B3 C3 D3 E3 F3 G3 H3 B4 C4 D4 E4 F4 G4 H4 B5 C5 D5 E5 F5 G5 H5 B6 C6 D6 E6 F6 G6 H6 B7 C7 D7 E7 F7 G7 H7 B8 C8 D8 E8 F8 G8 H8 NCNCNCVSSVIONCNC VSSDQ15/A-1BYTE#A16A15A14A12 DQ6DQ13DQ14DQ7A11A10A8 DQ4VCCDQ12DQ5A19NCRESET# DQ3DQ11DQ10DQ2A20A18WP#/ACC DQ1DQ9DQ8DQ0A5A6A17 NC A13 WE# RY/BY# B2 C2 D2 E2 F2 G2 H2 VSSOE#CE#A0A1A2A4 B1 C1 D1 E1 F1 G1 H1 NCNCVIONCNCNCNC NC 64-Ball Fortified BGA Top View, Balls Facing Down

8 Am29LV320MH/L 26517B4 January 31, 2007

A20–A0 = 21 Address inputs DQ14–DQ0 = 15 Data inputs/outputs DQ15/A-1 = DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode) CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP#/ACC = Hardware Write Protect input/Pro- gramming Acceleration input RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output BYTE# = Selects 8-bit or 16-bit mode V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V IO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ15–DQ0 (A-1) A20–A0 CE# OE# WE# RESET# RY/BY# WP#/ACC VIO BYTE#

January 31, 2007 26517B4 Am29LV320MH/L 9 DATA SHEET

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. Note: For the Am29LV320MH/L device, the last numeric digit in the speed option (e.g. R, 101, 112, 120) is used for internal purposes only. Please use OPNs as listed when placing orders. Am29LV320M H 120R PC I TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) F = Industrial (–40 °C to +85°C) with Pb-free Packages PACKAGE TYPE E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056) F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056) PC = 64-Ball Fortified Ball Grid Array 1.0 mm pitch, 13 x 11 mm package (LAA064) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = V IL) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected DEVICE NUMBER/DESCRIPTION Am29LV320M

32 Megabit (2 M x 16-Bit/4 M x 8-Bit) MirrorBit™ Uniform Sector Flash Memory

with VersatileIO™ Control, 3.0 Volt-only Read, Program, and Erase Valid Combinations for Speed (ns) VIO Range VCC Range Am29LV320MH90R, Am29LV320ML90R EI, FI, EF Am29LV320MH101, Am29LV320ML101 100 2.7–3.6 V 2.7–3.6 VAm29LV320MH112, Am29LV320ML112 110 1.65–3.6 V Am29LV320MH120, Am29LV320ML120 120 1.65–3.6 V Am29LV320MH101R, Am29LV320ML101R 100 2.7–3.6 V 3.0–3.6 VAm29LV320MH112R, Am29LV320ML112R 110 1.65–3.6 V Am29LV320MH120R, Am29LV320ML120R 120 1.65–3.6 V Valid Combinations for Fortified BGA Package Speed (ns) VIO Range VCC Range Order Number Package Marking Am29LV320MH90R, Am29LV320ML90R PCI, PCF L320MH90N, L320ML90N F 90 3.0– 3.6 V 3.0– 3.6 V Am29LV320MH101, Am29LV320ML101 L320MH01P , L320ML01P 100 2.7– 3.6 V 2.7– 3.6 V Am29LV320MH112, Am29LV320ML112 L320MH11P , L320ML11P 110 1.65– 3.6 V Am29LV320MH120, Am29LV320ML120 L320MH12P , L320ML12P 120 1.65– 3.6 V Am29LV320MH101R, Am29LV320ML101R L320MH01N, L320ML01N 100 2.7– 3.6 V 3.0– 3.6 V Am29LV320MH112R, Am29LV320ML112R L320MH11N, L320ML11N 110 1.65– 3.6 V Am29LV320MH120R, Am29LV320ML120R L320MH12N, L320ML12N 120 1.65– 3.6 V

10 Am29LV320MH/L 26517B4 January 31, 2007

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Device Bus Operations

1. Addresses are A20:A0 in word mode; A20:A-1 in byte mode. Sector addresses are A20:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

1. D IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

used as an input for the LSB (A-1) address function. tion” on page 9 for VIO options on this device.

0.3 V XX VCC ±

0.3 V XH X High-Z High-Z High-Z

January 31, 2007 26517B4 Am29LV320MH/L 11 DATA SHEET For example, a V I/O of 1.65–3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 V devices on the same data bus. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V IH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing speci- fications and to Figure 13 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Ad- dress bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to t ACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t PACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE. Fast page mode ac- cesses are obtained by keeping the “read-page ad- dresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command se- quences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Char- acteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system to write a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See “Write Buffer” for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated program- ming, or device damage may result. In addition, no ex- ternal pullup is necessary since the WP#/ACC pin has internal pullup to V CC. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Standby Mode When the system is not read ing or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced,

12 Am29LV320MH/L 26517B4 January 31, 2007

and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V IO ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 16 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Table 2. Sector Address Table

14 Am29LV320MH/L 26517B4 January 31, 2007

Notes: The address range is A20:A-1 in byte mode (BYTE# = VIL) or A20:A0 in word mode (BYTE# = VIH). Table 2. Sector Address Table (Continued)

accessed in-system through the command register. A6, A3, A2, A1, and A0 must be as shown in Table 3. Command Sequence section for more information. Table 3. Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

16 Am29LV320MH/L 26517B4 January 31, 2007

implemented via two methods. the first sector group unprotect write cycle. tact an AMD representative for details. Table 4. Sector Group Protection/Unprotection

scribed in “Sector Group Protection and Unprotection”. increased. See the table in “DC Characteristics”. Figure 1. Temporary Sector Group

1. All protected sector groups unprotected (If WP# = V IL,

the first or last sector will remain protected).

1. All previously protected sector groups are protected

18 Am29LV320MH/L 26517B4 January 31, 2007

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

being used to replace devices that are factory locked. addresses normally occupied by the first sector (SA0). verts to sending commands to sector SA0. 256-byte Secured Silicon sector. ming command sequence. See Command Definitions. ble to the Secured Silicon Sector. protected when the device is shipped from the factory. on ordering ESN Factory Locked devices. for details on using AMD’s ExpressFlash service. Table 5. Secured Silicon Sector Contents

20 Am29LV320MH/L 26517B4 January 31, 2007

Figure 3. Secured Silicon Sector Protect Verify or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. 55h, any time the device is ready to read array data. the system must write the reset command. device to reading array data.

Table 6. CFI Query Identification String Table 7. System Interface String

22 Am29LV320MH/L 26517B4 January 31, 2007

Table 8. Device Geometry Definition

Table 9. Primary Vendor-Specific Extended Query

24 Am29LV320MH/L 26517B4 January 31, 2007

Writing specific address and data commands or se- quences into the command register initiates device op- erations. Tables 10 and 11 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to read- ing array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a pro- gramming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. See the next section, Reset Command , for more informa- tion. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an aut oselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Pro- gramming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific ad- dresses: Note: The device ID is read over three cycles. SA = Sector Address Tables 10 and 11 show the address requirements and codes. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the de- vice is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Identifier Code A7:A0 (x16) A6:A-1 (x8) Manufacturer ID 00h 00h Device ID, Cycle 1 01h 02h Device ID, Cycle 2 0Eh 1Ch Device ID, Cycle 3 0Fh 1Eh Secured Silicon Sector Factory Protect 03h 06h Sector Protect Verify (SA)02h (SA)04h

January 31, 2007 26517B4 Am29LV320MH/L 25 DATA SHEET Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing an 8-word/16-byte random Elec- tronic Serial Number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Se- cured Silicon Sector region until the system issues the four-cycle Exit Secured S ilicon Sector command se- quence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. Ta- bles 10 and 11 show the address and data require- ments for both command sequences. See also “Secured Silicon Sector Flash Memory Region” for fur- ther information. Note that the ACC function and un- lock bypass modes are not available when the Secured Silicon Sector is enabled. Word/Byte Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 10 and 11 show the address and data requirements for the word/byte pro- gram command sequence, respectively. Note that the Secured Silicon Sector, auto select, and CFI functions are unavailable when a program operation is in progress. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status sec- tion for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Tables 10 and 11 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initi- ated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which pro- gramming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is se- lected by address bits A MAX–A4. All subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be per- formed across multiple write-buffer pages. This also

26 Am29LV320MH/L 26517B4 January 31, 2007

means that Write Buffer Programming cannot be per- formed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter dec- rements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Pro- gram Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last add ress location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load com- mand. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data load- ing stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the de- vice for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is re- quired when using Write-Buffer-Programming features in Unlock Bypass mode. Accelerated Program The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated programming, or device dam- age may result. In addition, no external pullup is nec- essary since the WP#/ACC pin has internal pullup to V CC. Figure 5 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams.

Figure 4. Write Buffer Programming Operation

1. When Sector Address is specified, any address in
2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

1. If this flowchart location was reached because

command. if DQ5=1, write the Reset command.

1. See Table 11 for command sequences required for

28 Am29LV320MH/L 26517B4 January 31, 2007

Figure 5. Program Operation μs (maximum) 5μs typical and updates the status bits. quences to enter and exit this region. Autoselect Command Sequence for more information. written after the device has resume programming.

30 Am29LV320MH/L 26517B4 January 31, 2007

tion Status section for information on these status bits. reading array data, to ensure data integrity. and Figure 19 section for timing diagrams. suspends the erase operation. if a sector is actively erasing or is erase-suspended. mation on these status bits. just as in the standard word program operation. a longer cumulative erase time than without suspends. Figure 7. Erase Operation

1. See Tables 10 and 11 for erase command sequence.
2. See the section on DQ3 for information on the sector

Table 10. Command Definitions (x16 Mode, BYTE# = V IH) RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. pulse, whichever happens later. or CE# pulse, whichever happens first. erased. Address bits A20–A15 uniquely select any sector. WC = Word Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are

bits above DQ7 are don’t care.

1. No unlock or command cycles required when device is in read
2. Reset command is required to return to read mode (or to

providing status information.

1. Fourth cycle of the autoselect command sequence is a read
2. Device ID must be read in three cycles.
3. If WP# protects highest address sector, data is 98h for factory
4. Data is 00h for an unprotected sector group and 01h for a
5. Total number of cycles in command sequence is determined by

cycles in command sequence is 21.

1. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. Unlock Bypass command is required prior to Unlock Bypass
2. Unlock Bypass Reset command is required to return to read

mode when device is in unlock bypass mode.

1. System may read and program in non-erasing sectors, or enter

command is valid only during a sector erase operation.

1. Erase Resume command is valid only during Erase Suspend
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

32 Am29LV320MH/L 26517B4 January 31, 2007

Table 11. Command Definitions (x8 Mode, BYTE# = V IL) RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. pulse, whichever happens later. or CE# pulse, whichever happens first. erased. Address bits A20–A15 uniquely select any sector. BC = Byte Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
5. Unless otherwise noted, address bits A20–A11 are don’t cares.
6. No unlock or command cycles required when device is in read
7. Reset command is required to return to read mode (or to

providing status information.

1. Fourth cycle of autoselect command sequence is a read cycle.

Sequence section or more information.

1. Device ID must be read in three cycles.
2. If WP# protects highest address sector, data is 98h for factory
3. Data is 00h for an unprotected sector group and 01h for a
4. Total number of cycles in command sequence is determined by

cycles in command sequence is 21.

1. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. Unlock Bypass command is required prior to Unlock Bypass
2. Unlock Bypass Reset command is required to return to read

mode when device is in unlock bypass mode.

1. System may read and program in non-erasing sectors, or enter

command is valid only during a sector erase operation.

1. Erase Resume command is valid only during Erase Suspend
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

34 Am29LV320MH/L 26517B4 January 31, 2007

RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, sev- eral RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. If the output is low (Busy), the device is actively eras- ing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 12 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or com- plete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any ad- dress, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm op- eration, successive read c ycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approxi- mately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the de- vice enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alterna- tively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro- gram algorithm is complete. Table 12 shows the outputs for Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences be- tween DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.

36 Am29LV320MH/L 26517B4 January 31, 2007

termine the status of the operation (top of Figure 9). in the erase-suspend-program mode). device will accept additional sector erase commands. last command might not have been accepted. Table 12. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
3. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

38 Am29LV320MH/L 26517B4 January 31, 2007

Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = V IL is ± 5.0 µA. 2. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. Maximum I CC specifications are tested with VCC = VCCmax. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. TIf VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH for these connections is VIO + 0.3 V 6. V CC voltage requirements. 7. V IO voltage requirements. 8. Not 100% tested. 9. Includes RY/BY# Parameter Symbol Parameter Description (Notes) Test Conditions Min Typ Max Unit ILI Input Load Current (1) VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, ACC Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILR Reset Leakage Current V CC = VCC max; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (2, 3) CE# = VIL, OE# = VIH,

5 MHz 3 34

1 MHz 13 43

ICC2 VCC Initial Page Read Current (2, 3) CE# = V IL, OE# = VIH

1 MHz 4 50

ICC3 VCC Intra-Page Read Current (2, 3) CE# = V IL, OE# = VIH

10 MHz 3 20

33 MHz 6 40 mA

ICC4 VCC Active Write Current (3, 4) CE# = V IL, OE# = VIH 50 60 mA ICC5 VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V, WP# = VIH 15 µ A ICC6 VCC Reset Current (3) RESET# = V SS ± 0.3 V, WP# = VIH 15 µ A ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 15 µ A VIL1 Input Low Voltage 1(5, 6) –0.5 0.8 V VIH1 Input High Voltage 1 (5, 6) 1.9 V CC + 0.5 V VIL2 Input Low Voltage 2 (5, 7) –0.5 0.3 x V IO V VIH2 Input High Voltage 2 (5, 7) 1.9 V IO + 0.5 V VHH Voltage for ACC Program Acceleration VCC = 2.7 –3.6 V 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.7 –3.6 V 11.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min = VIO 0.15 x VIO V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO V VOH2 IOH = –100 µA, VCC = VCC min = VIO VIO–0.4 V VLKO Low VCC Lock-Out Voltage (8) 2.3 2.5 V VIL1 Input Low Voltage 1(5, 6) –0.5 0.8 V

40 Am29LV320MH/L 26517B4 January 31, 2007

1. See Figure 12 and Table 13 for test specifications.
2. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation VIO ≠ VCC.

0 VRY/BY#

Figure 14. Read Operation Timing

• Figure shows device in word mode. Addresses are A1–A-1 for byte mode.

Figure 15. Page Read Timings

42 Am29LV320MH/L 26517B4 January 31, 2007

1. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC..

Description All Speed Options UnitJEDEC Std. Figure 16. Reset Timings

January 31, 2007 26517B4 Am29LV320MH/L 43 DATA SHEET AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. For 1–16 words/1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. AC specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after t POLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter Speed Options JEDEC Std. Description 90R 101, 101R 112, 112R 120, 120R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 240 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 7.5 µs Per Word Typ 15 µs Accelerated Effective Write Buffer Program Operation (Notes 2, 5) Per Byte Typ 6.25 µs Per Word Typ 12.5 µs Single Word/Byte Program Operation (Notes 2, 5) Byte Typ µs Word 60 Accelerated Single Word/Byte Programming Operation (Note 2) Byte Typ µs Word 54 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tBUSY WE# to RY/BY# Max 90 100 110 120 ns tPOLL Program Valid Before Status Polling (Note 7) Max 4 µs

44 Am29LV320MH/L 26517B4 January 31, 2007

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 17. Program Operation Timings Figure 18. Accelerated Program Timing Diagram

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. Illustration shows device in word mode.

Figure 19. Chip/Sector Erase Operation Timings

46 Am29LV320MH/L 26517B4 January 31, 2007

Figure 20. Data# Polling Timings (During Embedded Algorithms)

48 Am29LV320MH/L 26517B4 January 31, 2007

1. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

Figure 23. Temporary Sector Group Unprotect Timing Diagram

• For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.

Figure 24. Sector Group Protect and Unprotect Timing Diagram

50 Am29LV320MH/L 26517B4 January 31, 2007

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. For 1–16 words/1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter Speed Options JEDEC Std. Description 90R 101, 101R 112, 112R 120, 120R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 240 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 7.5 µs Per Word Typ 15 µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 6.25 µs Per Word Typ 12.5 µs Single Word/Byte Program Operation (Note 2, 5) Byte Typ µs Word 60 Accelerated Single Word/Byte Programming Operation (Note 2) Byte Typ µs Word 54 tWHWH2 tWHWH2 Sector Erase Operation (Note 2, 5) Typ 0.5 sec tRH RESET High Time Before Write (Note 1) Min 50 ns tPOLL Program Valid before Status Polling (Note 7) Max 4 µs

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Illustration shows device in word mode.

52 Am29LV320MH/L 26517B4 January 31, 2007

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, Programming specification assume that all bits are programmed to 00h. 2. Maximum values are measured at VCC = 3.0, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation. 5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence (s) for the program command. See Tables 12 and 13 for further information on command definitions. 8. The device has a minimum erase and pr ogram cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 3.5 sec Excludes 00h programming prior to erasure (Note 6)Chip Erase Time 32 64 sec Single Word/Byte Program Time (Note 3) 60 600 µs Excludes system level overhead (Note 7) Accelerated Single Word/Byte Program Time (Note 3) 54 540 µs Total Write Buffer Program Time (Note 4) 240 1200 µs Effective Write Buffer Program Time (Note 5) Per Byte 7.5 38 µs Per Word 15 75 µs Total Accelerated Write Buffer Program Time (Note 4) 200 1040 µs Effective Accelerated Write Buffer Program Time (Note 5) Per Byte 6.25 33 µs Per Word 12.5 65 µs Chip Program Time 31.5 73 sec Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA

January 31, 2007 26517B4 Am29LV320MH/L 53 DATA SHEET TSOP PIN AND BGA PACKAGE CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Symbol Parameter Desc ription Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 TSOP 6 7.5 pF BGA 4.2 5 pF COUT Output Capacitance V OUT = 0 TSOP 8.5 12 pF BGA 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 TSOP 7.5 9 pF BGA 3.9 4.7 pF Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

54 Am29LV320MH/L 26517B4 January 31, 2007

TS056/TSR056—56-Pin Standard and Reverse Pinout Thin Small Outline Package (TSOP) NOTES: 1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.) 2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). 3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. 4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. 5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15 mm PER SIDE. 6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.

7 THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10 mm AND 0.25 mm FROM THE LEAD TIP. 8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. 9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. 3160\\38.10A MO-142 (B) EC TS/TSR 56 NOM. --- --- 1.00 1.20 0.15 1.05 MAX. --- MIN. 0.95 0.20 0.230.17 0.22 0.270.17 --- 0.160.10 --- 0.210.10 20.00 20.2019.90 14.00 14.1013.90 0.60 0.700.50 3˚ 5˚0˚ --- 0.200.08 18.40 18.5018.30 0.05

0.50 BASIC

E R JEDEC PACKAGE SYMBOL A D c b e L N O

January 31, 2007 26517B4 Am29LV320MH/L 55 DATA SHEET PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package

56 Am29LV320MH/L 26517B4 January 31, 2007

Revision A (May 30, 2002) Initial release as Advance Information data sheet. Revision A+1 (September 3, 2002) Mirrorbit 32 Mbit Device Family Changed the 48-pin TSOP to 40-pin TSOP . Alternate CE# Controlled Erase and Program Operations Added tRH parameter to table. Erase and Program Operations Added tBUSY parameter to table. Figure 16. Program Operation Timings Added 101R, 112R, and 120R to Valid Combinations Table. Added Note 1. Read-Only Operations, Erase and Program Operations, Alternate CE# Controlled Erase and Program Operations, Added 101R, 112R, and 120R to speed options. Revision A+2 (November 15, 2002) Customer Lockable: Secured Silicon Sector NOT Programmed or Protected At the Factory Added second bullet and figure. Product Selector Guide and Read-Only Operations Added 30 ns to the 112R and 120R to Max page ac- cess time and Max OE# Access time. Changed the Chip Enable to Output High Z and Out- put Enable to Output High Z to 16 ns. Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Command Sequence Noted that the Secured Silicon Sector, autoselect, and CFI functions are unavailable when a program or erase operation is in progress. Common Flash Memory Interface (CFI) Changed CFI website address. DC Characteristics Added I LR parameter symbol to table. Removed V IL, VIH, VOL, and VOH and replaced with VIL, VIH, VOL, VOH1 and VOH2. Clarified note #5. Removed note #6. Read-Only Operations Added note #3. Absolute Maximum Rating Changed the Ambient Temperature with Power Ap- plied from –55°C to +125°C to –65°C to +125°C. Revision A+3 (February 14, 2003) Distinctive Characteristics Corrected performance characteristics. AC Characteristics Added Note. Input values in the t WHWH1 and tWHWH2 parameters in the Erase and Program Options table that were previ- ously TBD. Also added notes 5 and 6. Input values in the t WHWH1 and tWHWH2 parameters in the Alternate CE# Controlled Erase and Program Op- tions table that were previously TBD. Also added notes 5 and 6. Erase and Programming Performance Input values into table that were previously TBD. Added note 3 and 4. Revision B (May 7, 2003) Distinctive Characteristics Added typical active read current. Global Converted to full datasheet version. Modified Secured Silicon Sector Flash Memory Region section to in- clude ESN references. DC Characteristics Corrected typical and maximum values for the I CC1, ICC2, and ICC3. Erase and Program Operations and Alternate CE# Controlled Erase and Program Operations Changed Accelerated Effective Write Buffer Program Operation value.

January 31, 2007 26517B4 Am29LV320MH/L 57 DATA SHEET Erase and Programming Performance Input values into table that were previously TBD. Modi- fied notes. Removed Word references. Revision B +1 (February 12, 2004) Customer Lockable: Secured Silicon Sector NOT Programmed or Protected at the Factory Removed second paragraph. Table 10 & Table 11: Command Definitions Replaced the Addr information for both Program/Erase Suspend and Program/Erase Resume from BA to XXX. Erase Suspend/Erase Resume Commands Added note on flash device performance during suspend/erase mode AC Characteristics, Erase and Program Operations Removed Byte information for t WHWH1 parameter. Added tPOLL information and footnote. AC Characteristics Program Operation Timing s, Data# Polling Timings (During Embedded Algorithms, and Alternate CE# Controlled Write (Erase/Program) Operation Timings figures: Updated with t POLL information. AC Characteristics - Alternate CE# Controlled Erase and Program Operations Added tPOLL information and footnote. Erase and Programming Performance Added tPOLL information and footnote. Trademarks Updated. Cover Sheet and Title Page Added notation referencing superseding documenta- tion. Revision B+2 (October 27, 2004) Added Lead-free package options. Revision B+3 (December 14, 2005) Global This product has been retired and is not available for designs. For new and current designs, S29GL032A supersedes Am29LV320MH/L and is the factory-rec- ommended migration path. Please refer to the S29GL032A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Revision B4 (January 31, 2007) Global Changed SecSi Sector to Secured Silicon Sector. AC Characteristics Erase and Program Operations table: Changed t BUSY to a maximum specification. Deleted “t VCS” from tBUSY parameter name. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2001–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.