LTM4676A

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Rev AFor more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management The LT C®3882-1 is a dual, PolyPhase DC/DC synchronous step-down switching regulator controller with PMBus compliant serial interface. It uses a constant frequency, leading-edge modulation, voltage mode architecture for excellent transient response and output regulation. Each PWM channel can produce output voltages from 0.5V to 5.25V using a wide range of 3.3V compatible power stages, including power blocks, DrMOS or discrete FET drivers. Up to four L TC3882-1 devices can operate in parallel for 2-, 3-, 4-, 6- or 8-phase operation. System configuration and monitoring is supported by the L TpowerPlay™ software tool. The L TC3882-1 serial interface can read back input voltage, output voltage and current, temperature and fault status. Most operating parameters can be set via the digital interface or stored in internal EEPROM for use at power up. Switching frequency and phase, output voltage and device address can also be set using external configuration resistors. n PMBus/I2C Compliant Serial Interface – Monitor Voltage, Current, Temperature and Faults – Program Voltage, Soft-Start/Stop, Sequencing, Margining, AVP and UV/OV/OC Limits n 3V ≤ VINSNS ≤ 38V , 0.5V ≤ VOUT ≤ 5.25V n ±0.5% Output Voltage Error n Programmable PWM Frequency or External Clock Synchronization from 250kHz to 1.25MHz n Accurate PolyPhase® Current Sharing n Internal EEPROM with Fault Logging and ECC n IC Supply Range: 3V to 13.2V n Resistor or Inductor DCR Current Sensing n Power Good Output Voltage Monitor n Optional Resistor Programming for Key Parameters n 40-Pin (6mm × 6mm) QFN Package All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245, 5859606, 6144194, 6937178, 7420359 and 7000125.

APPLICATIONS

n High Current Distributed Power Systems n Servers, Network and Storage Equipment n Intelligent Energy Efficient Power Regulation L TC3882-1 SDA RUN1 ISENSE0+ ISENSE0– VSENSE0+ VSENSE0– VSENSE1– RUN0 FAUL T1 FAUL T0 FB0 COMP0 TSNS0 TSNS1 GND

38821 TA01a

IAVG_GND PWM0 VSENSE1+ ISENSE1– ISENSE1+ PWM1 VIN 7V TO 13.2V TO/FROM MCU SCL ALERT COMP1 VCC VINSNS FDMF5820DC FDMF5820DC INDUCTORS: COOPER FP1007R1-R22 SOME DETAILS OMITTED FOR CLARITY PWM VIN VOUT 70A SW GND IAVG1 IAVG0 TO/FROM EXTERNAL DEVICES PGOOD1 SYNC SHARE_CLK PGOOD0 PWM VIN SW GND Load Step Transient Current Sharing (Using FDMF5820DC DrMOS) PWM ENABLE OUTPUT TG/BG CONTROL HW WRITE PROTECT DEDICATED PGOOD OUTPUT DIFFERENTIAL VOUT SENSE L TC3882 • • • VOUT0 Only L TC3882-1 • VOUT0 & VOUT1 50µs/DIV IOUT 10A/DIV IL0, IL1 10A/DIV

38821 TA01b

Rev A For more information www.analog.com TABLE OF CONTENTS T

Description

T T T Operation M P S T O V M O L S P A I O O E R I F In H Po P H H ardwired PWM Response to Temperature Faults .. 25 H E F S F Fa F S S S S P D E P P MOS U F PC O O S T ime-Based Output Sequencing and Ramping ... 51 V U U P P E R I IC Co P MBus Communication and Command Processing ..64 S L TpowerPlay – An Interactive Digital Power GUI ... 65 I D PMBus COMMAND DET A PA P PA W M M G P C On ON MF O M P F

Rev AFor more information www.analog.com TABLE OF CONTENTS MFR MF I V V V V O V V M V M V V V V V O I M I I O M T TO T VO T T TO E MF MF O O S ST U S S S S STA S S MF MF C R M R M R M R R M R M R RE M F V V V I O U M TO M S MF M M T

Rev A For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS 0.3V to 40V S 0.3V to 3.6V 0.3V to 5.5V ASELn, VOUTn_CFG, FREQ_CFG, 0.3V to 2.75V Operating Junction Temperature 40°C to 125°C* 65°C to 150°C* *See Derating EEPROM Retention at Temperature in the Applications Information section for junction temperatures in excess of 125°C. (Note 1) 3940 38 37 36 35 34 33 32 31 11 2012 13 14 15 TOP VIEW GND UJ PACKAGE 40-LEAD (6mm × 6mm) PLASTIC QFN TJMAX = 125°C, θJA = 33°C/W , θJC = 2.5°C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB 16 17 18 19 COMP0 TSNS0 TSNS1 VINSNS IAVG_GND PGOOD0 PWM0 SYNC SCL SDA IAVG1 FB1 COMP1 PGOOD1 PWM1 V CC VDD33 SHARE_CLK V DD25 PHAS_CFG FB0 I AVG0 ISENSE0+ ISENSE0– VSENSE0+ VSENSE0– VSENSE1– VSENSE1+ ISENSE1– ISENSE1+ ALERT FAUL T0 FAUL T1 RUN0 RUN1 ASEL0 ASEL1 V OUT0_CFG VOUT1_CFG FREQ_CFG ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TC3882EUJ-1#PBF L TC3882EUJ-1#TRPBF L TC3882UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C L TC3882IUJ-1#PBF L TC3882IUJ-1#TRPBF L TC3882UJ-1 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. http://www.linear .com/product/L TC3882-1#orderinfo

Rev AFor more information www.analog.com

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IC Supply VCC VCC Voltage Range VDD33 = Internal LDO 4.5 13.8 V VDD33_EXT VDD33 Voltage Range VCC = VDD33 (Note 6) l 3 3.6 V VUVLO Undervoltage Lockout Threshold V DD33 Rising Hysteresis l 3 V mV IQ IC Operating Current 32 mA tINIT Controller Initialization Time Delay from RESTORE_USER_ALL, MFR_RESET or VDD33 > VUVLO Until TON_DELAY Can Begin 35 ms VDD33 Linear Regulator VDD33 VDD33 Regulator Output Voltage V CC ≥ 4.5V 3.2 3.3 3.4 V IDD33 VDD33 Current Limit VDD33 = 2.8V VDD33 = 0V mA mA V DD25 Linear Regulator VDD25 VDD25 Regulator Output Voltage 2.25 2.5 2.75 V IDD25 VDD25 Current Limit 95 mA PWM Control Loops VINSNS V IN Sense Voltage Range 3 38 V RVINSNS VINSNS Input Resistance 278 kΩ VOUT_R0 Range 0 Maximum VOUT Range 0 Set Point Error (Note 7) Range 0 Set Point Resolution 0.6V ≤ V OUT ≤ 5V 0.6V ≤ VOUT ≤ 5V l –0.5 5.25 ±0.2 1.375 0.5 V mV V OUT_R1 Range 1 Maximum VOUT Range 1 Set Point Error (Note 7) Range 1 Set Point Resolution 0.6V ≤ V OUT ≤ 2.5V 0.6V ≤ VOUT ≤ 2.5V l –0.5 2.65 ±0.2 0.6875 0.5 V mV I VSENSE VSENSE Input Current VSENSE+ = 5.5V VSENSE– = 0V 235 –335 µA µA V LINEREG VCC Line Regulation, No Output Servo 4.5V ≤ V CC ≤ 13.2V (See Test Circuit) –0.02 0.02 %/V AVP AVP ∆VOUT AVP = 10%, VOUT_COMMAND = 1.8V , I SENSE Differential Step 3mV to 12mV with IOUT_OC_WARN_LIMIT = 15mV l –118 –108 –96 mV AV(OL) Error Amplifier Open-Loop Voltage Gain 87 dB SR Error Amplifier Slew Rate 9.5 V/µs f0dB Error Amplifier Bandwidth (Note 12) 30 MHz ICOMP Error Amplifier Output Current Sourcing Sinking –2.6 mA mA R VSFB Resistance Between VSENSE+ and FB Range 0 Range 1 l l kΩ kΩ V ISENSE ISENSE Differential Input Range ±70 mV IISENSE ISENSE± Input Current 0V ≤ VPIN ≤ 5.5V –1 ±0.1 1 µA IAVG_VOS IAVG Current Sense Offset Referred to ISENSE Inputs l –600 ±175 650 µV µV VSIOS Slave Current Sharing Offset Referred to ISENSE Inputs l –800 ±300 700 µV µV fSYNC SYNC Frequency Error 250kHz ≤ fSYNC ≤ 1.25MHz l –10 10 % The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V , VSENSE0+ = VSENSE1+ = 1.8V , VSENSE0– = VSENSE1– = IAVG_GND = GND = 0V , fSYNC = 500kHz (externally driven) unless otherwise specified.

Rev A For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Voltage Supervisor VON_TOL Input ON/OFF Threshold Error 15V ≤ VIN_ON ≤ 35V l –2 2 % NVON Input ON/OFF Threshold Resolution 143 mV Output Voltage Supervisors VUVOV_R0 Range 0 Maximum Threshold Range 0 Error Range 0 Threshold Resolution Range 0 Threshold Hysteresis 2V ≤ V OUT ≤ 5V (Falling for UV and Rising for OV) l 5.5 V mV mV V UVOV_R1 Range 1 Maximum Threshold Range 1 Error Range 1 Threshold Resolution Range 1 Threshold Hysteresis 1V ≤ V OUT ≤ 2.5V (Falling for UV and Rising for OV) l 2.75 5.5 V mV mV Output Current Supervisors V ILIM_TOL Output Current Limit Tolerance I SENSE+ – ISENSE– 15mV < ISENSE+ – ISENSE– ≤ 30mV 30mV < ISENSE+ – ISENSE– ≤ 50mV 50mV < ISENSE+ – ISENSE– ≤ 70mV l l l –1.7 –2.5 –5.2 1.7 2.5 5.2 mV mV mV N lLIM ISENSE+ – ISENSE– Threshold Resolution 1LSB 0.4 mV ADC Readback Telemetry (Note 8) NVIN VINSNS Readback Resolution (Note 9) 10 Bits VIN_TUE VINSNS Total Unadjusted Readback Error 4.5V ≤ VINSNS ≤ 38V l 0.5 NDC PWM Duty Cycle Resolution (Note 9) 10 Bits DCTUE PWM Duty Cycle Total Unadjusted Readback Error PWM Duty Cycle = 12.5% –2 2 % N VOUT VOUT Readback Resolution 244 µV VOUT_TUE VOUT Total Unadjusted Readback Error 0.6V ≤ V OUT ≤ 5.5V , Constant Load l –0.5 ±0.2 0.5 N ISENSE IOUT Readback Resolution LSB Step Size (at ISENSE±) (Note 9) 0mV ≤ |I SENSE+ – ISENSE–| < 16mV 16mV ≤ |ISENSE+ – ISENSE–| < 32mV 32mV ≤ |ISENSE+ – ISENSE–| < 63.9mV 63.9mV ≤ |ISENSE+ – ISENSE–| ≤ 70mV 15.625 31.25 62.5 125 Bits µV µV µV µV ISENSE_TUE IOUT Total Unadjusted Readback Error |I SENSE+ – ISENSE–| ≥ 6mV , 0V ≤ VOUT ≤ 5.5V l –1 1 % ISENSE_OS IOUT Zero-Code Offset Voltage ±32 µV NTEMP Temperature Resolution 0.25 °C TEXT_TUE External Temperature Total Unadjusted Readback Error TSNS0, TSNS1 ≤ 1.85V (Note 10) MFR_PWM_MODE_L TC3882-1[6] = 0 MFR_PWM_MODE_L TC3882-1[6] = 1 l l T INT_TUE Internal Temperature Total Unadjusted Readback Error Internal Diode (Note 10) ±1 °C t CONVERT Update Rate (Note 11) 90 ms Internal EEPROM (Notes 4, 6) Endurance Number of Write Operations 0°C ≤ TJ ≤ 85°C During All Write Operations 10,000 Cycles Retention Stored Data Retention TJ ≤ 125°C 10 Years Mass Write Time STORE_USER_ALL Execution Duration 0°C ≤ T J ≤ 85°C During All Write Operations 0.2 2 s The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V , VSENSE0+ = VSENSE1+ = 1.8V , VSENSE0– = VSENSE1– = IAVG_GND = GND = 0V , fSYNC = 500kHz (externally driven) unless otherwise specified.

Rev AFor more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Inputs (SCL, SDA, RUNn, FAUL Tn, SYNC, SHARE_CLOCK) VIH Input High Voltage SCL, SDA, RUN0, RUN1, FAUL T0, FAUL T1 SYNC, SHARE_CLK l l 1.35 1.8 V V VIL Input Low Voltage SCL, SDA, RUN0, RUN1, FAUL T0, FAUL T1 SYNC, SHARE_CLK l l 0.8 0.6 V V V HYST Input Hysteresis SCL, SDA 80 mV CIN Input Capacitance SCL, SDA, RUN0, RUN1, FAUL T0, FAUL T1, SYNC, SHARE_CLK (Note 12) 10 pF t FIL T Input Digital Filter Delay FAUL T0, FAUL T1 RUN0, RUN1 µs µs Digital Outputs (SCL, SDA, RUNn, FAUL Tn, SYNC, SHARE_CLOCK, ALERT, PWMn, PGOODn) VOL Output Low Voltage ISINK = 3mA; SDA, SCL, RUN0, RUN1, FAUL T0, FAUL T1, SYNC, SHARE_CLK, ALERT, ISINK = 2mA; PWMn, PGOODn l l 0.2 0.4 0.3 V V VOH PWMn Output High Voltage ISOURCE = 2mA l 2.7 V ILKG Output Leakage Current 0V ≤ PWM0, PWM1, PGOOD0, PGOOD1 ≤ VDD33 0V ≤ FAUL T0, FAUL T1, SYNC, SHARE_CLK ≤ 3.6V 0V ≤ RUN0, RUN1 ≤ 5.5V 0V ≤ SCL, SDA, ALERT ≤ 5.5V l µA µA µA t RO PWMn Output Rise Time CLOAD = 30pF , 10% to 90% 5 ns tFO PWMn Output Fall Time CLOAD = 30pF , 90% to 10% 4 ns Serial Bus Timing fSMB Serial Bus Operating Frequency l 10 400 kHz tBUF Bus Free Time Between Stop and Start l 1.3 µs tHD,STA Hold Time After (Repeated) Start Condition. After This Period, the First Clock Is Generated l 0.6 µs tSU,STA Repeated Start Condition Setup Time l 0.6 µs tSU,STO Stop Condition Setup Time l 0.6 µs tHD,DAT Data Hold Time: Receiving Data T ransmitting Data l l 0.3 0.9 ns µs t SU,DAT Input Data Setup Time l 100 ns tTIMEOUT Clock Low Timeout l 25 35 ms tLOW Serial Clock Low Period l 1.3 10000 µs tHIGH Serial Clock High Period l 0.6 µs The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V , VSENSE0+ = VSENSE1+ = 1.8V , VSENSE0– = VSENSE1– = IAVG_GND = GND = 0V , fSYNC = 500kHz (externally driven) unless otherwise specified.

Rev A For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TC3882-1 is tested under pulsed load conditions such that T J ≈ TA. The L TC3882-1E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L TC3882-1I is guaranteed over the full –40°C to 125°C operating junction temperature range. Junction temperature T J is calculated in °C from the ambient temperature TA and power dissipation PD according to the formula: TJ = TA + (PD • θJA) where θJA is the package thermal impedance. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Refer to the Applications Information section. Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Note 4: EEPROM endurance, retention and mass write times are guaranteed by design, characterization and correlation with statistical process controls. Minimum retention applies only for devices cycled less than the minimum endurance specification. EEPROM read commands (e.g. RESTORE_USER_ALL) are valid over the entire specified operating junction temperature range. Note 5: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND unless otherwise specified. Note 6: Minimum EEPROM endurance, retention and mass write time specifications apply when writing data with 3.15V ≤ V DD33 ≤ 3.45V . EEPROM read commands are valid over the entire specified VDD33 operating range. Note 7: Specified VOUT error with AVP = 0% requires servo mode to be set with MFR_PWM_MODE_L TC3882-1 command bit 6. Performance is guaranteed by testing the L TC3882-1 in a feedback loop that servos VOUT to a specified value. Note 8: ADC tested with PWMs disabled. Comparable capability demonstrated by in-circuit evaluations. Total Unadjusted Error includes all gain and linearity errors, as well as offsets. Note 9: Internal 32-bit calculations using 16-bit ADC results are limited to 10-bit resolution by PMBus Linear 11-bit data format. Note 10: Limits guaranteed by TSNS voltage and current measurements during test, including ADC readback. Note 11: Data conversion is done in round robin fashion. All inputs signals are continuously scanned in sequence resulting in a typical conversion latency of 90ms. Note 12: Guaranteed by design. Note 13: Do not apply a voltage or current source directly to these pins. They should only be connected to passive RC loads, otherwise permanent damage may occur . Note 14: Do not apply a voltage source to this pin unless shorted to V CC. See Electrical Characteristics for applicable limits beyond which permanent damage may occur .

Rev AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current (1-Phase Using D12S1R880A Power Block) Typical L TC3882-1 Output Voltage Distribution at 0°C Efficiency and Loss vs Load (2-Phase Using FDMF5820DC DRMOS) L TC3882-1 1.0V Regulated Output vs Temperature Efficiency vs Load Current (3-Phase Using D12S1R845A Power Block) Typical L TC3882-1 Output Voltage Distribution at 105°C LOAD CURRENT (A) EFFICIENCY (%) 10 20 30

38821 G04

3.3V 2.5V 1.8V 1.5V 1.2V 1.0V VIN = 12V LOAD CURRENT (A) EFFICIENCY (%) 4020 60

38821 G05

VIN = 12V VOUT = 1.5V Typical Distribution of Slave IOUT Offset (Not Including DCR Mismatch) Typical Distribution of Slave I OUT Offset (Not Including DCR Mismatch) Typical Distribution of Slave I OUT Offset (Not Including DCR Mismatch) NUMBER OF ICs 4000 3500 2500 1500 500 3000 2000 1000

38821 G06

CH1 ISENSE OFFSET TO IDEAL (µV) –400 400 300 200 100–300–200–100 0

9595 UNITS

T A = –40°C TJ = –22°C CHO MASTER NUMBER OF ICs 3500 2500 1500 500 3000 2000 1000

38821 G07

CH1 ISENSE OFFSET TO IDEAL (µV) –400 400 300 200 100–300–200–100 0

8593 UNITS

T J = 38°C CHO MASTER NUMBER OF ICs 4500 2500 1500 500 4000 3500 3000 2000 1000

38821 G08

CH1 ISENSE OFFSET TO IDEAL (µV) –300 500 400 300 200 100–200–100 0

11783 UNITS

T J = 121°C CHO MASTER LOAD CURRENT (A) EFFICIENCY (%) POWERLOSS (W) 20 10 30

38821 G03

VIN = 12V VOUT = 1V SYNC = 500kHz TA (°C) VOUT (V) 1.001 1.0005 0.9995 1.0 0.999 0.9985

38821 G01

VIN = 12V VOUT_COMMAND = 1.0V DIGITAL SERVO ENGAGED I OUT = 6.5A NUMBER OF CHANNELS 1000 900 700 500 300 200 100 800 600 400

38821 G01a

VOUT ERROR (mV)

1094 UNITS

VOUT_COMMAND = 1.0V DIGITAL SERVO ENGAGED

1078 UNITS

VOUT_COMMAND = 1.0V DIGITAL SERVO ENGAGED VOUT ERROR (mV) –2.5 NUMBER OF CHANNELS 1200 1000 600 200 800 400 0.5 1 1.5 2

38821 G02

2.50–2 –1 –0.5–1.5

Rev A For more information www.analog.com Efficiency and Power Loss vs Input Voltage (1-Phase Using L TC4449) 3-Phase T ransient Response (Using D12S1R860A Power Block) 1-Phase Single Cycle Response (Using D12S1R860A Power Block with C OUT = 6 × 100µF X5R 1210) TYPICAL PERFORMANCE CHARACTERISTICS 3+1 Channel Crosstalk (Using D12S1R845A Power Blocks) Load Step T ransient Response Using AVP Line Step T ransient Response (1-phase Using L TC4449) VIN (V) EFFICIENCY (%) 100 POWERLOSS (W) 3.0 2.0 1.0 2.5 1.5 0.5 2010 2515

38821 G12

VO = 1.8V POWER FET : BSC050N04LS G SYNC FET : BSC010N04LS VOUT0 (1-PHASE) 20mV/DIV VOUT1 (3-PHASE) 20mV/DIV IOUT1 10A/DIV 100µs/DIV

38821 G15

25% LOAD STEP VOUT 50mV/DIV IO 10A/DIV 200µs/DIV

38821 G16

1.8V 200µs/DIV

38821 G17

100µs/DIV VOUT (10mV/DIV) IOUT (10A/DIV)

38821 G13

VOUT = 0.9V/90A VIN = 12V SYNC = 500kHz L = 210nH 25mVP-P 2µs/DIV IOUT (10A/DIV) VSW (10V/DIV) VOUT (20mV/DIV)

38821 G14

VOUT = 1V/25A VIN = 12V SYNC = 1MHz L = 210nH 3-Phase DC Output Current Sharing (Using D12S1R845A Power Block Load Step T ransient Current Sharing (Using FDMF6707B DrMOS) Load Dump T ransient Current Sharing (Using FDMF6707B DrMOS) TOTAL RAIL CURRENT (A) PHASE CURRENT (A) 60 70

38821 G09

IL1, IL2 10A/DIV VOUT 20mV/DIV IOUT 20A/DIV 5µs/DIVVOUT = 1V VIN = 12V SYNC = 500kHz L = 320nH

38821 G10

IL1, IL2 10A/DIV VOUT 20mV/DIV IOUT 20A/DIV 5µs/DIVVOUT = 1V VIN = 12V SYNC = 500kHz L = 320nH

38821 G11

Rev AFor more information www.analog.com Soft-Start Ramp Start-Up Into a Prebiased Load Soft-Off Ramp TYPICAL PERFORMANCE CHARACTERISTICS Output Overvoltage Threshold Error vs Temperature Output Overcurrent Threshold Error vs Temperature PWM Frequency vs Temperature TEMPERATURE (°C) –40 VOUT OV THRESHOLD ERROR (%) 0.10 0.05 –0.10 –0.05 –0.15 60 80

38821 G21

120 10020 40–20 0 VOUT_OV_FAUL T_LIMIT = 2V VOUT RANGE = 1 OUTPUT OC THRESHOLD ERROR (%) 1.2 0.8 0.4 1.0 0.6 0.2 –0.2 –0.4

38821 G22

TEMPERATURE (°C) –40 60 80 120 10020 40–20 0 PWM FREQUENCY (kHz) 500.2 500.1 499.9 499.7 500.0 499.8 499.6 499.5

38821 G23

TEMPERATURE (°C) –40 60 80 12010020 40–20 0 FREQUENCY_SWITCH = 500kHz RUN 2V/DIV VOUT 1V/DIV 5ms/DIV TOFF_DELAY = 10ms TOFF_FALL = 5ms

38821 G20

0.5V/DIV 1ms/DIV

38821 G18

IL1, IL2 10A/DIV VIN = 12V VOUT 0.5V/DIV 1ms/DIV

38821 G19

IL1, IL2 10A/DIV VIN = 12V VOUT_COMMAND INLRegulated Output vs Temperature VOUT_COMMAND DNL VOUT (V) 0.3 INL (LSB) 1.5 1.0 0.5 –0.5 –1.0 4.3 5.1 VOUT (V) 0.3 DNL (LSB) 1.0 0.8 0.4 –0.4 0.6 0.2 –0.2 –0.6 –0.8 4.3 5.1 TEMPERATURE (°C) –40 VOUT (V) 1.8000 1.7995 1.7985 1.7975 1.7990 1.7980 1.7970 60 80 120 10020 40–20 0 VOUT_COMMAND = 1.8V DIGITAL SERVO OFF

Rev A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS VIN(SNS) ADC TUE VOUT ADC TUE IOUT ADC TUE VINSNS (V) MEASUREMENT ERROR (mV) 30 35

38821 G24

VOUT (V) 0.5 MEASUREMENT ERROR (mV) 0.40 0.30 0.20 0.10 –0.10 –0.20 –0.30 –0.40 4.5

38821 G25

1.5 2.5 3.5 5.541 2 3 5 OUTPUT CURRENT (A) MEASUREMENT ERROR (mA)

38821 G26

SHARE_CLK Frequency vs Temperature IC Operating Current vs Temperature ACTUAL TEMPERATURE (°C) –45 –1.0 MEASUREMENT ERROR (°C) –0.8 –0.4 –0.2 1.0 0.4 –5 35 55

38821 G27

–0.6 0.6 0.8 0.2 –25 15 75 95 115 TEMPERATURE (°C) –50 SHARE_CLK FREQUENCY (kHz) 100 105 110 –30 –10 10 30

38821 G28

ICC OPERATING CURRENT (mA) 31.0 30.8 30.4 30.0 30.6 30.2 29.8 29.4 29.6

38821 G29

TEMPERATURE (°C) –40 60 80 12010020 40–20 0 VCC = 14V

Rev AFor more information www.analog.com PIN FUNCTIONS COMP0/COMP1 (Pin 1/Pin 28): Error Amplifier Outputs. PWM duty cycle increases with this control voltage. These are true low impedance outputs and cannot be directly connected together when active. For PolyPhase operation, wiring FB to V DD33 will three-state the error amplifier output of that channel, making it a slave. PolyPhase control is then implemented in part by connecting all slave COMP pins together to one master error amplifier output. TSNS0/TSNS1 (Pin 2/Pin 3): External Temperature Sense Inputs. The L TC3882-1 supports two methods of calcula- tion of external temperature based on forward-biased P/N junctions between these pins and GND. VINSNS (Pin 4): V IN Supply Sense. Connect to the V IN power supply to provide line feedforward compensation. A change in V IN immediately modulates the input to the PWM comparator and inversely changes the pulse width to provide excellent transient line regulation and fixed modulator voltage gain. An external lowpass filter can be added to this pin to prevent noisy signals from affecting the loop gain. I AVG_GND (Pin 5): I AVG Ground Reference. The same IAVG_GND should be shared between all channels of a PolyPhase rail and connected to system ground at a single point. IAVG_GND may be wired directly to GND on ICs that do not share phases with other chips. PGOOD/PGOOD1 (Pin 6/Pin 27): Power Good Indicator Open-Drain Outputs. These outputs are driven low through a 30µs filter when the respective channel output is below its programmed UV fault limit or above its programmed OV fault limit. If used, a pull-up resistor is required in the application. Operating voltage range is GND to V DD33. PWM0/PWM1 (Pin 7/Pin 26): PWM Three-State Control Outputs. These pins provide single-wire PWM switching control for each channel to an external gate driver , DrMOS or power block. Operating voltage range is GND to V DD33. SYNC (Pin 8): External Clock Synchronization Input and Open-Drain Output. If desired, an external clock can be applied to this pin to synchronize the internal PWM chan- nels. If the L TC3882-1 is configured as a clock master , this pin will also pull to ground at the selected PWM switching frequency with a 125ns pulse width. A pull-up resistor to 3.3V is required in the application if SYNC is driven by any L TC3882-1. Minimize the capacitance on this line to ensure its time constant is fast enough for the application. SCL (Pin 9): Serial Bus Clock Input. A pull-up resistor to 3.3V is required in the application. SDA (Pin 10): Serial Bus Data Input and Output. A pull-up resistor to 3.3V is required in the application. ALERT (Pin 11): Open-Drain Status Output. This pin may be connected to the system SMBALERT wire-AND inter- rupt signal and should be left open if not used. If used, a pull-up resistor is required in the application. Operating voltage range is GND to V DD33. FAUL T0/FAUL T1 (Pin 12/Pin 13): Programmable Digital Inputs and Open-Drain Outputs for Fault Sharing. Used for channel-to-channel fault communication and propaga- tion. These pins should be left open if not used. If used, a pull-up resistor to 3.3V is required in the application. RUN0/RUN1 (Pin 14/Pin 15): Run Control Inputs and Open-Drain Outputs. A voltage above 2V is required on these pins to enable the respective PWM channel. The L TC3882-1 will drive these pins low under certain reset/ restart conditions regardless of any PMBus command settings. A pull-up resistor to 3.3V is required in the ap - plication. ASEL0/ASEL1 (Pin 16/Pin 17): Serial Bus Address Select Pins. Connect optional 1% resistor dividers between V DD25 and GND to these pins to select the serial bus interface address. Refer to the Applications Information section for more detail. V OUT0_CFG/VOUT1_CFG (Pin 18/Pin 19): Output Voltage Configuration Pins. Connect optional 1% resistor divid- ers between V DD25 and GND to these pins to select the output voltage for each channel. Refer to the Applications Information section for more detail. FREQ_CFG (Pin 20): Frequency Configuration Pin. Connect an optional 1% resistor divider between V DD25 and GND to this pin to configure PWM switching frequency. Refer to the Applications Information section for more detail.

Rev A For more information www.analog.com PIN FUNCTIONS PHAS_CFG (Pin 21): Phase Configuration Pin. Connect an optional 1% resistor divider between VDD25 and GND to this pin to configure the phase of each PWM channel relative to SYNC. Refer to the Applications Information section for more detail. V DD25 (Pin 22): Internal 2.5V Regulator Output. Bypass this pin to GND with a low ESR 1µF capacitor . Do not load this pin with external current beyond that required for local L TC3882-1 configuration pins, if any. SHARE_CLK (Pin 23): Share Clock Open-Drain Output (bussed). Share Clock, nominally 100kHz, is used to sequence multiple rails in a power system utilizing more than one L TC PSM controller . A pull-up resistor is required in the application. Minimize the capacitance on this line to ensure the time constant is fast enough for the application. Operating voltage range is GND to V DD33. VDD33 (Pin 24): Internal 3.3V Regulator Output. Bypass this pin to GND with a low ESR 2.2µF capacitor . The L TC3882-1 may also be powered from an external 3.3V rail attached to this pin, if also shorted to V CC. Do not overload this pin with external system current. Local pull-up resistors for the L TC3882-1 itself may be powered from V DD33. Refer to the Applications Information section for more detail. VCC (Pin 25): 3.3V Regulator Input. Bypass this pin to GND with a capacitor (0.1µF to 1µF ceramic) in close proximity to the IC. VSENSE0–/VSENSE1– (Pin 35/Pin 34): Negative Output Voltage Sense Inputs. These pins must still be properly connected on slave channels for accurate output current telemetry. V SENSE0+/VSENSE1+ (Pin 36/Pin 33): Positive Output Voltage Sense Inputs. These pins must still be properly connected on slave channels for accurate output current telemetry. I SENSE0–/ISENSE1– (Pin 37/Pin 32): Current Sense Ampli- fier Inputs. The (–) inputs to the amplifiers are normally connected to the low side of a DCR sensing network or output current sense resistor for each phase. I SENSE0+/ISENSE1+ (Pin 38/Pin 31): Current Sense Ampli- fier Inputs. The (+) inputs are normally connected to the high side of an output current sense resistor or the R-C midpoint of a parallel DCR sense circuit. IAVG0/IAVG1 (Pin 39/Pin 30): Average Current Control Pins. A capacitor connected between these pins and I AVG_GND stores a voltage proportional to the average output current of the master channel. PolyPhase control is then imple - mented in part by connecting all slave IAVG pins together to the master I AVG output. This pin should be left open on channels that control single-phase outputs. Operating voltage range is GND to 2.1V . FB0/FB1 (Pin 40/Pin 29): Error Amplifier Inverting Inputs. These pins provide an internally scaled version of the output voltage for use in loop compensation. Refer to the Applications Information section for additional details on compensating the output voltage control loop with external components. GND (Exposed Pad Pin 41): Ground. All small-signal and compensation components should connect to this pad. The exposed pad must be soldered to a suitable PCB copper ground plane for proper electrical operation and to obtain the specified package thermal resistance.

Rev AFor more information www.analog.com BLOCK DIAGRAM 16-BIT ADC PWM1 VSENSE1± ANALOG MUX 3882-1 BD ISENSE1± INTERNAL TEMPERATURE PWM1 VINSNS BIAS AND HOUSEKEEPING 3.3V REGULATOR 2.5V REGULATOR MCU AND CUSTOM LOGIC TSNS1 VSENSE1± ISENSE1± IAVG1 TSNS0 PWM0 VSENSE0± ISENSE0± VINSNS VDD33 VCC PLLSYNC R_CONFIG SHARE_CLK PMBus RAM ROM EEPROM VOL TAGE REFERENCE VREF 12-BIT DAC INTERNAL DATA BUS PWM0 VINSNS ISENSE0± VSENSE0± IAVG0 IAVG_GND 12-BIT DAC PGOOD0 PWM0 PWM1 PGOOD1

Rev A For more information www.analog.com TEST CIRCUIT TIMING DIAGRAM OPERATION SDA SCL tHD(STA) tHD(DAT) tSU(STA) tSU(STO) tSU(DAT) tLOW tHD(SDA) tSP tBUF START CONDITION STOP CONDITION REPEATED START CONDITION START CONDITION tr tf trtf tHIGH 38821 TD (Channel 0 Example) 135 36 40 +DIGITAL L TC3882-1 COMP0FB0VSENSE0+ VR VSENSE0– 1.024V 12-BIT D/A L TC1055 TARGET = VOUT_COMMAND EA 38821 TC Overview The L TC3882-1 is a dual channel/dual phase, constant frequency analog voltage mode controller for DC/DC step- down applications. It features a PMBus compliant digital interface for monitoring and control of important power system parameters. The chip operates from an IC power supply between 3V and 13.2V and is intended for conversion from V IN between 3V and 38V to output voltages between 0.5V and 5.25V . It is designed to be used in a switching architecture with external FET drivers, including higher level integrations such as non-isolated power blocks. Major features include: Digitally Programmable Output Voltage

• Digitally Programmable Output Current Limit
• Digitally Programmable Input Voltage Super visor
• Digitally Programmable Output Voltage Super visors
• Digitally Programmable Switching Frequency
• Digitally Programmable On and Off Delay Times
• Digitally Programmable Soft-Start/Stop

Rev AFor more information www.analog.com OPERATION

• Operating Condition Telemetr y
• Ph ase Locked Loop for Synchronous PolyPhase Opera- tion (2, 3, 4, 6, or 8 phases)
• Fully Differential Load Sense
• Non-Volatile Configuration Memor y with ECC
• Optional External Configuration Resistors for Key Op- erating Parameters
• Optional Time-Base Inter connect for Synchronization Between Multiple Controllers
• Fault Event Data Logging
• Capable of Standalone Operation with Default Factory Configuration
• PMBus Revision

1.2 Compliant Interface up to 400kHz

The PMBus interface provides access to important power management data during system operation including: Average Input Voltage

• Average Output Voltages
• Average Output Currents
• Average PWM Duty Cycles
• Internal L TC3882-1 T emperature
• External Sensed Temperatures
• Warning and Fault Status, Including Input and Output Undervoltage and Overvoltage The L TC3882-1 supports four serial bus addressing schemes to access the individual PWM channels separately or jointly. Fault communication, reporting and system response behavior are fully configurable. T wo fault I/Os are pro - vided (FAUL T0, FAUL T1) that can be controlled indepen - dently. A separate ALERT pin also provides for a maskable SMBALERT#. Fault responses for each channel may be individually programmed, depending on the fault type. PMBus status commands allow fault reporting over the serial bus to identify a specific fault event. Main Control Loop The L TC3882-1 utilizes constant frequency voltage mode control with leading-edge modulation. This provides improved response to a load step increase, especially at larger V IN/VOUT ratios found in the low voltage, high cur- rent solutions demanded by modern digital subsystems. The L TC3882-1 leading-edge modulation ar chitecture does not have a minimum on-time requirement. Minimum duty cycle will be determined by performance limits of the external power stage. The IC is also capable of active voltage positioning (AVP) to afford the smallest output capacitors possible for a given output voltage accuracy over the anticipated full load range. The L TC3882-1 error amplifiers have high bandwidth, low offset and low out - put impedance, allowing the control loop compensation network to be optimized for very high crossover frequen- cies and excellent transient response. The controller also achieves outstanding line transient response by using input feedforward compensation to instantaneously adjust PWM duty cycle and significantly reduce output under/ overshoot during supply voltage changes. This also has the added advantage of making the DC loop gain independent of input voltage. The main PWM control loop used for each channel is illustrated in Figure 1. During normal operation the top MOSFET (power switch) driving choke L1 is commanded off when the clock for that channel resets the RS latch. The power switch is commanded back on when the main PWM comparator VC, sets the RS latch. The error ampli- fier EA output (COMP) controls the PWM duty cycle to match the FB voltage to the EA positive terminal voltage in steady state. A patented circuit adjusts this output for VINSNS line feedfor ward. The positive terminal of the EA is connected to the output of a 12-bit DAC with values ranging from 0V to 1.024V . The DAC value is determined by the resistor configuration pins detailed in application Table 8, by values retrieved from inter- nal EEPROM, or by a combination of PMBus commands to synthesize the desired output voltage. Refer to the following PMBus Command Details section of this document for more information. The L TC3882-1 supports two output ranges. EA can regulate the output voltage to 5.5x the DAC output (Range 0) or 2.75x the DAC output (Range 1).

38821 F01

Figure 1. L TC3882-1 PWM Control Loop Diagram

Rev AFor more information www.analog.com VC discriminates its positive input against an internally generated PWM voltage ramp. The positive input is a com- posite control based on COMP voltage with line feedforward compensation, and current sharing if the channel controls a slave phase. When the ramp falls below this voltage the comparator trips and sets the PWM latch. If load current increases, V SENSE+ and FB will droop slightly with respect to the 12-bit DAC output. This causes the COMP voltage to increase until the average inductor current matches the new load current and the desired output voltage is restored. Programmable comparators I LIM and I REV monitor peak instantaneous forward and reverse inductor current for pulse-by-pulse protection. The top power MOSFET is immediately commanded off if the programmed positive limit is reached, and the bottom MOSFET is immediately commanded off if the negative limit is reached. Repeated peak overcurrent events cause an overcurrent fault to be set. When the top MOSFET is commanded off, the bottom MOSFET is normally commanded on. In continuous con- duction mode (CCM) the bottom MOSFET stays on until comparator VC turns the top MOSFET back on. Otherwise in discontinuous conduction mode (DCM, also known as diode emulation) the bottom MOSFET is commanded off if the I REV comparator detects that the inductor current has decayed to approximately 0A. In any case the next PWM cycle starts when the clock for that channel again clears the RS latch. Power-Up and Initialization The L TC3882-1 is designed to provide stand-alone supply sequencing with controlled turn-on and turn-off functions. It operates from a single IC input supply of 3V to 13.2V while two on-chip linear regulators generate internal 2.5V and 3.3V . If V CC is below 4.5V , the VCC and V DD33 pins must be shorted together and limited to a maximum operating voltage of 3.6V . Controller configuration is reset by the internal UVLO threshold, where V DD33 must be at or above 3V and the internal 2.5V supply must be within about 20% of its regulated value. At that point the internal microcontroller begins initialization. A PMBus RESTORE_USER_ALL or MFR_RESET command forces this same initialization. The L TC3882-1 features an internal RAM built-in self-test (BIST) that runs during initialization. Should RAM BIST fail, the following steps are taken. Device responds only at device address 0x7C and global addresses 0x5A and 0x5B

• A persistent Memory Fault Detected is indicated by ST ATUS_CML
• Internal EEPROM is not accessed
• RUN n and SHARE_CLK are driven low continuously Normal operation can be restored if the RAM BIST sub - sequently passes, for instance as the result of another MFR_RESET command issued to address 0x7C. During initialization all PWM outputs are disabled. The RUNn pins and SHARE_CLK are held low and FAUL Tn pins are high impedance. External configuration resistors are identified and the contents of the onboard EEPROM are read into the controller command memory space. The L TC3882-1 can determine key operating parameters from external configuration resistors according to application Table 8 through Table 11. See the following Resistor Configuration Pins section for more detail. The resistor configuration pins only determine some of the preset values of the controller . The remaining values, retrieved from internal EEPROM, are programmed at the factory or with PMBus commands. If the configuration resistor pins are all open, the L TC3882-1 will use only EEPROM contents to determine all operating parameters. If Ignore Resistor Configuration Pins is set (bit 6 of MFR_CONFIG_ALL_L TC3882-1), the L TC3882-1 will use only its EEPROM contents to determine all operating parameters except device address. Unless both ASEL pins are completely open, the L TC3882-1 will always determine some portion of its device address from the resistors on these pins. See Serial Bus Addressing later in this section. The internal microcontroller typically requires 35ms to complete initialization from VDD33 ≥ 3V . At that point, an internal comparator monitors VINSNS, which must exceed the VIN_ON threshold before output power sequencing can begin (SHARE_CLK released, ready for TON_DELAY). Accurate readback telemetry can then require an additional 90ms for initial round-robin A/D conversions. OPERATION

Rev A For more information www.analog.com OPERATION Soft-Start The RUN pins are released for external control after the part initializes and VINSNS is greater than the VIN_ON threshold. If multiple L TC3882-1 ICs are used in an ap - plication, shared RUN pins are held low until all units initialize and VINSNS exceeds the VIN_ON threshold for all devices. A common SHARE_CLK signal can also ensure all connected devices use the same time reference for initial start-up even if RUN pins cannot be shared due to other design requirements. SHARE_CLK is not released by each IC until the conditions for power sequencing have been fully satisfied. After a channel RUN pin rises above 2V and any specified turn on delay (TON_DELAY) has expired, the L TC3882-1 performs an initial monotonic soft-start ramp on that chan- nel. This is carried out with a digitally controlled ramp of the regulated output voltage from 0V to the commanded voltage set point over the programmed TON_RISE period, allowing inrush current control. During the soft-start ramp, the L TC3882-1 does not initiate PWM operation until the commanded output exceeds the actual rail voltage. This allows the regulator to start up into a pre-biased load even when using gate drivers or power blocks that do not support discontinuous operation. The soft-start feature is disabled by setting the value of TON_RISE to any time less than 0.25ms. Time-Based Output Sequencing The L TC3882-1 supports time-based on and off output sequencing using a shared time reference (SHARE_CLK). Following a valid qualified command to turn on, each output is enabled after waiting its programmed TON_DELAY. This can be used to sequence outputs in a prescribed order that can be preprogrammed as needed without hardware modification. Channel off-sequencing is accomplished in a similar way with the TOFF_DELAY command. Output Ramping Control The L TC3882-1 supports synchronized output on and off ramping control using a shared time reference (SHARE_ CLK). Power rail on and off relationships similar to those of conventional analog tracking functions can be achieved by using programmed delays and TON_RISE and TOFF_FALL times. However , with L TC3882-1 digital control, on and off ramping methods need not be the same, and ramping configurations can be reprogrammed as needed without hardware modification. Programmable fault responses and fault sharing can ensure that any desired time-based output sequencing and ramping control is properly accomplished each time the system powers up or down. Refer to the Applications Information section for various L TC3882-1 hardware and PMBus command configurations needed to fully support synchronization for time-based sequencing and output ramping when using multiple ICs. Voltage-Based Output Sequencing It is also possible to sequence outputs using cascaded voltage events. To do this, the PGOOD status output from one PWM channel can be used to control the RUN pin of a downstream channel. This keeps the downstream channel off unless acceptable output conditions exist on the controlling channel. Output Disable Both PWM channels are disabled any time VINSNS is below the VIN_OFF threshold. The power stages are immediately shut off to stop the transfer of energy to the load(s) as quickly as possible. A PWM channel may also be disabled in response to certain internal fault conditions, an external fault propagated into a FAUL T pin, or loss of SHARE_CLK. In these cases the power stage is immediately shut off to stop the transfer of energy to the load as quickly as possible. Refer to the following Fault Detection and Handling section for ad - ditional details related to fault recovery. Each PWM channel can be disabled with a PMBus OPERA- TION command at any time if enabled by ON_OFF_CONFIG. This will force a controlled turn-off response with defined delay (TOFF_DELA Y) and ramp down rate (TOFF_FALL). The controller will maintain the programmed mode of operation for TOFF_FALL. In DCM, the controller will not draw current from the load and fall time will be set by output capacitance and load current.

Rev AFor more information www.analog.com OPERATION Finally, each PWM channel can be commanded off by pulling the associated RUN pin low. Pulling the RUN pin low can force the channel to perform a controlled turn off or immediately disable the power stage, depending on the programming of the ON_OFF_CONFIG command. Minimum Output Disable Times When a PMBus OPERATION command is used to turn off an L TC3882-1 channel, a minimum output disable time of 120ms is imposed regardless of how quickly the channel is commanded back on. If bit 4 of MFR_CHAN_CONFIG is clear , a PMBus command to turn the channel off also pulses the RUN pin low. Once the RUN pin is pulled low internally or externally, a minimum output disable time (RUN forced low) of TOFF_DELAY + TOFF_FALL + 136ms is enforced. If MFR_RESTART_DELAY is greater than this mandatory minimum, the larger value of MFR_RESTART_DELAY is used. In either case the L TC3882-1 holds its own RUN pin low during the entire disable period. These minimum off times allow a consistent channel restart with coher - ent monitor ADC values and make the L TC3882-1 highly compatible with other L TC PMBus digital power system management products. Output Short Cycle An output short cycle condition is created when a mas - ter channel is commanded back on while waiting for TOFF_DELA Y or TOFF_FALL to expire. Any time this occurs, the L TC3882-1 asserts the Short Cycle bit in ST ATUS_MFR_SPECIFIC. Device response at that point is governed by bits in MFR_CHAN_CONFIG_L TC3882-1 and SMBALERT_MASK. Refer to the detailed descriptions of those commands for additional details. Generally, the L TC3882-1 should be controlled so that short cycle condi- tions are not created during normal operation. Light Load Current Operation The L TC3882-1 has two modes of P WM operation: discon- tinuous conduction mode (DCM) and forced continuous conduction mode (CCM). Mode selection is made with the MFR_PWM_MODE command. In DCM, the inductor current is not allowed to reverse. The reverse current comparator I REV disables the external bottom MOSFET (synchronous rectifier) when the induc- tor current reaches approximately 0A, preventing it from going substantially negative. The external gate driver or power block must have short delays to a high impedance output, relative to the PWM cycle, to support DCM. Efficiency at light loads in CCM is lower than in DCM. Continuous conduction mode exhibits less inter ference with audio circuitry but may result in reverse inductor current, for instance at light loads or under large transient conditions. Switching Frequency and Phase There is a high degree of flexibility for setting the PWM operating frequency of the L TC3882-1. The switching frequency of the PWM can be established with an in - ternal oscillator or an external time base. The internal phase-locked loop (PLL) synchronizes PWM control to this timing reference with proper phase relation, whether the clock is provided internally or externally. The device can also be configured to provide the master clock to other ICs through PMBus command, EEPROM setting, or external configuration resistors as outlined in applica- tion Table 10. For PMbus or EEPROM configuration, the L TC3882-1 is designated as a clock master by clearing bit 4 of MFR_CONFIG_ALL_L TC3882-1. As clock master , the L TC3882-1 will drive its open-drain SYNC pin at the selected rate with a pulse width of 125ns. An external pull-up resistor between SYNC and V DD33 is required in this case. Only one device connected to SYNC should be designated to drive the pin. If more than one L TC3882-1 sharing SYNC is programmed as clock master , just one of the devices is automatically elected to provide the clock. The others disable their SYNC outputs and indicate this with bit 10 of MFR_PADS_L TC3882-1. The L TC3882-1 will automatically accept an external SYNC input, disabling is own SYNC drive if necessary, as long as the external clock frequency is greater than 1/2 of the programmed internal oscillator . Whether configured to drive SYNC or not, the L TC3882-1 can continue PWM operation at the selected frequency (FREQUENCY_SWITCH) using its own internal oscillator , if an external clock signal is subsequently lost. The MFR_PWM_CONFIG_L TC3882-1 command can be used to configure the phase of each channel. Desired phase

Rev A For more information www.analog.com OPERATION can also be set from EEPROM or external configuration resistors as outlined in Table 10. Phase designates the relationship between the falling edge of SYNC and the internal clock edge that resets the PWM latch. That reset turns off the top power switch, producing a PWM falling edge. Additional small propagation delays to the PWM control pins will apply. The phase relationships and frequency are independent of each other , providing numerous application options. Multiple L TC3882-1 ICs can be synchronized to realize a PolyPhase array. In this case the phases should be sepa- rated by 360/n degrees, where n is the number of phases driving the output voltage rail. PolyPhase Load Sharing Multiple LTC3882-1 ICs can be combined to provide a bal- anced load-share solution by configuring the necessar y pins. The SHARE_CLK and SYNC pins of all load-sharing ch annels should be bussed together . Connecting the SYNC pins synchronizes the PWM controllers with each other . Bussing the SHARE_CLK pins together allows the phases to start synchronously. Refer to the discussion in the previous Power-Up and Initialization section. The last device to see all start-up conditions satisfied controls the initiation of power sequencing for all phases. Due to the low output impedance of the L TC3882-1 error amplifiers, PolyPhase applications should use the error amplifier of only one phase as the master . The FB pins of each slave channel must be wired to V DD33, and the COMP pins of each slave phase must be connected to the master error amplifier COMP output. This disables the slave error amplifiers and provides a single point of voltage control and loop stabilization for the PolyPhase output rail. For PolyPhase load sharing the L TC3882-1 also incorporates an auxiliary current sharing loop. Referring back to Figure 1, the instantaneous current of each slave phase is sensed by current amplifier CA and compared to the I AVG pin. The IAVG and IAVG_GND pins of each phase are wired together , and a small capacitor (50pF to 200pF) between IAVG and IAVG_GND stores a voltage corresponding to the average master phase output current. The difference in this aver- age and the instantaneous phase current is integrated. The output of integrator S of each slave phase is then proportionally summed with the master error amplifier COMP output to adjust the duty cycle and balance the current contribution of that phase. Additional hardware configuration and digital programming requirements apply in PolyPhase systems. Refer to the Applications Informa- tion section for complete details on building PolyPhase rails with the LTC3882-1. Active V oltage Positioning Load slope is programmable in the L TC3882-1 via the MFR_VOUT_AVP PMBus command. The inductor cur - rent measured at the I SENSE pins is converted to a voltage which is then subtracted from the voltage reference at the positive input of the error amplifier . The final load slope is defined by the inductor current sense element and the bits set in the MFR_VOUT_AVP PMBus command. Setting MFR_VOUT_AVP to a value greater than 0.0% automatically disables output servo mode for that channel. Input Supply Monitoring The input supply voltage is sensed by the L TC3882-1 at the VINSNS pin. Undervoltage, overvoltage, valid on and off levels can be programmed for V IN. Refer to the following PMBus Command Details section for more information on programming the input supply thresholds. In addition, the telemetry ADC monitors the VINSNS voltage relative to GND. Conversion results are returned by the READ_VIN PMBus command. Output Voltage Sensing and Monitoring Both PWM channels allow remote, differential sensing of the load voltage with V SENSE pins. The channel 1 output sense pin VSENSE1– is internally shorted to GND (the exposed pad). The telemetry ADC is fully differential and makes its measurements of the output voltages of channels 0 and 1 at V SENSE0± and VSENSE1±, respectively. Conversion results are returned by the READ_VOUT PMBus command. Output Current Sensing and Monitoring Both channels allow differential sensing of the inductor current using either the inductor DCR or a resistor in series with the inductor across the I SENSE pins. When the ISENSE pins for a channel are multiplexed to the differential inputs

of approximately ±128mV and a noise floor of 7μV RMS. output current using inductor DCR or discrete resistors. diode-connected PNP transistor such as the MMBT3906. on-chip diode with a ∆VBE measurement and calculation. ASEL1, VOUT0_CFG, VOUT1_CFG, FREQ_CFG, and PHAS_CFG. by commands from the digital interface. Table 11. These pins can be used to select the entire be retrieved from the MFR_ADDRESS value in EEPROM. set to either of these values. Table 8. These pins select the output voltages for the

• VOUT_OV_FAUL T_LIMIT : +10%
• VOUT_OV_WARN_LIMIT : +7.5%
• VOUT_MAX: +7.5%
• VOUT_MARGIN_HIGH: +5%
• VOUT_MARGIN_LOW: –5%
• VOUT_UV_WARN_LIMIT : –6.5%
• VOUT_UV_FAUL T_LIMIT : –7% The FREQ_CFG pin settings are described in application

Table 9. This pin selects the switching frequency of the open, shorted to GND or ignored by EEPROM setting.

Rev A For more information www.analog.com OPERATION The PHAS_CFG pin settings are described in Table 10. This pin selects the phase relationships between the two channels and the selected clock source. Internal EEPROM with CRC and ECC The L TC3882-1 contains internal EEPROM with Error Correcting Coding (ECC) to store user configuration set- tings and fault log information. EEPROM endurance and retention for user space and fault log pages are specified in the Absolute Maximum Ratings and Electrical Charac- teristics table. The integrity of the entire onboard EEPROM is checked with a CRC calculation each time its data is to be read, such as after a power -on reset or execution of a RESTORE_USER_ ALL command. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC command is set, and the ALERT and RUN pins pulled low (PWM channels off). At that point the device will only respond at special address 0x7C, which is activated only after an invalid CRC has been detected. The chip will also respond at the global addresses 0x5A and 0x5B, but use of these addresses when attempting to recover from a CRC issue is not recommended. All power supply rails associated with either PWM channel of a device reporting an invalid CRC should remain disabled until the issue is resolved. L TC recommends that the EEPROM not be written when die temperature is greater than 85°C. If internal die tem- perature exceeds 130°C, all EEPROM operations except RESTORE_USER_ALL and MFR_RESET are disabled. Full EEPROM operation is not re-enabled until die temperature falls below 125°C. Refer to the Applications Information section for equations to predict retention degradation due to elevated operating temperatures. See the Applications Information section or contact the factory for details on efficient in-system EEPROM program- ming, including bulk EEPROM programming, which the LTC3882-1 also supports. Fault Detection A variety of fault and warning detection, reporting and handling mechanisms are provided by the L TC3882-1. Fault or warning detection capabilities include:

• Input Under/Overvoltage
• Output Under/Overvoltage
• Output Overcurrent (Peak and Average)
• Internal and External Overtemperature and External Undertemperature
• CML Fault (Communication, Memory , or Logic)
• External Fault Detection via Bidirectional F AUL T Pins Reporting is covered in following sections on status com- mands (registers) and ALERT pin function. Fault handling mechanisms include hardwired, low-level PWM safety responses that always occur , and higher-level program- mable event management. Both types are covered in the following sections. Input Supply Faults Input undervoltage and over voltage limits are determined from multiplexed monitor ADC conversions. Therefore the input UV/OV response is naturally deglitched by the 90ms typical conversion cycle of the ADC. There is no hardwired low-level PWM response for any input supply fault. Hardwired PWM Response to V OUT Faults VOUT undervoltage (UV) and overvoltage (OV) faults are detected by supervisor comparators. The OV and UV fault limits can be set in three ways:
• As a Percentage of VOUT if Using the Resistor Configu- ration Pins
• From Stored EEPROM Values
• By PMBus Command The output overvoltage comparator guards against transient overshoots as well as long term overvoltages at the output. When an output OV fault is detected the top MOSFET for that channel is commanded off and the bottom MOSFET is commanded on until the overvoltage condition is cleared

Rev AFor more information www.analog.com OPERATION or for PWM control protocol 0, reverse overcurrent is detected. See IOUT faults below. UV faults and warnings are masked if the channel has been commanded off or until all of the following criteria are achieved. TON_DELAY Has Expired

• TON_RISE Ramp Has Completed
• TON_MAX_FAUL T_LIMIT Has Been Reached
• IOUT_OC_FAUL T_LIMIT Has Not Been Reached
• TOFF_FALL Is Not in Progress Output UV warnings are determined from multiplexed monitor ADC conversions. The L TC3882-1 has no hard - wired PWM response for output UV faults or warnings. Power Good Indication (Master) An LTC3882-1 master phase indicates Power Good on its PGOOD pin and in PMBus commands ST ATUS_WORD (paged) and MFR_PADS_L TC3882-1 based on pro - grammed UV and OV fault limits. Power Good is indicated on a master phase as long as it is enabled to run and VOUT is between the UV and OV fault limits. If a master chan - nel is off for any reason, its PGOOD pin is driven low and Power Not Good is indicated in the status commands. Power Good Indication (Slave) As long as they are enabled, slave phases indicate Power Good on PGOOD and in PMBus status commands, unless a master error amplifier (EA) fault is detected. An EA fault indicates the bussed COMP voltage appears to be too high. When a slave detects an EA fault, its output is immedi - dately disabled and OV is indicated (see Figure 2). Any valid higher-level OV fault response and propagation may be set for a slave channel to handle a detected EA fault. If the OV fault response is set to ignore, the slave output is re-enabled when the EA/COMP condition clears. A slave indicates Power Not Good with PMBus status com- mands during an EA fault, but its PGOOD pin remains high impedance. If a slave phase is off for any other reason, its PGOOD pin is also driven low. Hardwired P WM Response to IOUT Faults The L TC3882-1 measures average IOUT from the voltage across the ISENSE pins, taking into account the sense resistor or DCR value and its associated temperature coefficient. Both are provided by PMBus command or EEPROM values. An output overcurrent (OC) fault condition is detected by a supervisor comparator for each PWM output when the sensed instantaneous current for that channel reaches its maximum allowed value. Refer to the IOUT_OC_ FAUL T_LIMIT PMBus command for details. When an OC fault is detected the controller immediately disables the top FET , and the bottom FET is normally commanded on for the remainder of that PWM cycle. If programmed to operate in CCM, the L TC3882-1 also uses the negative of IOUT_OC_FAUL T_LIMIT to detect a reverse overcurrent (ROC) fault. When an ROC fault occurs the controller immediately disables both top and bottom FETs, unless PWM output protocol 1 is selected with MFR_PWM_MODE_L TC3882-1. OC and ROC faults are both handled according to the IOUT_OC_FAUL T_RESPONSE for that channel. Either hardware response can result in current-limited operation using pulse truncation or skipping. Because the L TC3882-1 uses leading edge modulation, this will cause a shift in average phase toward 0° on the faulted channel and an increase in input ripple current Output OC warnings are determined from multiplexed monitor ADC conversions. The L TC3882-1 has no hardwired PWM response if an output OC warning occurs. Hardwired PWM Response to Temperature Faults An internal temperature sensor measured by the moni - tor ADC protects against EEPROM and other IC damage. When die temperature rises above 130°C, the LTC3882-1 will NACK any EEPROM-related command except RE - STORE_USER_ALL and MFR_RESET and issue a CML fault for Invalid/Unsupported Command. Normal EEPROM access is re-enabled when die temperature drops below 125°C. Above 160°C, the part shuts down all P WM outputs until die temperature is below 150°C. Internal temperature fault limits cannot be adjusted. Writing to the EEPROM above a die temperature of 85°C is strongly discouraged.

Rev A For more information www.analog.com OPERATION Refer to the Absolute Maximum Ratings for other important temperature limitations on internal EEPROM use. External temperature sensors may also be monitored by the onboard ADC. There is no hardwired PWM response for sensed external temperature faults or warnings. Hardwired PWM Response to Timing Faults There is no hardwired PWM response to any timing faults. TON_MAX_FAUL T_LIMIT is the time allowed for V OUT to rise and settle at start-up. The TON_MAX_FAUL T_LIMIT timer , which has a resolution of 10µs, is started after TON_DELAY has been reached and a soft-start sequence is started. If the VOUT_UV_FAUL T_LIMIT is not reached or an OC remains within the specified time, fault response is determined by the value of TON_MAX_FAUL T_RESPONSE. An internal watchdog detects if SHARE_CLK remains low for more than 64µs. The part then actively holds SHARE_CLK low for 120ms, ensuring all devices connected to this shared control observe a minimum RETRY_DELAY event.The L TC3882-1 sets the SHARE_CLK_LOW bit in MFR_COMMON to indicate this fault condition. External Faults There are no hardware-level responses to any external faults propagated into the IC through the FAUL Tn pins. Fault Handling Higher-level input and output fault event handling (response) can be programmed as described in the following PMBus Command Details section. For most faults, the L TC3882-1 can manage response in one of three ways: ignore, autono- mous recovery (hiccup), or latch off. The device takes no additional action beyond previously discussed hardware- level responses when programmed to ignore a fault. For autonomous recovery a new soft-start is attempted if the fault condition is not present after the MFR_RETR DELAY interval has elapsed. MFR_RETRY_DELAY can be set from 120ms to 83 seconds in 1ms increments. If the fault persists, the controller will continue to retry with an interval specified by the MFR_RETRY_DELAY command. This avoids damage to external regulator components caused by repetitive, rapid power cycling. No retry is attempted for a latch off fault response. In the latch off state the gate drivers for the external MOSFETs are immediately disabled to stop the transfer of energy to the load as quickly as possible. The output remains disabled until the channel is commanded off and then on, or IC supply power is cycled. Commanding a PWM channel off and on may require software and/or hardware intervention depending on its programmed configuration. The RUN pin must be released by any controlling external application circuits for that channel to restart from the latch off state. As the RUN pin for a given channel rises, associ- ated internal fault indications are cleared automatically. The LTC3882-1 can also be programmed to clear faults for both outputs based solely on the RUN voltage of just one chan- nel. See the MFR_CONFIG_ALL_L TC3882-1 command. The CLEAR_FAUL TS PMBus command can also be used to clear all fault bits at any time, independent of PWM channel state. Handling of some internally generated faults can be digitally deglitched. See Table 12. External faults propagated into the chip using FAUL Tn pins are not deglitched. Refer to the following section on FAUL T functions. Status Registers and ALERT Masking Figure 2 summarizes the internal L TC3882-1 status reg- isters accessible by PMBus command. These contain indication of various faults, warnings and other important operating conditions. As shown, the STA TUS_BYTE and STATUS_WORD commands also summarize contents of other status registers. Refer to PMBus Command Details for specific information. NONE OF THE ABOVE in STATUS_BYTE indicates that one or more of the bits in the most-significant nibble of STATUS_WORD are also set. In general, any asserted bit in a STATUS_x register also pulls the ALERT pin low. Once set, ALERT will remain low until one of the following occurs. A CLEAR_FAUL TS, RESTORE_USER_ALL or MFR_RE- SET Command Is Issued

• The Related Status Bit Is Written to a One
• The Faulted Channel Is Properly Commanded Off and Back On

Figure 2. L TC3882-1 Status Register Summary

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Rev A For more information www.analog.com OPERATION

• The L TC3882-1 Successfully T ransmits Its Address During a PMBus Alert Response Address (ARA)
• IC Supply Power Is Cycled With some exceptions, the SMBALERT_MASK command can be used to prevent the L TC3882-1 from asserting ALERT for bits in these registers on a bit-by-bit basis. These mask settings are promoted to STATUS_WORD and STATUS_BYTE in the same fashion as the status bits themselves. For example, if ALERT is masked for all bits in Channel 0 STATUS_VOUT , then ALERT is effectively masked for the VOUT bit in STATUS_WORD for PAGE 0. The BUSY bit in STATUS_BYTE also asserts ALERT low and cannot be masked. This bit can be set as a result of interaction between internal operation and PMBus com - munication. This fault occurs when a command is received that cannot be safely executed with one or both channels enabled. As discussed in Application Information, BUSY faults can be avoided by polling MFR_COMMON before executing some commands. Status information contained in MFR_COMMON and MFR_PADS_L TC3882-1 can be used to clarify the con - tents of STATUS_BYTE or STATUS_WORD as shown, but the contents of these registers do not affect the state of the ALER T pin and may not directly influence bits in STATUS_BYTE or STATUS_WORD. FAUL T Pin I/O The L TC3882-1 can map various fault indicators to their respective FAUL T pin using the MFR_FAUL T_PROPA - GATE_L TC3882-1 command. Channel-to-channel fault dependencies and communica- tion can be created by connecting FAUL T pins together . In the event of an internal fault, one or more of the channels is configured to pull the bussed FAUL T pins low. All chan- nels are then configured to shut down when the bussed FAUL T pins are pulled low (MFR_FAUL T_RESPONSE set to 0xc0). If latch off is the programmed response on the faulted channel, the FAUL T pin remains low until one of the following occurs: A CLEAR_FAUL TS, RESTORE_USER_ALL or MFR_RE- SET Command Is Issued
• The Related Status Bit Is Written to a One
• The Faulted Channel Is Properly Commanded Off and Back On
• IC Supply Power Is Cycled For autonomous group retry , the faulted channel is con- figured to release the FAUL T pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. As noted above, F AUL T pins may be configured as inputs to detect faults external to the controller that require an immediate response. External faults propagated into the chip using FAUL T pins are not deglitched. Refer to the MFR_FAUL T_PROPAGATE command for ad- ditional details. Fault Logging The L TC3882-1 features a fault log, providing telemetry recording capability. During normal operation log data is continuously updated in internal RAM. When a fault occurs that disables either PWM controller , recording to internal memory is halted, the fault log information is made avail- able from RAM via the MFR_FAUL T_LOG command, and the contents of the RAM log are copied into EEPROM. Refer to the Fault Log Operation section for more detail. EEPROM fault logging is allowed above a die temperature of 85°C, but 10 years of retention is not guaranteed. When die temperature exceeds 130°C EEPROM fault logging is delayed until the temperature drops below 125°C. Faults generating a log should be fully cleared before the log is erased to prevent generation of spurious fault logs. Faults propagated into the IC through FAUL Tn pins do not trigger a fault logging event. When the L TC3882-1 powers up it checks the EEPROM for a valid fault log. If one is found the Valid Fault Log bit in the STATUS_MFR_SPECIFIC PMBus command is set. Additional fault logging will be disabled until the L TC3882-1 receives a CLEAR_FAUL TS command. If the Memory Fault Detected bit is also set in STATUS_CML, then the stored fault log is partial. Data in one or more event records may be incomplete or incorrect and MFR_FAUL T_LOG_CLEAR should also be commanded after all faults are cleared in order to fully enable additional logging functions.

Table 1. L TC3882-1 Fault Log Contents Header Information 0 26 See Table 2. and all of Table 3 and Table 4. Event Record N-2 67 86 Older data record. Event Record N-5 127 146 Oldest recorded data. Table 2. Fault Log Header Information Fault Source [7:0] Reg 4 Refer to Table 3. MFR_REAL_TIME [7:0] Reg 5 48 bit share-clock counter value when fault occurred (200µs resolution). MFR_VOUT_PEAK (PAGE 0) [15:8] L16 11 Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS command. MFR_VOUT_PEAK (PAGE 1) [15:8] L16 13 Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS command. MFR_IOUT_PEAK (PAGE 0) [15:8] L11 15 Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS command. MFR_IOUT_PEAK (PAGE 1) [15:8] L11 17 Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS command. MFR_VIN_PEAK [15:8] L11 19 Peak READ_VIN since last power-on or CLEAR_PEAKS command. READ_TEMPERATURE1 (PAGE 0) [15:8] L11 21 External temperature sensor 0 during last event. READ_TEMPERATURE1 (PAGE 1) [15:8] L11 23 External temperature sensor 1 during last event. READ_TEMPERATURE2 [15:8] L11 25 Internal temperature sensor during last event. block byte count of zero if a fault log is not present.

1. Refer to Table 6 for an explanation of data formats. Each

Table 3. Fault Source Values Table 4. Fault Log Event Record

if the PMBus interface is not being utilized. Table 5. Factory Default Operation Summary external UT , TON_MAX, or output short cycle.

Rev A For more information www.analog.com OPERATION Serial Interface The L TC3882-1 has a PMBus compliant serial interface that can operate at any frequency between 10kHz and 400kHz. The L TC3882-1 is a bus slave device that communicates bidirectionally with a host (master) using standard PMBus protocols. The Timing Diagram found earlier in this docu- ment, along with related Electrical Characteristics table entries, define the timing relationships of the SDA and SCL bus signals. SDA and SCL must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. PMBus, an incremental extension of the SMBus standard, offers more robust operation than a 2-wire I2C interface. In addition to adding a protocol layer to improve interoper- ability and facilitate reuse, PMBus supports bus timeout recovery for system reliability , optional packet error check- ing to ensure data integrity, and peripheral hardware alerts for system fault management. In general, a programmable device capable of functioning as an I2C bus master can be configured for PMBus management with little or no change to hardware. However , not all I 2C controllers support repeat start (restart) required for PMBus reads. For a description of the minor extensions and exceptions PMBus makes to the SMBus standard, refer to PMBus Specification Part I Revision 1.2 Paragraph 5 on T ransport. For a description of the differences between SMBus and I 2C, refer to System Management Bus (SMBus) Specifi - cation Version 2.0 Appendix B on Differences Between SMBus and I 2C. The user is encouraged to reference Part I of the latest PMBus Power System Management Protocol Specifica - tion to understand how to interface the L TC3882-1 to a PMBus system. This specification can be found at http:// www.pmbus.org/specs.html. The L TC3882-1 uses the following standard serial interface protocols defined in the SMBus and PMBus specifications:

• Quick Command
• Send Byte
• Write Byte
• Write Word
• Read Byte
• Read Word
• Block Read
• Block Write – Block Read Process Call
• Alert Response Address The L TC3882-1 does not require PEC for Quick Command under any cir cumstances. The L TC3882-1 also supports group command protocol (GCP) as required by PMBus specification Part I, section 5.2.3. GCP is used to send com- mands to more than one PMBus device in one continuous transmission. It should not be used with commands that require the receiving device to respond with data, such as a STA TUS_BYTE command. Refer to Part I of the PMBus specification for additional details on using GCP . All L TC3882-1 message transmission types allow for packet error checking. The later section on Serial Communication Errors provides more detail on packet error checking. Figure 4 to Figure 20 illustrate these protocols. Figure 3 provides a key to the protocol diagrams. Not all protocol elements will be present in every data packet. For instance, not all packets are required to include the packet error code. A number shown above a field in these diagrams indicates the number of bits in that field. All data transfers are initiated by the present bus master regardless of how many times data direction flow may change during the subsequent transmission. The L TC3882-1 never functions as a bus master . This device includes handshaking features to ensure ro - bust system communication. Please refer to the PMBus Communication and Command Processing section in Applications Information for more details. Serial Bus Addressing The L TC3882-1 supports four types of serial bus ad - dressing: Global Bus Addressing
• Power Rail Addressing
• Individual Device Addressing
• Page+ Channel Addressing

global addresses is strongly discouraged. together to produce a single output voltage (PolyPhase). channels that might be required for reliable system control. pin programming and the MFR_ADDRESS command. the PAGE_PLUS commands for additional details. should be limited to command write operations. Figure 4. Quick Command Protocol Figure 5. Send Byte Protocol Figure 6. Send Byte Protocol with PEC Figure 3. PMBus Packet Protocol Diagram Element Key

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CONTINUATION OF PROTOCOL ...

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Figure 8. Write Byte Protocol with PEC Figure 11. Read Byte Protocol Figure 14. Read Word Protocol with PEC Figure 9. Write Word Protocol Figure 12. Read Byte Protocol with PEC Figure 15. Block Read Protocol Figure 10. Write Word Protocol with PEC Figure 13. Read Word Protocol

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Figure 7. Write Byte Protocol

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Figure 19. Alert Response Address Protocol Figure 20. Alert Response Address Protocol with PEC

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Figure 16. Block Read Protocol with PEC Figure 17. Block Write – Block Read Process Call Figure 18. Block Write – Block Read Process Call with PEC

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Rev A For more information www.analog.com OPERATION Serial Bus Timeout The L TC3882-1 implements a timeout feature to avoid hanging the serial interface. The data packet timer be - gins running at the first START event before the SLAVE ADDRESS write byte and ends with the STOP bit. Packet transmission must be completed before the timer expires, or the L TC3882-1 will tri-state the bus and ignore all mes- sage data. The data packet includes the SLA VE ADDRESS byte, COMMAND CODE byte, repeated STAR T and SLAVE ADDRESS byte (if a read operation), all ACKNOWLEDGE and flow control bits (R/W) and all data bytes. The packet timer is typically set to 30ms. If bit 3 of MFR_ CONFIG_ALL_L TC3882-1 is set, this period is extended to 255ms. The L TC3882-1 automatically allows a packet transmission time of 255ms for MFR_FAUL T_LOG block reads regardless of the setting of this bit. In no circum - stances will the timeout period be less than the t TIMEOUT specification (25ms minimum). The L TC3882-1 supports the full PMBus frequency range of 10kHz to 400kHz. Serial Communication Errors The L TC3882-1 supports the optional PMBus packet error checking protocol. This protocol appends a packet error code (PEC) to the end of applicable message transfers to improve communication reliability. The PEC is a CRC-8 error-checking byte calculated by the bus device sending the last data byte. Refer to SMBus specification 1.2 or higher for additional implementation details. All L TC3882-1 read operations will return a valid PEC if the bus master requests it. If bit 2 in the MFR_CONFIG_ALL_L TC3882-1 command is set, the IC will not act in response to a bus write operation unless a valid PEC is also received from the host. PEC errors on command writes, attempts to access un - supported commands, or writing invalid data to supported commands all cause the L TC3882-1 to generate a CML fault. The CML bit is then set in the STATUS_BYTE and STATUS_WORD commands, and the appropriate bit is set in the STATUS_CML command.

Table 6. Abbreviations of Supported Data Formats two’s compliment binary integers. where Y = b[15:0], an unsigned integer . tion that can be found at http://www.pmbus.org/specs.html. the Applications Information section for further details. and allows for a wide range of other data formats.

Table 7. PMBus Command Summary

command to TON_RISE ramp start. VOUT_COMMAND after TON_DELAY. command to TOFF_FALL ramp start. VOUT_COMMAND after TOFF_DELAY.

execution of RESTORE_USER_ALL or MFR_RESET .

Rev A For more information www.analog.com APPLICATIONS INFORMATION Efficiency Considerations Normally, one of the primary goals of any L TC3882-1 ap- plication will be to obtain the highest practical conversion efficiency. The efficiency of a switching regulator is equal to the output power divided by the input power . It is often useful to analyze individual losses to determine what is limiting the efficiency and to ascertain which change would produce the most improvement. Balancing or limiting these individual losses plays a dominant role in the component selection process outlined over the next few sections. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + …) where L1, L2, et al, are the individual losses as a percent- age of input power: 100 • PLn /PIN. Although all dissipative elements in the system produce losses, four main sources usually account for most of the losses in L TC3882-1 applications: IC supply current, I 2R losses, topside power MOSFET transition losses and total gate drive current. 1. The L TC3882-1 IC supply current is a DC value given in the Electrical Characteristics table. The absolute loss created by the IC itself is approximately this current times the V CC supply voltage. IC supply current typically results in a small loss (<0.1%). 2. I2R losses occur mainly in the DC resistances of the MOSFET , inductor , PCB routing, and input and output capacitor ESR. Since each MOSFET is only on for part of the cycle, its on-resistance is effectively multiplied by the percentage of the cycle it is on. Therefore the bot- tom MOSFET should have a much lower on-resistance R DS(ON) than the top MOSFET in high step-down ratio applications. It is crucial that careful attention is paid to the layout of the power path on the PCB to minimize its resistance. In a 2-phase 1.2V system, 1mΩ of PCB resistance at the output costs 5% in efficiency with the output running at 60A. T ransition losses apply only to the topside MOSFET and become significant when operating at high input voltages (typically above 12V). This loss can be minimized by choosing a driver with very low drive resistance and a MOSFET with low gate charge Q G, gate resistance RG and Miller capacitance CMILLER. Absolute transition loss can be estimated by: PTRANS = (1.7) • VIN2 • IOUT • CMILLER • fPWM 4. Gate drive current is equal to the sum of the top and bot- tom MOSFET gate charges multiplied by the frequency of operation. These charges are based on the gate voltage applied by the FET driver and can be determined from manufacturer cur ves like the one shown in Figure 21. Many driver ICs employ asymmetrical gate voltages for top and bottom FETs. Other sources of loss include body or Schottky diode conduction during the driver dependent non-overlap time and inductor core losses. These latter categories generally account for less than 2% total additional loss. PWM Frequency and Inductor Selection The selection of the PWM switching frequency is a trade-off between efficiency, transient response and component size. High frequency operation reduces the size of the inductor and output capacitor as well as increasing the maximum practical control loop bandwidth. However , efficiency is generally lower due to increased transition and switch - ing losses. The inductor value is related to the switching frequency f PWM and step-down ratio. It should be selected to meet choke ripple current requirements. The inductor value can be calculated using the following equation: L = VOUT f PWM • ΔIL ⎠⎟ • 1– VOUT VIN Allowing a larger value of choke ripple current (∆IL) leads to smaller L, but results in greater core loss and higher output voltage ripple for a given output capacitance and/ or ESR. A reasonable starting point for setting the ripple current is 30% of the maximum output current. The inductor saturation current rating needs to be higher than the peak inductor current during transient conditions. If I OUT is the maximum rated load current, then the maxi- mum transient current IMAX would normally be chosen to be some factor greater than IOUT (e.g., 1.6 • IOUT).

SAT value would be 2.2 • IOUT. during transient conditions with margin for DCR variation. cores. Also, core losses decrease as inductance increases. of wire, larger inductance and larger copper losses. inductance when the peak current capability is exceeded. the FET circuit position (main or synchronous switch). for the main switch application in switching regulators. voltage and maximum output current. curve included on most data sheets (Figure 21). Figure 21. Typical MOSFET Gate Charge Curve

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Rev A For more information www.analog.com APPLICATIONS INFORMATION The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: PMAIN = VOUT VIN IMAX( ) 2 (1+ δ)RDS(ON) + VIN

2 IMAX

RDR( ) CMILLER( ) • VGG – VTH(IL) + 1 VTH(IL) fPWM( ) PSYNC = VIN – VOUT VIN IMAX( ) 2 (1+ δ)RDS(ON) where δ is the temperature dependency of R DS(ON), RDR is the effective top driver resistance, VIN is the drain po- tential and the change in drain potential in the particular application. V GG is the applied gate voltage, V TH(IL) is the typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current, and C MILLER is the capacitance calculated using the technique previously described. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) versus temperature curve. Typical values for δ range from 0.005/°C to 0.01/°C de - pending on the particular MOSFET used. Both MOSFETs have I2R losses while the topside N-channel losses also include transition losses, which are highest at high input voltages. For VIN < 20V the high current ef- ficiency generally improves with larger MOSFETs, while for V IN > 20V the transition losses rapidly increase to the point that the use of a higher R DS(ON) device with lower C MILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. Multiple MOSFETs can be used in parallel to lower R DS(ON) and meet the current and thermal requirements if desired. If using discrete drivers and MOSFETs, check the stress on the MOSFETs by independently measuring the drain- to-source voltages directly across the device terminals. Beware of inductive ringing that could exceed the maximum voltage rating of the MOSFET . If this ringing cannot be avoided and exceeds the maximum rating of the device, choose a higher voltage rated MOSFET . MOSFET Driver Selection Gate driver ICs, DrMOS devices and power blocks with an interface compatible with the L TC3882-1 3.3V three-state PWM control output(s) can be used. An external resistor divider may be needed to set three-state control voltage outputs to mid-rail while in the high impedance state, de- pending on the driver selected. These external driver/power circuits do not typically present a heavy capacitive load to the L TC3882-1 PWM outputs. Suitable drivers such as the L TC4449 are capable of driving large gate capacitances at high transition rates. In fact, when driving MOSFETs with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (5Ω or less) to reduce noise and EMI caused by fast transitions. Using PWM Protocols For successful utilization of the driver selected, the appropriate L T3882-1 PWM control protocol must be programmed. The L TC3882-1 supports two three-state PWM control protocols. See bit 1, of the MFR_PWM_ MODE_L TC3882-1 PMBus command. The first of these protocols (bit 1=0) is for drivers controlled by a single 3-state input that have sufficiently short delay to the diode emulation state (both top and bottom power MOSFETs disabled in a fraction of a PWM cycle), such as the L TC4449. The second protocol (bit 1=1) handles all other 3.3V compatible drivers with a single 3-state control input. C IN Selection The input bypass capacitance for an L TC3882-1 circuit needs to have ESR low enough to keep the supply drop low as the top MOSFETs turn on, RMS current capability adequate to withstand the ripple current at the input, and a capacitance value large enough to maintain the input voltage until the input supply can make up the difference. Generally, a capacitor that meets the first two require - ments (particularly a non-ceramic type) will have far more

Rev AFor more information www.analog.com APPLICATIONS INFORMATION capacitance than is required to keep capacitance-based droop under control. The input capacitance voltage rating should be at least 1.4 times the maximum input voltage. Power loss due to ESR occurs as I 2R dissipation in the capacitor itself. The input capacitor RMS current and its impact on any preceding input network is reduced by PolyPhase architecture. It can be shown that the worst case RMS current occurs when only one controller is operating. The controller with the highest (V OUT)(IOUT) product should be used to determine the maximum RMS current requirement. Increasing the output current drawn from the other out-of-phase control- ler will decrease the input RMS ripple current from this maximum value. T wo channel out-of-phase operation typically reduces the input capacitor RMS ripple current by a factor of 30% to 70%. In continuous inductor conduction mode, the sour ce cur- rent of the top power MOSFET is approximately a square wave of duty cycle VOUT/VIN. The maximum RMS capacitor current in this case is given by: IRMS ≈ IOUT(MAX) VOUT VIN – VOUT( ) VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2 This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that manufacturer ripple current ratings for capacitors are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. Ceramic, tantalum, semiconductor electrolyte (OS-CON), hybrid conductive polymer (SUNCON) and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks. Ceramics have high voltage coeffi- cients of capacitance and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs suffer from higher inductance, larger case size and limited surface mount applicability; and electrolytic capacitors have higher ESR and can dry out. Sanyo OS-CON SVP(D) series, Sanyo POSCAP TQC series, or Panasonic EE-FT series aluminum electrolytic capacitors can be used in parallel with a couple of high performance ceramic capacitors as an effective means of achieving low ESR and high bulk capacitance. In addition to PWM bulk input capacitance, a small (0.01μF to 1μF) bypass capacitor between the chip VINSNS pin and ground, placed close to the L TC3882-1, is also sug- gested. A small resistor placed between the bulk C IN and the VINSNS pin provides further isolation between the two channels. However , if the time constant of any such R-C network on the VINSNS pin exceeds 30ns, dynamic line transient response can be adversely affected. C OUT Selection The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple ∆VOUT is approximately bounded by: ΔVOUT ≤ ΔIL ESR + 1 8 • fPWM • COUT where ∆IL is the inductor ripple current. ΔIL = VOUT L • fPWM 1– VOUT VIN Since ∆IL increases with input voltage, the output ripple voltage is highest at maximum input voltage. Typically once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Manufacturers such as Sanyo, Panasonic and Cornell Du- bilier should be considered for high performance through- hole capacitors. The OS-CON semiconductor electrolyte capacitor available from Sanyo has a good (ESR)(size) product. An additional ceramic capacitor in parallel with polarized capacitors is recommended to offset the effect of lead inductance. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or transient current

Figure 22. Type 3 Compensation Circuit current sharing loop is internally compensated. at the COMP pin is internally clamped.

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for in the frequency compensation. MOSFET drivers and the external MOSFETs themselves. Figure 23. Type 3 Compensation Frequency Response

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Rev AFor more information www.analog.com APPLICATIONS INFORMATION fC = crossover frequency = fPWM fZ1 (ERR)= fLC = 1 2πR2C1 fZ2(RES) = fC = 1 2π(R1+ R3)C3 fP1 (ERR)= fESR = 1 2πR2(C1//C2) fP2(RES) = 5fC = 1 2πR3C3 Required error amplifier gain at frequency fC is: ≈ 40log 1 + fC fLC – 20log 1 + fC fESR – 15.56 Once the value of resistor R1 (function of selected V OUT range) and pole/zero locations have been decided, the value of R2, C1, C2, R3 and C3 can be obtained from the previous equations. Compensating a switching power supply feedback loop is a complex task. The applications shown in this data sheet provide typical values, optimized for the power components shown. Though similar power components should suffice, substantially changing even one major power component may degrade performance significantly. Stability also may depend on circuit board layout. To verify the calculated component values, all new circuit designs should be prototyped and tested for stability. The L TPowerCAD software tool can be used as a guide through the entire power supply design process, includ- ing optimization of circuit component values according to system requirements. PCB Layout Considerations To prevent magnetic and electrical field radiation or high frequency resonant problems and to ensure correct IC operation, proper layout of the components connected to the L TC3882-1 is essential. Refer to Figure 24, which also illustrates current waveforms typically present in the circuit branches. R SENSE will be replaced with a dead short if DCR sensing is used. For maximum efficiency, the switch The external inductor/output capacitor combination makes a more significant contribution to loop behavior . These components cause a 2nd order amplitude roll-off that filters the PWM waveform, resulting in the desired DC output voltage. But the additional 180° phase shift produced by this filter causes stability issues in the feedback loop and must be frequency compensated. At higher frequencies, the reactance of the output capacitor will approach its ESR, and the roll-off due to the capacitor will stop, leaving –20dB/decade and 90° of phase shift. The transfer function of the Type 3 circuit shown in Figure 22 is given by the following equation: VCOMP VOUT sR1 (C1+ C2)[1+ s(C1//C2)R2](1+ sC3R3) The RC network across the error amplifier and the feed - forward components R3 and C3 introduce two pole-zero pairs to obtain a phase boost at the system unity-gain (crossover) frequency, f C. In theory, the zeros and poles are placed symmetrically around fC, and the spread between the zeros and the poles is adjusted to give the desired phase boost at f C. However , in practice, if the crossover frequency is much higher than the LC double-pole frequency, this method of frequency compensation normally generates a phase dip within the unity bandwidth and creates some concern regarding conditional stability. If conditional stability is a concern, move the error ampli- fier zero to a lower frequency to avoid excessive phase dip. The following equations can be used to compute the feedback compensation component values: fLC = 1 2π LCOUT fESR = 1 2πRESRCOUT choose:

PCB design priority list will help ensure proper topology.

1. Place a ground or DC voltage layer between a power

plane vias to minimize resistance and inductance. switching FETs with large size passive components. the switch node to any other trace or plane. to connect them to system ground. tors for the L TC3882-1 immediately adjacent to the IC. inductance, which further improves EMI performance. must be properly connected in the application at all times. Figure 25. The DCR of the inductor represents the small

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Figure 24. High Frequency Paths and Branch Current Waveforms tor is equal to the voltage drop across the inductor DCR. can also be measured using a good RLC meter . nodes. Capacitor C1 should be placed close to the IC pins. the sense resistor could represent a relatively small error . resistor values producing sense voltages less than 20mV . with operation up to 1MHz are becoming more common.

Figure 25. Inductor DCR Output Current Sense

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Figure 26. Discrete Resistor Output Current Sense waveform across a 2mΩ resistor with a 2010 footprint. sultant waveform looks resistive, as shown in Figure 28.

• tON •tOFF tON + tOFF BOOST TG L TC4449 VIN 12V TS VOUT

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ated with the turn-on of the primary switch. also provide the ADC inputs for output voltage telemetry.

noticeable an output voltage stair-step may become. the RUN pin goes low or if the part is commanded off. noticeable an output voltage stair-step may become. Figure 27. Voltage Measured Directly Across RSENSE Figure 28. Voltage Measured at ISENSE Pins

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The L TC3882-1 must enter the run state prior to soft-start.

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Figure 34. L TC3882-1 Time-Based Ratiometric Ramping Figure 35. Cascade Sequencing Configuration

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Figure 31. Example of 1ms TON_RISE Figure 33. L TC3882-1 Time-Based Coincident Supply Ramping Figure 32. L TC3882-1 Time-Based Supply Sequencing Figure 35. This configuration hardware disables the next

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Figure 36. Cascade Sequencing Waveforms

10 for additional examples of using AVP to advantage. point to avoid spurious warnings at full load. LOW also specify no-load values when AVP is enabled. bit) until the output is at the correct ADC reading. enabled after all of the following conditions are satisfied.

• The TON_RISE Sequence Is Complete
• A VOUT_UV_FAUL T Is Not Present
• An IOUT_OC_FAUL T Is Not Present
• MFR_AVP = 0% Digital ser vo mode then engages after TON_MAX_ FAUL T_LIMIT has expired as shown in Figure 29, unless that limit is set to 0s (infinite). In that case, the mode is engaged as soon as the above conditions are satisfied. Using AVP The L TC3882-1 features digitally programmable active voltage positioning (AVP), where output voltage set point is automatically adjusted as a function of output current at the full bandwidth of the converter . AVP normally entails specifying an output load line for a voltage mode switcher to allow current sharing between master phases connected in parallel. While AVP can be used to this effect in L TC3882-1 applications, use of the L TC3882-1 I AVG current sharing control loop is recommended instead. This will produce more accurate sharing across a wider number of phases without degrading supply output impedance. However , AVP can still be used to great benefit in L TC3882-1 applications. AVP can be applied to minimize the size of

Figure 37. Active Voltage Positioning

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Rev AFor more information www.analog.com APPLICATIONS INFORMATION 3. Set MFR_VOUT_AVP to a per centage that produces the desired output excursion as a function of current. For example, if the goal is to allow a 2.5% output change on a 3.3V 6-phase supply rated at 120A during an output load step from 20% to 80%, the following parameters should be programmed. First set an output current warning level for the master (one of six phases) just slightly higher than the rated full load to avoid spurious warnings. Typically this same setting would also be applied to the five slave phases. IOUT_OC_WARN_LIMIT = 1.1 • 120A/6 = 22A The open cir cuit output voltage calculation for the master phase must reflect that the AVP specification in this case only covers an output load swing of 60%. VOUT_COMMAND = 3.3V(1 + 0.5 • 0.025/0.6) = 3.3687V The AVP calculation must then account for the fact that IOUT_OC_W ARN_LEVEL is set higher than the 100% load point. 3.3687 = 4.487% With the output voltage at 3.3V at 50% load these set- tings will move V OUT from approximately 3.34V to about 3.26V when the output load of the rail moves from 24A to 96A. Note that V OUT will drop to 3.23V at full load in this design example. Digital output servo mode is automatically disabled if AVP is enabled on a master phase. AVP is active during all output ramping when enabled (e.g., a TON_RISE se - quence). AVP is disabled on master phases by program- ming MFR_VOUT_AVP to 0.0% (factory default). AVP is automatically disabled on phases configured as slaves (FB tied to VDD33). Because of related ISENSE input offsets, increased output voltage error can occur at all operating currents when AVP is engaged. To minimize this error a calibration offset can be added to the master phase VOUT_COMMAND value based on the READ_VOUT value obtained when operat - ing at a known output current of at least 20% of full load (READ_IOUT). The necessary correction, which will typi- cally be less than several per cent of the no load output voltage, is calculated as: VOS = VOUT_COMMAND 100 •IOUT_OC_WARN_LIMIT – READ_VOUT PWM Frequency Synchronization The L TC3882-1 incorporates an internal phase-locked loop (PLL) which enables synchronization of both PWM channels (falling edge PWM) to an external CMOS clock from 250kHz to 1.25MHz. The PLL is locked to the falling edge of the SYNC pin clock signal. This PLL also generates very accurate channel phase relationships which can be selected with the MFR_PWM_CONFIG_L TC3882-1 com- mand. For PolyPhase applications, all phases should be spaced evenly in the phase diagram for best results. For instance, a 4-phase system should use a separation of 90° between channels. The PLL has a lock detection circuit. If the PLL should lose l ock during operation, bit 4 of the STATUS_MFR_SPECIFIC command is asserted and the ALERT pin is pulled low, unless masked. The fault can be cleared by writing a 1 to STATUS_MFR_SPECIFIC bit 4. A spurious ALERT for an unlocked PLL may occur at start-up or during a reset if this fault is not masked. Neither PWM channel will transition from off to the RUN state until PLL lock is indicated. When transitioning a channel from off to RUN, bit 4 of STATUS_MFR_SPECIFIC will be set if the PWM ramp generator for that channel is not also locked to the desired PLL output frequency. If the SYNC pin is not externally clocked in the application, the PWMs will operate at the frequency specified by a non- zero FREQUENCY_SWITCH command. If that command is set to 0x0000 (external clock only) in EEPROM or with RCONFIG (FREQ_CFG pin grounded), then at power-up, or MFR_RESET , or RESTORE_USER_ALL, the PWM will not start without an external clock input. If the external clock is lost while programmed for external clock only, or if the PWM is simply switched to this setting under power with no external clock present, the PLL will start/run at

Rev A For more information www.analog.com the lowest free running frequency created by the internal VCO. This can be well below the intended PWM frequency of the application and may cause undesirable operation of the converter . For this reason, it is generally recommended that a useable PWM frequency be programmed for each channel, regardless of whether that particiular L TC3882-1 unit serves as clock master , or not. All channels of a PolyPhase rail are required to share SYNC pins. Between rails and for other configurations, such syn- chronization is optional. If the SYNC pin is shared between L TC3882-1s, only one L TC3882-1 should be programmed to control the SYNC output. PolyPhase Operation and Load Sharing When the L TC3882-1 is used in a PolyPhase application, the slave phases must be configured as such by con - necting their FB pins to VDD33. Among other things, this disables the error amplifiers of the slave phases. Five other pins must then also be shared between all channels of a PolyPhase rail: VINSNS

• COMP
• IAVG
• IAVG_GND
• SYNC Using a common VINSNS connection reduces the dynamic range required by the current loop and helps maintain well-controlled master modulator gain. The shared COMP signal allows the master phase error amplifier to control the duty cycle of all slave phases to produce the commanded output voltage. Slave phases can detect system faults that cause the master COMP (error amplifier) output to be too high. A slave phase detecting this kind of error amplifier fault im- mediately shuts off its PWM output, indicates the fault on its VOUT_OV Fault bit, and takes whatever additional action may be indicated by VOUT_OV_F AUL T_RESPONSE for that channel. If this response is set to only provide hardware- level response (0x00), then normal channel operation will automatically resume when the fault condition is cleared. The shared I AVG and IAVG_GND signals actively balance the amount of output current delivered from each channel using a secondary current sharing loop. A capacitor with a value between 100pF and 200pF should be placed between I AVG and IAVG_GND. This capacitance can be distributed across L TC3882-1 devices/pins for improved noise immunity. All I AVG_GND pins for a PolyPhase rail should be tied together and connected to a single ground point at or near the package paddle of the master phase. Load sharing accuracy is based primarily on the current sense amplifier offset of each phase (I AVG_VOS) and the offset of slave current error amplifiers (VSIOS). These are given in the EC table. Current sense gain errors between L TC3882-1 channels will be negligible. The secondary current sharing loop acts to average any errors among the phases. Because of this error averaging and the random nature of these variables, the EC table limits ensure actual per-phase offset will be less than or equal to ±300µV for most designs over the full operating temperature range. This signifies better than ±2% matching when ∆I SENSE = 15mV , not including external factors such as DCR make tolerance. It is necessary to properly connect V SENSE+ on a slave phase for accurate IOUT telemetry, even though slave phases do use need this information for PWM control. While not strictly required, the V SENSE± lines of slave phases can simply share with the master to provide additional output voltage telemetry. If the only concern is accurate slave I OUT telemetry, VSENSE+ for that channel may be locally wired to ISENSE–. VSENSE– on a slave phase should always be shorted to VSENSE– for its master channel. I OUT OC/ROC function is not affected by VSENSE± wiring. All phases must be synchronized to the same shared SYNC clock and should be programmed to run at the same default PWM frequency. Phases should be selected to be evenly spaced around a 360° phasor diagram, and all phases on a PolyPhase rail should be selected to have the same maximum duty cycle. Refer to details for MFR_ PWM_CONFIG_L TC3882-1. Figure 38 shows an example of connections for three phases and Figure 39 shows an example of an 8-phase rail. Additional shared signals in these figures highlight the ability of the L TC3882-1 to com- municate fault status between phases and rails, perform APPLICATIONS INFORMATION

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Figure 38. 3+1-Phase Application

Figure 39. 8-Phase Application

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Figure 41. Normalized RMS Input Ripple Current Figure 42. Normalized Output Ripple Current [IRMS ~ 0.3(DIC(PP))]

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Figure 40. Single and 2-Phase Current Waveforms

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report accurate output current telemetry for all phases. less the slave channel is used in active phase shedding. or used only to indicate operating status for that phase. telemetry and consistent fault handling across phases. external sources of error , such as inductor DCR tolerance. of ripple current in both the input and output capacitors. phases used. Figure 40 graphically illustrates the principle. sign peaks at an input voltage of twice the output voltage. is then theoretically reduced by a factor of four .

paged READ_TEMPERATURE_1 telemetry command. parallel with the diode-connected PNP . with its lower signal levels. the ideality factor to calculate the MFR_TEMP_1_GAIN. the direct p-n junction measurement. from that shown in Figure 44. well as Application Note 137. modifying their values on the fly is not recommended. resistor divider if they require identical programming. signals should not be routed near these pins. Figure 43. External ΔVBE Temperature Sense Figure 44. 2D+R Temperature Sense

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Table 8. VOUTn_CFG Resistor Programming start from this configuration. Table 9. FREQ_CFG Resistor Programming specified. Refer to Table 9 and 10. Table 10. PHAS_CFG Resistor Programming

should not be set to either of these values. Table 11. ASELn Resistor Programming that are terminated to VDD33. configuration resistor dividers. temperature is not exceeded under all operating conditions.

Rev AFor more information www.analog.com APPLICATIONS INFORMATION If an external source supplies VDD33 directly, the following formula may be used to estimate the maximum average power dissipation PD (in watts) of the L TC3882-1 PD = VDD33(0.024 + fPWM • 1.6e-5 + IRC25) The maximum junction temperature of the L TC3882-1 in °C may then be found from the following equation TJ = TA + 33 • PD with ambient temperature TA expressed in °C Derating EEPROM Retention at Temperature EEPROM read operations between 85°C and 125°C will not affect data storage. But retention will be degraded if the EEPROM is written above 85°C or stored above 125°C. If an occasional fault log is generated above 85°C, the slight reduction in data retention in the EEPROM fault log area will not affect the use of the function or other EEPROM storage. See the Operation section for other high tem - perature EEPROM functional details. Degradation in data can be approximated by calculating the dimensionless acceleration factor using the following equation. AF = e Ea k ⎠⎟ • 1 TUSE +273 − 1 TSTRESS +273 Where: AF = acceleration factor Ea = activation energy = 1.4eV TUSE = is the specified junction temperature TSTRESS = actual junction temperature in °C As an example, if the device is stored at 130°C for 10 hours, TSTRESS = 130°C, and AF = e 1.4 8.617•10 –5 ⎠⎟ • 1 398 − 1 403 = 1.66 indicating the effect is the same as operating the device at 125°C for 10 • 1.66 = 16.6 hours, resulting in a retention derating of 6.6 hours. Configuring Open-Drain Pins The L TC3882-1 has the following open-drain pins: 3.3V Pins 1. PGOODn 2. F AUL Tn 2. SYNC 3. SHARE_CLK 5V-Capable Pins (These pins operate correctly when pulled to 3.3V 1. RUNn 2. ALER T 3. SCL 4. SDA All of the above pins have on-chip pull-down transistors that can sink 3mA at 0.4V . The low-state threshold on these pins provides ample noise margin exists with 3mA of current. For 3.3V pins, 3mA of current is produced by a 1.1k pull-up resistor . Unless there are transient speed issues associated with the RC time constant of the net, a 10k resistor or larger is generally recommended. The pull-up resistor for PGOOD should be terminated to the L TC3882-1 V DD33 pin or a separate bias supply under 3.6V that is up before the L TC3882-1 is enabled. Otherwise, power-not-good may be falsely indicated after the PWM outputs are running. The SYNC pin has an on-chip pull-down transistor with the output held low for nominally 250ns when driven by the L TC3882-1. If the internal oscillator is set for 500kHz and the load is 100pF with a 1/3 rise time required, the resistor calculation is as follows: RPULLUP = 2µs – 250ns 3 • 100pF = 5.83k The closest 1% resistor is 5.76k. If timing errors are occurring or if the SYNC amplitude is not as large as required, monitor the waveform and determine if the RC time constant is too long for the

application. If possible reduce the parasitic capacitance. The closest 1% resistor is 30.1k. The closest 1% resistor value is 1k. signal to reach approximately 63% of the output value. data at PMBus speeds between 10kHz and 400kHz. by asserting bit 1 of MFR_CONFIG_ALL_L TC3882-1. communication speed exceeds 100kHz. Figure 45. Write Command Data Processing

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shaking status bits are in the MFR_COMMON register . will clear bit 6 of MFR_COMMON (L TC3882-1 Not BUSY). PMBus SCL rates above 400kHz is not recommended. normally be resolved by simply re-reading STATUS_WORD. Linear Technology demo circuit or user application. Figure 46. Example of a Polling Loop to Write VOUT_COMMAND register is provided in Figure 46.

Rev A For more information www.analog.com APPLICATIONS INFORMATION L TpowerPlay can also be used offline (no hardware pres- ent) to build multiple IC configuration files that can be saved and later reloaded. LTpowerPlay uses the DC1613 USB-to-I2C/SMBus/PMBus controller to communicate with a system for evaluation, development or debug. The software also features automatic update to remain up- to-date with the latest device drivers and documentation available from Linear Technology. A great deal of context sensitive help is available within L TpowerPlay, along with several tutorials. Complete information is available at http:// www.linear.com/ltpowerplay. Interfacing to the DC1613 The L TC DC1613 USB-to-I 2C/SMBus/PMBus controller can be interfaced to the L TC3882-1 on any board for programming, telemetry and system debug. This includes the DC1936 from Linear Technology, or any customer target system. The controller , when used in conjunction with L TpowerPlay, provides a powerful way to debug an entire power system. Faults are quickly diagnosed using telemetry, fault status registers and the fault log. The final configuration can be quickly developed and stored to the L TC3882-1 EEPROM and/or L TpowerPlay configuration file. The DC1613 can communicate with, program and even power one or more L TC3882-1s, regardless of whether system supplies are up. The DC2086 Powered Program- ming Adapter can be used to extend the power sourcing capability of the DC1613. Figure 47 illustrates an applica- tion schematic for in-system programming of multiple LTC3882-1s normally powered from a V CC system supply (5V to 12V). If VCC is applied, the DC1613 will not supply the L TC3882-1s on the board. If the DC2086 is used, PFETs with lower RDS(ON), such as the SiA907EDJT , should be used in place of the TP0101K devices. Figure 48 shows an example when the system normally provides 3.3V directly to the L TC3882-1(s). If system supplies are not up in either of these circuits, the DC1613 will power the L TC3882-1 V DD33 supply, allowing in-circuit configuration or manufacturing customization. These circuits also facilitate remote diagnostics, control and reprogramming of the L TC3882-1 while the host system is fully operational, permitting very flexible in- system debugging. If the system supply is restored while power is still applied by the DC1613 or DC2086, the L TC3882-1 can often be ready to initiate output soft-start before sufficient supply bias for the power stage has been established. Create additional L TC3882-1 delay with TON_DELAY or use a common system RUN line to control both the L TC3882-1 and its related power stages based on acceptable operat- ing parameters, as shown in Figure 55. The DC1613 I connections are opto-isolated from the host PC USB. The DC1613 3.3V current limit is only 100mA, so it should only be used to power one or two L TC3882-1s in-system. Because of this limited current sourcing capability, only the L TC3882-1s, their associated pull-up resistors and the I 2C pull-up resistors should be powered from the isolated 3.3V supply provided by the DC1613. Using the DC2086 will enable in-system programming of several tens of L TC3882-1 devices without normal system power applied. Any other device sharing the I 2C bus with the L TC3882-1 should not have body diodes between their SDA/SCL pins and their respective logic supply, because this will interfere with bus communication in the absence of system power . Hold the RUN pins low externally to avoid providing power to the load until the part is fully configured. Design Example As a design example, consider a 132W 2-phase applica- tion such as the one shown in Figure 53, where V IN = 36V , VOUT = 3.3V , and IOUT = 40A. A fully discrete power stage design is employed to allow better optimization given these demanding requirements. Assume that a secondary 5V supply will be available in the system for the L TC3882-1 V CC supply. The necessary local bypassing is then pro- vided for the VDD33 (2.2µF) and VDD25 (1µF) LDO outputs. These LDO outputs should not be shared with other ICs that might have outputs of the same name, because they have independent, internal control loops. When V DD33 is used as the L TC3882-1 supply input, it may be shared with other ICs operating from that 3.3V supply. Local HF bypassing of at least 0.1µF is still required on V DD33 in this case. First, the regulated output is established by programming the VOUT_COMMAND stored in EEPROM to 3.3V .

Figure 47. DC1613 Connection (VCC Supply)

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Figure 48. DC1613 Connections (VDD33 Supply)

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Rev A For more information www.analog.com The frequency and phase are also set by EEPROM values. Assume that solution footprint or vertical clearance is an issue, so operating frequency will need to be increased in an effort to minimize inductor value (size). This choice could also result from the need to have above average transient performance, although efficiency may be re - duced slightly. FREQUENCY_SWITCH is set to 1.0MHz. As a 2-phase system, MFR_PWM_CONFIG_L TC3882-1 is programmed to 0x14 to put Channel 0 phase at 0° and Channel 1 phase at 180°. This produces the lowest input ripple possible with this configuration and allows this output to synchronize with other rails via SHARE_CLK. The design will plan on a nominal output ripple of 70% of I OUT to minimize the magnetics volume, and the inductance value is chosen based on this assumption. Each channel supplies an average 20A to the output at full load, result- ing in a ripple of 14A P-P. A 200nH inductor per phase would create this peak-to-peak ripple at 1.0MHz. A Pulse PA0513.22L T 210nH inductor with a DCR of 0.32mΩ typical is selected. Setting IOUT_FAUL T_LIMIT to 35A per phase leaves plenty of headroom for transient conditions while still adequately protecting against the rated inductor saturation current of 45A at temperature. For top and bottom power FETs, the 40V rated Infineon BSC050N04LSG and BSC010N04LS are chosen, respec- tively. These afford both low R DS(ON) and low gate charge QG. T wo of each of these could be paralleled to achieve improved efficiency at full load, if desired. The L TC4449 gate driver is chosen for its fast response (13ns), suitable gate drive, V IN capability (38V) and the ease with which it can be interfaced to the L TC3882-1. Basic three-state control, CCM operation, fast boost refresh, low V OUT range and digital output voltage servo are selected by programming MFR_PWM_MODE_L TC3882-1 to 0xC0 for both channels. For input filtering, a 47μF SUNCON capacitor and four 22μF ceramic capacitors are selected to provide accept - able AC impedance against the designed converter ripple current. Four 470μF 9mΩ POSCAPs and two 100μF ceramic capacitors are chosen for the output to maintain supply regulation during severe transient conditions and to minimize output voltage ripple. A loop crossover frequency of 100kHz provides good transient performance while still being well below the switching frequency of the converter . The values of R29, R30 and C25 to C27 were determined to produce a nomi- nal system phase margin of about 65° at this bandwidth. For the DCR sense filter network, R = 3.09k and C = 220nF are chosen to match the L/DCR time constant of the induc- tor . PolyPhase connections (I AVG, et al) are shown in the schematic to ensure good output current sharing between the two power stages. External temperature sense will employ an accurate ∆VBE method, and Q1 and Q2 serve to sense the temperature of L1 and L2, respectively. These components will be located immediately adjacent to their chokes and the 10nF filter capacitors placed with the BJTs. Resistor configuration is used on the ASELn pins to pro- gram PMBus address (MFR_ADDRESS) to 0x4C. Each L TC3882-1 must be configured for a unique address. Using both ASEL n pins to accomplish this programming is recommended for simpliest in-system programming. Check the selected address to avoid collision with global addresses other any other specific devices. Identical MFR_RAIL_ADDRESS can be set in EEPROM for both channels to allow single-command control of common rail parameters such as IOUT_OC_FAUL T_LIMIT . The L TC3882-1 also responds to 7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS and MFR_RAIL_ADDRESS should not be set to either of these values. PMBus connection (three signals), as well as shared RUN control and fault propagation (FAUL T) are provided. SYNC can be used to synchronize other PWMs to this rail if required. Pull-ups are provided on all these shared open-drain signals assuming a maximum 100pF line load and PMBus rate of 100kHz. These pins should not be left floating. Termina- tion to 3.3V ensures the absolute maximum ratings for the pins are not exceeded. All other operating parameters such as soft start/stop and desired faults responses are programmed via PMBus command values stored in internal L TC3882-1 EEPROM. APPLICATIONS INFORMATION

Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device. will respond to read commands as if PAGE were set to 0x00 (Channel 0 results). This command has one data byte. may be sent with PAGE_PLUS_WRITE. a non-paged command, the Page Number byte is ignored. mand that has two data bytes is shown in Figure 49. Figure 49. Example of PAGE_PLUS_WRITE

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for channels comprising a PolyPhase output. Related commands: MFR_COMMON.

Figure 50. Example of PAGE_PLUS_READ The WRITE_PROTECT command is used to control PMBus write access to the L TC3882-1. 0x80 Disable all writes except WRITE_PROTECT , PAGE, STORE_USER_ALL and MFR_EE_UNLOCK commands. commands. Individual faults can also be cleared by writing a 1 to the respective status bit. ON_OFF_CONFIG and VOUT_COMMAND commands. Individual faults can be cleared by writing a 1 to the respective status bit. 0x00 Enables writes to all commands. This command has one data byte.

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the data returned by the command, all in one communication packet . data from a non-paged command, the Page Number byte is ignored. with PEC is shown in Figure 50. fault for Invalid/Unsupported Data.

Rev AFor more information www.analog.com PMBUS_REVISION The PMBUS_REVISION command returns the revision of the PMBus Specification that the device supports. The L TC3882-1 is compliant with PMBus Version 1.2, both Part I and Part II. This read-only command has one data byte. CAPABILITY The CAPABILITY command reports some key L TC3882-1 features to the PMBus host device. The L TC3882-1 supports packet error checking, 400kHz bus speeds and has an ALERT output. This read-only command has one data byte. GENERAL DEVICE CONFIGURATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PMBUS_REVISION 0x98 Supported PMBus version. R Byte Y Reg 0x22 V1.2 CAPABILIT Y 0x19 Summary of supported optional PMBus features. R Byte N Reg 0xB0 MFR_CONFIG_ALL_L TC3882-1 0xD1 L TC3882-1 device-level configuration. R/W Byte N Reg l 0x01 PMBus COMMAND DETAILS (Addressing and Write Protect) MFR_ADDRESS The MFR_ADDRESS command sets the seven bits of the PMBus device address for this unit (right justified). Setting this command to a value of 0x80 disables device-level addressing. The GLOBAL device addresses 0x5A and 0x5B cannot be disabled. The L TC3882-1 always responds at these addresses. Even if bit 6 of MFR_CONFIG_ALL_ L TC3882-1 is set to ignore the device resistor configuration pins, any valid address, or portion of an address, specified with external resistors on ASEL0 or ASEL1 is applied. If both of these pins are open, the device address is determined strictly by the MFR_ADDRESS value stored in EEPROM. Refer to the Operation section on Resistor Configuration Pins for additional details. This command has one data byte. MFR_RAIL_ADDRESS The MFR_RAIL_ADDRESS command sets a direct 7-bit PMBus address (right justified) for the active channel(s) as determined by the PAGE command. This address should be common to all channels attached to a single power supply rail. Setting this command to a value of 0x80 disables rail device addressing for the selected channel. Only command writes should be made to the rail address. If a read is performed from this address, a CML fault may result. This command has one data byte.

Rev A For more information www.analog.com ON_OFF_CONFIG The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to turn the PWM channel on and off. Supported Values: VALUE MEANING 0x1F OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off with the RUN pin. 0x1E OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off. 0x17 RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored. 0x16 RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored. Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored. This command has one data byte. ON, OFF AND MARGIN CONTROL COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE ON_OFF_CONFIG 0x02 RUN pin and PMBus on/off command configuration. R/W Byte Y Reg l 0x1E OPERATION 0x01 On, off and margin control. R/W Byte Y Reg l 0x80 MFR_RESET 0xFD Force full reset without removing power . Send Byte N PMBus COMMAND DETAILS (General Device Configuration) MFR_CONFIG_ALL_LTC3882-1 The MFR_CONFIG_ALL_L TC3882-1 command provides device-level configuration common to multiple L TC PMBus products. Bit Definitions: BIT MEANING 7 Enable fault logging. 6 Ignore resistor configuration pins. Does not apply to ASEL0 or ASEL1. 5 Disable CML fault for Quick Command message. 4 Disable SYNC output. 3 Enable 255ms PMBus timeout. 2 Require valid PEC for PMBus write. 1 Enable PMBus clock stretching. 0 Execute CLEAR_FAUL TS on rising edge of either RUN pin. If a legal command is received with an invalid PEC, the L TC3882-1 will not execute the command, regardless of the state of bit 2. If clock stretching is enabled, the L TC3882-1 only uses it as required, generally above SCL rates of 100kHz. This command has one data byte.

Rev AFor more information www.analog.com OPERATION The OPERATION command is used to turn the PWM channel on and off in conjunction with RUN pin hardware control. This command may also be used to move the output voltage to margin levels. VOUT changes commanded by OPERATION margin commands occur at the programmed VOUT_TRANSITION_RATE. The unit stays in the commanded operating state until an OPERATION command or RUN pin voltage instructs the device to change to another state. Execution of margin commands is delayed until any on-going TON_RISE or TOFF_FALL output sequencing is com - pleted. Margin values are affected by AVP function, if enabled. Margin operations that ignore faults are not supported by the LTC3882-1. Supported Values: VALUE MEANING 0xA8 Margin high. 0x98 Margin low. 0x80 On (V OUT back to nominal even if bit 3 of ON_OFF_CONFIG is not set). 0x40* Soft off (with sequencing). 0x00* Immediate off (no sequencing). *Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set. Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored. This command has one data byte. MFR_RESET This command provides a means to reset the L TC3882-1 from the serial bus. This forces the L TC3882-1 to turn off both PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of both PWM channels, if enabled. This write-only command has no data bytes. PMBus COMMAND DETAILS (On, Off and Margin Control)

Rev A For more information www.analog.com FREQUENCY_SWITCH The FREQUENCY_SWITCH command sets the switching frequency of both L TC3882-1 PWM channels in kilohertz. At most only one IC sharing SYNC should be programmed as clock master . See bit 4 in MFR_CONFIG_ALL_L TC3882-1. FREQUENCY_SWITCH value will determine the free-running frequency of PWM operation if an expected external clock source is not present or the bussed SYNC line becomes stuck due an external fault or conflict. Both PWM channels must be turned off by the RUNn pins, OPERATION command, or their combination, to process this command. If this command is sent while either PWM controller is operating, the L TC3882-1 will NACK the command byte, ignore the command and its data, and assert a BUSY fault. A PLL Unlocked status may be reported after changing the value of this command until the new frequency is established. Supported Frequencies: VALUE PWM FREQUENCY (TYPICAL) 0x0A71 1.25MHz 0x03E8 1MHz 0x0384 900kHz 0x02EE 750kHz 0x0258 600kHz 0xFBE8 500kHz 0xFB84 450kHz 0xFB20 400kHz 0xFABC 350kHz 0XFA58 300kHz 0xF3E8 250kHz 0x0000 External SYNC Only This command has two data bytes in Linear_5s_11s format. PWM CONFIGURATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE FREQUENCY_SWITCH 0x33 PWM frequency control. R/W Word N L11 kHz l 500kHz 0xFBE8 MFR_PWM_CONFIG_L TC3882-1 0xF5 L TC3882-1 PWM configuration common to both channels. R/W Byte N Reg l 0x14 MFR_CHAN_CONFIG_L TC3882-1 0xD0 L TC3882-1 channel-specific configuration. R/W Byte Y Reg l 0x1D MFR_PWM_MODE_L TC3882-1 0xD4 L TC3882-1 channel-specific PWM mode control. R/W Byte Y Reg l 0xC8 Related commands MFR_TEMP_1_GAIN_ADJUST , MFR_TEMP_1_OFFSET . PMBus COMMAND DETAILS (PWM Configuration)

Rev AFor more information www.analog.com MFR_PWM_CONFIG_LTC3882-1 The MFR_PWM_CONFIG_L TC3882-1 command controls PWM-related clocking for the L TC3882-1. Both PWM chan- nels must be turned off by the RUNn pins, OPERATION command, or their combination, to process this command. If this command is sent while either PWM controller is operating, the L TC3882-1 will NACK the command byte, ignore the command and its data, and assert a BUSY fault. Supported Values: BIT MEANING 7 (Reserved, must write as 0). 6 (Reserved, must write as 0). 5 (Reserved).

4 SHARE_CLK configuration:

0: SHARE_CLK continuously enabled once VINSNS ≥ VIN_ON after initialization. 1: SHARE_CLK always forced low if VINSNS ≤ VIN_OFF , then held low until VINSNS ≥ VIN_ON. 3 (Reserved). 2:0 Value Phase Maximum Duty CycleChannel 0 Channel 1 111b 135° 315° 87.5% 110b 90° 270° 101b 45° 225° 100b 0° 180° 011b 120° 300° 83.3% 010b 60° 240° 001b 0° 180° 000b 0° 120° Phase is expressed from the falling edge of SYNC to the falling edge of PWM. This command has one data byte. PMBus COMMAND DETAILS (PWM Configuration)

Rev A For more information www.analog.com MFR_CHAN_CONFIG_LTC3882-1 The MFR_CHAN_CONFIG_L TC3882-1 command provides per-channel configuration common to multiple L TC PMBus products. Bit Definitions: BIT MEANING 7:5 (Reserved).

4 RUN pin control:

0: When the channel is commanded off, the associated RUN pin is pulsed low for TOFF_DELAY + TOFF_FALL + 136ms (or MFR_RESTART_DELAY, if longer) regardless of the state of bit 3. 1: RUN pin is not pulsed low if channel is commanded off.

3 Short cycle control:

0: No special control. Device attempts to follow on/off commands exactly as issued. 1: Output is immediately disabled if commanded back on while waiting for TOFF_DELAY or TOFF_F ALL to expire. A minimum off time of 120ms is then enforced before the channel is turned back on. Additional delay will apply if bit 4 is clear .

2 SHARE_CLK output control:

0: No special control. 1: Output disabled if SHARE_CLK is held low. 1 (Reserved, must write as 0).

0 MFR_RETRY_DELAY control:

0: Output decay to 12.5% of programmed value required for retry after ANY action that turns off the rail. 1: Output decay not required for retry. This command has one data byte. PMBus COMMAND DETAILS (PWM Configuration)

Rev AFor more information www.analog.com MFR_PWM_MODE_LTC3882-1 The MFR_PWM_MODE_L TC3882-1 command sets important PWM controls for each channel. The addressed channel(s) must be turned off by its RUN pin, OPERATION command, or their combination, when this command is issued. Oth- erwise the L TC3882-1 will NACK the command byte, ignore the command and its data, and assert a BUSY fault. When bit 5 is cleared, the L TC3882-1 computes temperature in °C from ∆VBE measured by the ADC at the TSNSn pin as When bit 5 is set, the L TC3882-1 computes temperature in °C from TSNSn voltage measured by the ADC as For both equations, G = MFR_TEMP_1_GAIN • 2–14, and O = MFR_TEMP_1_OFFSET Supported Values: BIT MEANING

7 Output voltage range select:

0: Maximum VOUT = 5.25V . 1: Maximum VOUT = 2.65V . 6* Enable V OUT servo.

5 External temperature sense:

0: ∆VBE measurement. 1: Direct voltage measurement. 4:3 BOOST refresh width: 11b: 250ns 10b: 125ns 01b: 50ns 00b: 25ns 2 (Reserved).

1 PWM control protocol:

0: 3-State PWM output. 1: 3-State PWM output with no DCM (including soft-start) or hardware ROC response (including OV).

0 PWM mode:

0: Forced continuous inductor current. 1: Discontinuous inductor current. *This bit is ignored (servo disabled) if MFR_VOUT_AVP for this channel is programmed to a value greater than 0.0%. This command has one data byte. PMBus COMMAND DETAILS (PWM Configuration)

Rev A For more information www.analog.com VIN_ON The VIN_ON command sets the input voltage, in volts, required to start power conversion. This command has two data bytes in Linear_5s_11s format. VIN_OFF The VIN_OFF command sets the minimum input voltage, in volts, at which power conversion stops. This command has two data bytes in Linear_5s_11s format. VIN_OV_FAULT_LIMIT The VIN_OV_FAUL T_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes an input overvoltage fault. This command has two data bytes in Linear_5s_11s format. VIN_UV_WARN_LIMIT The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input under- voltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON command and the unit has been enabled. If the VIN_UV_WARN_LIMIT is then exceeded, the device: Sets the INPUT Bit in the STA TUS_WORD

• Sets the VIN Undervoltage Warning Bit in the STATUS_INPUT Command
• Notifies the Host by Asserting ALER T, Unless Masked INPUT VOL TAGE AND LIMITS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VIN_ON 0x35 Minimum input voltage to begin power conversion. R/W Word N L11 V l 6.5V 0xCB40 VIN_OFF 0x36 Decreasing input voltage at which power conversion stops. R/W Word N L11 V l 6.0V 0xCB00 VIN_OV_FAUL T_LIMIT 0x55 V IN overvoltage fault limit. R/W Word N L11 V l 15.5V 0xD3E0 VIN_UV_WARN_LIMIT 0x58 VIN undervoltage warning limit. R/W Word N L11 V l 6.3V 0xCB26 Related commands: STA TUS_INPUT , SMBALERT_MASK, READ_VIN, VIN_OV_FAUL T_RESPONSE PMBus COMMAND DETAILS (Input Voltage and Limits)

Rev AFor more information www.analog.com OUTPUT VOL TAGE AND LIMITS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VOUT_MODE 0x20 Output voltage format and exponent. R Byte Y Reg 2–12 0x14 VOUT_COMMAND 0x21 Nominal V OUT value. R/W Word Y L16 V l 1.0V 0x1000 MFR_VOUT_MAX 0xA5 Maximum value of any V OUT-related command. R Word Y L16 V l 5.6V 0x599A VOUT_MAX 0x24 Maximum V OUT that can be set by any command, including margin. R/W Word Y L16 V l 5.5V 0x5800 MFR_VOUT_AVP 0xD3 Specify VOUT load line. R/W Word Y L11 % l 0% 0x8000 VOUT_MARGIN_HIGH 0x25 V OUT at high margin, must be greater than VOUT_COMMAND. R/W Word Y L16 V l 1.05V 0x10CD VOUT_MARGIN_LOW 0x26 V OUT at low margin, must be less than VOUT_COMMAND. R/W Word Y L16 V l 0.95V 0x0F33 VOUT_OV_FAUL T_LIMIT 0x40 V OUT overvoltage fault limit. R/W Word Y L16 V l 1.1V 0x119A VOUT_OV_WARN_LIMIT 0x42 VOUT overvoltage warning limit. R/W Word Y L16 V l 1.075V 0x1133 VOUT_UV_WARN_LIMIT 0x43 VOUT undervoltage warning limit. R/W Word Y L16 V l 0.925V 0x0ECD VOUT_UV_FAUL T_LIMIT 0x44 V OUT undervoltage fault limit. R/W Word Y L16 V l 0.9V 0x0E66 Related commands: OPERATION, ST ATUS_WORD, STATUS_VOUT , SMBALERT_MASK, READ_VOUT , MFR_VOUT_PEAK, READ_POUT , VOUT_OV_FAUL T_ RESPONSE, VOUT_UV_FAUL T_RESPONSE PMBus COMMAND DETAILS (Output Voltage and Limits) VOUT_MODE The VOUT_MODE command gives the format used by the L TC3882-1 for output voltage related commands. Only Linear Mode is supported, with a mantissa expressed in microvolts. Sending the VOUT_MODE command to the L TC3882-1 using a write protocol will result in a CML fault. This read-only command has one data byte. VOUT_COMMAND The VOUT_COMMAND is used to set the output voltage in volts (no load value if AVP is enabled). Execution of this command is delayed until any on-going TON_RISE or TOFF_FALL output sequencing is completed, otherwise the output voltage moves to a new value at VOUT_TRANSITION_RATE. This command has two data bytes in Linear_16u format. MFR_VOUT_MAX The MFR_VOUT_MAX command returns the maximum value, in volts, allowed for any V OUT-related command, in - cluding VOUT_OV_FAUL T_LIMIT . This value represents the maximum regulated voltage the selected channel could be capable of producing. This read-only command has two data bytes in Linear_16u format.

Rev A For more information www.analog.com PMBus COMMAND DETAILS (Output Voltage and Limits) VOUT_MAX The VOUT_MAX command sets an upper limit, in volts, on the allowed value of any command that sets the output voltage, including VOUT_MARGIN_HIGH. Setting VOUT_MAX to a value greater than MFR_VOUT_MAX will result in a CML fault and VOUT_MAX will be set to the value of MFR_VOUT_MAX. A VOUT_MAX warning may also be gener - ated if VOUT_MAX is set above 5.5V in output range 0 or above 2.75V in range 1. This command ensures that any combination of commands attempting to set V OUT above VOUT_MAX will result in a warning with the output clamped at VOUT_MAX. When a VOUT_MAX warning occurs, the device takes the following actions:

• Sets The Offending Command Value to the V oltage Specified by VOUT_MAX
• Sets the VOUT Bit in the STA TUS_WORD
• Sets the VOUT_MAX Warning Bit in the ST ATUS_VOUT Command
• Notifies the Host by Asserting ALER T, Unless Masked This command has two data bytes in Linear_16u format. MFR_VOUT_AVP The MFR_VOUT_AVP command sets the change in output voltage, in percent, for a full-scale change in output current. MFR_VOUT_AVP can be used for active voltage positioning (AVP) requirements or passive current sharing schemes. The L TC3882-1 interprets the IOUT_OC_WARN_LIMIT value as full-scale current for AVP . If MFR_VOUT_AVP is non- zero, VOUT_COMMAND sets the maximum, no-load output voltage and servo mode for that channel is automatically disabled. Setting MFR_VOUT_AVP to 0.0% automatically disables the AVP function. Refer to the Applications Informa- tion section for additional details on range and resolution when using MFR_VOUT_AVP . This command has two data bytes in Linear_5s_11s format. VOUT_MARGIN_HIGH The VOUT_MARGIN_HIGH command programs the output voltage, in volts, to be produced when Margin High is set with the OPERA TION command (no load value if AVP is enabled). The value must be greater than VOUT_ COMMAND. This command has two data bytes in Linear_16u format. VOUT_MARGIN_LOW The VOUT_MARGIN_LOW command programs the output voltage, in volts, to be produced when Margin Low is set by the OPERATION command (no load value if AVP is enabled). The value must be less than VOUT_COMMAND. This command has two data bytes in Linear_16u format. VOUT_OV_FAULT_LIMIT The VOUT_OV_FAUL T_LIMIT command sets the value of the output voltage measured by the OV supervisor at the VSENSE± pins, in volts, which causes an output overvoltage fault. If VOUT_OV_FAUL T_LIMIT is modified while the channel is on, 10ms should be allowed for the new value to take effect. Modifying VOUT during that time can result an erroneous OV fault. The L TC3882-1 sets MFR_COMMON bits[6:5] low while it establishes the new VOUT_OV_FAUL T_LIMIT value. This command has two data bytes in Linear_16u format.

Rev AFor more information www.analog.com VOUT_OV_WARN_LIMIT The VOUT_OV_WARN_LIMIT command sets the value, in volts, of the output voltage measured by the ADC at the VSENSE± pins that causes an output overvoltage warning. If the VOUT_OV_WARN_LIMIT is exceeded, the device:

• Sets the VOUT Bit in the STA TUS_WORD
• Sets the VOUT Overvoltage Warning Bit in the STATUS_VOUT Command
• Notifies the Host by Asserting ALER T, Unless Masked This command has two data bytes in Linear_16u format. VOUT_UV_WARN_LIMIT The VOUT_UV_WARN_LIMIT command sets the value, in volts, of the output voltage measured by the ADC at the VSENSE± pins that causes an output undervoltage warning. If the VOUT_UV_WARN_LIMIT is exceeded, the device:
• Sets the VOUT Bit in the STA TUS_WORD
• Sets the VOUT Undervoltage Warning Bit in the STATUS_VOUT Command
• Notifies the Host by Asserting ALER T, Unless Masked This command has two data bytes in Linear_16u format. VOUT_UV_FAULT_LIMIT The VOUT_UV_FAUL T_LIMIT command sets the value of the output voltage measured by the UV supervisor at the VSENSE± pins, in volts, which causes an output undervoltage fault. This command has two data bytes in Linear_16u format. PMBus COMMAND DETAILS (Output Voltage and Limits)

Rev A For more information www.analog.com IOUT_CAL_GAIN The IOUT_CAL_GAIN command is used to set the resistance value of the output current sense element in milliohms. This command has two data bytes in Linear_5s_11s format. MFR_IOUT_CAL_GAIN_TC The MFR_IOUT_CAL_GAIN_TC command sets the temperature coefficient of the output current sense element in ppm/°C. Effective sense resistance, in milliohms, is computed by the L TC3882-1 as RSENSE = IOUT_CAL_GAIN • (1 + 1E-6 • MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1 – 27)) This command has two data bytes representing a 2’s compliment integer . IOUT_OC_FAULT_LIMIT The IOUT_OC_FAUL T_LIMIT command sets the value of the instantaneous peak output current, in amperes, which will cause the OC supervisor to detect an output overcurrent fault. The L TC3882-1 uses the computed effective sense resistance and the voltage across the I SENSE± inputs to determine the output current. The programmed limit voltage is rounded to the nearest 0.4mV in a range from 0.0mV to 80.0mV . Output overcurrent faults are ignored during TON_RISE and TOFF_FALL output sequencing. This command has two data bytes in Linear_5s_11s format. IOUT_OC_WARN_LIMIT The IOUT_OC_WARN_LIMIT command sets the value of the output current measured by the ADC, in amperes, that causes an output overcurrent warning. To provide meaningful responses, this value should be set below IOUT_OC_FAUL T_LIMIT minus 1/2 of the maximum anticipated ripple current. If the IOUT_OC_WARN_LIMIT is exceeded, the device: Sets the IOUT Bit in the STA TUS_WORD

• Sets the IOUT Overcurrent Warning Bit in the STATUS_IOUT Command
• Notifies the Host by Asserting ALER T, Unless Masked Output overcurrent warnings are ignored during TON_RISE and TOFF_FALL output sequencing. This command has two data bytes in Linear_5s_11s format. OUTPUT CURRENT AND LIMITS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE IOUT_CAL_GAIN 0x38 Ratio of I SENSE± voltage to sensed current. R/W Word Y L11 mΩ l 0.63mΩ 0xB285 MFR_IOUT_CAL_GAIN_TC 0xF6 Output current sense element temperature coefficient. R/W Word Y CF ppm/°C l 3900ppm/°C 0x0F3C IOUT_OC_FAUL T_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A l 29.75A 0xDBB8 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A l 20.0A 0xDA80 Related commands: STA TUS_IOUT , SMBALERT_MASK, READ_IOUT , MFR_IOUT_PEAK, READ_POUT , IOUT_OC_FAUL T_RESPONSE, MFR_VOUT_AVP PMBus COMMAND DETAILS (Output Current and Limits)

Rev AFor more information www.analog.com These commands can be used to establish required on/off sequencing for any number of system power supply rails. MFR_RESTART_DELAY The MFR_RESTART DELAY command specifies the minimum PWM off time (RUN low) in milliseconds. The L TC3882-1 will actively hold its RUN pin low for this length of time if a falling RUN edge is detected. After this delay, a standard start-up sequence can be initiated. A minimum of TOFF_DELAY + TOFF_FALL + 136ms is recommended for this com- mand value. Valid value range is 136ms to 65.52 seconds. The L TC3882-1 uses a resolution of 16ms for this command and will not produce delays outside of this range. This command has two data bytes in Linear_5s_11s format. TON_DELAY The TON_DELA Y command sets the delay, in milliseconds, between a start condition and the beginning of the output voltage rise. Values from 0ms to 83 seconds are considered valid, and the L TC3882-1 will not produce delays outside of this range. This command has two data bytes in Linear_5s_11s format. TON_RISE The TON_RISE command sets the desired time, in milliseconds, from the point the output starts to rise until it enters the regulation band. Values from 0 seconds to 1.3 seconds are considered valid, and the L TC3882-1 will not produce rise times outside of this range. Values of TON_RISE less than 0.25ms or resulting slopes greater than 4V/ms will result in an output step to the commanded voltage limited only by PWM analog loop response. This command has two data bytes in Linear_5s_11s format. OUTPUT TIMING, DELAYS, AND RAMPING COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_RESTART_DELAY 0xDC Minimum time RUN pin is held low by the L TC3882-1. R/W Word Y L11 ms l 500ms 0xFBE8 TON_DELAY 0x60 Delay from RUN pin or OPERATION on command to TON_RISE ramp start. R/W Word Y L11 ms l 0.0ms 0x8000 TON_RISE 0x61 T ime for VOUT to rise from 0V to VOUT_COMMAND after TON_DELAY. R/W Word Y L11 ms l 8.0ms 0xD200 TON_MAX_FAUL T_LIMIT 0x62 Maximum time for V OUT to rise above VOUT_UV_FAUL T_LIMIT after TON_DELAY. R/W Word Y L11 ms l 10.0ms 0xD280 VOUT_TRANSITION_RATE 0x27 V OUT slew rate for programmed output changes. R/W Word Y L11 V/ms l 0.25V/ms 0xAA00 TOFF_DELAY 0x64 Delay from RUN pin or OPERATION off command to TOFF_FALL ramp start. R/W Word Y L11 ms l 0.0ms 0x8000 TOFF_FALL 0x65 Time for VOUT to fall to 0V from VOUT_COMMAND after TOFF_DELAY. R/W Word Y L11 ms l 8.0ms 0xD200 TOFF_MAX_WARN_LIMIT 0x66 Maximum time for V OUT to decay below 12.5% of VOUT_COMMAND after TOFF_FALL completes. R/W Word Y L11 ms l 150ms 0xF258 Related commands: MFR_RETRY_DELA Y, STATUS_VOUT , SMBALERT_MASK, TON_MAX_FAUL T_RESPONSE, MFR_CHAN_CONFIG_L TC3882-1, MFR_PWM_MODE_L TC3882-1 PMBus COMMAND DETAILS (Output Timing, Delays, and Ramping)

Rev A For more information www.analog.com TON_MAX_FAULT_LIMIT The TON_MAX_FAUL T_LIMIT command sets the maximum time, in milliseconds, the unit is allowed from the beginning of TON_RISE to power up the output without passing VOUT_UV_FAUL T_LIMIT . A value of 0ms means there is no limit and the unit can attempt to bring up the output voltage indefinitely. The maximum allowed TON_MAX is 8 seconds. This command has two data bytes in Linear_5s_11s format. VOUT_TRANSITION_RATE The VOUT_TRANSITION_RATE command sets the rate at which the output voltage changes, in volts per millisecond (or mV/µs), in response to a VOUT_COMMAND or OPERATION (margin) command. This rate of change does not ap- ply to operations that fully turn the PWM channel on or off. Values from 1mV/ms to 4V/ms are considered valid. The LTC3882-1 will not produce V OUT transitions slower than 1mV/ms, and values exceeding 4V/ms cause the device to transition the output as quickly as possible, limited only by PWM analog loop response. This command has two data bytes in Linear_5s_11s format. TOFF_DELAY The TOFF_DELAY command sets the delay, in milliseconds, between a stop condition and the beginning of the output voltage fall. Values from 0s to 16s are considered valid. This command has two data bytes in Linear_5s_11s format. TOFF_FALL The TOFF_FALL command sets the time, in milliseconds, from the end of TOFF_DELAY until the output voltage is com- manded fully to zero. The part attempts to linearly reduce the commanded output voltage to zero during TOFF_FALL. At the end of this period, the PWM output is disabled. The part will maintain its programmed P WM operating mode during TOFF_FALL. Using continuous conduction mode will produce a well defined VOUT ramp off but may result in negative output current. The minimum supported fall time is 0.25ms, or any value that results in a rate of fall exceeding 4V/ms. Programmed values less than this will result in a commanded 0.25ms ramp, possibly limited by PWM analog loop response. Maximum fall time is 1.3 seconds. In discontinuous conduction mode, the controller will not be able to draw current from the load and fall time will be set by output capacitance and load current. This command has two data bytes in Linear_5s_11s format. TOFF_MAX_WARN_LIMIT The TOFF_MAX_WARN_LIMIT command sets the time, in milliseconds, the unit is allotted to have the output off after TOFF_FALL completes before a warning is issued. The output is considered off when V OUT is less than 12.5% of the VOUT_COMMAND value. A data value of 0ms means there is no limit and the unit can attempt to turn the output off indefinitely. There is also no limit enforced if bit 0 of MFR_CHAN_CONFIG_L TC3882-1 is set. This command has two data bytes in Linear_5s_11s format. PMBus COMMAND DETAILS (Output Timing, Delays and Ramping)

Rev AFor more information www.analog.com MFR_TEMP_1_GAIN The MFR_TEMP_1_GAIN command sets the slope used in the calculation of external temperature to account for non- idealities in the element and remote sensing errors, if any. Refer to the MFR_PWM_MODE_L TC3882-1 command for equation details. This command has two data bytes representing a 2’s complement integer . MFR_TEMP_1_OFFSET The MFR_TEMP_1_OFFSET command sets the offset used in the calculation of external temperature to account for non-idealities in the element and remote sensing errors, if any. The unit of measure for MFR_TEMP1_OFFSET depends on bit 5 of MFR_PWM_MODE. MFR_TEMP1_ OFFSET is expressed volts if this bit is set and in °C otherwise. Refer to the MFR_PWM_MODE_ L TC3882-1 command for equation details. This command has two data bytes in Linear_5s_11s format. OT_FAULT_LIMIT The OT_FAUL T_LIMIT command sets the value of sensed external temperature, in degrees Celsius, which causes an overtemperature fault. This command has two data bytes in Linear_5s_11s format. OT_WARN_LIMIT The OT_WARN_LIMIT command sets the value of sensed external temperature, in degrees Celsius, which causes an overtemperature warning. If the OT_WARN_LIMIT is exceeded, the device: Sets the TEMPERATURE Bit in the ST ATUS_BYTE

• Sets the Overtemperature Warning Bit in the ST ATUS_TEMPERATURE Command
• Notifies the Host by Asserting ALER T, Unless Masked This command has two data bytes in Linear_5s_11s format. EXTERNAL TEMPERATURE AND LIMITS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_TEMP_1_GAIN 0xF8 Set slope for external temperature calculations. R/W Word Y CF l 1.0 0x4000 MFR_TEMP_1_OFFSET 0xF9 Offset addend for external temperature calculations. R/W Word Y L11 °C or V l 0.0 0x8000 OT_FAUL T_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 °C l 100.0°C 0xEB20 OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 °C l 85.0°C 0xEAA8 UT_FAUL T_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 °C l –40.0°C 0xE580 Related commands: STA TUS_TEMPERATURE, SMBALERT_MASK, MFR_TEMPERATURE1_PEAK, OT_FAUL T_RESPONSE, UT_FAUL T_RESPONSE, STATUS_MFR_SPECIFIC, READ_TEMPERATURE_2, MFR_OT_FAUL T_RESPONSE, MFR_PWM_MODE_L TC3882-1 PMBus COMMAND DETAILS (External Temperature and Limits)

Rev A For more information www.analog.com UT_FAULT_LIMIT The UT_FAUL T_LIMIT command sets the value of sensed external temperature, in degrees Celsius, which causes an undertemperature fault. This command has two data bytes in Linear_5s_11s format. STATUS_BYTE The STATUS_BYTE command returns a one-byte summary of the most critical faults. STATUS_BYTE Message Contents: BIT STATUS BIT NAME MEANING 7* BUSY A fault was declared because the L TC3882-1 was unable to respond. 6 OFF This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled. 5 VOUT_OV An output overvoltage fault has occurred. 4 IOUT_OC An output overcurrent fault has occurred. 3 VIN_UV Not supported (L TC3882-1 returns 0). 2 TEMPERATURE A temperature fault or warning has occurred. 1 CML A communications, memory or logic fault has occurred. 0* NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred. *ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_FAUL TS command. This command has one data byte. STATUS REPORTING COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE STATUS_BYTE 0x78 One-byte channel status summary. R/W Byte Y Reg STATUS_WORD 0x79 T wo-byte channel status summary. R/W Word Y Reg STATUS_VOUT 0x7A V OUT fault and warning status. R/W Byte Y Reg STATUS_IOUT 0x7B I OUT fault and warning status. R/W Byte Y Reg STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg STATUS_TEMPERATURE 0x7D External temperature fault and warning status. R/W Byte Y Reg STATUS_CML 0x7E Communication, memory and logic fault and warning status. R/W Byte N Reg STATUS_MFR_SPECIFIC 0x80 L TC3882-1-specific status. R/W Byte Y Reg MFR_PADS_L TC3882-1 0xE5 State of selected L TC3882-1 pads. R Word N Reg MFR_COMMON 0xEF L TC-generic device status reporting. R Byte N Reg CLEAR_FAUL TS 0x03 Clear all set fault bits. Send Byte N MFR_INFO 0xB6 Manufacturer Specific Information R Word N Reg Refer to Figure 2 for a graphical depiction of these register contents and their relationships. PMBus COMMAND DETAILS (External Temperature Limits)

Rev AFor more information www.analog.com STATUS_WORD The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the STA- TUS_WORD is the same as the STATUS_BYTE command. STATUS_WORD High Byte Message Contents: BIT STATUS BIT NAME MEANING 15 VOUT An output voltage fault or warning has occurred. 14 IOUT An output current fault or warning has occurred. 13 INPUT An input voltage fault or warning has occurred. 12 MFR_SPECIFIC A fault or warning specific to the L TC3882-1 has occurred. 11 POWER_GOOD# The POWER_GOOD state is false if this bit is set. 10 FANS Not supported (L TC3882-1 returns 0). 9 OTHER Not supported (L TC3882-1 returns 0). 8 UNKNOWN Not supported (L TC3882-1 returns 0). This command has two data bytes. STATUS_VOUT The STATUS_VOUT command returns one byte of VOUT status information. STATUS_VOUT Message Contents: BIT MEANING 7 V OUT overvoltage fault. 6 V OUT overvoltage warning. 5 V OUT undervoltage warning. 4 V OUT undervoltage fault. 3 VOUT_MAX warning. 2 TON_MAX fault. 1 TOFF_MAX warning. 0 Not supported by the L TC3882-1 (returns 0). ALERT can be asserted if any of bits[7:1] are set. These may be cleared by writing a 1 to their bit position in STATUS_VOUT , in lieu of a CLEAR_FAUL TS command. This command has one data byte. STATUS_IOUT The STATUS_IOUT command returns one byte of IOUT status information. STATUS_IOUT Message Contents: BIT MEANING 7 I OUT overcurrent fault. 6 Not supported (L TC3882-1 returns 0). 5 I OUT overcurrent warning. 4:0 Not supported (L TC3882-1 returns 0). ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_IOUT , in lieu of a CLEAR_FAUL TS command. This command has one data byte. PMBus COMMAND DETAILS (Status Reporting)

Rev A For more information www.analog.com STATUS_INPUT The STATUS_INPUT command returns one byte of VIN (VINSNS) status information. STATUS_INPUT Message Contents: BIT MEANING 7 V IN overvoltage fault. 6 Not supported (L TC3882-1 returns 0). 5 V IN undervoltage warning. 4 Not supported (L TC3882-1 returns 0).

3 Unit off for insufficient V

IN. 2:0 Not supported (L TC3882-1 returns 0). ALERT can be asserted if bit 7 is set. Bit 7 may be cleared by writing it to a 1, in lieu of a CLEAR_FAUL TS command. This command has one data byte. STATUS_TEMPERATURE The STATUS_TEMPERATURE command returns one byte of sensed external temperature status information. STATUS_TEMPERATURE Message Contents: BIT MEANING 7 External overtemperature fault. 6 External overtemperature warning. 5 Not supported (L TC3882-1 returns 0). 4 External undertemperature fault. 3:0 Not supported (L TC3882-1 returns 0). ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_TEMPERATURE, in lieu of a CLEAR_FAUL TS command. This command has one data byte. STATUS_CML The STATUS_CML command returns one byte of status information on received commands, internal memory and logic. STATUS_CML Message Contents: BIT MEANING 7 Invalid or unsupported command received. 6 Invalid or unsupported data received. 5 Packet error check failed. 4 Memory fault detected. 3 Processor fault detected. 2 Reserved (L TC3882-1 returns 0). 1 Other communication fault. 0 Other memory or logic fault. ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_CML, in lieu of a CLEAR_FAUL TS command. This command has one data byte. PMBus COMMAND DETAILS (Status Reporting)

Rev AFor more information www.analog.com STATUS_MFR_SPECIFIC The STATUS_MFR_SPECIFIC command returns one byte with L TC3882-1-specific status information. STATUS_MFR_SPECIFIC Message Contents: BIT MEANING 7 Internal temperature fault (>160°C). 6 Internal temperature warning (>130°C). 5 EEPROM CRC error . 4 Internal PLL unlocked. 3 Fault log present. 2 Not supported (L TC3882-1 returns 0). 1 Output short cycled. 0 FAUL T low. If any supported bits are set, the MFR bit in the STATUS_WORD will be set and ALERT may be asserted. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_MFR_SPECIFIC, in lieu of a CLEAR_FAUL TS command. This command has one data byte. MFR_PADS_LTC3882-1 The MFR_PADS_L TC3882-1 command provides status of the L TC3882-1 digital I/O and control pins, in addition to general output voltage conditions. MFR_PADS_L TC3882-1 Message Contents: BIT MEANING 15 Channel 1 is a slave. 14 Channel 0 is a slave. 13:12 Not supported (L TC3882-1 returns 0). 11 ADC results for I OUT may be invalid. 10 SYNC output disabled externally. 9 Channel 1 POWER_GOOD (normally returns 1 if slave). 8 Channel 0 POWER_GOOD (normally returns 1 if slave). 7 L TC3882-1 forcing RUN1 low. 6 L TC3882-1 forcing RUN0 low. 5 RUN1 pin state. 4 RUN0 pin state. 3 L TC3882-1 forcing FAUL T1 low. 2 L TC3882-1 forcing FAUL T0 low. 1 FAUL T1 pin state. 0 FAUL T0 pin state. This read-only command has two data bytes. PMBus COMMAND DETAILS (Status Reporting)

Rev A For more information www.analog.com MFR_COMMON The MFR_COMMON command contains status bits that are common to multiple L TC PMBus products. MFR_COMMON Message Contents: BIT MEANING 7 L TC3882-1 not forcing ALERT low. 6 L TC3882-1 not BUSY. 5 L TC3882-1 calculations not pending. 4 L TC3882-1 output not in transition. 3 L TC3882-1 EEPROM initialized. 2 Not supported (L TC3882-1 returns 0). 1 SHARE_CLK timeout. 0 Not supported (L TC3882-1 returns 0). This read-only command has one data byte. MFR_INFO The MFR_INFO command contains additional status bits that are L TC3882-1-specific and may be common to multiple L TC PSM products. MFR_INFO Data Contents: BIT MEANING 15:6 Reserved. 5 EEPROM ECC status. 0: Corrections have been made in the EEPROM user space. 1: No corrections have been made in the EEPROM user space. 4:0 Reserved EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM bulk read operation. This read-only command has two data bytes. CLEAR_FAULTS The CLEAR_FAUL TS command clears any fault bits that have been set and deasserts (releases) the ALERT pin. This command clears all bits in all status commands simultaneously. CLEAR_FAUL TS does not cause a channel that has latched off for a fault condition to restart. Channels that are latched off for a fault condition are restarted when the output is commanded to turn off and then on through the OPERATION command or RUN pins, or IC supply power is cycled. If a fault is still present when CLEAR_FAUL TS is commanded, that fault bit will immediately be set and ALERT again asserted low. This write-only command has no data bytes. PMBus COMMAND DETAILS (Status Reporting)

Rev AFor more information www.analog.com TELEMETRY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE READ_VIN 0x88 Measured V IN. R Word N L11 V MFR_VIN_PEAK 0xDE Maximum V IN measurement since last MFR_CLEAR_PEAKS. R Word N L11 V READ_VOUT 0x8B Measured V OUT. R Word Y L16 V MFR_VOUT_PEAK 0xDD Maximum V OUT measurement since last MFR_CLEAR_PEAKS. R Word Y L16 V READ_IOUT 0x8C Measured I OUT. R Word Y L11 A MFR_IOUT_PEAK 0xD7 Maximum I OUT measurement since last MFR_CLEAR_PEAKS. R Word Y L11 A READ_POUT 0x96 Calculated output power . R Word Y L11 W READ_TEMPERATURE_1 0x8D Measured external temperature. R Word Y L11 °C MFR_TEMPERATURE_1_PEAK 0xDF Maximum external temperature measurement since last MFR_CLEAR_PEAKS. R Word Y L11 °C READ_TEMPERATURE_2 0x8E Measured internal temperature. R Word N L11 °C MFR_TEMPERATURE_2_PEAK 0xF4 Maximum internal temperature measurement since last MFR_CLEAR_PEAKS. R Word N L11 °C READ_DUTY_CYCLE 0x94 Measured commanded PWM duty cycle. R Word Y L11 % READ_FREQUENCY 0x95 Measured PWM input clock frequency. R Word Y L11 kHz MFR_CLEAR_PEAKS 0xE3 Clear all peak values. Send Byte N Related commands: IOUT_CAL_GAIN, MFR_IOUT_CAL_GAIN_TC, MFR_PWM_MODE_L TC3882-1 READ_VIN The READ_VIN command returns the input voltage measured between VINSNS and GND in volts. This read-only command has two data bytes in Linear_5s_11s format. MFR_VIN_PEAK The MFR_VIN_PEAK command reports the highest voltage, in volts, measured for READ_VIN. This peak value can be reset by a MFR_CLEAR_PEAKS command. This read-only command has two data bytes in Linear_5s_11s format. READ_VOUT The READ_VOUT command returns the output voltage measured at the V SENSE± pins in volts. This read-only command has two data bytes in Linear_16u format. MFR_VOUT_PEAK The MFR_VOUT_PEAK command reports the highest voltage, in volts, measured for READ_VOUT . This peak value can be reset by a MFR_CLEAR_PEAKS command. This read-only command has two data bytes in Linear_16u format. PMBus COMMAND DETAILS (Status Reporting)

Rev A For more information www.analog.com READ_IOUT The READ_IOUT command returns the output current in amperes. This value is computed from: The differential voltage measured across the ISENSE± pins

• The IOUT_CAL_GAIN value
• The MFR_IOUT_CAL_GAIN_TC value
• The READ_TEMPERATURE_1 value
• The MFR_TEMP_1_GAIN value
• The MFR_TEMP_1_OFFSET value This read-only command has two data bytes in Linear_5s_11s format. MFR_IOUT_PEAK The MFR_IOUT_PEAK command reports the highest current, in amperes, calculated for READ_IOUT . This peak value can be reset by a MFR_CLEAR_PEAKS command. This read-only command has two data bytes in Linear_5s_11s format. READ_POUT The READ_POUT command reports the output power in watts. The value is calculated from the product of the most recent correlated output voltage and current readings. This read-only command has two data bytes in Linear_5s_11s format. READ_TEMPERA TURE_1 The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element. This read-only command has two data bytes in Linear_5s_11s format. MFR_TEMPERATURE_1_PEAK The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, calculated for READ_TEMPERATURE_1. This peak value can be reset by a MFR_CLEAR_PEAKS command. This read-only command has two data bytes in Linear_5s_11s format. READ_TEMPERATURE_2 The READ_TEMPERATURE_2 command returns the L TC3882-1 internal temperature in degrees Celsius. This read-only command has two data bytes in Linear_5s_11s format. PMBus COMMAND DETAILS (Telemetry)

Rev AFor more information www.analog.com MFR_TEMPERATURE_2_PEAK The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, calculated for READ_TEMPERATURE_2. This peak value can be reset by a MFR_CLEAR_PEAKS command. This read-only command has two data bytes in Linear_5s_11s format. READ_DUTY_CYCLE The READ_DUTY_CYCLE command returns the duty cycle of the PWM control in percent. This will not be the exact duty cycle of the PWM switch node due to efficiency losses in the power stage and current consumption of the L TC3882-1 itself. This read-only command has two data bytes in Linear_5s_11s format. READ_FREQUENCY The READ_FREQUENCY command returns the switching frequency supplied to the internal PLL in kilohertz, whether derived internally or provided by external clock on the SYNC pin. This may not be the actual PWM output switching frequency during certain exception processing, such as an output overcurrent condition. This read-only command has two data bytes in Linear_5s_11s format. MFR_CLEAR_PEAKS The MFR_CLEAR_PEAKS command resets all stored _PEAK values. The L TC3882-1 determines new peak values after this command is received. This write-only command has no data bytes. PMBus COMMAND DETAILS (Telemetry)

Rev A For more information www.analog.com FAUL T RESPONSE AND COMMUNICATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VIN_OV_FAUL T_RESPONSE 0x56 V IN overvoltage fault response. R/W Byte Y Reg l 0x80 VOUT_OV_FAUL T_RESPONSE 0x41 V OUT overvoltage fault response. R/W Byte Y Reg l 0xB8 VOUT_UV_FAUL T_RESPONSE 0x45 V OUT undervoltage fault response. R/W Byte Y Reg l 0xB8 IOUT_OC_FAUL T_RESPONSE 0x47 Output overcurrent fault response. R/W Byte Y Reg l 0x00 OT_FAUL T_RESPONSE 0x50 External overtemperature fault response. R/W Byte Y Reg l 0xB8 UT_FAUL T_RESPONSE 0x54 External undertemperature fault response. R/W Byte Y Reg l 0xB8 MFR_OT_FAUL T_RESPONSE 0xD6 Internal overtemperature fault response. R/W Byte N Reg l 0xC0 TON_MAX_FAUL T_RESPONSE 0x63 Fault response when TON_MAX_FAUL T_LIMIT is exceeded. R/W Byte Y Reg l 0xB8 MFR_RETRY_DELAY 0xDB Minimum time before retry after a fault. R/W Word N L11 ms l 350ms 0xFABC SMBALERT_MASK 0x1B Mask ALERT Activity. Block R/W Y Reg l See CMD Details MFR_FAUL T_PROPAGATE_ L TC3882-1 0xD2 Configure status propagation via FAUL Tn pins. R/W Word Y Reg l 0x6993 MFR_FAUL T_RESPONSE 0xD5 PWM response when FAUL Tn pin is low. R/W Byte Y Reg l 0xC0 MFR_FAUL T_LOG 0xEE Read fault log data. R Block N Reg MFR_FAUL T_LOG_CLEAR 0xEC Clear existing EEPROM fault log. Send Byte N Related commands: STATUS_BYTE, STATUS_WORD, MFR_PADS_L TC3882-1, MFR_RESTART_DELAY, MFR_CHAN_CONFIG_L TC3882-1, MFR_FAUL T_ LOG_STORE, CLEAR_FAUL TS These commands detail programmable device responses for detected faults beyond the hardware-level actions described in the Operations section. L TC3882-1 hardware-level fault responses cannot be modified. Refer to Table 1 to Table 4 for details of fault log contents. PMBus warning event responses are listed under _WARN_LIMIT command details. VIN_OV_FAULT_RESPONSE The VIN_OV_FAUL T_RESPONSE command instructs the device on what action to take in response to an input overvolt- age fault. The format for this command is given in Table 13. The device also: Sets the INPUT Bit in the STA TUS_WORD

• Sets the VIN Overvoltage Fault Bit in the STATUS_INPUT Command
• Notifies the Host by Asserting ALER T, Unless Masked This command has one data byte. PMBus COMMAND DETAILS (Fault Response and Communication)

• Sets the VOUT_OV Bit in the STA TUS_BYTE
• Sets the VOUT Bit in the STA TUS_WORD
• Sets the VOUT Overvoltage Fault Bit in the STATUS_VOUT Command
• Notifies the Host by Asserting ALER T, Unless Masked This command has one data byte. VOUT_UV_FAULT_RESPONSE The VOUT_UV_FAUL T_RESPONSE command instructs the device on what action to take in response to an output undervoltage fault. The format for this command is given in Table 12. The device also:
• Sets the VOUT Bit in the STA TUS_WORD
• Sets the VOUT Undervoltage Fault Bit in the STATUS_VOUT Command,
• Notifies the Host by Asserting ALER T, Unless Masked This command has one data byte.

Table 12. Data Byte Contents for VOUT_OV_FAUL T_RESPONSE and VOUT_UV_FAUL T_RESPONSE

• Sets the corresponding fault bits in the status commands.
• Notifies the host by asserting ALER T, unless masked. The fault, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAUL TS command.
• The corresponding STA TUS_VOUT bit is written to a one.
• The output is commanded off, then on, by the RUN pin or OPERATION command.
• The device receives a RESTORE_USER_ALL command.
• The device receives an MFR_RESET command.
• IC supply power is cycled.

00 The L TC3882-1 continues to operate indefinitely with the

hardware response for the delay time specified by bits [2:0]. unit then disables the output and does attempt to restart.

10 The L TC3882-1 immediately disables the output and

responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. power supply input) is cycled.

111 The L TC3882-1 attempts to restart continuously without

limitation with an interval set by MFR_RETRY_DELAY. before the controller is disabled, depending on bits [7:6]. Hardware-level response, if any, will occur during this delay. These bits always return zero if bits [7:6] are not set to 0x2.

Rev A For more information www.analog.com IOUT_OC_FAULT_RESPONSE The IOUT_OC_FAUL T_RESPONSE command instructs the device on what action to take in response to an output overcurrent fault. The device also:

• Sets the IOUT_OC Bit in the STA TUS_BYTE
• Sets the IOUT Bit in the STA TUS_WORD
• Sets the IOUT Overcurrent Fault Bit in the STATUS_IOUT Command
• Notifies the Host by Asserting ALER T Output overcurrent faults are ignored during TON_RISE and TOFF_FALL output sequencing. Data Byte Contents for IOUT_OC_FAUL T_RESPONSE: BITS DESCRIPTION VALUE MEANING [7:6] For all values of bits [7:6], the L TC3882-1:
• Sets the corresponding fault bits in the status commands.
• Notifies the host by asserting ALER T, unless masked. The fault, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAUL TS command.
• The corresponding STA TUS_IOUT bit is written to a one.
• The output is commanded off, then on, by the RUN pin or OPERATION command.
• The device receives a RESTORE_USER_ALL command.
• The device receives an MFR_RESET command.
• IC supply power is cycled. 0x The L TC3882-1 continues to operate indefinitely with the normal hardware response described in the Operation section. The L TC3882-1 continues operating with the normal hardware response for the delay time specified by bits [2:0]. If the fault is continuously present for the entire delay, the unit then disables the output and does not attempt to restart.

11 The L TC3882-1 shuts down (disables the output) and

responds according to the retry setting in bits [5:3]. [5:3] Retry setting. 000-110 The L TC3882-1 does not attempt to restart. The output remains disabled until the fault is cleared, the device is commanded off and then on, or bias power is cycled. limitation with an interval set by MFR_RETRY_DELAY. This response persists until the unit is commanded off, bias power is removed, or another fault response forces shutdown without retry. [2:0] Delay time. xxx Response delay time in 16ms increments. This delay time determines how long the fault may have to persist before the controller is disabled, depending on bits [7:6]. These bits always return zero if bits [7:6] are not set to 0x2. Programming an unsupported IOUT_OC_FAUL T_RESPONSE value will generate a CML fault and the command will be ignored. This command has one data byte. PMBus COMMAND DETAILS (Fault Response and Communication)

Rev AFor more information www.analog.com OT_FAULT_RESPONSE The OT_FAUL T_RESPONSE command instructs the device on what action to take in response to an overtemperature fault. The format for this command is given in Table 13. The device also:

• Sets the TEMPERATURE Bit in the ST ATUS_BYTE
• Sets the Overtemperature Fault Bit in the STA TUS_TEMPERATURE Command
• Notifies the Host by Asserting ALER T, Unless Masked This command has one data byte. UT_FAULT_RESPONSE The UT_FAUL T_RESPONSE command instructs the device on what action to take in response to an undertemperature fault. The format for this command is given in Table 13. The device also:
• Sets the TEMPERATURE Bit in the ST ATUS_BYTE
• Sets the Undertemperature Fault Bit in the STA TUS_TEMPERATURE Command
• Notifies the Host by Asserting ALER T, Unless Masked This command has one data byte. MFR_OT_FAULT_RESPONSE The MFR_OT_FAUL T_RESPONSE command instructs the device on what action to take in response to an internal overtemperature fault (150°C to 160°C). The device also:
• Sets the MFR Bit in the STA TUS_WORD
• Sets the Overtemperature Fault Bit in the STA TUS_MFR_SPECIFIC Command
• Notifies the Host by Asserting ALER T, Unless Masked Supported Values: VALUE MEANING 0xC0 The L TC3882-1 continues to operate indefinitely with the normal hardware response described in the Operation section. 0x80 The L TC3882-1 shuts down immediately and does not attempt to restart. The output remains disabled until the fault is cleared and the unit is commanded off and then on, or bias power (L TC3882-1 power supply input) is cycled. Programming an unsupported MFR_OT_FAUL T_RESPONSE value will generate a CML fault and the command will be ignored. This command has one data byte. PMBus COMMAND DETAILS (Fault Response and Communication)

• Sets the VOUT Bit in the STA TUS_WORD
• Sets the TON_MAX_FAUL T Bit in the STATUS_VOUT Command
• Notifies the Host by Asserting ALER T, Unless Masked This command has one data byte.

Table 13. Data Byte Contents for the Following _FAUL T_RESPONSE Commands: VIN_OV , OT , UT and TON_MAX

• Sets the corresponding fault bits in the status commands.
• Notifies the host by asserting ALER T, unless masked. The fault, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAUL TS command.
• The corresponding fault bit is written to a one.
• The output is commanded off, then on, by the RUN pin or OPERATION command.
• The device receives a RESTORE_USER_ALL command.
• The device receives an MFR_RESET command.
• IC supply power is cycled. 00 The L TC3882-1 continues operating without interruption. Not supported. Writing this value will generate a CML fault.

10 The L TC3882-1 shuts down immediately (disables the

11 Not supported. Writing this value will generate a CML fault. commanded off and then on, or bias power is cycled. limitation with an interval set by MFR_RETRY_DELAY. [2:0] Delay time. xxx Not supported. Values ignored. The MFR_RETRY_DELAY command sets the time in milliseconds between restart attempts for all retry fault responses. leased. Legal values run from 120ms to 32.7 seconds. This command has two data bytes in Linear_5s_11s format.

Figure 52. Example of Reading SMBALERT_MASK Figure 51. Example of Setting SMBALERT_MASK SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_L TC3882-1. SMBALERT_MASK will generate a CML for Invalid/Unsupported Data. of any supported status register , again without PEC.

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Rev A For more information www.analog.com PMBus COMMAND DETAILS (Fault Response and Communication) Supported Values: BIT PROPAGATED CONDITION 15 Waiting for V OUT decay before restart. 14 V OUT short cycled (automatically deasserted 120ms after VOUT is fully OFF). 13 TON_MAX_FAUL T_LIMIT exceeded. 12 (Reserved, must be set to 0). 11 MFR_OT_FAUL T_LIMIT exceeded. 10 (Reserved, must be set to 0). 9 (Reserved, must be set to 0). 8 UT_FAUL T_LIMIT exceeded. 7 OT_FAUL T_LIMIT exceeded. 6 (Reserved). 5 (Reserved). 4 VIN_OV_FAUL T_LIMIT exceeded. 3 (Reserved). 2 IOUT_OC_FAUL T_LIMIT exceeded. 1 VOUT_UV_FAUL T_LIMIT exceeded. 0 VOUT_OV_FAUL T_LIMIT exceeded. This command has two data bytes. MFR_FAULT_RESPONSE The MFR_FAUL T_RESPONSE command instructs the device on what action to take in response to a FAUL T pin being pulled low by anything other than an internal fault. Supported Values: VALUE MEANING 0xC0 Related PWM output is immediately disabled. 0x00 Input ignored, PWM operation continues without interruption. When a FAUL T pin is low, the device also:

• Sets the MFR_SPECIFIC Bit in the STA TUS_WORD
• Sets Bit 0 in the STA TUS_MFR_SPECIFIC Command to Indicate FAUL T Is or Has Been Low
• Notifies the Host by Asserting ALER T, Unless Masked This command has one data byte.

TIMEOUT parameter is extended when this command is executed and a fault log is present. is similar to a strip chart recorder . When a fault occurs, the contents are written into EEPROM for nonvolatile storage.

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Figure 53. Fault Log Conceptual Diagram required to clear related bit 3 in STATUS_MFR_SPECIFIC. This write-only command has no data bytes.

Rev A For more information www.analog.com PMBus COMMAND DETAILS (EEPROM User Access) EEPROM USER ACCESS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE STORE_USER_ALL 0x15 Store entire operating memory in EEPROM. Send Byte N NA RESTORE_USER_ALL 0x16 Restore entire operating memory from EEPROM. Send Byte N NA MFR_COMPARE_USER_ALL 0xF0 Compare operating memory with EEPROM contents. Send Byte N MFR_FAUL T_LOG_STORE 0xEA Force transfer of fault log from operating memory to EEPROM. Send Byte N MFR_EE_UNLOCK 0xBD (contact the factory) MFR_EE_ERASE 0xBE (contact the factory) MFR_EE_DATA 0xBF (contact the factory) USER_DATA_00 0xB0 EEPROM word reserved for L TpowerPlay. R/W Word N Reg l USER_DATA_01 0xB1 EEPROM word reserved for L TpowerPlay. R/W Word Y Reg l USER_DATA_02 0xB2 EEPROM word reserved for OEM use. R/W Word N Reg l USER_DATA_03 0xB3 EEPROM word available for general data storage. R/W Word Y Reg l 0x0000 USER_DATA_04 0xB4 EEPROM word available for general data storage. R/W Word N Reg l 0x0000 Related commands: MFR_CONFIG_ALL_L TC3882-1 Note that if the L TC3882-1 die temperature exceeds 130°C, execution of any command in the above table except RE- STORE_USER_ALL and MFR_FAUL T_LOG_STORE will be disabled until the IC temperature drops below 125°C. RE- STORE_USER_ALL is executed immediately, and MFR_FAUL T_LOG_STORE is executed after the IC temperature drops below 125°C. Refer to Table 4 for details of fault log contents. Using any command that writes data to the EEPROM is strongly discouraged if bit 6 of STATUS_MFR_ SPECIFIC is set, indicating the internal die temperature is above 85°C. Data retention of 10 years is not guaranteed if the EEPROM is written above a junction temperature of 85°C. STORE_USER_ALL The STORE_USER_ALL command instructs the PMBus device to copy the entire contents of the operating memory to internal EEPROM PMBus configuration space. This write-only command has no data bytes. RESTORE_USER_ALL The RESTORE_USER_ALL command instructs the PMBus device to copy the entire contents of the internal EEPROM to matching locations in operating memory. The values in operating memory are overwritten by the values retrieved from EEPROM. Both channels should be turned off prior to issuing this command. The L TC3882-1 ensures both PWM channels are off, loads the operating memory from internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both PWM channels, if enabled This write-only command has no data bytes. MFR_COMPARE_USER_ALL The MFR_COMPARE_USER_ALL command instructs the L TC3882-1 to compare current operating memory (PMBus com- mand values in RAM) with the contents of the internal EEPROM. If the compared memories differ , a CML fault is generated. This write-only command has no data bytes.

Rev AFor more information www.analog.com PMBus COMMAND DETAILS (EEPROM User Access) MFR_ID The MFR_ID command returns the manufacturer ID of the L TC3882-1 using 8-bit ASCII characters. This read-only command is in block format. MFR_MODEL The MFR_MODEL command returns the L TC part number using 8-bit ASCII characters. This read-only command is in block format. MFR_SERIAL The MFR_SERIAL command returns the serial number of this specific device using a maximum of fourteen 8-bit ASCII characters. This read-only command is in block format. MFR_SPECIAL_ID The MFR_SPECIAL_ID command returns a 16-bit word representing the part name. 0x424X denotes the part is a L TC3882-1. X is adjustable by the manufacturer . This read-only command has 2 data bytes. UNIT IDENTIFICATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_ID 0x99 Manufacturer identification. R String N ASC LT C MFR_MODEL 0x9A L TC model number . R String N ASC L TC3882-1 MFR_SERIAL 0x9E Device serial number . R Block N Reg MFR_SPECIAL_ID 0xE7 Manufacturer code representing the L TC3882-1 R Word N Reg 0x424X PMBus COMMAND DETAILS (Unit Identification) MFR_FAULT_LOG_STORE The MFR_FAUL T_LOG_STORE command forces a data log to be written to internal EEPROM as if a fault event had occurred. This command will generate a CML fault if the Enable Fault Logging bit is cleared in MFR_CONFIG_ALL_L TC3882-1. This write-only command has no data bytes. MFR_EE_xxxx The MFR_EE_xxxx commands facilitate bulk programming of the L TC3882-1 internal EEPROM. Contact the factory for details. USER_DATA_0x The USER_DATA_0x commands provide uncommitted EEPROM locations that may be applied as system scratchpad space. USER_DATA_00 and USER_DATA_01 should not be modified when using the L TpowerPlay GUI. Some contract manufacturers also reserve use of USER_DATA_02 for their own inventory control.

Figure 54. 36V Input 3.3V/40A 1.0MHz Converter with Discrete Gate Drivers

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Figure 55. High Density 1.5V/45A 650kHz Converter Using Dual Power Block

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Rev A For more information www.analog.com PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 6.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH R = 0.45 OR 0.35 × 45° CHAMFER 0.40 ±0.10 40 39 BOTTOM VIEW—EXPOSED PAD

4.50 REF

(4-SIDES) 4.42 ±0.10 4.42 ±0.10 4.42 ±0.05 4.42 ±0.05 0.75 ±0.05 R = 0.115 TYP 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UJ40) QFN REV Ø 0406 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 4.50 ±0.05 (4 SIDES) 5.10 ±0.05 6.50 ±0.05 0.25 ±0.05 R = 0.10 TYP 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø)

Rev AFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 04/18 Added ECC Reduced initialization time Reduced conversion time 1, 17, 24 5, 19

Figure 56. 1V/40A and 1.8V/30A 500kHz Converter with DrMOS Power Stage

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