LTM4677

LTM4676A LINER | Alldatasheet

Document overview

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Technical content

For more information www.linear .com/L TM4676A Typical applicaTion FeaTures DescripTion Dual 13A or Single 26A µModule Regulator with Digital Power System Management The LTM®4676A is a dual 13A or single 26A step-down µModule® (micromodule) DC/DC regulator with 40ms turn-on time. It features remote configurability and telemetry-monitoring of power management parameters over PMBus— an open standard I 2C-based digital interface protocol . The LTM4676A is comprised of fast analog control loops, precision mixed-signal circuitry, EEPROM, power MOSFETs, inductors and supporting components. The LTM4676A’s 2-wire serial interface allows outputs to be margined, tuned and ramped up and down at program- mable slew rates with sequencing delay times. Input and ou tput currents and voltages, output power, temperatures, uptime and peak values are readable. At start-up, output voltages, switching frequency, and channel phase angle assignments can be set by pin-strapping resistors. The LTpowerPlay™ GUI and DC1613 USB-to-PMBus converter and demo kits are available. The LTM4676A is pin-compatible and the improved performance version of the LTM4676.

applicaTions

n Dual, Fast, Analog Loops with Digital Interface for Control and Monitoring n Wide Input Voltage Range: 4.5V to 26.5V n Output Voltage Range: 0.5V to 5.5V n ±0.5% Maximum DC Output Error Over Temperature n ±2.5% Current Readback Accuracy at 10A Load n 400kHz PMBus-Compliant I2C Serial Interface n Integrated 16-Bit ∆Σ ADC n Supports Telemetry Polling Rates Up to 125Hz n Constant Frequency Current Mode Control n Parallel and Current Share Multiple Modules n All 7-Bit Slave Addresses Supported n Pin-Compatible to Dual 18A LTM4677 n 16mm × 16mm × 5.01mm BGA Package Readable Data: n Input and Output Voltages, Currents, and Temperatures n Running Peak Values, Uptime, Faults and Warnings n Onboard EEPROM Fault Log Record with ECC Writable Data and Configurable Parameters: n Output Voltage, Voltage Sequencing and Margining n Digital Soft-Start/Stop Ramp n OV/UV/OT , UVLO, Frequency and Phasing n System Optimization, Characterization and Data Min- ing in Prototype, Production and Field Environments L, L T , L TC, L TM, Linear Technology, the Linear logo, µModule and PolyPhase are registered trademarks and L TpowerPlay is a trademark of Analog Devices, Inc. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide. Dual 13A µModule Regulator with Digital Interface for Control and Monitoring* Using PMBus and L TpowerPlay to Monitor Telemetry and Margin VOUT0/VOUT1 During Load Pattern Tests. 10Hz Polling Rate. 12VIN 22µF ON/OFF CONTROL FAUL T INTERRUPTS, POWER SEQUENCING PWM CLOCK AND TIME-BASE SYNCHRONIZATION VIN 5.75V TO 26.5V VOSNS0– VOUT0, ADJUSTABLE UP TO 13A 100µF V OSNS0 VOUT0VIN0 VIN1 SVIN LOAD0 VOUT1, ADJUSTABLE UP TO 13A 100µF I 2C/SMBus I/F WITH PMBus COMMAND SET TO/FROM IPMI OR OTHER BOARD MANAGEMENT CONTROLLER LOAD1 RUN0 RUN1 WP *FOR COMPLETE CIRCUIT , SEE FIGURE 69 L TM4676A GND 4676A TA01a SGND SCL SDA ALERT VOSNS1 VOUT1 GPIO0 GPIO1 REGISTER WRITE PROTECTION SYNC SHARE_CLK 1.1 1.0

0.9 VOUT0 (V)

VOUT1 (V) 0.8 1.9 1.8 1.7 1.6 0 3 6 TIME (SEC) Output Voltage Readback, V OUT Margined 7.5% Low 4676A TA01b 9 12 IOUT0 (A) IOUT1 (A) 0 3 6 TIME (SEC) Output Current Readback, Varying Load Pattern 4676A TA01c 9 12 1.5 1.0

0.5 IIN0 (A)

IIN1 (A) 2.4 1.6 0.8 0 3 6 TIME (SEC) Input Current Readback 4676A TA01d 9 12

54 CHANNEL 0 TEMP (°C)

CHANNEL 1 TEMP (°C) 0 3 6 TIME (SEC) Power Stage Temperature Readback 4676A TA01e 9 12 Click to view associated Video Design Idea.

For more information www.linear .com/L TM4676A Table oF conTenTs T

Description

T T Operation P P EE Se De F R Re R R Fa B P I O L S M V ariable Delay Time, Soft-Start and Output Voltage Di S U F O P RCONFIG Pin-Straps (External Resistor V C onnecting the USB to the I2C/SMBus/PMBus L TpowerPlay: An Interactive GUI for Digital Power P T hermal Considerations and Output Current Derating ...65 EM S L T S imilarity Between PMBus, SMBus and I 2C PM A G O PW Vo C Te T T

For more information www.linear .com/L TM4676A pin conFiguraTionabsoluTe MaxiMuM raTings Terminal Voltages: FSWPHCFG, VOUTnCFG, VTRIMnCFG, ASEL .. –0. 3V to 2.75V VDD33, GPIOn, SYNC, SHARE_CLK, WP , 3V to 0.3V Temperatures Internal Operating Temperature Range C to 125°C C to 125°C Peak Solder Reflow Package Body Temperature ... 24 5°C (Note 1) VIN0 VIN1 VOUT0 VOUT1 A B C D E F G H J K L M 2 3 4 5 6 7 TOP VIEW 8 9 10 11 12 GND GND GND GND BGA PACKAGE 144-LEAD (16mm × 16mm × 5.01mm) GND GND TJMAX = 125°C, θJCtop = 8.8°C/W , θJCbottom = 0.8°C/W , θJB = 1.3°C/W , θJA = 10.3°C/W θ VALUES DETERMINED PER JESD51-12 WEIGHT = 3.3 GRAMS orDer inForMaTion PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (See Note 2)DEVICE FINISH CODE LTM4676AEY#PBF SAC305 (RoHS) LTM4676AY e1 BGA 4 –40°C to 125°C LTM4676AIY#PBF SAC305 (RoHS) LTM4676AY e1 BGA 4 –40°C to 125°C LTM4676AIY SnPb (63/37) LTM4676AY e0 BGA 4 –40°C to 125°C Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container . Pad or ball finish code is per IPC/JEDEC J-STD-609.

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For more information www.linear .com/L TM4676A elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V, FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage Test Circuit 1 Test Circuit 2; VIN_OFF < VIN_ON = 4.25V l l 5.75 4.5 26.5 5.75 V V V OUTn Range of Output Voltage Regulation V OUT0 Differentially Sensed on VOSNS0+/VOSNS0– Pin-Pair; VOUT1 Differentially Sensed on VOSNS1/SGND Pin-Pair; Commanded by Serial Bus or with Resistors Present at Start-Up on V OUTnCFG and/or VTRIMnCFG l l 0.5 0.5 5.5 5.5 V V V OUTn(DC) Output Voltage, Total Variation with Line and Load (Note 5) V OUTn Low Range (MFR_PWM_MODEn [1] = 1b), FREQUENCY_SWITCH = 250kHz Digital Servo Engaged (MFR_PWM_MODE n[6] = 1b) Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b) l 0.995 0.985 1.000 1.000 1.005 1.015 V V Input Specifications I INRUSH(VIN) Input Inrush Current at Start-Up Test Cir cuit 1, VOUTn = 1V, VIN = 12V; No Load Besides Capacitors; TON_RISEn = 3ms 400 mA IQ(SVIN) Input Supply Bias Current Forced Continuous Mode, MFR_PWM_MODE n[0] = 1b RUNn = 5V, RUN1-n = 0V Shutdown, RUN0 = RUN1 = 0V mA mA I S(VINn,PSM) Input Supply Current in Pulse-Skipping Mode Operation Pulse-Skipping Mode, MFR_PWM_MODE n[0] = 0b, IOUTn = 100mA 20 mA IS(VINn,FCM) Input Supply Current in Forced-Continuous Mode Operation Forced Continuous Mode, MFR_PWM_MODE n[0] = 1b IOUTn = 100mA IOUTn = 13A 1.37 mA A IS(VINn,SHUTDOWN) Input Supply Current in Shutdown Shutdown, RUN n = 0V 50 µA Output Specifications IOUTn Output Continuous Current Range (Note 6) 0 13 A ∆VOUTn(LINE) VOUTn Line Regulation Accuracy Digital Servo Engaged (MFR_PWM_MODE n[6] = 1b) Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b) SVIN and VINn Electrically Shorted Together and INTVCC Open Circuit; IOUTn = 0A, 5.75V ≤ VIN ≤ 26.5V, VOUT Low Range (MFR_PWM_MODEn[1] = 1b) FREQUENCY_SWITCH = 250kHz (Referenced to 12VIN) (Note 5) l 0.03 0.03 ±0.2 %/V ∆VOUTn(LOAD) VOUTn Load Regulation Accuracy Digital Servo Engaged (MFR_PWM_MODE n[6] = 1b) Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b) 0A ≤ IOUTn ≤ 13A, VOUT Low Range, (MFR_PWM_MODEn[1] = 1b) FREQUENCY_SWITCH = 250kHz (Note 5) l 0.03 0.2 0.5 V OUTn(AC) Output Voltage Ripple 10 mVP-P fS (Each Channel) V OUTn Ripple Frequency FREQUENCY_SWITCH Set to 500kHz (0xFBE8) l 462.5 500 537.5 kHz ∆VOUTn(START) Turn-On Overshoot TON_RISE n = 3ms (Note 12) 8 mV tSTART Turn-On Start-Up Time Time from V IN Toggling from 0V to 12V to Rising Edge of GPIOn. TON_DELAYn = 0ms, TON_RISEn = 3ms, MFR_GPIO_PROPAGATEn = 0x0100, MFR_GPIO_RESPONSEn = 0x0000 l 35 40 ms

For more information www.linear .com/L TM4676A elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V, FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tDELAY(0ms) Turn-On Delay Time Time from First Rising Edge of RUN n to Rising Edge of GPIOn. TON_DELAYn = 0ms, TON_RISEn = 3ms, MFR_GPIO_PROPAGATEn = 0x0100, MFR_GPIO_RESPONSEn = 0x0000. VIN Having Been Established for at Least 40ms l 2.75 3.1 3.5 ms ∆VOUTn(LS) Peak Output Voltage Deviation for Dynamic Load Step Load: 0A to 6.5A and 6.5A to 0A at 6.5A/µs, Figure 69 Circuit, V OUTn = 1V, VIN = 12V (Note 12) 50 mV tSETTLE Settling Time for Dynamic Load Step Load: 0A to 6.5A and 6.5A to 0A at 6.5A/µs, Figure 69 Circuit, V OUTn = 1V, VIN = 12V (Note 12) 35 µs IOUTn(OCL_PK) Output Current Limit, Peak Cycle-by-Cycle Inductor Peak Current Limit Inception 22.5 A I OUTn(OCL_AVG) Output Current Limit, Time Averaged Time-Averaged Output Inductor Current Limit Inception Threshold, Commanded by IOUT_OC_FAULT_LIMIT n (Note 12) 15.6A; See IO-RB-ACC Specification (Output Current Readback Accuracy) Control Section VFBCM0 Channel 0 Feedback Input Common Mode Range VOSNS0– Valid Input Range (Referred to SGND) VOSNS0+ Valid Input Range (Referred to SGND) l l –0.1 0.3 5.7 V V VFBCM1 Channel 1 Feedback Input Common Mode Range SGND Valid Input Range (Referred to GND) V OSNS1 Valid Input Range (Referred to SGND) l l –0.3 0.3 5.7 V V VOUT-RNG0 Full-Scale Command Voltage, Range 0 (Notes 7, 15) VOUTn Commanded to 5.500V, MFR_PWM_MODEn[1] = 0b Resolution LSB Step Size 5.422 1.375 5.576 V Bits mV V OUT-RNG1 Full-Scale Command Voltage, Range 1 (Notes 7, 15) VOUTn Commanded to 2.750V, MFR_PWM_MODEn[1] = 1b Resolution LSB Step Size 2.711 0.6875 2.788 V Bits mV R VSENSE0+ VOSNS0+ Impedance to SGND 0.05V ≤ VVOSNS0+ – VSGND ≤ 5.5V 41 kΩ RVSENSE1 VOSNS1 Impedance to SGND 0.05V ≤ VVOSNS1 – VSGND ≤ 5.5V 37 kΩ tON(MIN) Minimum On-Time (Note 8 ) 45 ns Analog OV/UV (Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_LIMIT Monitors) NOV/UV_COMP Resolution, Output Voltage Supervisors (Note 15) 8 Bits V OV-RNG Output OV Comparator Threshold Detection Range (Note 15) High Range Scale, MFR_PWM_MODEn[1] = 0b Low Range Scale, MFR_PWM_MODEn[1] = 1b 0.5 5.6 2.7 V V V OU-STP Output OV and UV Comparator Threshold Programming LSB Step Size (Note 15) High Range Scale, MFR_PWM_MODEn[1] = 0b Low Range Scale, MFR_PWM_MODEn[1] = 1b mV mV

For more information www.linear .com/L TM4676A elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V, FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOV-ACC Output OV Comparator Threshold Accuracy (See Note 14) 2V ≤ VVOSNS0+ – VVOSNS0– ≤ 5.6V, MFR_PWM_MODE0[1] = 0b 1V ≤ VVOSNS0+ – VVOSNS0– ≤ 2.7V, MFR_PWM_MODE0[1] = 1b 0.5V ≤ VVOSNS0+ – VVOSNS0– < 1V, MFR_PWM_MODE0[1] = 1b 2V ≤ VVSENSE1 – VSGND ≤ 5.6V, MFR_PWM_MODE1[1] = 0b 1.5V ≤ VVSENSE1 – VSGND ≤ 2.7V, MFR_PWM_MODE1[1] = 1b 0.5V ≤ VVSENSE1 – VSGND < 1.5V, MFR_PWM_MODE1[1] = 1b l l l l l l ±20 ±30 mV mV V UV-RNG Output UV Comparator Threshold Detection Range (Note 15) High Range Scale, MFR_PWM_MODEn[1] = 0b Low Range Scale, MFR_PWM_MODEn[1] = 1b 0.5 5.4 2.7 V V V UV-ACC Output UV Comparator Threshold Accuracy (See Note 14) 2V ≤ VVSENSE0+ – VVSENSE0– ≤ 5.4V, MFR_PWM_MODE0[1] = 0b 1V ≤ VVSENSE0+ – VVSENSE0– ≤ 2.7V, MFR_PWM_MODE0[1] = 1b 0.5V ≤ VVSENSE0+ – VVSENSE0– < 1V, MFR_PWM_MODE0[1] = 1b 2V ≤ VVOSNS1 – VSGND ≤ 5.4V, MFR_PWM_MODE1[1] = 0b 1.5V ≤ VVOSNS1 – VSGND ≤ 2.7V, MFR_PWM_MODE1[1] = 1b 0.5V ≤ VVOSNS1 – VSGND < 1.5V, MFR_PWM_MODE1[1] = 1b l l l l l l ±20 ±30 mV mV t PROP-OV Output OV Comparator Response Times Overdrive to 10% Above Programmed Threshold 35 µs t PROP-UV Output UV Comparator Response Times Underdrive to 10% Below Programmed Threshold 50 µs Analog OV/UV SV IN Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF) NSVIN-OV/UV-COMP SVIN OV/UV Comparator Threshold-Programming Resolution (Note 15) 8 Bits SV IN-OU-RANGE SVIN OV/UV Comparator Threshold-Programming Range l 4.5 20 V SVIN-OU-STP SVIN OV/UV Comparator Threshold-Programming LSB Step Size (Note 15) 82 mV SV IN-OU-ACC SVIN OV/UV Comparator Threshold Accuracy 9V < SVIN ≤ 20V 4.5V ≤ SVIN ≤ 9V l l ±2.5 ±225 mV tPROP-SVIN-HIGH-VIN SVIN OV/UV Comparator Response Time, High VIN Operating Configuration Test Circuit 1, and: VIN_ON = 9V; SVIN Driven from 8.775V to 9.225V VIN_OFF = 9V; SVIN Driven from 9.225V to 8.775V l l µs µs t PROP-SVIN-LOW-VIN SVIN OV/UV Comparator Response Time, Low VIN Operating Configuration Test Circuit 2, and: VIN_ON = 4.5V; SV IN Driven from 4.225V to 4.725V VIN_OFF = 4.5V; SVIN Driven from 4.725V to 4.225V l l µs µs Channels 0 and 1 Output Voltage Readback (READ_VOUT NVO-RB Output Voltage Readback Resolution and LSB Step Size (Note 15) 16 244 Bits µV V O-F/S Output Voltage Full-Scale Digitizable Range V RUNn = 0V (Notes 7, 15) 8 V VO-RB-ACC Output Voltage Readback Accuracy Channel 0: 1V ≤ V VOSNS0+ – VVOSNS0– ≤ 5.5V Channel 0: 0.6V ≤ VVOSNS0+ – VVOSNS0– < 1V Channel 1: 1V ≤ VVOSNS1 – VSGND ≤ 5.5V Channel 1: 0.6V ≤ VVOSNS1 – VSGND < 1V l l l l Within ±0.5% of Reading Within ±5mV of Reading Within ±0.5% of Reading Within ±5mV of Reading

For more information www.linear .com/L TM4676A elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V, FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tCONVERT-VO-RB Output Voltage Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15) MFR_ADC_CONTROL = 0x0D (Notes 9, 15) MFR_ADC_CONTROL = 0x05 or 0x09 (Notes 9, 15) ms ms ms Input Voltage (SV IN) Readback (READ_VIN) NSVIN-RB Input Voltage Readback Resolution and LSB Step Size (Notes 10, 15) 10 15.625 Bits mV SV IN-F/S Input Voltage Full-Scale Digitizable Range (Notes 11, 15) 38.91 V SV IN-RB-ACC Input Voltage Readback Accuracy READ_VIN, 4.5V ≤ SV IN ≤ 26.5V l Within ±2% of Reading tCONVERT-SVIN-RB Input Voltage Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15) MFR_ADC_CONTROL = 0x01 (Notes 9, 15) ms ms Channels 0 and 1 Output Current (READ_IOUT n), Duty Cycle (READ_DUTY_CYCLEn), and Computed Input Current (MFR_READ_IINn) Readback NIO-RB Output Current Readback Resolution and LSB Step Size (Notes 10, 12) 10 15.6 Bits mA I O-F/S, II-F/S Output Current Full-Scale Digitizable Range and Input Current Range of Calculation (Note 12) ±40 A I O-RB-ACC Output Current, Readback Accuracy READ_IOUT n, Channels 0 and 1, 0 ≤ IOUTn ≤ 10A, Forced-Continuous Mode, MFR_PWM_MODEn[1:0] = 10b l Within 250mA of Reading IO-RB(13A) Full Load Output Current Readback I OUTn = 13A (Note 12). See Histograms in Typical Performance Characteristics 13.1 A NII-RB Computed Input Current, Readback Resolution and LSB Step Size (Notes 10, 12) 10 1.95 Bits mA I I-RB-ACC Computed Input Current, Readback Accuracy, Neglecting I SVIN MFR_READ_IINn, Channels 0 and 1, 0 ≤ IOUTn ≤ 10A, Forced-Continuous Mode, MFR_PWM_MODEn[1:0] = 10b, MFR_IIN_OFFSETn = 0mA l Within 150mA of Reading tCONVERT-IO-RB Output Current Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15) MFR_ADC_CONTROL = 0x0D (Notes 9, 15) MFR_ADC_CONTROL = 0x06 or 0x0A (Notes 9, 15) ms ms ms t CONVERT-II-RB Computed Input Current, Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15) 90 ms N DUTY-RB Resolution, Duty Cycle Readback (Notes 10, 15) 10 Bits D RB-ACC Duty Cycle TUE READ_DUTY_CYCLE n, 16.3% Duty Cycle (Note 15) ±3 % tCONVERT-DUTY-RB Duty Cycle Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15) 90 ms Temperature Readback for Channel 0, Channel 1, and Controller (Respectively: READ_TEMPERATURE_1 0, READ_TEMPERATURE_11, and READ_TEMPERATURE_2) TRES-RB Temperature Readback Resolution Channel 0, Channel 1, and Controller (Note 15) 0.0625 °C TRB-CH-ACC(72mV) Channel Temperature TUE, Switching Action Off Channels 0 and 1, PWM Inactive, RUN n = 0V, ∆VTSNSna = 72mV l Within ±3°C of Reading

For more information www.linear .com/L TM4676A elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V, FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TRB-CH-ACC(ON) Channel Temperature TUE, Switching Action On READ_TEMPERATURE_1n, Channels 0 and 1, PWM Active, RUNn = 5V (Note 12) Within ±3°C of Reading TRB-CTRL-ACC(ON) Control IC Die Temperature TUE, Switching Action On READ_TEMPERATURE_2, PWM Active, RUN 0 = RUN1 = 5V (Note 12) Within ±1°C of Reading tCONVERT-TEMP-RB Temperature Readback Update Rate MFR_ADC_CONTROL = 0x00 (Notes 9, 15) MFR_ADC_CONTROL = 0x06 or 0x0A (Notes 9, 15) ms ms INTV CC Regulator VINTVCC Internal VCC Voltage No Load 6V ≤ VIN ≤ 26.5V 4.8 5 5.2 V ∆VINTVCC(LOAD) VINTVCC INTVCC Load Regulation 0mA ≤ I INTVCC ≤ 50mA 0.5 ±2 % VDD33 Regulator VVDD33 Internal VDD33 Voltage 3.2 3.3 3.4 V ILIM(VDD33) VDD33 Current Limit V DD33 Electrically Short-Circuited to GND 70 mA VVDD33_OV VDD33 Overvoltage Threshold (Note 15) 3.5 V VVDD33_UV VDD33 Undervoltage Threshold (Note 15) 3.1 V VDD25 Regulator VVDD25 Internal VDD25 Voltage 2.5 V ILIM(VDD25) VDD25 Current Limit V DD25 Electrically Short-Circuited to GND 50 mA Oscillator and Phase-Locked Loop (PLL) fOSC Oscillator Frequency Accuracy FREQUENCY_SWITCH = 500kHz (0xFBE8) 250kHz ≤ FREQUENCY_SWITCH ≤ 1MHz (Note 15) l ±7.5 ±7.5 f SYNC PLL SYNC Capture Range FREQUENCY_SWITCH Set to Frequency Slave Mode (0x0000); MFR_CONFIG_ALL[4] = 1b; SYNC Driven by External Clock; 3.3VOUT l 225 1100 kHz VTH,SYNC SYNC Input Threshold V SYNC Rising (Note 15) VSYNC Falling (Note 15) 1.5 V V V OL,SYNC SYNC Low Output Voltage I SYNC = 3mA l 0.3 0.4 V ISYNC SYNC Leakage Current in Frequency Slave Mode 0V ≤ V SYNC ≤ 3.6V MFR_CONFIG_ALL[4] = 1b l ±5 µA θSYNC-θ0 SYNC-to-Channel 0 Phase Relationship, Lag from Falling Edge of Sync to Rising Edge of Top MOSFET (MT0) Gate (Note 15) MFR_PWM_CONFIG[2:0] = 000b, 01Xb MFR_PWM_CONFIG[2:0] = 101b MFR_PWM_CONFIG[2:0] = 001b MFR_PWM_CONFIG[2:0] = 1X0b 120 Deg Deg Deg Deg θ SYNC-θ1 SYNC-to-Channel 1 Phase Relationship, Lag from Falling Edge of Sync to Rising Edge of Top MOSFET (MT1) Gate (Note 15) MFR_PWM_CONFIG[2:0] = 011b MFR_PWM_CONFIG[2:0] = 000b MFR_PWM_CONFIG[2:0] = 010b, 10Xb MFR_PWM_CONFIG[2:0] = 001b MFR_PWM_CONFIG[2:0] = 110b 120 180 240 270 300 Deg Deg Deg Deg Deg

For more information www.linear .com/L TM4676A elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V, FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM settings and per Test Circuit 1, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS EEPROM Characteristics Endurance (Note 13) 0°C ≤ TJ ≤ 85°C During EEPROM Write Operations (Note 3) l 10,000 Cycles Retention (Note 13) TJ < TJ(MAX), with Most Recent EEPROM Write Operation Having Occurred at 0°C ≤ TJ ≤ 85°C (Note 3) l 10 Years Mass_Write Mass Write Operation Time Execution of STORE_USER_ALL Command, 0°C ≤ TJ ≤ 85°C (ATE-Tested at TJ = 25°C) (Notes 3, 13) 440 4100 ms Digital I/Os V IH Input High Threshold Voltage SCL, SDA, RUNn, GPIOn (Note 15) SHARE_CLK, WP (Note 15) 1.35 1.8 V V V IL Input Low Threshold Voltage SCL, SDA, RUN n, GPIOn (Note 15) SHARE_CLK, WP (Note 15) 0.8 0.6 V V V HYST Input Hysteresis SCL, SDA (Note 15) 80 mV VOL Output Low Voltage SCL, SDA, ALERT, RUN n, GPIOn, SHARE_CLK: ISINK = 3mA l 0.3 0.4 V IOL Input Leakage Current SDA, SCL, ALERT, RUN n: 0V ≤ VPIN ≤ 5.5V GPIOn and SHARE_CLK: 0V ≤ VPIN ≤ 3.6V l l µA µA t FIL TER Input Digital Filtering RUN n (Note 15) GPIOn (Note 15) µs µs C PIN Input Capacitance SCL, SDA, RUN n, GPIOn, SHARE_CLK, WP (Note 15) 10 pF PMBus Interface Timing Characteristics fSMB Serial Bus Operating Frequency (Note 15) 10 400 kHz tBUF Bus Free Time Between Stop and Start (Note 15) 1.3 μs t HD,STA Hold Time After Repeated Start Condition Time Period After Which First Clock Is Generated (Note 15) 0.6 µs t SU,STA Repeated Start Condition Setup Time (Note 15) 0.6 μs t SU,STO Stop Condition Setup Time (Note 15) 0.6 μs t HD,DAT Data Hold Time Receiving Data (Note 15) T ransmitting Data (Note 15) 0.3 0.9 µs µs t SU,DAT Data Setup Time Receiving Data (Note 15) 0.1 μs tTIMEOUT_SMB Stuck PMBus Timer Timeout Measured from the Last PMBus Start Event: Block Reads, MFR_CONFIG_ALL[3] = 0b (Note 15) Non-Block Reads, MFR_CONFIG_ALL[3] = 0b (Note 15) MFR_CONFIG_ALL[3] = 1b (Note 15) 150 250 ms ms ms t LOW Serial Clock Low Period (Note 15) 1.3 10000 μs tHIGH Serial Clock High Period (Note 15) 0.6 μs

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elecTrical characTerisTics

Note 1: Stresses beyond those listing under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating conditions for extended periods may affect device reliability and lifetime. Note 2: The LTM4676A is tested under pulsed-load conditions such that T J ≈ TA. The LTM4676AE is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4676AI is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: The LTM4676A’s EEPROM temperature range for valid write commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention, execution of the “STORE_USER_ALL” command—i.e., uploading RAM contents to NVM—outside this temperature range is not recommended. However , as long as the LTM4676A’s EEPROM temperature is less than 130°C, the LTM4676A will obey the STORE_USER_ALL command. Only when EEPROM temperature exceeds 130°C, the LTM4676A will not act on any STORE_USER_ALL transactions: instead, the LTM4676A NACKs the serial command and asserts its relevant CML (communications, memory, logic) fault bits. EEPROM temperature can be queried prior to commanding STORE_USER_ALL; see the Applications Information section. Note 4: The two power inputs—V IN0 and VIN1—and their respective power outputs—VOUT0 and VOUT1—are tested independently in production. A shorthand notation is used in this document that allows these parameters to be refered to by “VINn” and “VOUTn”, where n is permitted to take on a value of 0 or 1. This italicized, subscripted “n” notation and convention is extended to encompass all such pin names, as well as register names with channel-specific, i.e., paged data. For example, VOUT_COMMAND n refers to the VOUT_COMMAND command code data located in Pages 0 and 1, which in turn relate to Channels 0 (V OUT0) and Channel 1 (VOUT1). Registers containing non-page-specific data, i.e., whose data is “global” to the module or applies to both of the module's Channels lack the italicized, subscripted “n”, e.g., FREQUENCY_SWITCH. Note 5: V OUTn (DC) and line and load regulation tests are performed in production with digital servo disengaged (MFR_PWM_MODEn[6] = 0b) and low VOUTn range selected (MFR_PWM_MODEn[1]) = 1b. The digital servo control loop is exercised in production (setting MFR_PWM_ MODE n[6] = 1b), but convergence of the output voltage to its final settling value is not necessarily observed in final test—due to potentially long time constants involved—and is instead guaranteed by the output voltage readback accuracy specification. Evaluation in application demonstrates capability; see the Typical Performance Characteristics section. Note 6: See output current derating curves for different V IN, VOUT, and TA, located in the Applications Information section. Note 7: Even though VOUT0 and VOUT1 are specified for 6V absolute maximum, the maximum recommended regulation-command voltage is: 5.5V for a high-VOUT range setting of MFR_PWM_MODEn[1]=0b; 2.5V for a low-VOUT range setting of MFR_PWM_MODEn[1]=1b. Note 8: Minimum on-time is tested at wafer sort. Note 9: Data conversion is performed in round-robin (cyclic) fashion. All telemetry signals are continuously digitized, and reported data is based on measurements not older than 90ms, typical. Some telemetry parameters can be digitized at a faster update rate by configuring MFR_ ADC_CONTROL. Note 10: The following telemetry parameters are formatted in PMBus- defined “Linear Data Format”, in which each register contains a word comprised of 5 most significant bits—representing a signed exponent, to be raised to the power of 2—and 11 least significant bits—representing a signed mantissa: input voltage (on SV IN), accessed via the READ_VIN command code; output currents (IOUTn), accessed via the READ_IOUTn command codes; module input current (IVIN0 + IVIN1 + ISVIN), accessed via the READ_IIN command code; channel input currents (IVINn + 1/2 • ISVIN), accessed via the MFR_READ_IINn command codes;and duty cycles of channel 0 and channel 1 switching power stages, accessed via the READ_DUTY_CYCLE n command codes. This data format limits the resolution of telemetry readback data to 10 bits even though the internal ADC is 16 bits and the LTM4676A’s internal calculations use 32-bit words. Note 11: The absolute maximum rating for the SV IN pin is 28V. Input voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled down from the SVIN pin. Note 12: These typical parameters are based on bench measurements and are not production tested. Note 13: EEPROM endurance and retention are guaranteed by wafer-level testing for data retention. The minimum retention specification applies for devices whose EEPROM has been cycled less than the minimum endurance specification, and whose EEPROM data was written to at 0°C ≤ T J ≤ 85°C. Downloading NVM contents to RAM by executing the RESTORE_USER_ALL or MFR_RESET commands is valid over the entire operating temperature range and does not influence EEPROM characteristics. Note 14: Channel 0 OV/UV comparator threshold accuracy for MFR_PWM_MODE 0[1] = 1b tested in ATE at VVOSNS0+ – VVOSNS0– = 0.5V and 2.7V. 1V condition tested at IC-Level, only. Channel 1 OV/UV comparator threshold accuracy for MFR_PWM_MODE 1[1] = 1b tested in ATE with VVOSNS1-VSGND = 0.5V and 2.7V. 1.5V condition tested at IC-level, only. Note 15: Tested at IC-level ATE.

For more information www.linear .com/L TM4676A Efficiency vs Output Current, 5VIN, VOUT0 and VOUT1 Paralleled, VIN = SVIN = VINn = INTVCC Efficiency vs Output Current, VOUT1 = 5V, VOUT0 = OFF , VIN = SVIN = VINn, INTVCC Open Efficiency vs Output Current, 24V IN, VOUT0 and VOUT1 Paralleled, VIN = SVIN = VINn, INTVCC Open Efficiency vs Output Current, IN, VOUT0 and VOUT1 Paralleled, VIN = SVIN = VINn, INTVCC Open Efficiency vs Output Current, 12V IN, VOUT0 and VOUT1 Paralleled, VIN = SVIN = VINn, INTVCC Open OUTPUT CURRENT (A) 0 2 4 22 24 26 4676A G01 6 8 10 12 14 16 18 20 100 3.3VOUT, 425kHz 2.5VOUT, 425kHz 1.8VOUT, 425kHz 1.5VOUT, 350kHz 1.2VOUT, 350kHz 1.0VOUT, 350kHz 0.9VOUT, 350kHz EFFICIENCY (%) OUTPUT CURRENT (A) 0 2 4 22 24 26 4676A G02 6 8 10 12 14 16 18 20 100 3.3VOUT, 575kHz 2.5VOUT, 500kHz 1.8VOUT, 425kHz 1.5VOUT, 350kHz 1.2VOUT, 350kHz 1.0VOUT, 350kHz 0.9VOUT, 350kHz EFFICIENCY (%) OUTPUT CURRENT (A) 0 2 4 22 24 26 4676A G03 6 8 10 12 14 16 18 20 100 3.3VOUT, 650kHz 2.5VOUT, 575kHz 1.8VOUT, 500kHz 1.5VOUT, 425kHz 1.2VOUT, 350kHz 1.0VOUT, 350kHz 0.9VOUT, 350kHz EFFICIENCY (%) OUTPUT CURRENT (A) 0 2 4 22 24 26 4676A G04 6 8 10 12 14 16 18 20 100 3.3VOUT, 750kHz 2.5VOUT, 650kHz 1.8VOUT, 500kHz 1.5VOUT, 425kHz 1.2VOUT, 350kHz 1.0VOUT, 250kHz 0.9VOUT, 250kHz EFFICIENCY (%) OUTPUT CURRENT (A) 0 1 2 11 12 13 4676A G05 3 4 5 6 7 8 9 10 100 8VIN, 500kHz 12VIN, 750kHz 24VOUT, 1MHz EFFICIENCY (%) Typical perForMance characTerisTics TA = 25°C, 12VIN to 1VOUT, unless otherwise noted. Single Phase Single Output Pulse-Skipping (Discontinuous) Mode Efficiency, V IN = SVIN = VINn, INTVCC Open, MFR_PWM_MODEn[0] = 0b OUTPUT CURRENT (A) 0 1 2 11 12 13 4676A G06 3 4 5 6 7 8 9 10 24VIN TO 5VOUT, 1MHz 12VIN TO 1.5VOUT, 425kHz EFFICIENCY (%)

For more information www.linear .com/L TM4676A READ_TEMPERATURE_2 (Control IC Temperature Error) vs Junction Temperature, RUN n = 0V READ_VIN (Input Voltage Readback Telemetry) Error vs SV IN, RUNn = 0V MFR_READ_IINn (Input Current Readback) Error vs (IVINn + ISVIN), MFR_PWM_MODEn[0]=1b, IOUTn Swept from 0A to 13A, One Channel at a Time, RUN 1-n = 0V READ_VOUTn (Output Voltage Readback) Error vs VOUTn IOUTn = No Load, RUN1-n = 0V READ_IOUTn (Output Current Readback) Error vs IOUTn Typical perForMance characTerisTics TA = 25°C, 12VIN to 1VOUT, unless otherwise noted. ACTUAL TEMPERATURE (°C) –45 –1.0 MEASUREMENT ERROR (°C) –0.8 –0.4 –0.2 1.0 0.4 –5 35 55 4676A G18 –0.6 0.6 0.8 0.2 –25 15 75 95 115 VOUT (V) 0.5 MEASUREMENT ERROR (mV) 4.5 4676A G16 –20 –10 –30 1.5 2.5 3.5 5.5 SPECIFIED UPPER LIMIT SPECIFIED LOWER LIMIT CHANNEL 0 CHANNEL 1 IOUT (A) –300 MEASUREMENT ERROR (mA)–200 –100 100 CHANNEL 0 CHANNEL 1 200 300 3.25 6.50 9.75 13.00 SPECIFIED UPPER LIMIT SPECIFIED LOWER LIMIT 4676A G17 SVIN (V) –600 MEASUREMENT ERROR (mV)–400 –200 200 400 600 10 16 22 28 SPECIFIED UPPER LIMIT SPECIFIED LOWER LIMIT 4676A G19 IINn + ISVIN (A) –200 MEASUREMENT ERROR (mA) –100 100 200 0.2 0.4 0.6 0.8 4676A G20 1.0 1.2 1.4 CHANNEL 0 CHANNEL 1 SPECIFIED UPPER LIMIT SPECIFIED LOWER LIMIT

For more information www.linear .com/L TM4676A pin FuncTions PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y . GND (A4, A6-10, B4-B9, C4, C6-C9, D4, D7, E3, F3, M6-10): Power Ground of the LTM4676A. Power return for VOUT0 and VOUT1. VOUT0 (A1-3, B1-3, C1-3, D1-3): Channel 0 Output Voltage. VOSNS0+ (D9): Channel 0 Positive Differential Voltage Sense Input. Together , VOSNS0+ and VOSNS0– serve to kelvin-sense the VOUT0 output voltage at V OUT0’s point of load (POL) and provide the differential feedback signal directly to Channel 0’s control loop and voltage supervisor circuits. V OUT0 can regulate up to 5.5V output. Command VOUT0’s target regulation voltage by serial bus. Its initial command value at SV IN power-up is dictated by NVM (non-volatile memory) contents (factory default: 1.000V)—or , option- ally, may be set by configuration resistors; see V OUT0CFG, VTRIM0CFG and the Applications Information section. VOSNS0– (E9): Channel 0 Negative Differential Voltage Sense Input. See VOSNS0+. Typical perForMance characTerisTics TA = 25°C, 12VIN to 1VOUT, unless otherwise noted. READ_OUT of 20 LTM4676As (DC1811B-B) 12VIN, 1VOUT, TJ = –40°C, IOUTn = 13A, System Having Reached Thermally Steady-State Condition, No Airflow READ_OUT of 20 LTM4676As (DC1811B-B) 12V IN, 1VOUT, TJ = 25°C, IOUTn = 13A, System Having Reached Thermally Steady-State Condition, No Airflow READ_OUT of 20 LTM4676As (DC1811B-B) 12V IN, 1VOUT, TJ = 125°C, IOUTn = 13A, System Having Reached Thermally Steady-State Condition, No Airflow READ_IOUT CHANNEL READBACK (A) 13.12500 13.15625 13.18750 13.21875 13.25000 13.28125 13.31250 13.34375 13.37500 NUMBER OF CHANNELS 4676A G21 READ_IOUT CHANNEL READBACK (A) 13.00000 13.03125 13.06250 13.09375 13.12500 13.15625 13.18750 13.21875 13.25000 NUMBER OF CHANNELS 4676A G22 READ_IOUT CHANNEL READBACK (A) 12.96875 13.00000 13.03125 13.06250 13.09375 13.12500 13.18750 13.15625 13.21875 NUMBER OF CHANNELS 4676A G23 VORB0+ (D10): Channel 0 Positive Readback Pin. Shorted to VOSNS0+ internal to the LTM4676A. If desired, place a test point on this node and measure its impedance to V OUT0 on one’s hardware (e.g., motherboard, during in circuit test (ICT) post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between V OSNS0+ and VOUT0. VORB0– (E10): Channel 0 Negative Readback Pin. Shorted to VOSNS0– internal to the LTM4676A. If desired, place a test point on this node and measure its impedance to GND on one’s hardware (e.g., motherboard, during ICT post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between V OSNS0– and GND (VOUT0 power return). VOUT1 (J1-3, K1-3, L1-3, M1-3): Channel 1 Output Voltage. VOSNS1 (H9): Channel 1 Positive Voltage Sense Input. Connect VOSNS1 to V OUT1 at the POL. This provides the feedback signal for Channel 1's control loop and voltage supervisor circuits. V OUT1 can regulate up to 5.5V output. Command VOUT1’s target regulation voltage by serial bus. Its initial command value at SVIN power-up is dictated by

For more information www.linear .com/L TM4676A pin FuncTions NVM (non-volatile memory) contents (factory default: 1.000V)—or , optionally, may be set by configuration resistors; see VOUT1CFG, VTRIM1CFG and the Applications Information section. SGND (F7-8, G7-8): Channel 1 Negative Voltage Sense Input. See VOSNS1. Additionally, SGND is the signal ground return path of the LTM4676A. If desired, one may place a test point on one of the four SGND pins and measure its impedance to GND on one’s hardware (e.g., motherboard, during ICT post-assembly process) to provide a means of verifying the integrity of the feedback signal connec - tion between the other three SGND pins and GND (V OUT1 power return). SGND is not electrically connected to GND internal to the LTM4676A. Connect SGND to GND local to the LTM4676A. V ORB1 (J9): Channel 1 Positive Readback Pin. Shorted to VOSNS1 internal to the LTM4676A. At one’s option, place a test point on this node and measure its impedance to VOUT1 on one’s hardware (e.g., motherboard, during ICT post-assembly process) to provide a means of verifying the integrity of the feedback signal connection between V OUT1 and VOSNS1. VIN0 (A11-12, B11-12, C11-12, D11-12, E12): Positive Power Input to Channel 0 Switching Stage. Provide suf - ficient decoupling capacitance in the form of multilayer ceramic capacitors (MLCCs) and low ESR electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stage. MLCCs should be placed as close to the LTM4676A as physically possible. See Layout Recommendations in the Applications Information section. VIN1 (H12, J11-12, K11-12, L11-12, M11-12): Positive Power Input to Channel 1 Switching Stage. Provide suf - ficient decoupling capacitance in the form of MLCCs and low ESR electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stage. MLCCs should be placed as close to the LTM4676A as physically possible. See Layout Recommendations in the Applications Information section. SW 0 (B10): Switching Node of Channel 0 Step-Down Converter Stage. Used for test purposes or EMI-snubbing heavier than that supported by SNUB 0. May be routed a short distance to a local test point to monitor switching action of Channel 0, if desired, but do not route near any sensitive signals; otherwise, leave electrically isolated (open). SW 1 (L10): Switching Node of Channel 1 Step-Down Converter Stage. Used for test purposes or EMI-snubbing heavier than that supported by SNUB 1. May be routed a short distance to a local test point to monitor switching action of Channel 1, if desired, but do not route near any sensitive signals; otherwise, leave open. SNUB 0 (A5): Access to Channel 0 Switching Stage Snubber Capacitor . Connecting an optional resistor from SNUB0 to GND can reduce radiated EMI, with only a minor penalty towards power conversion efficiency. See the Applications Information section. Pin should otherwise be left open. SNUB 1 (M5): Access to Channel 1 Switching Stage Snubber Capacitor . Connecting an optional resistor from SNUB1 to GND can reduce radiated EMI, with only a minor penalty towards power conversion efficiency. See the Applications Information section. Pin should otherwise be left open. SV IN (F11-12): Input Supply for LTM4676A’s Internal Control IC. In most applications, SV IN connects to V IN0 and/or VIN1, in which case no external decoupling beyond that already allocated for VIN0/VIN1 is required. If SVIN is operated from an auxiliary supply separate from VIN0/VIN1, decouple this pin to GND with a capacitor (0.1μF to 1μF). INTV CC (F9, G9): Internal Regulator , 5V Output. When op- erating the LTM4676A from 5.75V ≤ SVIN ≤ 26.5V, an LDO generates INTVCC from SVIN to bias internal control circuits and the MOSFET drivers of the LTM4676A. No external decoupling is required. INTVCC is regulated regardless of the RUNn pin state. When operating the LTM4676A with 4.5V ≤ SVIN < 5.75V, INTVCC must be electrically shorted to SVIN. VDD33 ( J7): Internally Generated 3.3V Power Supply Output Pin. This pin should only be used to provide ex- ternal current for the pull-up resistors required for GPIO SHARE_CLK, and SYNC, and may be used to provide external current for pull-up resistors on RUN n, SDA, SCL and ALERT. No external decoupling is required.

For more information www.linear .com/L TM4676A pin FuncTions VDD25 (J6): Internally Generated 2.5V Power Supply Output Pin. Do not load this pin with external current; it is used strictly to bias internal logic and provides current for the internal pull-up resistors connected to the configuration- programming pins. No external decoupling is required. ASEL (G4): Serial Bus Address Configuration Pin. On any given I 2C/SMBus serial bus segment, every device must have its own unique slave address. If this pin is left open, the LTM4676A powers up to its default slave address of 0x4F (hexadecimal), i.e., 1001111 b (industry standard convention is used throughout this document: 7-bit slave addressing). The lower four bits of the LTM4676A’s slave address can be altered from this default value by connecting a resistor from this pin to SGND. Minimize capacitance— especially when the pin is left open—to assure accurate detection of the pin state. F SWPHCFG (H4): Switching Frequency, Channel Phase- Interleaving Angle and Phase Relationship to SYNC Con- figuration Pin. If this pin is left open—or , if the LTM4676A is configured to ignore pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL [6] = 1b—then the LTM4676A’s switching frequency ( FREQUENCY_SWITCH) and chan- nel phase relationships (with respect to the SYNC clock; MF R_PWM_CONFIG [2:0]) are dictated at SVIN power-up according to the LT M4676A’s NVM contents. Default factory values are : 500kHz operation ; Channel 0 at 0°; and Channel 1 at 180 °C (convention throughout this document: a phase angle of 0° means the channel ’s switch node rises coincident with the falling edge of the SYNC pulse). Connecting a resistor from this pin to SGND (and using the factory-default NVM setting of MFR_CONFIG_ALL [6] = 0 b) allows a convenient way to configure multiple LT M4676As with identical NVM contents for different switching frequencies of operation and phase interleaving angle settings of intra- and extra- module-paralleled channels —all, without GUI interven - tion or the need to “cu stom pre-program ” module NVM contents. (See the Applications Information section.) Minimize capacitance —especially when the pin is left open—to assure accurate detection of the pin state. V OUT0CFG ( G5): Output Voltage Select Pin for V OUT0, Coarse Setting. If the V OUT0CFG and V TRIM0CFG pins are both left open —or, if the LT M4676A is config - ured to ignore pin-strap (RCONFIG) resistors, i.e., MFR _CONFIG_ALL[6] = 1b—then the LTM4676A’s target VOUT0 output voltage setting ( VOUT_COMMAND0) and associated power-good and OV/UV warning and fault thresholds are dictated at SV IN power-up according to the LTM4676A’s NVM contents. A resistor* connected from this pin to SGND—in combination with resistor pin settings on VTRIM0CFG, and using the factory-default NVM setting of MFR_CONFIG_ALL[6] = 0 b—can be used to config - ure the LTM4676A ’s Channel 0 output to power-up to a VOUT_COMMAND va lue (and associated output voltage monitoring and protection/fault-detection thresholds) dif- ferent from those of NVM contents. (See the Applications In formation section.) Connecting resistor(s) from VOUT0CFG to SGND and/or V TRIM0CFG to SGND in this manner al - lows a convenient way to configure multiple LTM4 676As with identical NVM contents for different output voltage settings—all without GUI intervention or the need to “custom-pre-program” module NVM contents. Minimize capacitance— especially when the pin is left open —to assure accurate detection of the pin state. Note that use of RCONFIGs on V OUT0CFG/VTRIM0CFG can affect the VOUT0 range setting (MFR_PWM_MO DE0[1]) and loop gain. VTRIM0CFG (H5): Output Voltage Select Pin for VOUT0, Fine Setting. Works in combination with V OUT0CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of Channel 0, at SV IN power-up. (See V OUT0CFG and the Applications Information section.) Minimize capacitance— especially when the pin is left open—to assure accurate detection of the pin state. Note that use of RCONFIGs* on V OUT0CFG/VTRIM0CFG can affect the VOUT0 range setting (MFR_PWM_MODE0[1]) and loop gain. VOUT1CFG (G6): Output Voltage Select Pin for VOUT1, Coarse Setting. If the VOUT1CFG and VTRIM1CFG pins are both left open—or , if the LTM4676A is configured to ignore pin- strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6] = b—then the LTM4676A’s target V OUT1 output voltage setting (VOUT_COMMAND1) and associated OV/UV warn- ing and fault thresholds are dictated at SV IN power-up *In applications where VOUT0 and VOUT1 are paralleled, the respective VOUTnCFG and VTRIMnCFG pin-pairs can be electrically connected together; common RCONFIG resistors can be applied whose values are half of what is prescribed in Table 2 and Table 3. See Figure 42 for example.

For more information www.linear .com/L TM4676A pin FuncTions according to the LTM4676A’s NVM contents, in precisely the same fashion that the V OUT0CFG and VTRIM0CFG pins affect the respective settings of V OUT0 /Channel 0. (See VOUT0CFG, V TRIM0CFG and the Applications Information section.) Minimize capacitance—especially when the pin is left open—to assure accurate detection of the pin state. Note that use of RCONFIGs* on V OUT1CFG/VTRIM1CFG can affect the V OUT1 range setting (MFR_PWM_MODE 1[1]) and loop gain. VTRIM1CFG (H6): Output Voltage Select Pin for VOUT1, Fine Setting. Works in combination with V OUT1CFG to affect the VOUT_COMMAND (and associated output voltage monitoring and protection/fault-detection thresholds) of Channel 1, at SV IN power-up. (See V OUT1CFG and the Applications Information section.) Minimize capacitance— especially when the pin is left open—to assure accurate detection of the pin state. Note that use of RCONFIGs* on V OUT1CFG/VTRIM1CFG can affect the VOUT1 range setting (MFR_PWM_MODE1[1]) and loop gain. SYNC (E7): PWM Clock Synchronization Input and Open- Drain Output Pin. The setting of the FREQUENCY_SWITCH command dictates whether the LTM4676A is a “sync master” or “sync slave” module. When the LTM4676A is a sync master , FREQUENCY_SWITCH contains the com- manded switching frequency of Channels 0 and 1—in PMBus linear data format— and it drives its SYNC pin low for 500ns at a time, at this commanded rate. In contrast, a sync slave uses MFR_CONFIG_ALL[4]=1 b and does not pull its SYNC pin low. The LTM4676A’s PLL synchronizes the LTM4676A’s PWM clock to the waveform present on the SYNC pin—and therefore, a resistor pull-up to 3.3V is required in the application, regardless of whether the LTM4676A is a sync master or slave. EXCEPTION: driving the SYNC pin with an external clock is permissible; see the Applications Information section for details. SCL (E6): Serial Bus Clock Open-Drain Input (Can Be an Input and Output, if Clock Stretching is Enabled). A pull-up resistor to 3.3V is required in the application for digital communication to the SMBus master(s) that nominally drive this clock. The LTM4676A will never encounter scenarios where it would need to engage clock stretching unless SCL communication speeds exceed 100kHz—and even then, LTM4676A will not clock stretch unless clock stretching is enabled by means of setting MFR_CONFIG_ALL[1] = 1 b. The factory-default NVM configuration setting has MFR_CONFIG_ALL[1] = 0 b: clock stretching disabled. If communication on the bus at clock speeds above 100kHz is required, the user’s SMBus master(s) need to implement clock stretching support to assure solid serial bus communications, and only then should MFR_CONFIG_ALL[1] be set to 1 b. When clock stretching is enabled, SCL becomes a bidirectional, open- drain output pin on LTM4676A. SDA (D6): Serial Bus Data Open-Drain Input and Output. A pull-up resistor to 3.3V is required in the application. ALERT (E5): Open-Drain Digital Output. A pull-up resistor to 3.3V is required in the application only if SMBALERT interrupt detection is implemented in one’s SMBus system. SHARE_CLK (H7): Share Clock, Bidirectional Open-Drain Clock Sharing Pin. Nominally 100kHz. Used for synchro- nizing the time base between multiple LTM4676 As (and any other Linear Technology devices with a SHARE_CLK pin)—to realize well-defined rail sequencing and rail track- ing. Tie the SHARE_CLK pins of all such devices together; all devices with a SHARE_CLK pin will synchronize to the fastest clock. A pull-up resistor to 3.3V is required when synchronizing the time base between multiple devices. If synchronizing the time base between multiple devices is not needed and MFR_CHAN_CONFIGn[2] = 0b, only then is a pull-up resistor not required. GPIO 0, GPIO1 (E4 and F4, Respectively): Digital, Program- mable General Purpose Inputs and Outputs. Open-drain outputs and/or high impedance inputs. The LTM4676A’s factor y-default NVM configurations for MFR_GPIO_ PROPAGATEn—0x6893—and MFR_GPIO_RESPONSEn— 0xC0—are such that: (1) when a channel-specific fault con- dition is detected—such as channel OT (overtemperature) or output UV/OV —the respective GPIOn pin pulls logic low; (2) when a non-channel specific fault condition is detect- ed—such as input OV or control IC OT—both GPIOn pins pull logic low; (3) the LTM4676A ceases switching action on Channel 0 and 1 when its respective GPIO n pin is logic *In applications where VOUT0 and VOUT1 are paralleled, the respective VOUTnCFG and VTRIMnCFG pin-pairs can be electrically connected together; common RCONFIG resistors can be applied whose values are half of what is prescribed in Table 2 and Table 3. See Figure 42 for example.

For more information www.linear .com/L TM4676A pin FuncTions low. Most significantly, this default configuration provides for graceful integration and inter-operation of LTM4676A with paralleled channel(s) of other LTM4676A(s)—in terms of properly coordinating efforts in starting, ceasing, and resuming switching action and output voltage regulation, in unison—all without GUI intervention or the need to “custom-preprogram” module NVM contents. Pull-up resis- tors from GPIO n to 3.3V are required for proper operation in the vast majority of applications. (Only if the LTM4676A’s MFR_GPIO_RESPONSEn value were set to 0x00 might pull-ups be unnecessary. See the Applications Information section for details.) WP (K6): Write Protect Pin, Active High. An internal 10μA current source pulls this pin to V DD33. If WP is open circuit or logic high, only I 2C writes to PAGE, OP - ERATION, CLEAR_FAULTS , MFR_CLEAR_PEAKS and MFR_EE_UNLOCK are supported. Additionally, individual faults can be cleared by writing 1 b’s to bits of interest in registers prefixed with “STATUS”. If WP is low, I2C writes are unrestricted. RUN0, RUN1 (F5 and F6, Respectively): Enable Run Input for Channels 0 and 1, Respectively. Open-drain input and output. Logic high on these pins enables the respective outputs of the LTM4676A. These open-drain output pins hold the pin low until the LTM4676A is out of reset and SV IN is detected to exceed VIN_ON. A pull-up resistor to 3.3V is required in the application. Do not pull RUN logic high with a low impedance source. TSNS 0a, TSNS0b (D5 and C5, Respectively): Channel 0 Temperature Excitation/Measurement and Thermal Sensor Pins, Respectively. Connect TSNS0a to TSNS0b. This allows the LTM4676A to monitor the Power Stage Temperature of Channel 0. TSNS 1a, TSNS1b (J5 and K5, Respectively): Channel 1 Temperature Excitation/Measurement and Thermal Sensor Pins, Respectively. In most applications, connect TSNS1a to TSNS 1b. This allows the LTM4676A to monitor the Power Stage Temperature of Channel 1. See the Applica- tions Information section for information on how to use TSNS 1a to monitor a temperature sensor external to the module, e.g., a PN junction on the die of a microprocessor . ISNS0a+, ISNS0b+ (F2 and F1, Respectively): Channel 0 Positive Current Sense and Kelvin Sense Pins, Respectively. Connect I SNS0a+ to ISNS0b+. ISNS1a+, ISNS1b+ (H2 and H1, Respectively): Channel 1 Positive Current Sense and Kelvin Sense Pins, Respectively. Connect I SNS1a+ to ISNS1b+. ISNS0a–, ISNS0b– (E2 and E1, Respectively): Channel 0 Negative Current Sense and Kelvin Sense Pins, Respec- tively. Connect I SNS0a– to ISNS0b–. ISNS1a–, ISNS1b– (G2 and G1, Respectively): Channel 1 Negative Current Sense and Kelvin Sense Pins, Respec- tively. Connect I SNS1a– to ISNS1b–. COMP0a, COMP1a (E8 and H8, Respectively): Current Control Threshold and Error Amplifier Compensation Nodes for Channels 0 and 1, Respectively. The trip threshold of each channel’s current comparator increases with a respective rise in COMP na voltage. Small filter capacitors (22pF) internal to the LTM4676A on these COMP pins (terminated to SGND) introduce high frequency roll off of the error-amplifier response, yielding good noise rejection in the control loop. See COMP 0b/COMP1b. COMP0b, COMP1b (D8 and J8, Respectively): Internal Loop Compensation Networks for Channels 0 and 1, Re- spectively. For the vast majority of applications, the internal, default loop compensation of the LTM4676 A is suitable to apply “as is”, and yields very satisfactory results: apply the default loop compensation to the control loops of Chan- nels 0 and 1 by simply connecting COMP 0a to COMP 0b and COMP1a to COMP1b, respectively. In contrast, when more specialized applications require a personal touch the optimization of control loop response, this can be easily accomplished by connecting (an) R-C network(s) from COMP 0a and/or COMP 1a—terminated to SGND— and leaving COMP0b and/or COMP1b open, as desired. DNC (C10, E11, H11, K10): Do not connect these pins to external circuitry. Solder these pins only to mounting pads on the PC board for mechanical integrity. These pads must remain electrically open circuit.

For more information www.linear .com/L TM4676A siMpliFieD block DiagraM Decoupling requireMenTs VIN0 VOUT0 VIN 5.75V TO 26.5V SW0 SNUB0 GND ISNS0b– ISNS0b+ ISNS0a+ ISNS0a– TSNS0b TSNS0a VOSNS0+ VORB0+ VOSNS0– LOCAL HIGH FREQ MLCCs VORB0– COMP0a COMP0b VOUT1 SW1 SNUB1 GND ISNS1b– ISNS1b+ ISNS1a+ ISNS1a– TSNS1b TSNS1a VOSNS1[+] SGND [VOSNS1–] COMP1a CONTROLLER SIGNAL GND COMP1b SYNC ASEL 4676A F01 VDD25 VOUT0CFG VTRIM0CFG VTRIM1CFG VOUT1CFG FSWPHCFG SCL 5V TOLERANT ; PULL-UP RESISTORS NOT SHOWN 5V TOLERANT ; PULL-UP RESISTORS NOT SHOWN 3.3V TOLERANT ; PULL-UP RESISTOR NOT NEEDED SDA ALERT WP RUN0 RUN1 GPIO0 GPIO1 SHARE_CLK COUT0LF COUT1LF COUT1HFCOUT0HF VOUT0 ADJUSTABLE UP TO 5.5V UP TO 13A SVIN 1µF2.2nF 1µF MT0 600nH 600nH THERMAL SENSOR THERMAL SENSORMB0 MT1 MB1 2.2µF 2.2µF INTVCC VDD33 VIN1 CINHCINL THERMAL SENSOR ANALOG READBACK SIGNALS TO ERROR AMPLIFIER POWER CONTROL ANALOG SECTION POWER MANAGEMENT DIGITAL SECTION LOAD0 LOCAL HIGH FREQ MLCCs LOAD1 VORB1[+] VOUT1 ADJUSTABLE UP TO 5.5V UP TO 13A 2.2nF INTERNAL COMP SPI SLAVE SPI MASTER SYNC DRIVER OSC (32MHz) DIGITAL ENGINE EEPROM ROM RAM INTERNAL COMPADC 3.3V TOLERANT ; PULL-UP RESISTORS NOT SHOWN 3.3V TOLERANT ; PULL-UP RESISTOR NOT SHOWN CONFIGURATION RESISTORS TERMINATING TO SGND NOT SHOWNFigure 1. Simplified LTM4676A Block Diagram SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CINH External High Frequency Input Capacitor Requirement (5.75V ≤ VIN ≤ 26.5V, VOUTn Commanded to 1.000V) IOUT0 = 13A, 3 × 22μF, or 4 × 10μF IOUT1 = 13A, 3 × 22μF, or 4 × 10μF 40 66 µF COUTnHF External High Frequency Output Capacitor Requirement (5.75V ≤ V IN ≤ 26.5V, VOUTn Commanded to 1.000V) IOUT0 = 13A IOUT1 = 13A 400 400 µF µF TA = 25°C. Using Figure 1 configuration.

For more information www.linear .com/L TM4676A FuncTional DiagraM VIN0 CINHCINL COUT0LF (Computed Total Input Current, IVINO + IVIN1 + ISVIN: READ_IIN) (Computed Channel 0 Input Current, IVIN0 + 1/2 • ISVIN: MFR_READ_IIN0) (Computed Channel 1 Input Current, IVIN1 + 1/2 • ISVIN: MFR_READ_IIN1) VIN 5.75V TO 26.5V (SVIN Telemetry: READ_VIN and MFR_VIN_PEAK) (PWM0 Telemetry: READ_DUTY_CYCLE0) (PWM1 Telemetry: READ_DUTY_CYCLE1) (IOUT0 Telemetry: READ_IOUT0 and MFR_IOUT_PEAK0) (IOUT1 Telemetry: READ_IOUT1 and MFR_IOUT_PEAK1) Channel 0 Thermal Sensor (Telemetry: READ_TEMPERATURE_10 and MFR_TEMPERATURE_1_PEAK0) Channel 1 Thermal Sensor (Telemetry: READ_TEMPERATURE_11 and MFR_TEMPERATURE_1_PEAK1) + + –– SVIN INTVCC VDD33 VIN1 INT FIL TER MT0 MT1 MB1MB0 POWER CONTROL ANALOG SECTIONVOUT0 GND ISNS0b– COUT0HF COUT1LF COUT1HF VOUT0 ADJUSTABLE UP TO 5.5V UP TO 13A VOUT1 ADJUSTABLE UP TO 5.5V UP TO 13A SW0 SNUB0 Optional Snubber Resistor for Moderate Reduction in EMI (Size: EIA0603 ~EIA2512) RSNUB0 UP TO Optional Snubber Resistor for Moderate Reduction in Radiated EMI (Size: EIA0603 ~EIA2512) RSNUB1 UP TO ZISNS0b– ISNS0b+ VOUT1 GND ISNS1b– SW1 SNUB1 ISNS1b+ ZISNS0b+ ISNS0a+ TSNS0b TSNS0a ∆ISNS0a, Channel 0 Current Sense Signal Channel 1 Current Sense Signal, ∆ISNS1a Channel 1 (VOUT1) Voltage Feedback Signal (Differential when Terminating SGND at LOAD1 as Shown) ∆VOSNS0, Differential Feedback Signal Channel 0 (VOUT0) Voltage Feedback Signal Channel 0 Current Demand Signal Channel 1 Current Demand Signal Channel 0 Internal Loop Compensation Channel 1 /uni00A0 Internal Loop Compensation Power Controller Thermal Sensor (Telemetry: READ_TEMPERATURE_2) ZISNS0a ZCOMP0b ISNS0a– ISNS1a+ TSNS1b TSNS1a VORB1[+] ISNS1a– VOSNS0+ VORB0+ VOSNS0– VOSNS1[+] SGND [VOSNS1–] VORB0– COMP0a COMP0b SCL SDA WP RUN0 RUN1 GPIO0 GPIO1 SHARE_CLK ALERT COMP1a COMP1b TMUX 2µA 30µA CURRENT MODE PWM CTRL. LOOPS, LIN. REGULATORS, DACs ADC, UV/OV COMPARATORS, VCO AND PLL, MOSFET DRIVERS AND POWER SWITCH LOGIC ∆VOSNS0 VOSNS1 ∆ISNS0a ∆ISNS1a SVIN÷39 PWM0 PWM1 8:1 MUX VTSNS DACs, OV/UV Comparators, Other POWER MANAGEMENT DIGITAL SECTION DIGITAL ENGINE, INCLUDING: ROM, RAM, NVM AND OSCILLATOR 16-BIT ADC SPI SLAVE R R TO E/A 22pF 22pF 1nF + 20k/uni03A9 1nF + 20k/uni03A9 A = 1 R R LOCAL HIGH FREQ MLCCs LOCAL HIGH FREQ MLCCs OUT0 Telemetry: READ_VOUT0 and MFR_VOUT_PEAK0) (VOUT1 Telemetry: READ_VOUT1 and MFR_VOUT_PEAK1) (LOAD0 Power Consumption Telemetry: READ_POUT0) LOAD0 ZCOMP1b ZISNS1a (LOAD1 Power Consumption Telemetry: READ_POUT1) LOAD1 Controller Signal GND (Switching Frequency Telemetry: READ_FREQUENCY) SYNC VDD25 ASEL FSWPHCFG VOUT0CFG VTRIM0CFG Configuration Resistors Terminating to SGND Not Shown V OUT1CFG VTRIM1CFG 4676A FD 14.3k 3.3V Tolerant; Pull-Up Resistor Not Shown SPI MASTER DIGITAL ENGINE, MAIN CONTROL EEPROMRAM SYNC DRIVERROM PROGRAM VDD33 COMPARE I2C-BASED SMBus INTERFACE WITH PMBus COMMAND SET (10kHz TO 400kHz COMPATIBLE) CHANNEL TIMING MANAGEMENT UVLO OSC (32MHz) CONFIG DETECT SINC3 VDD33 VDD33 10µA 5V Tolerant; Pull-Up Resistors Not Shown 5V Tolerant; Pull-Up Resistors Not Shown 3.3V Tolerant; Pull-Up Resistor Not Needed 3.3V Tolerant; Pull-Up Resistors Not Shown ZISNS1b– ZISNS1b+

For more information www.linear .com/L TM4676A TesT circuiTs Test Circuit 1. LTM4676A ATE High VIN Operating Range Configuration, 5.75V ≤ VIN ≤ 26.5V CINH 10µF CINL 150µF VIN 5.75V TO 26.5V COUTH0 100µF V OUT0 1V ADJUSTABLE UP TO 13A V OUT1 1V ADJUSTABLE UP TO 13A VIN0 VIN1 SVIN VDD33 SCL SDA ALERT RUN RUN1 GPIO0 GPIO1 SYNC SHARE_CLK WP V OUT0 TSNS0a TSNS0b ISNS0a+ ISNS0b+ ISNS0a– ISNS0b– VORB0+ VOSNS0+ VOSNS0– VORB0– VORB1 VOUT1 TSNS1a TSNS1b ISNS1a+ ISNS1b+ ISNS1a– ISNS1b– VOSNS1 SGND INTVCC VDD25 SW0 SW1 SNUB0 SNUB1 COMP0a COMP0b COMP1a COMP1b ASEL F SWPHCFG VOUT0CFG VTRIM0CFG VOUT1CFG VTRIM1CFG GND + COUTL0 OPT* COUTL1 OPT* LOAD0 COUTH1 100µF L TM4676A LOAD1 SMBus INTERFACE WITH PMBus COMMAND SET ON/OFF CONTROL, FAUL T MANAGEMENT AND POWER SEQUENCING PWM CLOCK SYNCH TIME BASE SYNCH (PULL-UP RESISTORS ON DIGITAL I/O PINS NOT SHOWN) RTH1 30.1k *COUTL0, COUTL1 NOT USED IN ATE TESTING RTH0 30.1k 4676A TC01 CTH1 470pF CTH0 470pF Test Circuit 2. LTM4676A ATE Low VIN Operating Range Configuration, 4.5V ≤ VIN ≤ 5.75V RTH1 30.1k *COUTL0, COUTL1 NOT USED IN ATE TESTING RTH0 30.1k CTH1 470pF CTH0 470pF CINH 10µF C INL 150µF VIN 4.5V TO 5.75V COUTH0 100µF V OUT0 1V ADJUSTABLE UP TO 13A V OUT1 1V ADJUSTABLE UP TO 13A VIN0 VIN1 SVIN VDD33 SCL SDA ALERT RUN RUN1 GPIO0 GPIO1 SYNC SHARE_CLK WP INTVCC VDD25 SW0 SW1 SNUB0 SNUB1 COMP0a COMP0b COMP1a COMP1b ASEL F SWPHCFG VOUT0CFG VTRIM0CFG VOUT1CFG VTRIM1CFG GND LOAD0 COUTH1 100µF L TM4676A LOAD1 SMBus INTERFACE WITH PMBus COMMAND SET ON/OFF CONTROL, FAUL T MANAGEMENT AND POWER SEQUENCING PWM CLOCK SYNCH TIME BASE SYNCH (PULL-UP RESISTORS ON DIGITAL I/O PINS NOT SHOWN) 4676A TC02 COUTL0 OPT* COUTL1 OPT* VOUT0 TSNS0a TSNS0b ISNS0a+ ISNS0b+ ISNS0a– ISNS0b– VORB0+ VOSNS0+ VOSNS0– VORB0– VORB1 VOUT1 TSNS1a TSNS1b ISNS1a+ ISNS1b+ ISNS1a– ISNS1b– VOSNS1 SGND

For more information www.linear .com/L TM4676A operaTion POWER MODULE INTRODUCTION The LTM4676 A is a highly configurable dual 13A out - put standalone nonisolated switching mode step-down DC/DC power supply with built-in EEPROM NVM (non- volatile memory) with ECC and I2C-based PMBus/SMBus 2-wire serial communication interface capable of 400kHz SCL bus speed. T wo output voltages can be regulated OUT0, VOUT1—collectively, VOUTn) with a few external input and output capacitors and pull-up resistors. Read- back telemetry data of average input and output voltages and currents, Channel P WM duty cycles, and module temperatures are continually digitized cyclically by an integrated 16-bit ADC (analog-to-digital converter). Many fault thresholds and responses are customizable. Data can be autonomously saved to EEPROM when a fault occurs, and the resulting fault log can be retrieved over I 2C at a later time, for analysis. The LTM4676A provides precisely regulated output volt- ages between 0.6VDC to 5.5VDC (±0.5% above 1VDC , ±5mV below 1VDC ). The target output voltage can be set according to pin-strapping resistors (V OUTnCFG and VTRIMnCFG pins), NVM/register settings, and altered on the fly via the I 2C interface. The output voltage can be modified by the user at any time with a write to PMBus VOUT_COMMAND. Executing this command has a typical latency less than 10ms. Writes to PMBus OPERATION have a typical latency less than 1ms. The NVM factory-default switching frequency is 500kHz and the phase-interleaving angle between its two channels is 180°. Channel switch- ing frequency, phase angle, and phase relationship with re spect to the falling edge of the SYNC pin waveform can be configured according to a pin-strap resistor (FSWPHCFG pin) and NVM/register settings —though, not on the fly during regulation. The 7-bit I2C slave address of the module defaults to the value retrieved from MFR_ADDRESS[6:0] at power-up (factory default: 0x4F), but the least significant four bits of the address are set by resistor pin-strapping the ASEL pin. Bits [6:4] of MFR_ADDRESS can be writ - ten and stored to EEPROM. Between the ASEL resistor pi n-strap and user-configurable MFS_ADDRESS[6:4], the LTM4676A can take on any 7-bit slave address desired. With the exception of the ASEL pin, the module can be configured to ignore all pin-strap resistors, if desired (see MFR_CONFIG_ALL [6]). The LTM4676A is a pin-compatible replacement to the LTM4676, with enhanced feature set. n Tighter output voltage regulation accuracy (total DC error): ±0.5% rather than ±1%, for VOUTn ≥ 1V; ±5mV rather than ±1%, for 0.6V ≤ VOUTn < 1V. n The module’ s turn-on start-up time (see tSTART in the Electrical Characteristics table) has been reduced to 35ms (40ms, maximum, over temperature). n VOUT0 and V OUT1 are both configurable for up to 5.5VOUT. n An LTM4676A synchronizing to an external SYNC clock can be configured for better fault tolerance, i.e., the behavior of a “sync slave”-configured LTM4676A can be set to automatically operate at its nominal target switching frequency in the absence of a SYNC clock, rather than operate at the lower-end of its PLL sync- capture range. n MFR_ADC_CONTROL and MFR_ADC_TELEMETRY_ STATUS are new commands, enabling faster telemetry update rates—up to 125Hz in LTM4676A, compared to 10Hz in LTM4676, nominal. n PMBus compliance to Version 1.2 of Part I and Part II of PMBus Specifications documents. The LTM4676A sup- ports the PAGE_PLUS_READ, PAGE_PLUS_WRITE and SMBALERT_MASK commands. n Improved fault logging. See Appendix C, PMBus Com- mand Details. EEPROM enhanced with ECC. n For parallel-output applications, the differential ampli- fier sensing VOSNS0+/VOSNS0– can be used to regulate the paralleled VOUT0 and VOUT1 outputs. VOSNS1 can be connected to VOSNS0+ and SGND can be connected to power GND local to the module rather than at the point of load sensing-point, for routing convenience (MFR_PWM_CONFIG[7]). n Any 7-bit slave address can be assigned to the LTM4676A. Bits [6:4] of MFR_ADDRESS are user- configurable and can be stored to EEPROM. The least significant nibble of MFR_ADDRESS is assigned by the resistor pin-strap setting on the ASEL pin.

For more information www.linear .com/L TM4676A operaTion Table 1 provides a summary of LTM4676A’s supported PMBus commands, as well as a direct comparison to those of the LTM4676. For details on the supported commands, payloads and data formats see Appendix C: PMBus Com- mand Details. For introductory information about the PMBus Specifica- tion, see Appendix A : Similarity Between PMBus, SMBus and I2C 2-Wire Interface. For information about the data communication link layer and timing diagrams, see Ap - pendix B: PMBus Serial Digital Interface. Major features of the LTM4676 A strictly from a DC/DC converter power delivery point of view are as follows: n Up to 13A Output Current Delivery from Each of T wo Integrated Power Stages (See Front Page Figure)—or Up to 26A Output, Combined (See Figure 35 and Figure 42). n Wide Input Voltage Range: DC/DC Step-Down Con- version from 5.75V to 26.5V Input (See Figure 69). n DC/DC Step-Down Conversion from 4.5V to 5.75V Input, Connecting SVIN to INTVCC (See Figure 35). n DC/DC Step-Down Conversion Possible from Less Than 4.5V Input When an Auxiliary 5V Bias Supply Powers SVIN and INTVCC (See Figure 37). n Output Voltage Range: 0.5V to 5.5V on both VOUT0 and VOUT1. n Differential Remote Sensing of V OUT0 (V OSNS0 +/ VOSNS0–). For paralleled outputs, the VOSNS0+/VOSNS0– pin-pair can be configured as the feedback path for both V OUT0 and VOUT1 (see Figure 42 and, optionally, MFR_PWM_CONFIG[7]). n Start-Up Into a Pre-Biased Load Without Sinking Current. n Four LTM4676As Can Be Paralleled to Deliver Up to 100A (See Figure 39). n One LTM4676A Can Be Paralleled with Three LTM4620A or LTM4630 Modules to Deliver Up to 130A; Infer Rail Status and Telemetry of Paralleled LTM4620A or LTM4630 via the Sole LTM4676A (See Figure 40). n Discontinuous Mode Operation Available for Higher Light-Load Efficiency (MFR_PWM_MODE n[0]). n Output Current Limit and Overvoltage Protection. n Three Integrated Temperature Sensors, Over/Under - temperature Protection. n Constant Frequency Peak Current Mode Control. n Configurable Switching Frequency, 250kHz to 1MHz; Synchronizable to External Clock; Seven Configurable Channel Phase Interleaving Settings. n Internal Loop Compensation Provided; External Loop Compensation Can Be Applied, if Preferred. n Integrated Snubber Capacitors Enable EMI Reduction by Placing External Snubber Resistors Adjacent to the Module (see Figures 32 and 33). n Low Profile (16mm × 16mm × 5.01mm) BGA Package Power Solution Requires Only Input and Output Capaci- tors; at Most, Nine Pull-Up Resistors for Open-Drain Digital Signals; at Most, Six Pull-Down Resistors to Configure All Possible Pin-Strapping Options. Features of the LTM4676A that enable power system management, rail sequencing, and fault monitoring and reporting are as follows: n I2C-based PMBus/SMBus 2-Wire Serial Communication Interface (SDA, SCL) with ALERT Interrupt Pin, SCL Clock Capable of 400kHz Bus Communication Speeds with Clock Low Extending—or 100kHz, Otherwise. n Configurable Output Voltage. n Configurable Input Undervoltage Comparators (UVLO Rising, UVLO Falling). n Configurable Switching Frequency. n Configurable Current Limit. n Configurable Output Over/Undervoltage Comparators. n Configurable Turn-On and T urn-Off Delay Times. n Configurable Output Ramp Rise and Fall Times. n Non-Volatile Configuration Memory (NVM EEPROM) with ECC to Configure Aforementioned Settings, and More— Yielding Standalone Operation, if Desired, and

For more information www.linear .com/L TM4676A operaTion Also Enabling In-Situ Changes to the LTM4676A’s Configuration in Embedded Designs. n Monitoring and Reporting of Telemetry Data: Average Output and Input Currents and Voltages, Internal Tem- peratures, and Power Stage Duty Cycles—Continuously Digitized Cyclically by a 16-Bit ADC.

• Peak Observed Output Current and V oltage, Input Voltage, and Module Temperatures Can Be Polled and Cleared/Reset.
• ADC Latency Not Greater than 90ms, Nominal.
• Option to Monitor One External Temperature in Lieu of Channel 1 (VOUT1) Module Power Stage Temperature. n Monitoring, Reporting, and Configurable Response to Latching and Non-Latching Individual Fault and/or Warning Status, Including but Not Limited to: Output Over/Undervoltages.
• Input (SVIN) Over/Undervoltages.
• Module Input and Power Stage Output Overcurrents.
• Module Power Stage Over/Undertemperatures.
• Internal Control IC Overtemperature.
• Communication, Memory and Logic (CML) Faults. n Fault Logging Upon Detection of a Fault Condition. The LTM4676 A Can Be Configured to Automatically Upload a Fault Log to Its NVM, Consisting of: an Uptime Counter , Peak Observed Telemetry, Telemetry Gathered from the Six Most Recent Rounds of Cyclical ADC Data Leading Up to the Detection of the Fault That T riggered Fault Log Writing, and Fault Status Associated with That ADC History. n T wo Configurable Open-Drain General Purpose Input/ Output Pins ( GPIO0, GPIO1), Which Can Be Used for:
• Fault Reporting, e.g., as a System Interrupt Signal.
• Coordinating Turn-On/Off of the LTM4676A in Mul- tiphase/Multirail Systems.
• Propagating an Unfiltered Power Good Signal (Output of a V OUTn Undervoltage Comparator) to Command Turn-On/Off of a Downstream Rail. n A Write Protect (WP) Pin and Configurable WRITE_ PROTECT Register to Protect the Internal Configuration of RAM and NVM Against Unintended Changes via I2C. n Time-Base Interconnect (SHARE_CLK, 100kHz Heart- beat) for Synchronization in the T ime Domain Between Multiple LTM4676As. n Optional External Configuration Resistors (RCONFIGs) for Setting Start-Up Output V oltages, Switching Fre - quency and Channel-to-Channel Phase Interleaving Angle. n Any 7-Bit Slave Address Can Be Assigned to the LTM4676A (0x4F Default), Configured by Resistor Pin Strapping the ASEL Pin and User-Editable Bits [7:4] of MFR_ADDRESS. P OWER MODULE CONFIGURABILIT Y AND READBACK DATA This section of the data sheet describes all the configurable features and readable data of the LTM4676A accessible via I2C. The relevant command code name(s) are indi - cated by use of all capital letters, e.g., “VIN_ON”. Refer to T able 1 and Appendix C: PMBus Command Details of this data sheet for details of the command code, payload size, data format and factory-default value. Specific reg - ister bits of some registers are indicated with the use of brackets, i.e., “[” and “]”. The least significant bit (LSB) of a register is bit number zero, indicated by “[0]”. The most significant bit of a byte-long (8-bit-long) register is bit number seven, indicated by “[7]”. The most significant bit (MSB) of a word-long (16-bit-long) register is bit number fifteen, indicated by “[15]”. Multiple bits of a register can be alluded to with the use of a colon, e.g., bits 2, 1 and 0 of the MFR_PWM_CONFIG register are indicated by “MFR_PWM_CONFIG[2:0]”. Bits can take on values of 0 b or 1b. The subscripted “b” suffix indicates the number’s value is in binary. Values in hexadecimal are indicated with a “0x” prefix. For example, decimal value “89” is indicated by 0x59 and 01011001 b (8-bit-long values), as well as 0x0059 and 0000000001011001b (16-bit-long values). One further shorthand notion the reader will notice is the italicized “ n” or “n”. “n” can take on a value of 0 or 1—and provides an easy way to refer to registers which are paged

For more information www.linear .com/L TM4676A operaTion commands, i.e., register names which have the same com- mand code value but can be configured independently (or yield channel-specific telemetr y) for Channel 0 (Page 0, or 0x00) vs Channel 1 (Page 1, or 0x01). Registers lack- ing an “n” are therefore easily identified as being global in nature, i.e., common to both Channels/Outputs. For example, the switching frequency setting commanded by register FREQUENCY_SWITCH is common to both channels, and lacks “ n”. Another example: the READ_VIN register contains the digitized input voltage as seen at the SV IN pin, and SVIN is unique, i.e., common to both Chan- nels. In contrast, the nominal commanded output voltage is indicated by the register VOUT_COMMAND n. The “n” indicates that VOUT_COMMAND can be set differently for Channel 0 vs Channel 1. Executing the PAGE Com - mand (Command Code 0x00) with payload 0x00 sets the LTM4676 A to write/read data pertaining to Channel 0 in all subsequent I2C transactions until the Page is changed. Executing the PAGE Command with payload 0x01 sets the LTM4676A to write/read data pertaining to Channel 1 in all subsequent I 2C transactions until the Page is changed. Executing the PAGE Command with payload 0xFF sets the LTM4676A to write data pertaining to Channels 0 and 1 in all subsequent I 2C write transactions until the Page is changed. Reads from and writes to global registers do not require setting the Page to 0xFF . Reads from channel- specific (i.e., non-global) registers when the Page is set to 0xFF result in the LTM4676A reporting the value on Page 0x00 (i.e., Channel 0-specific data). The list below itemizes aspects of the LTM4676A relating to power supply functions that are configurable by I communications—provided the state of the WP (write protect) pin and the WRITE_PROTECT register value permit the I 2C writes—and by EEPROM settings: n Output start-up voltages (VOUT_COMMAND n), the maximum commandable output voltages (VOUT_MAXn), output margin high (VOUT_MARGIN_HIGHn) and margin low (VOUT_MARGIN_LOWn) command voltages, and output over/undervoltage warning and fault thresholds (VOUT_OV_WARN_LIMIT n, VOUT_OV_FAULT_LIMITn , VOUT_UV_WARN_LIMIT n, and VOUT_UV_FAULT_ LIMITn). Additionally, these values can be configured at SVIN power-up according to resistor-pin strapping of the VOUT0CFG, VTRIM0CFG, VOUT1CFG and/or VTRIM1CFG pins, provided MFR_CONFIG_ALL[6] = 0b. n Output voltages, on the fly, including transition rate V/∆t), VOUT_TRANSITION_RATE n— either by I 2C writes to the VOUT_COMMAND n, VOUT_MARGIN_ HIGHn, or VOUT_MARGIN_LOWn registers, and/or to the OPERATIONn register . n Input undervoltage-lockout, rising ( VIN_ON) and input undervoltage lockout, falling (VIN_OFF), based on the SV IN pin voltage. n Switching frequency (FREQUENCY_SWITCH) and chan- nel phase-interleaving angle (MFR_PWM_CONFIG[2:0]). However , these parameters can be changed via I 2C communications only when the LTM4676A’s channels are off, i.e., not switching. The LTM4676A synchronizes its switching frequency to a clock signal supplied to its SYNC pin when MFR_CONFIG_ALL[4]=1 b. These pa - rameters can be configured at SVIN power-up according to resistor-pin strapping of the FSWPHCFG pin, provided MFR_CONFIG_ALL[6] = 0b. n Output voltage turn-on and turn-off sequencing and associated watchdog timers, namely: Output voltage turn-on delay time (the time delay from the LTM4676 A being commanded to turn on, e.g., by the RUNn pin toggling from logic low to high, before switching action commences. TON_DELAYn).

• Output voltage soft-start ramp-up time (TON_RISEn).
• The amount of time (TON_MAX_FAULT_LIMITn) per- mitted to elapse after the LTM4676A is commanded to turn on, e.g., by the RUN n pin toggling from logic low to high, after which, if the output voltage fails to exceed the output undervoltage fault threshold (VOUT_UV_FAULT_LIMIT n), the LTM4676A’s output (VOUTn) is declared to have not come up in a timely manner .
• The LTM4676 A’s response to any such afore- mentioned TON_MAX_FAULT_LIMIT n event (TON_MAX_FAULT_RESPONSEn).
• Output voltage soft-stop ramp-down time (TOFF_FALLn).

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• Output voltage turn-off delay time (the time delay from the LTM4676A being commanded to turn off, e.g., by the RUNn pin toggling from logic high to low, before switching action ceases. TOFF_DELAYn).
• When commanded to turn off its output— or, when turning off its output in response to a fault— configuring whether the LTM4676A's output (V OUTn) becomes high impedance (“ High-Z” or “ three state”—turning off both MTn and MBn in the power stage). (“Immediate Off”, ON_OFF_CONFIG n[0] = 1b vs configuring the output voltage to be ramped down according to TOFF_FALL n and/or TOFF_DELAYn set- tings, ON_OFF_CONFIGn[0] = 0b).
• The amount of time (TOFF_MAX_WARN_LIMIT n) permitted to elapse after the LTM4676A is supposed to have turned off its output, i.e., at the end of the period dictated by TOFF_FALL n, after which, If the output voltage has not fallen below 12.5% of the former target voltage of regulation, the LTM4676A’s output (V OUTn) is declared to have not powered down in a timely manner . n Configurable output voltage restart time. Subsequent to the RUN n pin being pulled low, the LTM4676A pulls RUNn logic low, itself, and the output cannot be restarted until a minimum time has elapsed—the restart delay time. This delay assures proper sequencing of all system rails. The minimum restart delay processed by the LTM4676A is the longer of (TOFF_DELAY n + TOFF_FALLn + 136ms) vs the commanded MFR_RESTART_DELAY n register value. At the end of this delay, the LTM4676A releases its RUN n pin. n Configurable fault-hiccup retry delay time. When a fault occurs in which the LTM4676A’s fault response behavior to that fault is to reattempt power-up of its output voltage after said fault ceases to be present (e.g., “Infinite Retry”), the delay time for the LTM4676A to re-engage switching action is the longer of the MFR_RETRY_DELAY n time vs the time required for the output to decay below 12.5% of the formerly com- manded output voltage value (unless this lattermost criteria, i.e., requiring the output to decay below 12.5% is negated by the setting of MFR_CHAN_CONFIG n[0] to “1b”—which is the LTM4676A’s factory-NVM default setting). n Output over/undervoltage fault responses ( VOUT_OV_ FAULT_RESPONSEn, VOUT_UV_FAULT_RESPONSEn). n Time-averaged current limit warning and instantaneous p eak (cycle-by-cycle) fault thresholds, and fault response (IOUT_OC_WARN_LIMITn, IOUT_OC_FAULT_LIMITn, IOUT_OC_FAULT_RESPONSEn). n Channel (VOUT0, VOUT1) overtemperature warning and fault thresholds, and fault response (OT_WARN_LIMITn, OT_FAULT_LIMITn, OT_FAULT_RESPONSEn). n Channel (V OUT0 , V OUT1 ) undertemperature fault thresholds and fault response (UT_FAULT_LIMIT n, UT_FAULT_RESPONSEn). n Input overvoltage fault threshold and response (VIN_OV_FAULT_LIMIT, VIN_OV_FAULT_RESPONSE), based on the SVIN pin voltage. n Input undervoltage warning threshold (VIN_UV_WARN_ LIMIT) based on the SV IN pin voltage. n Module input overcurrent warning threshold (IIN_OC_WARN_LIMIT) The control IC within the LTM4676 A module ceases switching action if control IC temperature exceeds 160°C (Note 12). The control IC resumes operation after a 10°C cool-down hysteresis. Note that these typical parameters are based on measurements in a lab oven and are not production tested. This overtemperature protection is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operat- ing junction temperature may impair device reliability or permanently damage the device. T IME-AVERAGED AND PEAK READBACK DA TA Time-averaged telemetr y readback data accessible via I2C communications follow: n Channel output current (READ_IOUT n) and peak ob- served value of READ_IOUTn (MFR_IOUT_PEAKn).

For more information www.linear .com/L TM4676A operaTion n Channel output voltage (READ_VOUT n) and peak ob - served value of READ_VOUTn (MFR_VOUT_PEAKn). n Channel output power (READ_POUTn). n Channel input current (MFR_READ_IINn) and module input current (READ_IIN). n Channel temperatures (READ_TEMPERATURE_1n) and peak observed values of READ_TEMPERATURE_1 n (MFR_TEMPERATURE_1_PEAKn). n Control IC temperature (READ_TEMPERATURE _2) and peak observed value (MFR_TEMPERATURE_2_PEAK). n Input voltage (READ_VIN ), based on the voltage of the SVIN pin, and peak observed value of READ_VIN (MFR_VIN_PEAK). n Channel topside power MOSFET (MTn ) duty cycle (READ_DUTY_CYCLEn) Digitized cyclical telemetry is available at a 10Hz update rate, typical. Through the use of the MFR_ADC_CONTROL command, some signals of interest can be digitized more frequently—up to a 125Hz update rate, typical. Availability of newly digitized telemetry data can be made known via the MFR_ADC_TELEMETRY_STATUS command. Peak observed values of telemetry readback data can be cleared with the MFR_CLEAR_PEAKS I 2C command, provided the WRITE_PROTECT register value permits it. (Executing MFR_CLEAR_PEAKS can be performed regard- less of the state of the WP pin.) Details on the LTM4676A’s Fault Log Feature follow: n Fault logging is enabled when MFR_CONFIG_ALL[7] = 1b. n A fault log is present in NVM when STATUS_MFR_ SPECIFICn[3]Reports “1b”, which is propagated to the MFR Bit (Bit 12) of the STATUS_WORD register . n Retrieving fault log data, if present, is performed with the MFR_FAULT_LOG command. 147 bytes of data are retrieved using the PMBus-defined variant to the SMBus block read protocol. n The fault log contents in NVM, if present, are cleared by executing the MFR_FAULT_LOG_CLEAR command. n The fault log will not be written if a fault log is already present in NVM. n The LTM4676A can be forced to write a fault log to its NVM by executing the MFR_FAULT_LOG_STORE command; the LTM4676A will behave as if a channel faulted off. Note the command is NACKed and a CML fault is reported if a fault log is already present at the time of executing MFR_FAULT_LOG_STORE. When an external stimulus pulls the LTM4676A’s GPIO n pin(s) logic low, the respective channel (V OUTn) either: takes no action on it, i.e., ignores it completely— if MFR_GPIO_RESPONSEn = 0x00; or , turns off immediately, i.e., the power stage(s) become high impedance (“inhibited”)— if MFR_GPIO_RESPONSEn = 0xC0. The MFR_GPIO_PROPAGATEn register contents config- ure which fault(s) cause the LTM4676A to pull its GPIOn pin(s) logic low. I2C communications are originated by the user’s (system’s) I2C master device. Writes/reads to/from Channel 0 of the LTM4676A (VOUT0: PAGE 0x00), to/from Channel 1 of the LTM4676A (VOUT1: PAGE 0x01), or writes to both Channels 0 and 1 of the LTM4676A (VOUT0 and VOUT1: PAGE 0xFF) are possible. The target channel(s) of interest are selected by the I2C master by executing the PAGE command and sending the appropriate argument (0x00, 0x01, 0xFF) in the payload. The PAGE command is unrestricted, i.e., not affected by the WP pin or WRITE_PROTECT register settings. The LTM4676A always responds to its global slave ad- dresses, 0x5A and 0x5B. Commands sent to the global address 0x5A act the same as if the PAGE command were set to 0xFF , i.e., received commands are written to both channels simultaneously. Commands sent to the global address 0x5B are applied to the PAGE active at the time of the global address transaction, i.e., allows channel-specific command of all LTM4676A devices on the bus. I 2C commands not listed above that relate to Fault Status and EEPROM NVM Operations follow. Writing of the fol- lowing is possible provided the state of the WP (write protect) pin and the WRITE_PROTECT register value permits the I2C writes:

For more information www.linear .com/L TM4676A operaTion n Soliciting (reading) module fault status and clearing (writing) module fault status (CLEAR_FAULTS, STATUS_ BYTEn, STATUS_WORDn, STATUS_VOUTn, STATUS_ IOUTn, STATUS_INPUT, STATUS_TEMPERATURE n, STATUS_CML [ communications, memory, and/or logic], and STATUS_MFR_SPECIFICn [miscellaneous]). n Storing the LTM4676A’ s user-writable RAM register data to the EEPROM NVM (STORE_USER_ALL). n An alternate means to the S TORE_USER_ALL command to directly erase and write the LTM4676A’s EEPROM contents, protected by unlock keys, to facilitate program- ming of the LTM4676 A EEPROM in environments such as ICT (in-circuit test) and bulk programming by, e.g., embedded hardware or by the L TpowerPlay GUI. Also, a means to directly read the LTM4676A EEPROM contents (MFR_EE_UNLOCK, MFR_EE_ERASE, MFR_EE_DATA). n Instigating a soft reset of the LTM4676 A without power- cycling SVIN power (MFR_RESET). The MFR_RESET command triggers the download of EEPROM NVM data to RAM registers, as if SV IN power had been cycled. n Forcing a download of EEPROM NVM data to RAM reg- isters ( RESTORE_USER_ALL). This is indistinguishable from executing MFR_RESET. Other data that can be obtained from the LTM4676A via I2C communications are as follows: n Soliciting the LTM4676 A for its PMBus capabilities, as defined by PMBus (CAPABILITY):

• PEC (packet error checking). Note, the LTM4676A requires valid PEC in I 2C communications when MFR_CONFIG_ALL[2] = 1b. The NVM factory-default configuration is MFR_CONFIG_ALL[2] = 0b, i.e., PEC not required.
• I2C communications can be supported at up to 400kHz SCL bus speed. Note, clock low extending (clock stretching) must be enabled on the LTM4676A to ensure robust communications above 100kHz SCL bus speeds, i.e., MFR_CONFIG_ALL[1] = 1 b. The NVM factory-default configuration is MFR_CONFIG_ ALL[1] = 0 b, i.e. Clock stretching is disabled.
• The LTM4676 A has an SMBALERT (ALERT) pin and does support the SMBus ARA (alert response address) protocol. n Soliciting the module for the maximum output voltage it can be commanded to produce (MFR_VOUT_MAXn). n Soliciting the device for the data format of its output voltage-related registers (VOUT_MODE n). n Soliciting the device for the revisions of PMBus specifica- tions that it supports (Part I: Rev. 1.2 ; Part II: Rev 1.2). n Soliciting the device for the identification of the manu- facturer of the LTM4676A, “ LT C” (MFR_ID) and the manufacturer code representing the LTM4676A and revision, 0x47EX (MFR_SPECIAL_ID). n Soliciting the device for its part number , “LTM4676A” (MFR_MODEL). n Soliciting the module for its serial umber (MFR_SERIAL). n The digital status of the LTM4676A’ s I/O pads and validity of the ADC (MFR_PADS) and WP pin status (MFR_COMMON[0]). The following list indicates other aspects of the LTM4676A relating to power system management and power se - quencing that are configurable by I 2C communications— provided the state of the WP (write protect) pin and the WRITE_PROTECT register value permit the I 2C writes—and by EEPROM settings: n Providing multiple means to read/write data directly to a particular channel of the LTM4676A by assign - ing additional slave address for channels 0 and 1 (MFR_RAIL_ADDRESS n), the benefit of which is that it reduces page command usage and associated I2C traffic. It also facilitates altering the same register of multiple LTM4676A in unison without invoking the PMBus group command protocol. See also PAGE_PLUS_READ and PAGE_PLUS_WRITE. n Configuring the output voltage to be on or off by means other than the RUN n pin (ON_OFF_CONFIGn[3], OPERA- TION commands).

For more information www.linear .com/L TM4676A operaTion n Configuring whether the LTM4676 A performs a CLEAR_FAULTS command upon itself when ei - ther RUNn pin toggles from logic low to logic high. (MFR_CONFIG_ALL[0]). n Configuring whether the LTM4676 A pulls RUNn logic low when the LTM4676A is commanded off by other means (MFR_CHAN_CONFIGn[4]). n Configuring the response of the LTM4676A when it is commanded to turn on its output prior to the completion of processing TOFF_DELAYn and TOFF_FALLn power- down sequencing (MFR_CHAN_CONFIGn[3]). n Configuring whether the LTM4676 A’s output is disabled when SHARE_CLK is held low (MFR_CHAN_ CONFIG n[2]). n Configuring whether the ALER T pin is pulled low when GPIOn is pulled low by external stimulus (MFR_CHAN_CONFIGn[1]). n Setting the value of the MFR_IIN_OFFSET n registers, representing an estimate of the current drawn by the SV IN pin. The SVIN pin current is not measured by the LTM4676A but the MFR_IIN_OFFSETn is used in com- puting and reporting channel and total module input currents (MFR_READ_IIN n, READ_IIN). n Three words (six bytes) of the LTM4676 A’s EEPROM that are available for storing user data. (USER_DATA_03n, USER_DATA_04). n Invoking or releasing several levels of I2C write protec- tion (WRITE_PROTECT). n Configuring the bus timeout for 255ms (MFR_CONFIG_ ALL[3]=1b) if the host needs more time to complete I2C transactions. n Determining whether the user-editable RAM register values are identical to the contents of the user NVM (MFR_COMPARE_USER_ALL). n Setting the programmable output voltage range of VOUT to a narrower range (0.5V to 2.75V) in order to achieve a higher resolution of V OUT adjustment than is available by default (MFR_PWM_MODEn[1]). MFR_PWM_MODE cannot be changed on the fly; switching action must be off. Note that altering the VOUT range alters the gain of the control loop and may therefore require loop compensation to be adjusted. n Altering the temperature coefficient of the LTM4676A’s current sensing elements, if needed (MFR_IOUT_CAL_ GAIN_TCn) (uncommon to alter this parameter from its NVM-Factory default setting). n Altering the gain or offset of the power stage sensors (MFR_TEMP_1_GAIN n and MFR_TEMP_1_OFFSETn)— or that of the external temperature sensor , when an external temperature sensor is used on the TSNS pin. (Uncommon to alter this parameter from its NVM- factory default setting). n Configuring whether the LTM4676 A Pulls SHARE_CLK logic low when SVIN has fallen outside Its UVLO thresh- olds (MFR_PWM_CONFIG[4] ). MFR_PWM_CONFIG cannot be changed on the fly; switching action must be off (uncommon to alter this parameter from its NVM- factory default setting). n Configuring whether the LTM4676A’ s output voltage digital servos are active vs disengaged (MFR_PWM_ MODE n[6]. Uncommon to alter this parameter from its NVM-factory default settings). n Configuring whether the LTM4676A’ s current limit range is set to high range vs low range. (MFR_PWM_ MODE n[7]. Not recommended to alter this parameter from its NVM-factory default settings). Remaining LTM4676A status that can be queried over I2C communications follow: n Access to three “hand-shaking” status bits (MFR_ COMMON[6:4]) to ease implementation of PMBus busy protocols, i.e., enabling fast and robust system level communication through polling of these bits to infer LTM4676A’s readiness to act on subsequent I 2C writes. (See PMBus communication and command processing, in the Applications Information section.) n Providing a means to determine whether the LTM4676 A NVM download to RAM has occurred (“NVM Initialized,” MFR_COMMON[3]).

For more information www.linear .com/L TM4676A operaTion n Providing a means other than ARA protocol to de- termine whether the LTM4676 A is pulling ALERT low (MFR_COMMON[7]). n Detecting a SHARE_CLK timeout event (MFR_COMMON[1]). n Verifying or Altering the Slave Address of the LTM4676A (MFR_ADDRESS). P OWER MODULE OVER VIEW A dedicated remote-sense amplifier precisely kelvin-senses V OUT0’s load via the differential pin-pair formed by VOSNS0+ and VOSNS0–. VOUT0 can be commanded to between 0.5VDC and 5.5VDC. VOUT1 is sensed via the pin-pair formed by VOSNS1 and signal ground of the module’s SGND. VOUT1 can be commanded to between 0.5VDC and 5.5VDC. Output voltage readback telemetry is available over I (READ_VOUTn registers). Peak output voltage readback telemetry is accessible in the MFR_READ_VOUT_PEAKn registers. If VOSNS0– exceeds VOSNS+, no phase reversal of the differentially-sensed output voltage feedback signal occurs (Note 12). Similarly, no phase reversal occurs when SGND exceeds V OSNS1(Note 12). For added flexibility, the VOSNSO+/VOSNSO– feedback pins can be configured as the control loop feedback path for both V OUT0 and VOUT1 by setting MFR_PWM_CONFIG[7]=1b. (See Figure 42). The typical application schematic is shown in Figure 69 on the back page of this data sheet. The LTM4676A can operate from input voltages between 5.75V and 26.5V (see front page figure). In this configura- tion, INTV CC MOSFET driver and control IC bias is gener- ated internally by an LDO fed from SV IN to produce 5V at up to 100mA peak output current. Additional internal LDOs—3.3V (V DD33), derived from INTV CC, and 2.5V (VDD25), derived from V DD33—bias the LTM4676A’s digital circuitry. When INTVCC is connected to SV IN, the LTM4676A can operate from input voltages between 4.5V and 5.75V (see Figure 35). Control IC bias (SV IN) is routed independent of the inputs to the power stages (VIN0, VIN1); this enables step-down DC/DC conversion from less than 4.5V input (see Figure 37), so long as auxiliary power (4.5V ~ 26.5V) is available to bias the control IC appropriately. Furthermore, the inputs of the two power stages are not connected together internal to the module; therefore, DC/DC step-down conversion from two different source power supplies can be performed. Per Note 6 of the Electrical Characteristics section, the output current may require derating for some operating scenarios. Detailed derating guidance is provided in the Applications Information section. The LTM4676A contains dual integrated constant frequency current mode control buck regulators (Channel 0 and Channel 1) whose built-in power MOSFETs are capable of fast switching speed. The factory NVM-default switching frequency clocks SYNC at 500kHz, to which the regula - tors synchronize their switching frequency. The default phase-interleaving angle between the channels is 180°. A pin-strapping resistor on FSWPHCFG configures the fre- quency of the SYNC clock (switching frequency) and the channel phase relationship of the channels to each other and with respect to the falling edge of the SYNC signal. (Not all possible combinations of switching frequency and phase-angle assignments are settable by resistor pin programming; see Table 4. Configure the LTM4676A’s NVM to implement settings not available by resistor-pin strapping.) When a F SWPHCFG pin-strap resistor sets the channel phase relationship of the LTM4676A’s channels, the SYNC clock is not driven by the module; instead, SYNC becomes strictly a high impedance input and channel switching frequency is then synchronized to SYNC provided by an externally-generated clock or sibling LTM4676A with pull-up resistor to V DD33. Switching frequency and phase relationship can be altered via the I2C interface, but only when switching action is off, i.e., when the module is not regulating either output. See the Applications Information section for details. Internal feedback loop compensation for Regulator 0 is available by connecting COMP 0a to COMP0b. (For Regula- tor 1, the connection is from COMP1a to COMP1b.) With current mode control and internal feedback loop com - pensation, the LTM4676A module has sufficient stability margins and good transient per formance with a wide range of output capacitors —even all-ceramic MLCCs. Table 20 provides guidance on input and output capacitors recommended for many common operating conditions. The Linear Technology μModule Power Design Tool is

and leaving COMPnb open circuit. impedance during NVM-download-to-RAM initialization. up due to the latch-off conditions imposed. turn-off in a unified fashion. Figure 2. Event (Voltage) Based Sequencing

For more information www.linear .com/L TM4676A operaTion TON_RISEn register . In the presence of a pre-biased VOUTn condition, the output voltage is brought into regulation in the same manner as aforementioned, with the exception that inductor current is prevented from going negative (the module’s controller is operated in discontinuous mode operation during start-up). In both cases, the output voltage reaches regulation in a consistent time, as measured with respect to RUN n toggling high. See start-up oscilloscope shots in the Typical Performance Characteristics section. Pulling the RUN n pin below 0.8V turns off the DC/DC converter , i.e., forces the respective regulator into a shutdown state. Factory NVM-default settings configure the LTM4676A to turn off its power stage MOSFETs im - mediately, thereby becoming high impedance. The output voltage then decays according to whatever output capaci- tance and load impedance is present. Alternatively, NVM/ register settings can configure the LTM4676 A to actively discharge VOUTn when RUNn is pulled logic low, accord- ing to prescribed TOFF_DELAY n delay and TOFF_FALL n ramp-down times. See the Applications Information section for details. The LTM4676A does not feature an explicit, analog TRACK pin. Rail-to-rail tracking and sequencing is handled digitally, as explained previously. Bussing the open-drain SHARE_CLK pins of all LTM4676As (and providing a pull-up resistor to V DD33) provides a means for all LTM4676As in the system to synchronize their time-base (or “heartbeat”) to the fastest SHARE_CLK clock. Sharing the heartbeat amongst all LTM4676A en - sures that all rails are sequenced according to expectations; it negates timing errors that could other wise materialize due to SHARE_CLK (time-base) tolerance and part-to-part variation. to ISNS0b–; ISNS1a+ to I SNS1b+; and I SNS1a– to I SNS01b–. Current sense information is derived from across the power inductors (ISNSnb+/ISNSnb– pin-pairs) internal to the LTM4676A and made available to the internal control IC’s current control loops and ADC sensors (I SNSna+/ISNSna–) by the aforementioned connections. Output current readback telemetry is available over I 2C (READ_IOUTn registers). Peak output current readback telemetry is available in the MFR_READ_IOUT_PEAK n registers. Output power readback is computed by the LTM4676A according to: READ_POUTn = READ_VOUTn • READ_IOUTn Alternating excitation currents of 2µA and 30µA are sourced from each of the TSNS 0a and TSNS1a pins. Con- necting TSNS0a to TSNS0b, and then TSNS1a to TSNS1b, temperature sensing of the Channel 0 and Channel 1 power stages is realized by the LTM4676A digitizing the voltages that appear at the PNP transistor temperature sensors that reside at pins TSNS 0b and TSNS1b, respec- tively. The LTM4676A performs what is known in the industry as delta VBE ( ∆VBE) computations and makes channel (power stage) temperature telemetry available over I 2C (READ_TEMPERATURE_1n). The junction tem- perature of the control IC within the LTM4676A is also available over I 2C (READ_TEMPERATURE_2). Observed peak Channel temperatures can be read back in registers READ_MFR_TEMPERATURE_1_PEAK n. Observed peak temperature of the control IC can be read back in register MFR_READ_TEMPERATURE_2_PEAK. For a fixed load current, the amplitude of the current sense information changes over temperature due to the temperature coefficient of copper (inductor DCR), which is approximately 3900ppm/°C. This would introduce sig- nificant current readback error over the operating range of the module if not for the fact that the LTM4676A’s temperature readback information is used in conjunction with the perceived current sense signal to yield temperature- corrected current readback data. If desired, it is possible to use only the temperature readback information derived from the TSNS 0a/TSNS0b pins to yield temperature-corrected current readback data for both Channels 0 and 1. This frees up the Channel 1 temperature sensor to monitor a temperature sensor external to the LTM4676A. This is achieved by setting MFR_PWM_MODE 0[4] = 1 b (the NVM-factory default value is 0b). This degrades the current readback accuracy of Channel 1—more so when Channel 0 and Channel 1 are not paralleled outputs. However , the TSNS 1a pin becomes available to be connected to an external diode- connected small-signal PNP transistor (such as 2N3906) and 10nF X7R capacitor , i.e., an external temperature

For more information www.linear .com/L TM4676A operaTion sensor , whose temperature readback data and peak value are available over I2C (READ_TEMPERATURE_11, MFR_ READ_TEMPERATURE_1_PEAK1). Implementation of the aforementioned is as follows: (1) local to the LTM4676A, electrically connect a 10nF X7R capacitor directly from TSNS1a to SGND; (2) differentially route a pair of traces from the LTM4676A's TSNS1a and SGND pins to the tar- get PNP transistor; (3) electrically connect the emitter of the PNP transistor to TSN S1a; (4) electrically connect the collector and base of the PNP transistor to SGND. Power stage duty cycle readback telemetry is available over I2C (READ_DUTY_CYCLEn registers). Computed channel input current readback is computed by the LTM4676A as: MFR_READ_IINn = READ_DUTY_CYCLEn • READ_IOUTn + MFR_IIN_OFFSETn Computed module input current readback is computed by the LTM4676A as: READ_IIN =MFR_READ_IIN 0 +MFR_READ_IIN 1 where MFR_IIN_OFFSETn is a register value representing the SVIN input bias current. The SV IN current is not dig- itized by the module. The factory NVM-default value of MFR_IIN_OFFSETn is 30.5mA, representing the contribu- tion of current drawn by each of the module’s channels on the SV IN pin, when the power stages are operating in forced continuous mode at the factory-default switching frequency of 500kHz. See Table 8 in the Applications In- formation section for recommended MFR_IIN_OFFSET n setting vs Switching Frequency. The aforementioned method by which input current is calculated yields an ac- curate current readback value even at light load currents, but only as long as the module is configured for forced continuous operation (NVM-factor y default). SV IN and peak SVIN readback telemetry is accessible via I2C in the READ_VIN and MFR_VIN_PEAK registers, respectively. The power stage switch nodes are brought out on the SWn pin for functional operation monitoring and for optional installation of a resistor-capacitor snubber circuit (termi- nated to GND) for reduced EMI. Internal 2.2nF snubber capacitors connected directly to the switch nodes further facilitate implementation of a snubber network, if desired. See the Application Information section for details. The LTM4676 A features a write protect (WP) pin. If WP is open circuit or logic high, I2C writes are severely restricted: only I2C writes to the PAGE, OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS, and MFR_EE_UNLOCK commands are supported, with the exception that individual fault bits can be cleared by writing a “1 b” to the respective bits in the STATUS_* registers. Register reads are never restricted. Not to be confused with the WP pin, the LTM4676A fea- tures a WRITE_PROTECT register , which is also used to restrict I 2C writes to register contents. Refer to Appendix C: PMBus Command Details for details. The WP pin and the WRITE_PROTECT register provide a level of protection against accidental changes to RAM and EEPROM contents. The LTM4676A supports all possible 7-bit slave addresses. The factory NVM-default slave address is 0x4F . The lower four bits of the LTM4676A’s slave address can be altered from this default value by connecting a resistor from the ASEL pin to SGND. See Table 5 in the Applications Information section for details. Bits[6:4] can be altered by writing to the SLAVE_ADDRESS command. The value of the SLAVE_ADDRESS command can be stored to NVM, however , the lower four bits of the SLAVE_ADDRESS is always dictated by the ASEL resistor pin-strap setting. Up to four LTM4676A modules (8 channels) can be par- alleled, suitable for powering ~100A loads such as CPUs and GPUs. (See Figure 39) The LTM4676A can be paral- leled with LTM4620A or LTM4630 modules, as well (see Figure 40and Figure 41). EEPROM The LTM4676A’s control IC contains an internal EEPROM (non-volatile memory, NVM) with Error Correction Coding (ECC) to store configuration settings and fault log informa- tion. EEPROM endurance retention and mass write opera- tion time are specified in the Electrical Characteristics and Absolute Maximum Ratings sections. Write operations at T J < 0°C or at TJ > 85°C are possible although the Electri- cal Characteristics are not guaranteed and the EEPROM retention characteristics may be degraded. Read opera - tions performed at junction temperatures between –40°C and 125°C do not degrade the EEPROM. The fault logging function, which is useful in debugging system problems

For more information www.linear .com/L TM4676A operaTion that may occur at high temperatures, only writes to fault log-specific EEPROM locations (partitions). If occasional writes to these registers occur above 85°C junction, the slight degradation in the data retention characteristics of the fault log does not undermine the usefulness of the function. It is recommended that the EEPROM not be written when the control IC die temperature is greater than 85°C. If the die temperature exceeds 130°C, the LTM4676A’s control IC disables all EEPROM write operations. EEPROM write operations are subsequently re-enabled when the die temperature drops below 125°C. The degradation in EEPROM retention for temperatures >125°C can be approximated by calculating the dimen - sionless acceleration factor using the following equation: AF = e Ea k ⎝⎜ ⎞ ⎠⎟• 1 TUSE +273 – 1 TSTRESS +273 where: AF = acceleration factor Ea = activation energy = 1.4eV K = 8.617

• 10–5 eV/°K TUSE = 125°C specified junction temperature TSTRESS = actual junction temperature in °C Example: Calculate the effect on retention when operating at a junction temperature of 135°C for 10 hours. TSTRESS = 130°C TUSE = 125°C AF The equivalent operating time at 125°C = 16.6 hours. Thus the overall retention of the EEPROM was degraded by 6.6 hours as a result of operating at a junction tempera- ture of 130°C for 10 hours. The effect of the overstress is negligible when compared to the overall EEPROM retention rating of 87,600 hours at a maximum junction temperature of 125°C. Th e integrity of the EEPROM is checked with a CRC calcula- tion each time its data is read, such as after a power-on reset or execution of a RESTORE_USER_ALL or MFR_RESET command. If CRC error occurs, the MFR bit is set in the STATUS_BYTE and STATUS_WORD commands. The NVM CRC error bit in the STATUS_MFR_SPECIFIC com- mand is set and the ALERT and RUN pins are pulled low disabling the output as a safety measure. The device will only respond at special address 0x 7C or global addresses 0x5A and 0x5B. Internal EEPROM with CRC Protection and ECC The LTM4676A contains internal EEPROM with Error Correction Coding (ECC) to store user configuration set- tings and fault log information. EEPROM endurance and retention for user space and fault log pages are specified in the Absolute Maximum Ratings and Electrical Charac- teristics table. The integrity of the EEPROM memory is checked with a CRC calculation each time its data is to be read, such as after a power-on reset. A CRC error will prevent the controller from leaving the OFF state. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT and RUN pins will be pulled low. At that point the device will respond at special ad - dress 0x7C, which is only activated after an invalid CRC has been detected. The module will also respond to global addresses 0x5A and 0x5B, but all L TC PSM modules and ICs will respond to these addresses so users must be careful when using global addresses. EEPROM repair can be attempted by writing the desired configuration to the controller and executing a STORE_USER_ALL command followed by a CLEAR_FAULTS command. Contact the factory if EEPROM repair is unsuccessful. See the Applications Information section and Application Note 145, or contact the factory for details on efficient in- system EEPROM programming, including bulk EEPROM programming, which the LTM4676A also supports.

For more information www.linear .com/L TM4676A operaTion SERIAL INTERFACE The LTM4676 A serial interface is a PMBus compliant slave device and can operate at any frequency between 10kHz and 400kHz. The address is configurable using either the EEPROM or an external resistor divider . In addition the LTM4676A always responds to the global broadcast address of 0x5A (7 bit) or 0x5B (7 bit). Address 0x5A is not paged and is performed on both channels. 0x5B respects the page command. Because address 0x5A does not support page, it can not be used for any paged reading commands. The serial interface supports the following protocols defined in the PMBus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word and 7) read block 8) PAGE_PLUS_READ, 9) PAGE_PLUS_WRITE 10) SMBALERT_MASK read, 11) SMBALERT_MASK write. All read operations will return a valid PEC if the PMBus master requests it. If the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL com- mand, the PMBus write operations will not be acted upon until a valid PEC has been received by the LTM4676A. Communication Protection PEC write errors (if PEC_REQUIRED is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a CML fault. The CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_CML command, and the ALERT pin is pulled low. D EVICE ADDRESSING The LTM4676 A offers four different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ARA). Global addressing provides a means of the PMBus master to address all LTM4676A devices on the bus. The LTM4676A global address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and can- not be disabled. Commands sent to the global address act the same as if PAGE is set to a value of 0xFF . Commands sent are written to both channels simultaneously. Global command 0x5B (7 bit) or 0xB6 (8 bit) is paged and allows channel specific command of all LTM4676A devices on the bus. Other L TC device types may respond at one or both of these global addresses; therefore do not read from global addresses. Rail addressing provides a means for the bus master to simultaneously communicate with all channels con - nected together to produce a single output voltage (PolyPhase ®). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_ADDRESS command, allowing for any logical grouping of channels that might be required for reliable system control. Do not read from rail addresses because multiple L TC devices may respond. Device addressing provides the standard means of the PMBus master communicating with a single instance of an LTM4676A. The value of the device address is set by a combination of the ASEL configuration pin and the MFR_ADDRESS command. When this addressing means is used, the PAGE command determines the channel being acted upon. Device addressing can be disabled by writing a value of 0x80 to the MFR_ADDRESS. All four means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. Communication to LTM4676A devices at global and rail addresses should be limited to command write operations. F AUL T DETECTION AND HANDLING A variety of fault and warning reporting and handling mechanisms are available. Fault and warning detection capabilities include: n Input OV/FAUL T Protection and UV Warning n Average Input OC Warn n Output OV/UV Fault and Warn Protection n Output OC Fault and Warn Protection n Internal and External Overtemperature Fault and Warn Protection n External Undertemperature Fault Protection n CML Fault (Communication, Memory or Logic) n External Fault Detection via the Bidirectional GPIO n Pins.

For more information www.linear .com/L TM4676A operaTion In addition, the LTM4676A can map any combination of fault indicators to their respective GPIOn pin using the propagate GPIOn response commands, MFR_GPIO_PROPAGATEn. Typical usage of a GPIO pin is as a driver for an external crowbar device, overtemperature alert, overvoltage alert or as an interrupt to cause a microcontroller to poll the fault commands. Alternatively, the GPIO n pins can be used as inputs to detect external faults downstream of the control- ler that require an immediate response. The GPIO0 and/or GPIO1 pins can also be configured as power good outputs. Power good indicates the controller output is within the OV/UV fault thresholds. At power-up the pin will initially be three-state. If it is necessary to have the desired polar- ity on the pin at power-up in this configuration, attach a Schottky diode between the RUN pin of the propagated power good signal and the GPIO pin. The Cathode must be attached to RUN and the Anode to the GPIO pin (see Figure 2). If the GPIO pin is set to a power good status, the MFR_GPIO_RESPONSE must be ignore otherwise a latched off condition exists. As described in the Soft-Start section, it is possible to control start-up through concatenated events. If GPIOn is used to drive the RUN pin of another controller , the unfiltered VOUT_UV fault limit should be mapped to the GPIO pin. Any fault or warning event will cause the ALERT pin to as- sert low unless the ALERT is masked by the SMBALERT_ MASK command. The pin will remain asserted low until the CLEAR_FAULTS command is issued, the fault bit is written to a 1, the PMBus master successfully reads the device ARA register , bias power is cycled or a MFR_RESET or RESTORE_USER_ALL command is issued. Channel specific faults are cleared if the RUN pins are toggled OFF/ ON or the part is commanded OFF/ON via PMBus. If bit 0 of MFR_CONFIG_ALL is set to a 1, toggling the RUN pins OFF/ON or commanding the part OFF/ON via PMBus clears all faults. The MFR_GPIO_PROPAGATE n command determines if the GPIO pins are pulled low when a fault is detected; however , the ALERT pin is always pulled low if a fault or warning is detected and the status bits are updated unless the ALERT pin is masked using the SMBALERT_MASK command. Output and input fault event handling is controlled by the corresponding fault response byte as specified in Table 24 to Table 28. Shutdown recovery from these types of faults can either be autonomous or latched. For autonomous recovery, the faults are not latched, so if the fault condition is not present after the retry interval has elapsed, a new soft-start is attempted. If the fault persists, the controller will continue to retry. The retry interval is specified by the MFR_RETRY_DELAY command and prevents damage to the regulator components by repetitive power cycling. The MFR_RETRY_DELAY must be greater than 120ms. It can not exceed 83.88 seconds. Channel-to-channel fault dependencies can be created by connecting GPIO n pins together . In the event of an internal fault, one or more of the channels is configured to pull the bussed GPIO n pins low. The other channels are then configured to shut down when the GPIO n pins are pulled low. For autonomous group retry, the faulted channel is configured to release the GPIO n pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. If the fault response is LATCH_OFF, the GPIO pin remains asserted low until either the RUN pin is toggled OFF/ON or the part is commanded OFF/ON. The toggling of the RUN either by the pin or OFF/ON command will clear faults associated with the channel. If it is desired to have all faults cleared when either RUN pin is toggled, set bit 0 of MFR_CONFIG_ALL to a 1. The status of all faults and warnings is summarized in the STATUS_WORD and STATUS_BYTE commands. RESPONSES TO VOUT AND IOUT FAUL TS VOUT OV and UV conditions are monitored by comparators. The OV and UV limits are set in three ways. n As a Percentage of the VOUT if Using the Resistor Con- figuration Pins n In EEPROM if Either Programmed at the Factory or Through the GUI n By PMBus Command

For more information www.linear .com/L TM4676A operaTion The IIN and IOUT overcurrent monitors are performed by ADC readings and calculations. Thus these values are based on average currents and can have a nominal time latency of up to 90ms. The IOUT calculation accounts for the power inductor DCR and the temperature coefficient of the inductor's copper winding. The input current is equal to the sum of output current times the respective channel duty cycle plus the input offset current for each channel. If this calculated input current exceeds the IIN_OC_WARN_LIMIT the ALERT pin is pulled low and the IIN_OC_WARN bit is asserted in the STATUS_INPUT register . The LTM4676A provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (hic- cup). The retry interval is set in MFR_RETRY_DELAY n and can be from 120ms to 83.88 seconds in 1ms increments. The shutdown for OV/UV and OC can be done immediately or after a user selectable deglitch time. Output Overvoltage Fault Response A programmable overvoltage comparator (OV) guards against transient overshoots as well as long-term over- voltages at the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared regardless of the PMBus VOUT_OV_FAULT_RESPONSE n command byte value. This hardware level fault response delay is typically 2µs from the overvoltage condition to BG asserted high. Using the VOUT_OV_FAULT_RESPONSE n command, the user can select any of the following behaviors: n OV Pull-Down Only (OV cannot be ignored) n Shut Down (Stop Switching) Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAYn Either the Latch Off or Retry fault responses can be de - glitched in increments of (0 to 7) • 10µs. See Table 24. Output Undervoltage Response The response to an under voltage comparator output can be either: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAYn Either the Latch Off or Retry fault responses can be de - glitched in increments of (0 to 7) • 10µs. See Table 25. Peak Output Overcurrent Fault Response Due to the current mode control algorithm, peak inductor current is always limited on a cycle by cycle basis. The value of the peak current limit is specified in the Electrical Characteristics table. The current limit circuit operates by limiting the COMP na maximum voltage. DCR sensing is used so the COMPna maximum voltage has a temperature dependency directly proportional to the TC of the DCR of the inductor . The LTM4676A automatically monitors the power stage temperature sensors and modifies the maximum allowed COMP na to compensate for this term. The overcurrent fault processing circuitry can execute the following behaviors: n Current Limit Indefinitely n Shut Down Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAYn The overcurrent responses can be deglitched in increments of (0 to 7) • 16ms. See Table 26. R ESPONSES TO TIMING FAUL TS TON_MAX_FAULT_LIMITn is the time allowed for VOUT to rise and settle at start-up. The TON_MAX_FAULT_LIMITn condition is predicated upon detection of the VOUT_UV_ FAULT_LIMITn as the output is undergoing a SOFT_START sequence. The TON_MAX_FAULT_LIMITn time is started after TON_DELAYn has been reached and a SOFT_START

For more information www.linear .com/L TM4676A sequence is started. The resolution of the TON_MAX_ FAULT_LIMITn is 10µs. If the VOUT_UV_FAULT_LIMITn is not reached within the TON_MAX_FAULT_LIMITn time, the response of this fault is determined by the value of the TON_MAX_FAULT_RESPONSE n command value. This response may be one of the following: n Ignore n Shut Down (Stop Switching) Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAYn This fault response is not deglitched. A value of 0 in TON_MAX_FAULT_LIMIT n means the fault is ignored. The TON_MAX_FAULT_LIMITn should be set longer than the TON_RISEn time. It is recommended TON_MAX_FAULT_ LIMITn always be set to a non-zero value, otherwise the output may never come up and no flag will be set to the user . See Table 28. RESPONSES TO SVIN OV FAUL TS SVIN overvoltage is measured with the ADC; therefore, the response is naturally deglitched by up to the 90ms typical response time of the ADC. The fault responses are: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAYn See Table 28. RESPONSES TO OT/UT FAUL TS Internal Overtemperature Fault/Warn Response An internal temperature sensor protects against EEPROM damage. Above 85°C, no writes to EEPROM are recom - mended. Above 130°C, the internal over temperature warn threshold is exceeded and the part disables EEPROM writes and does not re-enable until the temperature has dropped to 125°C. When the die temperature exceed 160°C the operaTion internal over temperature fault response is enabled and the PWM is disabled until the die temperature drops below 150°C. Temperature is measured by the ADC. Internal temperature faults cannot be ignored. Internal temperature limits cannot be adjusted by the user . See Table 27. External Overtemperature and Undertemperature Fault Response Two temperature sensors within the LTM4676A are used to sense power stage temperature. The OT_FAULT_ RESPONSEn and UT_FAULT_RESPONSEn commands are used to determine the appropriate response to an over - temperature and undertemperature condition, respectively. The fault responses are: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely using the Time Interval Specified in MFR_RETRY_DELAYn See Table 28. RESPONSES TO EXTERNAL FAUL TS When either GPIOn pin is pulled low, the OTHER bit is set in the STATUS_WORD command, the appropriate bit is set in the STATUS_MFR_SPECIFC command, and the ALERT pin is pulled low. Responses are not deglitched. Each chan- nel can be configured to ignore or shut down then retry in response to its GPIO n pin going low by modifying the MFR_GPIO_RESPONSEn command. To avoid the ALERT pin asserting low when GPIO is pulled low, assert bit 1 of MFR_CHAN_CONFIG n, or mask the ALERT using the SMBALERT_MASK command. FAUL T LOGGING The LTM4676 A has fault logging capability. Data is logged into memory in the order shown in Table 30. The data to be stored in the fault log is being continuously stored in

For more information www.linear .com/L TM4676A operaTion internal volatile memory. When a fault event occurs, the recording into internal volatile memory is halted, the fault log information is available from the MFR_FAULT_LOG command, and the contents of the internal memory are copied into EEPROM. Fault logging is allowed at temperatures above 85°C; howe ver , retention of 10 years is not guaranteed. When the die temperature exceeds 130°C the fault logging is delayed until the die temperature drops below 125°C. After the fault condition that created the fault log event has been removed, clear the fault before the fault log data is erased, or else the part will immediately issue another fault log. When the LTM4676A powers-up, it checks the EEPROM for a valid fault log. If a valid fault log exists in EEPROM, the “Valid Fault Log” bit in the STATUS_MFR_SPECIFIC command will be set and an ALERT event will be generated. Also, fault logging will be blocked until the LTM4676A has received a MFR_FAULT_LOG_CLEAR command before fault logging will be re-enabled. The information is stored in EEPROM in the event of any fault that disables the controller on either channel. An external GPIO n pulling low will not trigger a fault logging event. BUS TIMEOUT PROTECTION The LTM4676 A implements a timeout feature to avoid hanging the serial interface. The data packet timer begins at the first START event before the device address write byte. Data packet information must be completed within 25ms or the LTM4676A will three-state the bus and ignore the given data packet. If more time is required, assert bit 3 of MFR_CONFIG_ALL to allow typical bus timeouts of 255ms. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the PEC byte if applicable. The LTM4676A allows longer PMBus timeouts for block read data packets. This timeout is proportional to the length of the block read. The additional block read timeout applies primarily to the MFR_FAULT_LOG command. In no circumstances will the timeout period be less than the t TIMEOUT_SMB specification of 32ms (typical). The user is encouraged to use as high a clock rate as pos- sible to maintain efficient data packet transfer between all devices sharing the serial bus interface. The LTM4676A supports the full PMBus frequency range from 10kHz to 400kHz.

For more information www.linear .com/L TM4676A pMbus coMManD suMMary Table 1. Summary of Supported Commands and Feature Differences Between the LTM4676A and the LTM4676 (Items of Greatest LTM4676A NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES LTM4676 NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES PAGE PAGE 0x00 Channel or page currently targeted for paged communications. No difference: 0x00, read/write, non-paged, not stored in NVM. 86 OPERATION n 0x01 Operating mode control. On/off, margin high and margin low. No difference: 0x80, read/write, paged, stored in user-editable NVM. 90 ON_OFF_CONFIGn 0x02 RUN n pin and On/Off Configuration. No difference: 0x1F , read/write, paged, stored in user-editable NVM. 89 CLEAR_FAULTS 0x03 Clear any fault bits that have been set. No difference: default value not applicable, send byte only, non-paged, not stored in NVM. 114 PAGE_PLUS_WRITE 0x05 Write a command directly to a specified page. Default value not applicable, write- only, non-paged, not stored in NVM. Command not supported. 86 PAGE_PLUS_READ 0x06 Read a command directly from a specified page. Default value not applicable, read/ write, non-paged, not stored in NVM. Command not supported. 87 WRITE_PROTECT 0x10 Level of protection provided by the device against accidental changes. No difference: 0x00, read/write, non-paged, stored in user-editable NVM. 87 STORE_USER_ALL 0x15 Store user operating memory to EEPROM (user-editable NVM). No difference: default value not applicable, send byte only, non-paged, not stored in NVM. 125 RESTORE_USER_ ALL 0x16 Restore user operating memory from EEPROM. Default value not applicable, send byte only, non-paged, not stored in NVM. Identical to MFR_RESET command (0xFD). Reser ved. Execute MFR_RESET command (0xFD), instead. 126 CAPABILITY 0x19 Summary of PMBus optional communication protocols supported by this device. No difference: 0xB0, read-only, non-paged, not stored in NVM. 113 PMBUS COMMANDS Table 1 lists supported PMBus commands and manufacturer specific commands. A complete description of these commands can be found in the “PMBus Power System Management Protocol Specification – Part II – Revision 1.2." Users are encouraged to reference this specification. Exceptions or manufacturer specific implementations are listed in Table 1. All commands from 0xD0 through 0xFF not listed in this table are implicitly reserved by the manufacturer. Users should avoid blind writes within this range of commands to avoid undesired operation of the part. All commands from 0x00 through 0xCF not listed in this table are implicitly not supported by the manufacturer. Attempting to access non-supported or reserved commands may result in a CML command fault event. All output voltage settings and measurements are based on the VOUT_MODE setting of 0x14. This translates to an exponent of 2 –12. If PMBus commands are received faster than they are being processed, the part may become too busy to handle new commands. In these circumstances the part follows the protocols defined in the PMBus Specification v1.2, Part II, Section 10.8.7, to communicate that it is busy. The part includes handshaking features to eliminate busy errors and simplify error handling software while ensuring robust communication and system behavior. Please refer to the PMBus Communication and Command Processing subsection in the Applications Information section for details.

For more information www.linear .com/L TM4676A pMbus coMManD suMMary LTM4676A NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES LTM4676 NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES PAGE SMBALERT_MASK n 0x1B Mask ALERT activity. Default mask values: STATUS_VOUT n = 0x00, STATUS_IOUTn = 0x00, STATUS_INPUT = 0x00, STATUS_TEMPERATURE n = 0x00, STATUS_CML = 0x00, STATUS_MFR_SPECIFIC n = 0x11. Read/write, paged as indicated, 10 bytes total, stored in NVM Command not supported. 115 VOUT_MODE n 0x20 Output voltage format/exponent. No difference: 0x14 (2 –12), read-only, paged, not stored in NVM. 94 VOUT_COMMANDn 0x21 Nominal output voltage set point. No difference: 0x1000 (1.000V), read/write, paged, stored in user-editable NVM. VOUT_MAXn 0x24 The upper limit on the commandable output voltage. Page 0x00: 0x599A (5.600V) Page 0x01: 0x599A (5.600V) Read/write, paged, stored in user- editable NVM. Page 0x00: 0x4000 (4.000V). Page 0x01: 0x5666 (5.400V). Read/write, paged, stored in user editable NVM. VOUT_MARGIN_ HIGH n 0x25 Margin high output voltage set point. Must be greater than VOUT_COMMAND No difference: 0x10CD (1.050V), read/write, paged, stored in user-editable NVM. VOUT_MARGIN_ LOW n 0x26 Margin low output voltage set point. Must be less than VOUT_COMMAND No difference: 0x0F33 (0.950V), read/write, paged, stored in user-editable NVM. VOUT_ TRANSITION_RATE n 0x27 The rate at which the output voltage changes when VOUTn is commanded to a new value via I 2C. No difference: 0x8042 (0.001V/ms), read/write, paged, stored in user- editable NVM. 101 FREQUENCY_ SWITCH 0x33 The switching frequency setting. No difference: 0xFBE8 (500kHz), read/write, non-paged, stored in user- editable NVM. VIN_ON 0x35 The undervoltage lockout (UVLO)- rising threshold. No difference: 0xCAC0 (5.500V), as monitored on the “SV IN” pin, read/ write, non-paged, stored in user-editable NVM. VIN_OFF 0x36 The undervoltage lockout (UVLO)- falling threshold. No difference: 0xCAA0 (5.250V) , as monitored on the “SVIN” pin, read/ write, non-paged, stored in user-editable NVM. IOUT_CAL_GAINn 0x38 The ratio of the voltage at the control IC’s current-sense pins to the sensed current, in mΩ, at 25°C. T rimmed at ATE, read/write, paged, stored in factory-only NVM. Writes to this register not recommended. T rimmed at ATE, read-only, paged, stored in factory-only NVM. VOUT_OV_FAULT_ LIMIT n 0x40 Output overvoltage fault limit. No difference: 0x119A (1.100V), read/write, paged, stored in user-editable NVM. VOUT_OV_FAULT_ RESPONSE n 0x41 Action to be taken by the device when an output overvoltage fault is detected. No difference: 0x7A (20µs glitch filter; non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user- editable NVM. 104 VOUT_OV_WARN_ LIMIT n 0x42 Output overvoltage warning threshold. 0x1133 (1.075V), read/write, paged, stored in user-editable NVM. 0x111F (1.070V), read/write, paged, stored in user-editable NVM. VOUT_UV_WARN_ LIMIT n 0x43 Output undervoltage warning threshold. 0x0ECD (0.925V), read/write, paged, stored in user-editable NVM. 0x0EE1 (0.930V), read/write, paged, stored in user-editable NVM. VOUT_UV_FAULT_ LIMIT n 0x44 Output undervoltage fault limit. No difference: 0x0E66 (0.900V), read/write, paged, stored in user-editable NVM.

For more information www.linear .com/L TM4676A pMbus coMManD suMMary LTM4676A NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES LTM4676 NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES PAGE VOUT_UV_FAULT_ RESPONSE n 0x45 Action to be taken by the device when an output undervoltage fault is detected. No difference: 0xB8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable NVM. 105 IOUT_OC_FAULT_ LIMIT n 0x46 Output overcurrent fault threshold (cycle-by-cycle inductor peak current). No difference: 0xDADB (22.84A), read/write, paged, stored in user-editable NVM. IOUT_OC_FAULT_ RESPONSE n 0x47 Action to be taken by the device when an output overcurrent fault is detected. No difference: 0x00 (try to regulate through the fault condition/event; limit the cycle-by-cycle peak of the inductor current to not exceed the commanded IOUT_OC_FAULT_LIMIT), read/write, paged, stored in user- editable NVM. 107 IOUT_OC_WARN_ LIMIT n 0x4A Output overcurrent warning threshold (time-averaged inductor current). No difference: 0xD3E6 (15.59A), read/write, paged, stored in user-editable NVM. OT_FAULT_LIMIT n 0x4F Overtemperature fault threshold. No difference: 0xF200 (128°C), read/write, paged, stored in user-editable NVM. 100 OT_FAULT_ RESPONSE n 0x50 Action to be taken by the device when an overtemperature fault is detected via TSNS n a. No difference: 0xB8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable NVM. 109 OT_WARN_LIMIT n 0x51 Overtemperature warning threshold. No difference: 0xEBE8 (125°C), read/write, paged, stored in user-editable NVM. 100 UT_FAULT_LIMIT n 0x53 Undertemperature fault threshold. No difference: 0xE530 (–45°C), read/write, paged, stored in user-editable NVM. 100 UT_FAULT_ RESPONSE n 0x54 Response to undertemperature fault events. No difference: 0x00 (ignore; continue without interruption), read/write, paged, stored in user-editable NVM, read/write, paged, stored in user- editable NVM. 109 VIN_OV_FAULT_ LIMIT 0x55 Input supply (SV IN) overvoltage fault limit. No difference: 0xDB60 (27.0V), read/write, non-paged, stored in user- editable NVM. VIN_OV_FAULT_ RESPONSE n 0x56 Response to input overvoltage fault events. No difference: 0xB8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable NVM. 103 VIN_UV_WARN_ LIMIT 0x58 Input undervoltage warning threshold. No difference: 0xCAA6 (5.297V), read/write, non-paged, stored in user- editable NVM. IIN_OC_WARN_ LIMIT 0x5D Input supply overcurrent warning threshold. No difference: 0xD300 (12A), read/write, non-paged, stored in user- editable NVM. POWER_GOOD_ON n 0x5E Output voltage at or above which a power good should be asserted. Not supported. PGOOD thresholds set by VOUT_ OV/UV_FAULT_LIMITs. 0x0EE1 (0.9299V), read/write, paged, stored in user-editable NVM. N/A POWER_GOOD_ OFF n 0x5F Output voltage at or below which a power good should be de- asserted. Not supported. PGOOD thresholds set by VOUT_ OV/UV_FAULT_LIMITs. 0x0EB8 (0.9199V), read/write, paged, stored in user-editable NVM. N/A TON_DELAY n 0x60 Time from RUN n and/or OPERATIONn on to output rail turn-on. No difference: 0x8000 (0ms), read/write, paged, stored in user-editable NVM. 101 TON_RISE n 0x61 Time from when the output voltage reference starts to rise until it reaches its commanded setting. No difference: 0xC300 (3ms), read/write, paged, stored in user-editable NVM. 101

For more information www.linear .com/L TM4676A pMbus coMManD suMMary LTM4676A NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES LTM4676 NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES PAGE TON_MAX_FAULT_ LIMIT n 0x62 Turn-on watchdog timeout fault threshold (time permitted for VOUT n to reach or exceed VOUT_ UV_FAULT_LIMITn after turn-on command is received). No difference: 0xCA80 (5ms), read/write, paged, stored in user-editable NVM. 101 TON_MAX_FAULT_ RESPONSE n 0x63 Action to be taken by the device when a TON_MAX_FAULTn event is detected. No difference: 0xB8 (non-latching shutdown; autonomous restart upon fault removal), read/write, paged, stored in user-editable NVM. 106 TOFF_DELAY n 0x64 Time from RUN and/or Operation off to the start of TOFF_FALLn ramp. No difference: 0x8000 (0ms), read/write, paged, stored in user-editable NVM. 102 TOFF_FALL n 0x65 Time from when the output voltage reference starts to fall until it reaches 0V. No difference: 0xC300 (3ms), read/write, paged, stored in user-editable NVM. 102 TOFF_MAX_WARN_ LIMIT n 0x66 Turn-off watchdog timeout fault threshold (time permitted for VOUT n to decay to or below 12.5% of the commanded VOUTn value at the time of receiving a turn-off command). No difference: 0x8000 (no limit; warning is disabled), read/write, paged, stored in user-editable NVM. 102 STATUS_BYTE n 0x78 One byte summary of the unit’s fault condition. No difference: default value not applicable, read/write, paged, not stored in NVM. 116 STATUS_WORD n 0x79 T wo byte summary of the unit’s fault condition. No difference: default value not applicable, read/write, paged, not stored in NVM. 116 STATUS_VOUT n 0x7A Output voltage fault and warning status. No difference: default value not applicable, read/write, paged, not stored in NVM. 117 STATUS_IOUT n 0x7B Output current fault and warning status. No difference: default value not applicable, read/write, paged, not stored in NVM. 117 STATUS_INPUT 0x7C Input supply (SV IN) fault and warning status. No difference: default value not applicable, read/write, non-paged, not stored in NVM. 117 STATUS_ TEMPERATURE n 0x7D TSNS na-sensed temperature fault and warning status for READ_ TEMERATURE_1 n . No difference: default value not applicable, read/write, paged, not stored in NVM. 118 STATUS_CML 0x7E Communication and memory fault and warning status. No difference: default value not applicable, read/write, non-paged, not stored in NVM. 118 STATUS_MFR_ SPECIFIC n 0x80 Manufacturer specific fault and state information. No difference: default value not applicable, read/write, paged, not stored in NVM. 118 READ_VIN 0x88 Measured input supply (SV IN) voltage. No difference: default value not applicable, read-only, non-paged, not stored in NVM. 122 READ_IIN 0x89 Calculated total input supply current. No difference: default value not applicable, read-only, non-paged, not stored in NVM. 122 READ_VOUT n 0x8B Measured output voltage. No difference: default value not applicable, read-only, paged, not stored in NVM. 122 READ_IOUTn 0x8C Measured output current. No difference: default value not applicable, read-only, paged, not stored in NVM. 122 READ_ TEMPERATURE_1 n 0x8D Measurement of TSNS n a-sensed temperature. No difference: default value not applicable, read-only, paged, not stored in NVM. 122

For more information www.linear .com/L TM4676A pMbus coMManD suMMary LTM4676A NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES LTM4676 NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES PAGE READ_ TEMPERATURE_2 0x8E Measured control IC junction temperature. No difference: default value not applicable, read-only, non-paged, not stored in NVM. 123 READ_DUTY_ CYCLE n 0x94 Measured duty cycle of MT n. No difference: default value not applicable, read-only, paged, not stored in NVM. 123 READ_POUTn 0x96 Calculated output power . No difference: default value not applicable, read-only, paged, not stored in NVM. 123 PMBUS_REVISION 0x98 PMBus revision supported by this device. 0x22 (Revision 1.2 of Part I and Revision 1.2 of Part II of PMBus Specification documents), read-only, non-paged, not stored in NVM. 0x11 (Revision 1.1 of Part I and Revision 1.1 of Part II of PMBus Specification documents), read-only, non-paged, not stored in NVM. 112 MFR_ID 0x99 Manufacturer identification, in ASCII No difference: “LT C”, read-only, non-paged. 113 MFR_MODEL 0x9A Manufacturer’s part number , in ASCII LTM4676A, read-only, non-paged. LTM4676, read-only, non-paged. 113 MFR_SERIAL 0x9E Serial number of this specific unit. Up to nine bytes of custom-formatted data that identify the unit’s configuration, read-only, non-paged. 113 MFR_VOUT_MAX n 0xA5 Maximum allowed output voltage. 0x5B34 (5.700V) on both channels. Read-only, paged, not stored in user-editable NVM. 0x4189 (4.096V) on Channel 0, 0x5800 (5.500V) on Channel 1. Read-only, paged, not stored in user-editable NVM. USER_DATA_00 0xB0 OEM reserved data. Read/write, non-paged, stored in user-editable NVM. Recommended against altering. Read/write, non-paged, stored in user-editable NVM. Recommended against altering. 112 USER_DATA_01 n 0xB1 OEM reserved data. Read/write, paged, stored in user-editable NVM. Recommended against altering. Read/write, paged, stored in user-editable NVM. Recommended against altering. 112 USER_DATA_02 0xB2 OEM reserved data. Read/write, non-paged, stored in user-editable NVM. Recommended against altering. Read/write, non-paged, stored in user-editable NVM. Recommended against altering. 112 USER_DATA_03 n 0xB3 User-editable words available for the user . No difference: 0x0000, read/write, paged, stored in user-editable NVM. 112 USER_DATA_04 0xB4 A user-editable word available for the user . No difference: 0x0000, read/write, non-paged, stored in user-editable NVM. 112 MFR_INFO 0xB6 Manufacturing specific information Default value not applicable, read only, non-paged, not stored in NVM. Bit 5 is 0 b when ECC has made a correction to data derived from the EEPROM user space. Command not supported. 121 MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access by MFR_EE_ERASE and MFR_EE_ DATA commands. No difference: default value not applicable, read/write, non-paged, not stored in NVM. 131<DT> MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk programming by MFR_EE_DATA. No difference: default value not applicable, read/write, non-paged, not stored in NVM. 131<DT> MFR_EE_DATA 0xBF Data transferred to and from EEPROM using sequential PMBus word reads or writes. Supports bulk programming. No difference: default value not applicable, read/write, non-paged, not stored in NVM. 131<DT>

For more information www.linear .com/L TM4676A pMbus coMManD suMMary LTM4676A NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES LTM4676 NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES PAGE MFR_CHAN_ CONFIG_* n 0xD0 Channel-specific configuration bits. No difference: 0x1F , read/write, paged, stored in user-editable NVM. Register is named “MFR_CHAN_CONFIG” and referred to as “MFR_CHAN_ CONFIG_LTM467X” in L TpowerPlay. MFR_CONFIG_ ALL_* 0xD1 Global configuration bits, i.e., common to both V OUT channels 0 and 1. Same as LTM4676 except: Bit 4 configures whether the SYNC drive circuit is active (0 b) or inactive (1b); Bit 3 configures whether the Stuck PMBus Timer Timeout is 150ms for Block Reads and 32ms for Non- Block Reads (0 b) or 250ms for all Reads (1b). 0x09, read/write, non-paged, stored in user-editable NVM. Register is named “MFR_CONFIG_ALL” and referred to as “MFR_CONFIG_ALL_ LTM467X” in L TpowerPlay. Bit 4 is reserved. MFR_GPIO_ PROPAGATE_* n 0xD2 Configuration bits for propagating faults to the GPIOn pins. No difference: 0x6893, read/write, paged, stored in user-editable NVM. Register is named “MFR_GPIO_PROPAGATE” and referred to as “MFR_ GPIO_PROPAGATE_LTM467X” in L TpowerPlay. 110 MFR_PWM_ MODE_* n 0xD4 Configuration for the PWM engine of each VOUT channel. 0xC1, read/write, paged, stored in user-editable NVM. Bit 1 commands whether the output is in high range (0 b) or low range (1b). Bit 0 commands whether the output is operating in Forced Continuous Conduction Mode (1 or Discontinuous Mode (0b). Command is named MFR_ PWM_MODE and referred to as MFR_PWM_MODE_LTM467X in L TpowerPlay. 0xC2, read/write, paged, stored in user-editable NVM. Bits 1:0 command the operating mode of the output. Command is named MFR_PWM_MODE and referred to as MFR_PWM_MODE_ LTM467X in L TpowerPlay. MFR_GPIO_ RESPONSE n 0xD5 Action to be taken by the device when the GPIOn pin is asserted low by circuitry external to the unit. No difference: 0xC0 (make the respective output’s power stage high impedance, i.e., three-stated; autonomous restart upon fault removal), read/write, paged, stored in user-editable NVM. 111 MFR_OT_FAULT_ RESPONSE 0xD6 Action to be taken by the device when a control IC junction overtemperature fault is detected. No difference: 0xC0 (make the respective output’s power stage high impedance, i.e., three-stated; autonomous restart upon fault removal), read-only, non-paged, not stored in user-editable NVM. 108 MFR_IOUT_PEAK n 0xD7 Maximum measured value of READ_IOUTn since the last MFR_ CLEAR_PEAKS. No difference: default value not applicable, read-only, paged, not stored in NVM. 124 MFR_ADC_ CONTROL 0xD8 ADC telemetry parameter for repeated fast ADC readback. 0x00, read/write, not paged, not stored in NVM. Allows telemetry readback rates up to 125Hz instead of 10Hz, nominal. Use PAGE_PLUS_ READ/WRITE commands instead of the LTM4676's former MFR_ CHANNEL_ADDRESS n command. 0x80, read/write, paged, stored in user-editable NVM. MFR_ CHANNEL_ADDRESS n, the slave address to the PAGE-activated channel. 124 MFR_ADC_ TELEMETRY_ STATUS 0xDA ADC status during short-loop. Default value not applicable, read/ write, not paged, not stored in NVM. ADC status indicating most recently digitized telemetry when engaged in short round-robin loop (MFR_ADC_CONTROL = 0x0D) Command not supported. 125 MFR_RETRY_ DELAY n 0xDB Retry interval during fault-retry mode. No difference: 0xF3E8 (250ms), read/write, paged, stored in user-editable NVM. 103

For more information www.linear .com/L TM4676A pMbus coMManD suMMary LTM4676A NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES LTM4676 NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES PAGE MFR_RESTART_ DELAY n 0xDC Minimum interval (nominal) the RUNn pin is pulled logic low by internal circuitry. 0xFA58 (300ms), read/write, paged, stored in user-editable NVM. 0xF258 (150ms), read/write, paged, stored in user-editable NVM. 103 MFR_VOUT_PEAK n 0xDD Maximum measured value of READ_VOUTn since the last MFR_CLEAR_PEAKS. No difference: default value not applicable, read-only, paged, not stored in NVM. 123 MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since the last MFR_ CLEAR_PEAKS. No difference: default value not applicable, read-only, non-paged, not stored in NVM. 123 MFR_ TEMPERATURE_1_ PEAK n 0xDF Maximum value of TSNS na measured temperature since the last MFR_CLEAR_PEAKS. No difference: default value not applicable, read-only, paged, not stored in NVM. 123 MFR_CLEAR_ PEAKS 0xE3 Clears all peak values. No difference: default value not applicable, send byte only, non-paged, not stored in NVM. 114 MFR_PADS 0xE5 Digital status of the I/O pads. No difference: default value not applicable, read-only, non-paged, not stored in NVM. 119 MFR_ADDRESS 0xE6 LTM4676A's I 2C slave address, right-justified. 0x4F , read/write, non-paged, stored in user-editable NVM. Bits[6:4] represent the user-configurable upper 3 bits of the 7-bit slave address of the device. Bits[3:0] are dictated by the ASEL resistor pin- strap setting. Setting this command to 0x80 disables device-specific addressing. 0x4F , read-only, non-paged, stored in factory-only NVM. Least significant four bits augmented by ASEL resistor pin-strap. Cannot take on value 0x80; device-specific addressing cannot be disabled. MFR_SPECIAL_ID 0xE7 Manufacturer code representing IC silicon and revision 0x47EX, read-only, non-paged. 0x440X or 0x448X, read-only, non- paged. 113 MFR_IIN_OFFSET n 0xE9 Coefficient used in calculations of READ_IIN and MFR_READ_IINn, representing the contribution of input current drawn by the control IC, including the MOSFET drivers. No difference: 0x8BE7 (0.0305A), read/write, paged, stored in user-editable NVM. MFR_FAULT_LOG_ STORE 0xEA Commands a transfer of the fault log from RAM to EEPROM. This causes the part to behave as if a channel has faulted off. No difference: default value not applicable, send byte only, non-paged, not stored in NVM. 127 MFR_FAULT_LOG_ CLEAR 0xEC Initialize the EEPROM block reserved for fault logging and clear any previous fault logging locks. No difference: default value not applicable, send byte only, non-paged, not stored in NVM. 127 MFR_READ_IIN n 0xED Calculated input current, by channel. No difference: default value not applicable, read-only, paged, not stored in NVM. 122 MFR_FAULT_LOG 0xEE Fault log data bytes. This sequentially retrieved data is used to assemble a complete fault log. No difference: default value not applicable, read-only, non-paged, stored in fault-log NVM. 127 MFR_COMMON 0xEF Manufacturer status bits that are common across multiple L TC ICs/ modules. No difference: default value not applicable, read-only, non-paged, not stored in NVM. 119

For more information www.linear .com/L TM4676A pMbus coMManD suMMary LTM4676A NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES LTM4676 NVM FACTORY -DEFAUL T VALUE AND/OR ATTRIBUTES PAGE MFR_COMPARE_ USER_ALL 0xF0 Compares current command contents (RAM) with NVM. No difference: default value not applicable, send byte only, non-paged, not stored in NVM. 126 MFR_ TEMPERATURE_2_ PEAK 0xF4 Maximum measured control IC junction temperature since last MFR_CLEAR_PEAKS. No difference: default value not applicable, read-only, non-paged, not stored in NVM. 123 MFR_PWM_ CONFIG_* 0xF5 Configuration bits for setting the phase interleaving angles of Channels 0 and 1, SHARE_CLK behavior in UVLO, and using the fully differential amplifier to regulate paralleled output channels. 0x10, read/write, non-paged, stored in user-editable NVM. When bit 7 is 0 b, Channel 1's output is regulated by the VOSNS1 and SGND feedback signals. When bit 7 is 1b, Channel 1's output is regulated by the V OSNS0+ and VOSNS0– feedback signals. Only set bit 7 to b for PolyPhase rail applications. The command is named MFR_ PWM_CONFIG and referred to as MFR_PWM_CONFIG_LTM467X in L TpowerPlay. 0x10, read/write, non-paged, stored in user-editable NVM. Channel 1 output regulated strictly by V OSNS1 and SGND feedback signals. Bit 7 reserved and must be 0 b. The command is named MFR_PWM_CONFIG and referred to as MFR_PWM_CONFIG_LTM467X in L TpowerPlay. MFR_IOUT_CAL_ GAIN_TC n 0xF6 Temperature coefficient of the current sensing element. No difference: 0x0F14 (3860ppm/°C), read/write, paged, stored in user- editable NVM. MFR_TEMP_1_ GAIN n 0xF8 Sets the slope of the temperature sensors that interface to TSNSna. 0x3FAE (0.995, in custom units), read/write, paged, stored in user- editable NVM. 0x4000 (1.000 in custom units), read/ write, paged, stored in user-editable NVM. MFR_TEMP_1_ OFFSET n 0xF9 Sets the offset of the TSNS na temperature sensor with respect to –273.1°C. No difference: 0x8000 (0.0), read/write, paged, stored in NVM. 99 MFR_RAIL_ ADDRESS n 0xFA Common address for PolyPhase outputs to adjust common parameters. No difference: 0x80, read/write, paged, stored in NVM. 88 MFR_RESET 0xFD Commanded reset without requiring a power down. No difference: default value not applicable, send byte only, non-paged, not stored in NVM. Identical to RESTORE_USER_ALL.

Table 2. VOUTnCFG Pin Strapping Look-Up Table for the

32.4 See Table 3 See Table 3

USER_ALL, over the lifetime of one’s product. Table 3. VTRIMnCFG Pin Strapping Look-Up Table for the USER_ALL, over the lifetime of one’s product.

Table 4. FSWPHCFG Pin Strapping Look-Up Table to Set the LTM4676A's Switching Frequency and Channel Phase-Interleaving

5.23 Sync Slave** 0° 240° 010b 1b

4.22 Sync Slave** 0° 120° 011b 1b

3.24 Sync Slave** 60° 240° 101b 1b

2.43 Sync Slave** 120° 300° 110b 1b

1.65 Sync Slave** 90° 270° 001b 1b

0.787 Sync Slave** 0° 180° 000b 1b

0 Sync Slave** 120° 240° 100b 1b

SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product. Phase subsection of the Applications Information section for details).

For more information www.linear .com/L TM4676A applicaTions inForMaTion Table 5. ASEL Pin Strapping Look-Up Table to Set the R/W = Read/Write bit in control byte. 0x5B regardless of the NVM or ASEL resistor configuration values. RESTORE_USER_ALL, over the lifetime of one’s product. Table 6. LTM4676A MFR_ADDRESS Command Examples

0 R/W7 BIT 8 BIT

Rail4 0x5A 0xB4 0 1 0 1 1 0 1 0 0 Global4 0x5B 0xB6 0 1 0 1 1 0 1 1 0 Default 0x4F 0x9E 0 1 0 0 1 1 1 1 0 Example 1 0x40 0x80 0 1 0 0 0 0 0 0 0 Example 2 0x41 0x82 0 1 0 0 0 0 0 1 0 Disabled2,3 1 0 0 0 0 0 0 0 0 Note 1: This table can be applied to the MFR_RAIL_ADDRESSn command, but not the MFR_ADDRESS command. Note 2: A disabled value in one command does not disable the device, nor does it disable the Global address. Note 3: A disabled value in one command does not inhibit the device from responding to device addresses specified in other commands. Note 4: It is not recommended to write the value 0x00, 0x0C (7 bit), 0x5A (7 bit), 0x5B (7 bit), or 0x7C (7 bit) to the MFR_RAIL_ ADDRESS n or MFR_ADDRESS commands.

For more information www.linear .com/L TM4676A applicaTions inForMaTion VIN TO VOUT STEP-DOWN RATIOS There are restrictions in the maximum VIN and VOUT step- down ratio that can be achieved for a given input voltage. Each output of the LTM4676A is capable of 95% duty cycle at 500kHz, but the V IN to V OUT minimum dropout is still a function of its load current and will limit output current capability related to high duty cycle on the topside switch. Minimum on-time t ON(MIN) is another consideration in operating at a specified duty cycle while operating at a certain frequency due to the fact that t ON(MIN) < D/fSW, where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 45ns. See Note 6 in the Electrical Characteristics section for output current guideline. I NPUT CAP ACITORS The LTM4676 A module should be connected to a low ac- impedance DC source. For the regulator input four 22µF input ceramic capacitors are used to handle the RMS ripple current. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long in- ductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. For a buck converter , the switching duty-cycle can be estimated as: Dn = VOUTn VINn Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: ICINn(RMS) = IOUTn(MAX) η% • Dn • 1−Dn( ) In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher-rated electrolytic aluminum capacitor , or a Polymer capacitor . O UTPUT CAP ACITORS The LTM4676A is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output volt- age ripple and transient requirements. COUT can be a low ESR tantalum capacitor , a low ESR polymer capacitor or ceramic capacitor . The typical output capacitance range for each output is from 400µF to 700µF. Additional output filtering may be required by the system designer , if further reduction of output ripple or dynamic transient spikes is required. Table 20 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 6.5A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 20 matrix, and the Linear Technology µModule Power Design Tool will be provided for stability analysis. Multiphase operation reduces effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology µModule Power Design Tool can calculate the output ripple reduc- tion as the number of implemented phases increases by N times. A small value 10Ω resistor can be placed in series from VOUTn to the V OSNS0+ or VOSNS1 pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. L IGHT LOAD CURRENT OPERA TION The LTM4676 A has two modes of operation: high efficiency, discontinuous conduction mode or forced continuous conduction mode. The mode of operation is configured by bit 0 of the MFR_PWM_MODE n command (discontinuous conduction is always the start-up mode, forced continuous is the default running mode).

For more information www.linear .com/L TM4676A applicaTions inForMaTion If a channel is enabled for discontinuous mode operation, the inductor current is not allowed to reverse. The reverse current comparator , I REV , turns off the bottom MOSFET (MBn) just before the inductor current reaches zero, pre- venting it from reversing and going negative. Thus, the controller can operate in discontinuous (pulse-skippng) operation. In for ced continuous operation, the induc - tor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined solely by the voltage on the COMP na pin. In this mode, the efficiency at light loads is lower than dis- continuous mode operation. However , continuous mode exhibits lower output ripple and less interference with audio circuitry. Forced continuous conduction mode may result in reverse inductor current, which can cause the input supply to boost. The VIN_OV_FAULT_LIMIT can detect this (if SV IN is connected to VIN0 and/or VIN1) and turn off the offending channel. However , this fault is based on an ADC read and can nominally take up to 90ms to detect. If there is a concern about the input supply boosting, keep the part in discontinuous conduction operation. S WITCHING FREQUENCY AND PHASE The switching frequency of the LTM4676A’s channels is established by its analog phase-locked-loop (PLL) locking on to the clock present at the module’s SYNC pin. The clock waveform on the SYNC pin can be generated by the LTM4676A’s internal circuitry when an external pull-up resistor to 3.3V (e.g., V DD33) is provided, in combination with the LTM4676A control IC’s FREQUENCY_SWITCH command being set to one of the following supported values: 250kHz, 350kHz, 425kHz, 500kHz, 575kHz, 650kHz, 750kHz, 1MHz (see Table 8 for hexadecimal values). In this configuration, the module is called a “sync master”: using the factory-default setting of MFR_CONFIG_ALL[4]=0 b, SYNC becomes a bidirectional open-drain pin, and the LTM4676A pulls SYNC logic low for nominally 500ns at a time, at the prescribed clock rate. The SYNC signal can be bused to other LTM4676A modules (configured as “sync slaves”), for purposes of synchronizing switching frequencies of multiple modules within a system—but only one LTM4676A should be configured as a “sync master”; the other LTM4676A(s) should be configured as “sync slaves”. There are two recommended ways to configure an LTM4676A as a “sync slave”:

• Apply an appropriate pin-strap resistor setting on the F SWPHCFG pin (see Table 4) and use the factory default setting MFR_CONFIG_ALL[6] = 0 b. This configures MFR_CONFIG_ALL[4] = 1b and FREQUENCY_SWITCH according to EEPROM settings (0xFBE8 factory de- fault, corresponding to 500kHz). The LTM4676A’s SYNC pin thus becomes a high impedance input and the module synchronizes its frequency to that of the externally applied clock, provided that the frequency of the externally applied clock exceeds ~45% of the target frequency (FREQUENCY_SWITCH). If the SYNC clock is absent, the module responds by operating at its target frequency, indefinitely. If and when the SYNC clock is restored, the module automatically phase-locks to the SYNC clock as normal. The only shortcoming of this approach is: the EEPROM must be configured per above guidance; resistor pin-strapping options on the F SWPHCFG pin alone cannot provide fault-tolerance to the absence of the SYNC clock.
• Set FREQUENCY_SWITCH command to 0x0000 and MFR_CONFIG_ALL[4] = 1b. Using MFR_CONFIG_ ALL[4] = 1b, the LTM4676A’s SYNC pin becomes a high impedance input, only—i.e., it does not drive SYNC low. The module synchronizes its frequency to that of the clock applied to its SYNC pin. The only shortcoming of this approach is: in the absence of an externally applied clock, the switching frequency of the module will default to the low end of its frequency- synchronization capture range (~225kHz). The FREQUENCY_SWITCH command can be altered via I 2C commands, but only when switching action is disengaged, i.e., the module’s outputs are turned off. The FREQUENCY_SWITCH command takes on the value stored in NVM at SV IN power-up, but is overridden according to a resistor pin-strap applied between the FSWPHCFG pin and SGND only if the module is configured to respect resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0 b). Table 4 highlights available resistor pin-strap and corresponding FREQUENCY_SWITCH settings.

turn-on of the top MOSFETs, MTn. MFR_PWM_CONFIG[2:0] settings. until NVM contents have been downloaded to RAM. is 83ns, shy of the 90ns guardband recommendation. switching frequency becomes 650kHz. Table 7. Recommended Switching Frequency for Various

but the ripple voltage and current will increase. A must enter its run state prior to soft-start. and SVIN exceeds the VIN_ON threshold for all devices. the signal use the same time base. n to any value less than 0.250ms. assure the voltage ramp is controlled to the desired slope. the regulator to start up into a pre-biased load. TON_DELAYn times to achieve ratiometric rail tracking. configuration, all timing parameters must be the same. Table 8. Recommended MFR_IIN_OFFSETn Setting vs *See Appendix C: PMBus Command Details, L11 data format.

1. After the TON_RISEn sequence is complete
2. After the TON_MAX_FAULT_LIMITn time is reached;

or the IOUT_OC_FAULT_LIMITn is no longer active.

1. After the TON_MAX_FAULT_LIMITn time has expired

The maximum rise time is limited to 1.3 seconds. of the control loops have the digital servo mode enabled. other due to slight differences in the reference circuits. the VIN_ON threshold is crossed. DD33 supply is externally driven. Figure 4. TOFF_DELAYn and TOFF_FALLn

For more information www.linear .com/L TM4676A applicaTions inForMaTion communications are valid in this supply configura - tion. If SV IN has not been applied to the LTM4676A, MFR_COMMON[3] will be asserted low, indicating that NVM has not initialized. If this condition is detected, the part will only respond to addresses 0x5A and 0x5B. To initialize the part issue the following set of commands: global address 0x5B command 0xBD data 0x2B followed by global address 0x5B command 0xBD and data 0xC4. The part will now respond to the correct address. Configure the part as desired then issue a STORE_USER_ALL. When SV IN is applied a MFR_RESET or RESTORE_USER_ALL, command must be issued to allow the PWM to be enabled and valid ADC conversions to be read. F AUL T DETECTION AND HANDLING The LTM4676A GPIOn pins are configurable to indicate a variety of faults including OV/UV , OC, OT , timing faults, peak overcurrent faults. In addition the GPIOn pins can be pulled low by external sources to indicate to the LTM4676A the presence of a fault in some other portion of the system. The fault response is configurable via PMBus Command Code names with a _RESPONSE suffix and allows the following options: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAYn Refer to Appendix C and the PMBus specification for more details. The OV response is automatic and rapid. If an OV is de - tected, MTn is turned off and BGn is turned on, until the OV condition clears. Fault logging is available on the LTM4676 A. The fault logging is configurable to automatically store data when a fault occurs that causes the unit to fault off. The header portion of the fault logging table contains peak values. It is possible to read these values at any time. This data will be useful while troubleshooting the fault. If the LTM4676A internal temperature is in excess of 85°C or below 0°C, the write into the NVM is not recommended. The data will still be held in RAM, unless the 3.3V supply UVLO threshold is reached. If the die temperature exceeds 130°C all NVM communication is disabled until the die temperature drops below 125°C, with the exception of the RESTORE_USER_ALL command, which is valid at any temperature. O PEN-DRAIN PINS Note that up to nine pull-up resistors are required for proper operation of the LTM4676A:

• Three for the SMBus/I2C interface (the SCL, SDA, and ALERT pins); two, only if the system SMBus host does not make use of the ALERT interrupt. (These are 5V tolerant). One each for the RUN0 and RUN1 pins (or , just one to RUN0 and RUN 1, if RUN 0 and RUN 1 are electrically connected together). (These are 5V tolerant).
• One each for GPIO0 and GPIO1 (or , just one to GPIO0 and GPIO1, if GPIO0 and GPIO1 are electrically connected together). (These are 3.3V tolerant).
• One on SHARE_CLK , required, for the LTM4676A to establish a heartbeat time base for timing-related op - erations and functions (output voltage ramp-up timing, voltage margining transition timing, SYNC open-drain drive frequency). (SHARE CLK is 3.3V tolerant). One on SYNC, in order for the LTM4676 A to phase lock to the frequency generated by the open-drain output of its digital engine. EXCEPTION: in some applications, it is desirable to drive the LTM4676A’s SYNC pin with a hard-driven (low impedance) external clock. This is the only scenario where the LTM4676A does not require a pull-up resistor on SYNC. However , be aware that the SYNC pin can be low impedance during NVM initialization, i.e., during download of EEPROM contents to RAM (for ~50ms [Note 12] after SV IN power is ap- plied). Therefore, the hard-driven clock signal should only be applied to the LTM4676 A SYNC pin through a

For more information www.linear .com/L TM4676A applicaTions inForMaTion series resistor whose impedance limits current into the SYNC pin during NVM initialization to less than 10mA. If FREQUENCY_SWITCH=0x0000, any clock signal should be provided prior to the RUN n pins toggle from logic low to logic high, or else the switching frequency of the LTM4676A will start off at the low end of its PLL- capture range (~225kHz) until the SYNC clock becomes established. (SYNC is 3.3V tolerant). All the above pins interface to pull-down transistors within the module that can sink 3mA at 0.4V. The low threshold on the pins is 0.8V; thus, plenty of margin on the digital signals with 3mA of current. For 3.3V pins, 3mA of current is a 1.1k resistor . Unless there are transient speed issues associated with the RC time constant of the resistor pull- up and parasitic capacitance to ground, a 10k resistor or larger is generally recommended. For high speed signals such as the SDA, SCL and SYNC, a lower value resistor may be required. The RC time con- stant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. For a 100pF load and a 400kHz PMBus communication rate, the rise time must be less than 300ns. The resistor pull-up on the SDA and SCL pins with the time constant set to 1/3 the rise time: RPULLUP = tRISE 3•100pF =1 k Be careful to minimize parasitic capacitance on the SDA and SCL pins to avoid communication problems. To estimate the loading capacitance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. This is one time constant. The SYNC pin interfaces to a pull-down transis - tor within the module whose output is held low for nominally 500ns per switching period. If the internal oscillator is set for 500kHz and the load is 100pF and a 3x time constant is required, the resistor calculation is as follows: RPULLUP = 2µs – 500ns 3•100pF =5k The closest 1% resistor is 4.99k. If timing errors are occurring or if the SYNC frequency is not as fast as desired, monitor the waveform and determine if the RC time constant is too long for the application. If possible reduce the parasitic capacitance. If not reduce the pull up resistor sufficiently to assure proper timing. P HASE-LOCKED LOOP AND FREQUENCY SYNCHRONIzA TION The LTM4676 A has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector . The PLL is locked to the falling edge of the SYNC pin. The phase relationship between channel channel 1 and the falling edge of SYNC is controlled by the lower 3 bits of the MFR_PWM_CONFIG command. For PolyPhase applications, it is recommended all the phases be spaced evenly. Thus for a 2-phase system the signals should be 180° out of phase and a 4-phase system should be spaced 90°. The phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complemen- tary current sources that charge or discharge the internal filter network. The PLL lock range is guaranteed between 225kHz and 1.1MHz. The PLL has a lock detection cir cuit. If the PLL should lose lock during operation, bit 4 of the STATUS_MFR_SPECIFIC command is asserted and the ALERT pin is pulled low. The fault can be cleared by writing a 1 to the bit. If the user does not wish to see the PLL_FAULT, even if a synchronization clock is not available at power up, bit of the MFR_CONFIG_ALL command must be asserted. If the SYNC signal is not clocking in the application, the PLL runs at the lowest free running frequency of the VCO. This will be well below the intended PWM frequency of the application and may cause undesirable operation of the converter .

For more information www.linear .com/L TM4676A applicaTions inForMaTion If the PWM (SWn) signal appears to be running at too high a frequency, monitor the SYNC pin. Extra transitions on the falling edge will result in the PLL trying to lock on to noise instead of the intended signal. Review routing of digital control signals and minimize crosstalk to the SYNC signal to avoid this problem. Multiple LTM4676As are required to share the SYNC pin in PolyPhase configura - tions; for other configurations, it is optional. If the SYNC pin is shared between LTM4676 As, only one LTM4676A can be programmed with a frequency output. All the other LTM4676As must be configured for external clock (MFR_CONFIG_ALL[4]=1 b, and/or see Table 4). RCONFIG PIN-STRAPS (EXTERNAL RESISTOR CONFIGURATION PINS) The LTM4676 A default NVM is programmed to respect the RCONFIG pins. If a user wishes the output voltage, PWM frequency and phasing and the address to be set without programming the part or purchasing specially programmed parts, the RCONFIG pins can be used to establish these parameters— provided MFR_CONFIG_ ALL[6] = 0 b. The RCONFIG pins only require a resistor terminating to SGND of the LTM4676A. The RCONFIG pins are only monitored at initial power up and during a reset (MFR_RESET or RESTORE_USER_ALL) so modi - fying their values perhaps using a DAC after the part is powered will have no effect. To assure proper operation, the value of RCONFIG resistors applied to the LTM4676A pin-strapping pins must not deviate more than ±3% away from the target nominal values indicated in lookup Table 2 to Table 5, over the lifetime of the product. Thin film, 1% tolerance (or better), ±50ppm/°C-T .C.R. rated (or better) resistors from vendors such as KOA Speer , Panasonic, Vishay and Yageo are good candidates. Noisy clock signals should not be routed near these pins. Note that bits [3:0] of MFR_ADDRESS are dictated by the ASEL pin-strap resistor regardless of the setting of MFR_CONFIG_ALL[6]. V OL TAGE SELECTION When an output voltage is set using the RCONFIG pins on VOUTn _CFG and VTRIMn_CFG (MFR_CONFIG_ALL[6] = 0b), the following parameters are set as a percentage of the output voltage:

• VOUT_OV_FAULT_LIMIT +10%
• VOUT_OV_WARN +7.5%
• VOUT_MAX +7.5%
• VOUT_MARGIN_HI +5%
• VOUT_MARGIN_LO –5%
• VOUT_UV_WARN –6.5%
• VOUT_UV_FAULT_LIMIT –7% CONNECTING THE USB TO THE I2C/SMBus/PMBus CONTROLLER TO THE LTM4676A IN SYSTEM The L TC USB to I 2C/SMBus/PMBus controller can be interfaced to the LTM4676A on the user’s board for pro- gramming, telemetry and system debug. The controller , when used in conjunction with LTpowerPlay , provides a powerful way to debug an entire power system. Faults are quickly diagnosed using telemetry, fault status registers and the fault log. The final configuration can be quickly developed and stored to the LTM4676A EEPROM. Figure 5 and Figure 6 illustrate the application schemat- ics for powering, programming and communicating with one or more LTM4676As via the L TC I2C/SMBus/PMBus controller regardless of whether or not system power is present. If system power is not present the dongle will power the LTM4676A through the VDD33 supply pin. To initialize the part when SVIN is not applied and the VDD33 pin is powered use global address 0x5B command 0xBD data 0x2B followed by address 0x5B command 0xBD data 0xC4. The part can now be communicated with, and the

For more information www.linear .com/L TM4676A applicaTions inForMaTion project file updated. To write the updated project file to the NVM issue a STORE_USER_ALL command. When SV IN is applied, a MFR_RESET or RESTORE_USER_ALL must be issued to allow the PWM to be enabled and valid ADCs to be read. Because of the controllers limited current sourcing capabil- ity, only the LTM4676As, their associated pull-up resistors and the I 2C pull-up resistors should be powered from the ORed 3.3V/3.4V supply. In addition, any device sharing the I 2C bus connections with the LTM4676A must not have body diodes between the SDA/SCL pins and their respective V DD node because this will interfere with bus communication in the absence of system power . In Figure 5, the dongle will not bias the LTM4676As when SV IN is present. It is recommended the RUN n pins be held low to avoid providing power to the load until the part is fully configured. The L TC controller/adapter I 2C connections are opto-iso- lated from the PC USB. The 3.3V/3/4V from the controller/ adapter and the LTM4676 A VDD33 pin must be driven to each LTM4676A with a separate PFET or diode, according to Figure 5 and Figure 6. Only when SV IN is not applied is it permissible for the VDD33 pins to be electrically in parallel because the INTVCC LDO is off. The DC1613’s 3.3V current limit is 100mA but typical VDD33 currents are under 15mA. The VDD33 does back drive the INTVCC pin. Normally this is not an issue if SVIN is open. The DC2086 is capable of delivering 3.4V at 2A. Using a 4-pin header in Figure 5 or Figure 6 maximizes flexibility to alter the LTM4676A’s NVM contents at any stage of the user’s product development and production cycles. If the LTM4676A’s NVM is “pre-programmed”, i.e., contains its finalized configuration, prior to being soldered to the user’s PCB/motherboard—or , if other means have been provided for altering the LTM4676A's NVM contents in the user’s system—then the 3.3V/3.4V pin on the header is not needed, and a 3-pin header is sufficient to establish GUI communications. The LTM4676A can be purchased with customized NVM contents; consult factory for details. Alternatively, the NVM contents of the LTM4676A can be configured in a mass production environment by design- ing for it in ICT (in-circuit test), or by providing a means of applying SVIN while holding the LTM4676A’s RUN pins low. Communication to the module must be made possible via the SCL and SDA pins/nets in all NVM programming scenarios. Recommended headers are found in Table 9 and Table 10.

Table 9. 4-Pin Headers, 2mm Pin-to-Pin Spacing, Gold Flash or Plating, Compatible with DC2086 Cables Table 10. 3-Pin Headers, 2mm Pin-to-Pin Spacing, Gold Flash or Plating, Compatible with DC2086 Cables Table 11. Recommended 4-Pin Header Pinout (Pin Numbering

2 GND SCL

3 SCL GND

Table 12. Recommended 3-Pin Header Pinout (Pin Numbering

1 SDA SCL

2 GND GND

3 SCL SDA

Figure 7. L TPowerPlay Table 13. 4-Pin Male-to-Male Shrouded and Keyed Adapter

For more information www.linear .com/L TM4676A applicaTions inForMaTion It is recommended that all command writes (write byte, write word, etc.) be preceded with a polling loop to avoid the extra complexity of dealing with busy behavior and unwanted ALERT notification. A simple way to achieve this is by creating SAFE_WRITE_BYTE() and SAFE_WRITE_ WORD() subroutines. The above polling mechanism allows one’s software to remain clean and simple while robustly communicating with the part. For a detailed discussion of these topics and other special cases please refer to the application note section located at www.linear .com/ designtools/app_notes. When communicating using bus speeds at or below 100kHz, the polling mechanism shown here provides a simple solution that ensures robust communication without clock stretching. At bus speeds in excess of 100kHz, it is strongly recommended that the part be configured to en- able clock stretching. This requires a PMBus master that supports clock stretching. System software that detects and properly recovers from the standard PMBus NACK/ BUSY faults as described in the PMBus Specification v1.2, Part II, Section 10.8.7 is required to communicate above 100kHz without clock stretching. Clock stretching will not extend the PMBus speed beyond the specified 400kHz. T HERMAL CONSIDERA TIONS AND OUTPUT CURRENT DERATING The thermal resistances reported in the Pin Configuration section of this data sheet are consistent with those pa - rameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simula - tion, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients is found in JESD51 -12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their appli - cation at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Con- figuration section are, in and of themselves, not relevant to providing guidance of thermal performance ; instead, the derating curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section gives four thermal coeffi - cients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below: θJA, the thermal resistance from junction to ambi - ent, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operating condition. θJCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator , the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing pack - ages but the test conditions don’t generally match the user’s application. θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resis- tance where almost all of the heat flows through the bottom of the µModule regulator and into the board, and is really the sum of the θ JCbottom and the thermal

with multiplicative factors with ambient temperature. These approximate factors are listed in Table 14. current or power while increasing ambient temperature. and 3.3V outputs with and without air flow and heat sinking. Table 14. Power Loss Multiplicative Factors vs Ambient

See also Figure 43, 12VIN to 5VOUT derating curves.

AS THE FEEDBACK SIGNAL FOR REGULATING VOUT1. Figure 39. Four Paralleled LTM4676A Producing 1VOUT at Up to 100A. Integrated Power System Management

Figure 40. One LTM4676A Operating In Parallel with 3xLTM4620A or 3xLTM4630 (See Demo Boards DC2106B-A, DC2106B-B)

check that repeat start is supported. Part 1 Revision 1.2: Paragraph 5: T ransport. notes, and the L TpowerPlay GUI are indicated in Table 21. Table 21. Data Format Terminology subsection of the Applications Information section for further details.

for channels comprising a PolyPhase output. Related commands: MFR_COMMON. Pages 0x00 and 0x01 correspond to channel 0 and channel 1, respectively, in this device. will respond to read commands as if PAGE were set to 0x00 (channel 0 results). This command has one data byte. may be sent with PAGE_PLUS_WRITE. a non-paged command, the Page Number byte is ignored. mand that has two data bytes is shown in Figure 63. Figure 63. Example of PAGE_PLUS_WRITE

the data returned by the command, all in one communication packet . data from a non-paged command, the Page Number byte is ignored. with PEC is shown in Figure 64. fault for Invalid/Unsupported Data. value of this command unless the WRITE_PROTECT command is more stringent. respective bits in the STATUS registers. Enable writes to all commands when WRITE_PROTECT is set to 0x00. This command has one data byte. Figure 64. Example of PAGE_PLUS_READ

For more information www.linear .com/L TM4676A If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK and CLEAR_FAULTS commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS registers. MFR_ADDRESS The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device. Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B, cannot be deactivated. If RCONFIG is set to ignore (MFR_CONFIG_ALL[6]=1b), the ASEL pin is still used to determine the LSB of the channel address. If the ASEL pin is open, the LTM4676A will use the four LSBs of the MFR_ADDRESS stored in EEPROM. Values of 0x5A, 0x5B, 0x0C, and 0x7C are not recommended. This command has one data byte. MFR_RAIL_ADDRESS The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value of this command should be common to all devices attached to a single power supply rail. The user should only perform command writes to this address. If a read is performed from this address and the rail devices do not respond with EXACTL Y the same value, the LTM4676A will detect bus contention and set a CML com- munications fault. Setting this command to a value of 0x80 disables rail device addressing for the channel. This command has one data byte. GENERAL CONFIGURA TION REGISTERS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_CHAN_CONFIG 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1F MFR_CONFIG_ALL 0xD1 Configuration bits that are common to all pages. R/W Byte N Reg Y 0x09 MFR_CHAN_CONFIG General purpose configuration command common to multiple L TC products. BIT MEANING

7 Reserved

6 Reserved

5 Reserved

4 Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF 3 Short Cycle. When asserted the output will immediate off if commanded ON while waiting for TOFF_DELAY or TOFF_FALL. TOFF_MIN of 120ms is honored then the part will command ON.

2 SHARE_CLOCK control, if SHARE_CLOCK is held low, the output is disabled

1 No GPIO ALERT, ALERT is not pulled low if GPIO is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are propagated on GPIO 0 Disables the VOUT decay value requirement for MFR_RETRY_TIME processing. When this bit is set to a 0, the output must decay to less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low to high. This command has one data byte. appenDix c: pMbus coMManD DeTails

7 Enable Fault Logging

6 Ignore Resistor Configuration Pins

5 Disable CML fault for Quick Command message

4 Disable SYNC out

3 Enable 255ms Time Out

the part will accept commands with invalid PEC.

1 Enable the use of PMBus clock stretching

0 Enables a low to high transition on either RUN pin to issue a

This command has one data byte. MFR_RESET 0xFD Commanded reset without requiring a power-down. Identical to RESTORE_USER_ALL. turn the unit on and off. This includes how the unit responds when power is applied. Table 22. Supported Values 0x1F OPERATION value and RUN n pin must both command the device to start/run. Device executes immediate off when commanded off. 0x17 RUN n pin control with immediate off when commanded off. OPERATION on/off control ignored. 0x16 RUN n pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored. Note: A high on the RUNn pin is always required to start power conversion. Power conversion will always stop with a low on RUNn. Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored. This command has one data byte.

example ON is changed to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation command is sequence off. Margin High (Ignore Faults) and Margin Low (Ignore Faults) operations are not supported by the LTM4676A. The part defaults to the Sequence Off state. This command has one data byte. Table 23. OPERATION Command Detail Register OPERATION Data Contents Note: Attempts to write a reserved value will cause a CML fault. This command provides a means by which the user can perform a reset of the LTM4676A. Identical to RESTORE_USER_ALL. This write-only command has no data bytes.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails PWM CONFIG COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_PWM_MODE 0xD4 Configuration for the PWM engine of each channel. R/W Byte Y Reg Y 0xC1 MFR_PWM_CONFIG 0xF5 Set numerous parameters for the DC/DC controller including phasing. R/W Byte N Reg Y 0x10 FREQUENCY_SWITCH 0x33 Switching frequency of the controller . R/W Word N L11 kHz Y 500 0xFBE8 MFR_PWM_MODE The MFR_PWM_MODE command allows the user to program the PWM controller to use, discontinuous (pulse-skipping mode), or forced continuous conduction mode. BIT MEANING

7 Range of I LIMIT

0 – Low Current Range 1 – High Current Range

6 Enable Servo Mode

4 Page 0 Only: Use of TSNS

1a-Sensed Temperature Telemetry 0 - Temperature sensed via TSNS1a is used to temperature-correct the current-sense information digitized by Channel 1's current sense input, ISNS1a+/ISNS1a–. 1 - Temperature sensed via TSNS0a is used to temperature-correct the current-sense information digitized by Channel 1's current sense input, ISNS1a+/ISNS1a–. Telemetry obtained from the thermal sensor connected to TSNS1a can be external to the module, if desired.

3 Reserved

2 Reserved

1 Voltage Range

0 - Hi Voltage Range 5.5 volts max 1 - Lo Voltage Range 2.75 volts max

0 PWM Mode

Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this command. Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command. Changing this bit value changes the PWM loop gain and compensation. Changing this bit value whenever an output is active may have detrimental system results. Bit [6] The LTM4676A will not servo while the part is OFF , ramping on or ramping off. When set to a one, the output servo is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC and the VOUT_COMMAND (or the appropriate margined value). Bit [1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes the PWM loop gain and compensation. This bit value cannot be changed when an output is active. This command has one data byte.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails MFR_PWM_CONFIG The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the part must be commanded off. If the part is in the RUN state and this command is written, the command will be ignored and a BUSY fault will be asserted. Bit 7 allows remote differential voltage sensing for PolyPhase rail applications. BIT MEANING

7 EA Connection

0 – Independent EA and Channel Outputs 1 – EA1 uses EA0 input for PolyPhase operation 6 Reserved.

4 Share Clock Enable : If this bit is 1, the

SHARE_CLK pin will not be released until SV IN > VIN_ON. The SHARE_CLK pin will be pulled low when SVIN < VIN_OFF. If this bit is 0, the SHARE_CLK pin will not be pulled low when SVIN < VIN_OFF except for the initial application of SVIN. BIT [2:0] CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES) 000b 0 180 001b 90 270 010b 0 240 011b 0 120 100b 120 240 101b 60 240 110b 120 300 Do not assert Bit [7] unless it is a PolyPhase application and both VOUT pins are tied together and both COMPna pins are tied together . This command has one data byte.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails FREQUENCY_SWITCH The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of a PMBus device. See Table 7 for recom- mended values. Supported Frequencies: VALUE [15:0] RESUL TING FREQUENCY (TYP) 0x0000 External Oscillator 0xF3E8 250kHz 0xFABC 350kHz 0xFB52 425kHz 0xFBE8 500kHz 0x023F 575kHz 0x028A 650kHz 0x02EE 750kHz 0x03E8 1000kHz The part must be in the OFF state to process this command. Either the RUN pins must be low or the part must be commanded off. If the part is in the RUN state and this command is written, the command will be ignored and a BUSY fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be detected as the PLL locks onto the new frequency. This command has two data bytes and is formatted in Linear_5s_11s format. V OL TAGE Input Voltage (SVIN) and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VIN_OV_FAULT_ LIMIT 0x55 Input supply (SV IN) overvoltage fault limit. R/W Word N L11 V Y 27.0 0xDB60 VIN_UV_WARN_LIMIT 0x 58 Input supply (SVIN) undervoltage warning limit. R/W Word N L11 V Y 5.297 0xCAA6 VIN_ON 0x35 Input voltage (SVIN) at which the unit should start power conversion. R/W Word N L11 V Y 5.500 0xCAC0 VIN_OFF 0x36 Input voltage (SVIN) at which the unit should stop power conversion. R/W Word N L11 V Y 5.250 0xCAA0 VIN_OV_FAULT_LIMIT The VIN_OV_FAULT_LIMIT command sets the value of the measured (SV IN) input voltage, in volts, that causes an input overvoltage fault. The fault is detected with the A/D converter resulting in latency up to 90ms, typical. This command has two data bytes and is formatted in Linear_5s_11s format.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails VIN_UV_WARN_LIMIT The VIN_UV_WARN_LIMIT command sets the value of the SVIN input voltage that causes an SVIN input undervoltage warning. The warning is detected with the A/D converter resulting in latency up to 90ms, typical. This command has two data bytes and is formatted in Linear_5s_11s format. VIN_ON The VIN_ON command sets the SV IN input voltage, in volts, at which the unit should start power conversion. This command has two data bytes and is formatted in Linear_5s_11s format. VIN_OFF The VIN_OFF command sets the SVIN input voltage, in volts, at which the unit should stop power conversion. This command has two data bytes and is formatted in Linear_5s_11s format. Output Voltage and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VOUT_MODE 0x20 Output voltage format and exponent (2 –12). R Byte Y Reg 2–12 0x14 VOUT_MAX 0x24 Upper limit on the commanded output voltage including VOUT_MARGIN_HIGH. R/W Word Y L16 V Y 5.6 0x599A VOUT_OV_FAULT_ LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1 0x119A VOUT_OV_WARN_ LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075 0x1133 VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. Must be greater than VOUT_COMMAND. R/W Word Y L16 V Y 1.05 0x10CD VOUT_COMMAND 0x21 Nominal output voltage set point. R/W Word Y L16 V Y 1.0 0x1000 VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. Must be less than VOUT_COMMAND. R/W Word Y L16 V Y 0.95 0x0F33 VOUT_UV_WARN_ LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925 0x0ECD VOUT_UV_FAULT_ LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 0.9 0x0E66 MFR_VOUT_MAX 0xA5 Maximum allowed output voltage including VOUT_OV_FAULT_LIMIT. R Word Y L16 V 5.7 0x5B34 VOUT_MODE The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode (only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write commands. This read-only command has one data byte.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails VOUT_MAX The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can com - mand regardless of any other commands or combinations. The maximum allowed value of this command is 5.7 volts. The maximum output voltage the LTM4676 A can produce is 5.5 volts including VOUT_MARGIN_HIGH. However , the VOUT_OV_FAULT_LIMIT can be commanded as high as 5.7 volts. This command has two data bytes and is formatted in Linear_16u format. VOUT_OV_FAULT_LIMIT The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured at the sense pins, in volts, which causes an output overvoltage fault. If the VOUT_OV_FAULT_LIMIT is modified and the switcher is active, allow 10ms after the command is modified to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of MFR_COMMON. Either bit is low if the part is busy. If this wait time is not met, and the VOUT_COMMAND is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher . If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN, the GPIO pin will not assert if VOUT_OV_FAULT is propa- gated. The LTM4676A will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected. This command has two data bytes and is formatted in Linear_16u format. VOUT_OV_WARN_LIMIT The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured at the sense pins, in volts, which causes an output voltage high warning. The READ_VOUT value will be used to determine if this limit has been exceeded. In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked. This condition is detected by the ADC so the response time may be up to 90ms, typical. This command has two data bytes and is formatted in Linear_16u format. VOUT_MARGIN_HIGH The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to “Margin High”. The value must be greater than VOUT_COMMAND. The maximum guaranteed value on VOUT_MARGIN_HIGH is 5.5 volts. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails VOUT_COMMAND The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed value on VOUT is 5.5 volts. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_MARGIN_LOW The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_WARN_LIMIT The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured at the sense pins, in volts, which causes an output voltage low warning. In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked. This condition is detected by the ADC so the response time may be up to 90ms, typical. This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_FAULT_LIMIT The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured at the sense pins, in volts, which causes an output undervoltage fault. This command has two data bytes and is formatted in Linear_16u format. MFR_VOUT_MAX The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel including VOUT_OV_FAULT_ LIMIT. If the output voltages are set to high range (Bit 1 of MFR_PWM_MODE set to a 0) MFR_VOUT_MAX for channel 0 and 1 is 5.7V. If the output voltages are set to low range (Bit 1 of MFR_PWM_MODE set to a 1) the MFR_VOUT_MAX for both channels is 2.75V. Entering VOUT_COMMAND values greater than this will result in a CML fault and the output voltage setting will be clamped to the maximum level. This read-only command has 2 data bytes and is formatted in Linear_16u format.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails CURRENT Input Current Calibration COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_IIN_OFFSET 0xE9 Coefficient used to add to the input current to account for the IQ of the part. R/W Word Y L11 A Y 0.0305 0x8BE7 MFR_IIN_OFFSET The MFR_IIN_OFFSET command allows the user to set an input current representing the quiescent current of each channel. For accurate results at low output current, the part should be in continuous conduction mode. (MFR_PWM_ MODE[0]=1 b). See Table 8 for recommended values. This command has 2 data bytes and is formatted in Linear_5s_11s format. Output Current Calibration COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE IOUT_CAL_GAIN 0x38 The ratio of the voltage at the current sense pins to the sensed current. R/W Word Y L11 mΩ Factory- Only NVM T rimmed, 3.28mΩ typical MFR_IOUT_CAL_GAIN_TC 0x F6 Temperature coefficient of the current sensing element. R/W Word Y CF Y 3860 0x0F14 IOUT_CAL_GAIN The IOUT_CAL_GAIN command is nominally used to set the resistance value of the current sense element, in mil - liohms. (see also MFR_IOUT_CAL_GAIN_TC). Writes to this register result in a NACK and do not impact output current readback telemetry This command has two data bytes and is formatted in Linear_5s_11s format. MFR_IOUT_CAL_GAIN_TC The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_GAIN inductor DCR in ppm/°C. This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 • –6. Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by: [1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)] . DCR sensing will have a typical value of 3900. The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT, READ_IIN, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT. Writes to this register are not recommended; use the factory- default value. Input Current COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE IIN_OC_WARN_LIMIT 0x5D Input overcurrent warning limit. R/W Word N L11 A Y 12 0xD300

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails IIN_OC_WARN_LIMIT The IIN_OC_WARN_LIMIT command sets the value of the input current, in amperes, that causes a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded. In response to the IIN_OC_WARN_LIMIT being exceeded, the device:

• Sets the OTHER bit in the STATUS_BYTE
• Sets the INPUT bit in the upper byte of the STATUS_WORD
• Sets the IIN Overcurrent Warning bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin, unless masked This condition is detected by the ADC so the response time may be up to 90ms, typical. This command has two data bytes and is formatted in Linear_5s_11s format. Output Current COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A Y 22.84 0xDADB IOUT_OC_WARN_LIMIT 0x 4A Output overcurrent warning limit. R/W Word Y L11 A Y 15.59 0xD3E6 IOUT_OC_FAULT_LIMIT The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in amperes. When the controller is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The programmed overcurrent fault limit value is rounded up to the nearest one of the following set of discrete values: 25mV/IOUT_CAL_GAIN Low Range (1.5x Nominal Loop Gain) MFR_PWM_MODE [7]=028.6mV/IOUT_CAL_GAIN 32.1mV/IOUT_CAL_GAIN 35.7mV/IOUT_CAL_GAIN 39.3mV/IOUT_CAL_GAIN 42.9mV/IOUT_CAL_GAIN 46.4mV/IOUT_CAL_GAIN 50mV/IOUT_CAL_GAIN 37.5mV/IOUT_CAL_GAIN High Range (Nominal Loop Gain) MFR_PWM_MODE [7]=142.9mV/IOUT_CAL_GAIN 48.2mV/IOUT_CAL_GAIN 53.6mV/IOUT_CAL_GAIN 58.9mV/IOUT_CAL_GAIN 64.3mV/IOUT_CAL_GAIN 69.6mV/IOUT_CAL_GAIN 75mV/IOUT_CAL_GAIN Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation: IOUT_OC_FAULT_LIMIT = IOUT_CAL_GAIN
• (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails The L TpowerPlay GUI automatically convert the voltages to currents. The IOUT range is set with bit 7 of the MFR_PWM_MODE command. The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL. This command has two data bytes and is formatted in Linear_5s_11s format. IOUT_OC_WARN_LIMIT This command sets the value of the output current that causes an output overcurrent warning in amperes. The READ_IOUT value will be used to determine if this limit has been exceeded. In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked. This condition is detected by the ADC so the response time may be up to 90ms, typical. The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL. This command has two data bytes and is formatted in Linear_5s_11s format T EMPERA TURE Power Stage DCR Temperature Calibration COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_TEMP_1_GAIN 0xF8 Sets the slope of the power stage temperature sensor . R/W Word Y CF Y 0.995 0x3FAE MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the power stage temperature sensor with respect to –273.1°C. R/W Word Y L11 C Y 0 0x8000 MFR_TEMP_1_GAIN The MFR_TEMP_1_GAIN command will modify the slope of the power stage temperature sensor to account for non- idealities in the element and errors associated with the remote sensing of the temperature in the inductor . This command has two data bytes and is formatted in 16-bit 2’s complement integer . N = 8192 to 32767. The effective adjustment is N • 2–14. The nominal value is 1. MFR_TEMP_1_OFFSET The MFR_TEMP_1_OFFSET command will modify the offset of the power stage temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor . This command has two data bytes and is formatted in Linear_5s_11s format. The part starts the calculation with a value of –273.15 so the default adjustment value is zero.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails Power Stage Temperature Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE OT_FAULT_LIMIT 0x4F Power stage overtemperature fault limit. R/W Word Y L11 C Y 128 0xF200 OT_WARN_LIMIT 0x51 Power stage overtemperature warning limit. R/W Word Y L11 C Y 125 0xEBE8 UT_FAULT_LIMIT 0x53 Power stage undertemperature fault limit. R/W Word Y L11 C Y –45 0xE530 OT_FAULT_LIMIT The OT_FAULT_LIMIT command sets the value of the power stage temperature, in degrees Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. This condition is detected by the ADC so the response time may be up to 90ms, typical. This command has two data bytes and is formatted in Linear_5s_11s format. OT_WARN_LIMIT The OT_WARN_LIMIT command sets the value of the power stage temperature, in degrees Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. In response to the OT_WARN_LIMIT being exceeded, the device:

• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked. This condition is detected by the ADC so the response time may be up to 90ms, typical. This command has two data bytes and is formatted in Linear_5s_11s format. UT_FAULT_LIMIT The UT_FAULT_LIMIT command sets the value of the power stage temperature, in degrees Celsius, which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. This condition is detected by the ADC so the response time may be up to 90ms, typical. This command has two data bytes and is formatted in Linear_5s_11s format.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails TIMING Timing—On Sequence/Ramp COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE TON_DELAY 0x60 Time from RUN and/or Operation on to output rail turn-on. R/W Word Y L11 ms Y 0.0 0x8000 TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value. R/W Word Y L11 ms Y 3.0 0xC300 TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for VOUT to cross the VOUT_UV_FAULT_LIMIT. R/W Word Y L11 ms Y 5.0 0xCA80 VOUT_TRANSITION_RATE 0x27 Rate the output changes when VOUT commanded to a new value. R/W Word Y L11 V/ms Y 0.001 0x8042 TON_DELAY The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. Values from 0ms to 83 seconds are valid. This command has two data bytes and is formatted in Linear_5s_11s format. TON_RISE The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during TON_RISE events. If TON_RISE is less than 0.25ms, the LTM4676A digital slope will be bypassed. The output voltage transition will be controlled by the analog performance of the PWM switcher . The maximum allowed slope is 4V/ms. This command has two data bytes and is formatted in Linear_5s_11s format. TON_MAX_FAULT_LIMIT The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. The maximum limit is 83 seconds. This command has two data bytes and is formatted in Linear_5s_11s format. VOUT_TRANSITION_RATE When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the output voltage to change this command set the rate in V/ms at which the output voltage changes. This commanded rate of change does not apply when the unit is commanded on or off. This command has two data bytes and is formatted in Linear_5s_11s format.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails Timing—Off Sequence/Ramp COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start of TOFF_FALL ramp. R/W Word Y L11 ms Y 0.0 0x8000 TOFF_FALL 0x65 Time from when the output starts to fall until the output reaches zero volts. R/W Word Y L11 ms Y 3.0 0xC300 TOFF_MAX_WARN_LIMIT 0x 66 Maximum allowed time, after TOFF_FALL completed, for the unit to decay below 12.5%. R/W Word Y L11 ms Y 0.0 0x8000 TOFF_DELAY The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. Values from 0 to 83 seconds are valid. This command is excluded from fault events. This command has two data bytes and is formatted in Linear_5s_11s format. TOFF_FALL The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt- age is commanded to zero. It is the ramp time of the V OUT DAC. When the VOUT DAC is zero, the part will three-state. The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate. time is 1.3 seconds. The maximum allowed slope is 4V/ms. In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. This command has two data bytes and is formatted in Linear_5s_11s format. TOFF_MAX_WARN_LIMIT The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to turn off the output until a warning is asserted. The output is considered off when the V OUT voltage is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete. TOFF_MAX_WARN is not enabled in VOUT_DECAY is disabled. A data value of 0ms means that there is no limit and that the unit can attempt to turn off the output voltage indefinitely. Other than 0, values from 120ms to 524 seconds are valid. This command has two data bytes and is formatted in Linear_5s_11s format. Precondition for Restart COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_RESTART_ DELAY 0xDC Delay from actual RUN active edge to virtual RUN active edge. R/W Word Y L11 ms Y 300 0xFA58

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails MFR_RESTART_DELAY This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms. Note: The restart delay is different than the retry delay. The restart delay pulls run low for the specified time, after which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time, set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_ RESTART_DELAY after the RUN pin is pulled high if the output decay bit 1 is enabled in MFR_CHAN_CONFIG and the output takes a long time to decay below 12.5% of the programmed value. This command has two data bytes and is formatted in Linear_5s_11s format. F AUL T RESPONSE Fault Responses All Faults COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_RETRY_ DELAY 0xDB Retry interval during FAUL T retry mode. R/W Word Y L11 ms Y 250 0xF3E8 MFR_RETRY_DELAY This command sets the time in milliseconds between restarts if the fault response is to retry the controller at specified intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments. Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG. This command has two data bytes and is formatted in Linear_5s_11s format. Fault Responses Input Voltage (SV IN) COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VIN_OV_FAULT_RESPONSE 0x56 Action to be taken by the device when an SV IN input supply overvoltage fault is detected. R/W Byte Y Reg Y 0xB8 VIN_OV_FAULT_RESPONSE The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an (SVIN) input overvoltage fault. The data byte is in the format given in Table 28. The device also: Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE

• Set the INPUT bit in the upper byte of the STATUS_WORD

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails

• Sets the SVIN Overvoltage Fault bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALER T pin, unless masked. This command has one data byte. Fault Responses Output Voltage COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0x7A VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0xB8 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 VOUT_OV_FAULT_RESPONSE The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. The data byte is in the format given in Table 24. The device also:
• Sets the VOUT_OV bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked. The only value recognized for this command are: 0x80–The device shuts down (disables the output) and the unit does not attempt to retry. The output remains disabled until the fault is cleared (PMBus, Part II, Section 10.7). 0xB8–The device shuts down (disables the output) and device attempts retry continuously, without limitation, until it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault condition causes the unit to shut down. 0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is com- manded OFF then ON or the RUN pin is asserted low then high or MFR_RESET or RESTORE_USER_ALL through the command or removal of SVIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7. 0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or the part is commanded OFF then ON or the RUN pin is asserted low then high or MFR_RESET or RESTORE_USER_ALL through the command or removal of SV IN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7. Any other value will result in a CML fault and the write will be ignored. This command has one data byte.

Table 24. VOUT_OV_FAULT_RESPONSE Data Byte Contents

• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUNn pin, the OPERATION command, or the combined action of the RUNn pin and OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4676A. 00 Part performs OV pull down only (i.e., turns off the top MOSFET and turns on lower MOSFET while V OUT is > VOUT_OV_FAULT)

01 The PMBus device continues operation for the delay time

10 The device shuts down immediately (disables the output) and

responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault.

111 The PMBus device attempts to restart continuously, without

undervoltage fault. The data byte is in the format given in Table 25.

• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked. The UV fault and warn are masked until the following criteria are achieved: 1) The TON_MAX_FAULT_LIMIT has been reached 2) The TON_DELAY sequence has completed 3) The TON_RISE sequence has completed 4) The VOUT_UV_FAULT_LIMIT threshold has been reached 5) The IOUT_OC_FAULT_LIMIT is not present The UV fault and warn are masked whenever the channel is not active. The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing. This command has one data byte.

Table 25. VOUT_UV_FAULT_RESPONSE Data Byte Contents

• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the OPERATION command, or the combined action of the RUNn pin and OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4676A 00 The PMBus device continues operation without interruption. (Ignores the fault functionally)

10 The device shuts down (disables the output) and responds

according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. detected. Only valid for deglitched off state. fault. The data byte is in the format given in Table 28.

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
• Notifies the host by asserting ALERT pin, unless masked.
• A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0. This command has one data byte. Fault Responses Output Current COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE IOUT_OC_FAULT_RESPONSE 0x47 Action to be taken by the device when an output overcurrent fault is detected. R/W Byte Y Reg Y 0x00

overcurrent fault. The data byte is in the format given in Table 26.

• Sets the IOUT_OC bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked. This command has one data byte.

Table 26. IOUT_OC_FAULT_RESPONSE Data Byte Contents

• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the OPERATION command, or the combined action of the RUNn pin and OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4676A.

00 The LTM4676A continues to operate indefinitely while

constant-current or brick-wall limiting).

10 The LTM4676A continues to operate, maintaining the output

regard to the output voltage, for the delay time set by bits [2:0].

11 The LTM4676A shuts down immediately and responds as

programmed by the Retry Setting in bits [5:3].

111 The device attempts to restart continuously, without limitation,

is set by the MFR_RETRY_DELAY command. down. Only valid for deglitched off state. internal overtemperature fault is detected.

overtemperature fault. The data byte is in the format given in Table 27.

• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
• Notifies the host by asserting ALER T pin, unless masked. This command has one data byte.

Table 27. Data Byte Contents MFR_OT_FAULT_RESPONSE

• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the OPERATION command, or the combined action of the RUNn pin and OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4676A 00 Not supported. Writing this value will generate a CML fault. 01 Not supported. Writing this value will generate a CML fault

responds according to the retry setting in bits [5:3]. 11 The device’s output is disabled while the fault is present. disabled until the fault is cleared. 001-111 Not supported. Writing this value will generate CML fault. stage undertemperature fault is detected.

temperature fault. The data byte is in the format given in Table 28.

• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked. This condition is detected by the ADC so the response time may be up to 90ms, typical. This command has one data byte. UT_FAULT_RESPONSE The UT_FAULT_RESPONSE command instructs the device on what action to take in response to a power stage under- temperature fault. The data byte is in the format given in Table 28. The device also: Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked. This condition is detected by the ADC so the response time may be up to 90ms, typical. This command has one data byte.

Table 28. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE, OT_FAULT_RESPONSE, UT_FAULT_RESPONSE

• Sets the corresponding fault bit in the status commands, and
• Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the OPERATION command, or the combined action of the RUNn pin and OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4676A 00 The PMBus device continues operation without interruption. 01 Not supported. Writing this value will generate a CML fault.

responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. retry interval is set by the MFR_RETRY_DELAY command.

propagated to the GPIO pins. formatted as shown in Table 29. Faults can only be propagated to the GPIO if they are programmed to respond to faults. This command has two data bytes. Table 29. GPIOn Propagate Fault Configuration. The GPIO0 and GPIO1 pins are designed to provide electrical notification of selected events to RESPONSE is not set to ignore, the part will latch off and never be able to start. RESPONSE is not set to ignore, the part will latch off and never be able to start.

*The PWRGD status is designed as an indicator and not to be used for power supply sequencing. This command determines the controller’s response to the GPIOn pin being pulled low by an external source. 0xC0 GPIO_INHIBIT The LTM4676A will three-state the output in response to the GPIO pin pulled low. 0x00 GPIO_IGNORE The LTM4676A continues operation without interruption.

• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails

• Sets the GPIOB bit in the STATUS_MFR_SPECIFIC command, and
• Notifies the host by asserting ALERT pin, unless masked. The ALERT pin pulled low can be disabled by setting bit[1] of MFR_CHAN_CFG. This command has one data byte. SCRA TCHPAD COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE USER_DATA_00 0xB0 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA USER_DATA_01 0xB1 Manufacturer reserved for L TpowerPlay. R/W Word Y Reg Y NA USER_DATA_02 0xB2 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA USER_DATA_03 0xB3 A NVM word available for the user . R/W Word Y Reg Y 0x0000 USER_DATA_04 0xB4 A NVM word available for the user . R/W Word N Reg Y 0x0000 USER_DATA_00 through USER_DATA_04 These commands are non-volatile memory locations for customer storage. The customer has the option to write any value to the USER_DATA_nn at any time. However , the L TpowerPlay software and contract manufacturers use some of these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable inventory control and incompatibility with these products. These commands have 2 data bytes and are in register format. I DENTIFICA TION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PMBUS_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.2. R Byte N Reg 0x22 CAPABILITY 0x19 Summary of PMBus optional communication protocols supported by this device. R Byte N Reg 0xB0 MFR_ID 0x99 The manufacturer ID of the LTM4676A in ASCII. R String N ASC LT C MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC LTM4676A MFR_SERIAL 0x9E Serial number of this specific unit in ASCII. R Block N CF NA MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTM4676A. R Word N Reg 0x47EX PMBus_REVISION The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTM4676A is PMBus Version 1.2 compliant in both Part I and Part II. This read-only command has one data byte.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails CAPABILITY This command provides a way for a host system to determine some key capabilities of a PMBus device. The LTM4676A supports packet error checking, 400kHz bus speeds, and ALERT pin. This read-only command has one data byte. MFR_ID The MFR_ID command indicates the manufacturer ID of the LTM4676A using ASCII characters. This read-only command is in block format. MFR_MODEL The MFR_MODEL command indicates the manufacturer’s part number of the LTM4676A using ASCII characters. This read-only command is in block format. MFR_SERIAL The MFR_SERIAL command contains up to 9 bytes of custom formatted data used to uniquely identify the LTM4676A configuration. This read-only command is in block format. MFR_SPECIAL_ID The 16-bit word representing the part name. The 0x47E prefix denotes the part is an LTM4676A, X is adjustable by the manufacturer . This read-only command has 2 data bytes.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails FAUL T WARNING AND ST ATUS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM DEFAUL T VALUE CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte N NA SMBALERT_MASK 0x1B Mask ALERT Activity. Block R/W Y Reg Y See CMD Details MFR_CLEAR_PEAKS 0xE3 Clears all peaks values. Send Byte N NA STATUS_BYTE 0x78 One byte summary of the unit’s fault condition. R/W Byte Y Reg NA STATUS_WORD 0x79 T wo byte summary of the unit’s fault condition. R/W Word Y Reg NA STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA STATUS_IOUT 0x7B Output current fault and warning status. R/W Byte Y Reg NA STATUS_INPUT 0x7C Input supply (SV IN) fault and warning status. R/W Byte N Reg NA STATUS_ TEMPERATURE 0x7D TSNS na-sensed fault and warning status for READ_TEMERATURE_1. R/W Byte Y Reg NA STATUS_CML 0x7E Communication and memory fault and warning status. R/W Byte N Reg NA STATUS_MFR_ SPECIFIC 0x80 Manufacturer specific fault and state information. R/W Byte Y Reg NA MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg NA MFR_COMMON 0xEF Manufacturer status bits that are common across multiple L TC ICs/modules. R Byte N Reg NA MFR_INFO 0xB6 Manufacturing specific information. R Word N Reg NA CLEAR_FAULTS The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault occurs within that time frame it may be cleared before the status register is set. This write-only command has no data bytes. The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut down for a fault condition are restarted when: The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERA TION command, to turn off and then to turn back on, or

• MFR_RESET or RESTORE_USER_ALL command is issued.
• Bias power is removed and reapplied to the integrated circuit MFR_CLEAR_PEAKS The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET or RESTORE_USER_ALL will initiate this command. This write-only command has no data bytes.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails STATUS_BYTE The STATUS_BYTE command returns a one-byte summary of the most critical faults. STATUS_BYTE Message Contents: BIT STATUS BIT NAME MEANING 7 BUSY A fault was declared because the LTM4676A was unable to respond. 6 OFF This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled. 5 VOUT_OV An output overvoltage fault has occurred. 4 IOUT_OC An output overcurrent fault has occurred. 3 VIN_UV Not supported (LTM4676A returns 0). 2 TEMPERATURE A temperature fault or warning has occurred. 1 CML A communications, memory or logic fault has occurred. 0 NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred. This command has one data byte Any supported fault bit in this command will initiate an ALERT event. STATUS_WORD The STATUS_WORD command returns a two-byte summary of the channel’s fault condition. The low byte of the STATUS_WORD is the same as the STATUS_BYTE command. STATUS_WORD High Byte Message Contents: BIT STATUS BIT NAME MEANING 15 VOUT An output voltage fault or warning has occurred. 14 IOUT An output current fault or warning has occurred. 13 INPUT An SV IN input voltage fault or warning has occurred. 12 MFR_SPECIFIC A fault or warning specific to the LTM4676A has occurred. 11 POWER_GOOD# The POWER_GOOD state is false if this bit is set. 10 FANS Not supported (LTM4676A returns 0). 9 OTHER Not supported (LTM4676A returns 0). 8 UNKNOWN Not supported (LTM4676A returns 0). Any supported fault bit in this command will initiate an ALERT event. This command has two data bytes.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails STATUS_VOUT The STATUS_VOUT command returns one byte of VOUT status information. STATUS_VOUT Message Contents: BIT MEANING 7 V OUT overvoltage fault. 6 V OUT overvoltage warning. 5 V OUT undervoltage warning. 4 V OUT undervoltage fault. 3 VOUT_MAX warning. 2 TON_MAX fault. 1 TOFF_MAX warning. 0 Not supported by the LTM4676A (returns 0). ALERT can be asserted if any of bits[7:1] are set. These may be cleared by writing a 1 to their bit position in STATUS_VOUT, in lieu of a CLEAR_FAULTS command. This command has one data byte. STATUS_IOUT The STATUS_IOUT command returns one byte of IOUT status information. STATUS_IOUT Message Contents: BIT MEANING 7 I OUT overcurrent fault. 6 Not supported (LTM4676A returns 0). 5 I OUT overcurrent warning. 4:0 Not supported (LTM4676A returns 0). ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_IOUT, in lieu of a CLEAR_FAULTS command. This command has one data byte. STATUS_INPUT The STATUS_INPUT command returns one byte of VIN (SVIN) status information. STATUS_INPUT Message Contents: BIT MEANING 7 SV IN overvoltage fault. 6 Not supported (LTM4676A returns 0). 5 SV IN undervoltage warning. 4 Not supported (LTM4676A returns 0).

3 Unit off for insufficient SV

IN voltage. 2 Not supported (LTM4676A returns 0). 1 Input over current warning.

0 Not supported (LTM4676A returns 0)

ALERT can be asserted if bit 7 is set. Bit 7 may be cleared by writing it to a 1, in lieu of a CLEAR_FAULTS command. This command has one data byte.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails STATUS_TEMPERATURE The STATUS_TEMPERATURE command returns one byte of sensed power stage temperature status information. STATUS_TEMPERATURE Message Contents: BIT MEANING 7 External overtemperature fault. 6 External overtemperature warning. 5 Not supported (LTM4676A returns 0). 4 External undertemperature fault. 3:0 Not supported (LTM4676A returns 0). ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_TEMPERATURE, in lieu of a CLEAR_FAULTS command. This command has one data byte. STATUS_CML The STATUS_CML command returns one byte of status information on received commands, internal memory and logic. STATUS_CML Message Contents: BIT MEANING 7 Invalid or unsupported command received. 6 Invalid or unsupported data received. 5 Packet error check failed. 4 Memory fault detected. 3 Processor fault detected. 2 Reserved (LTM4676A returns 0). 1 Other communication fault. 0 Other memory or logic fault. ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_CML, in lieu of a CLEAR_FAULTS command. This command has one data byte. STATUS_MFR_SPECIFIC The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information. Each channel has a copy of the same information. Only bit 0 is page specific. The format for this byte is: BIT MEANING 7 Internal Temperature Fault Limit Exceeded. 6 Internal Temperature Warn Limit Exceeded. 5 NVM CRC Fault.

4 PLL is Unlocked

3 Fault Log Present

0 GPIO Pin Asserted Low by External Device (paged)

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails If any of these bits are set, the MFR bit in the STATUS_WORD will be set. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Exception: The fault log present bit can only be cleared by issuing the MFR_FAULT_LOG_CLEAR command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. MFR_PADS This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit assignments of this command are as follows: BIT ASSIGNED DIGITAL PIN

15 V DD33 OV Fault

14 V DD33 UV Fault

13 Reserved

12 Reserved

11 ADC Values Invalid, Occurs During Start-Up

10 SYNC Output Disabled Due to External Clock

9 PowerGood1

8 PowerGood0

7 Device Driving RUN1 Low

6 Device Driving RUN0 Low

5 RUN1

4 RUN0

3 Device Driving GPIO1 Low

2 Device Driving GPIO0 Low

1 GPIO1

0 GPIO0

A 1 indicates the condition is true. This read-only command has two data bytes. MFR_COMMON The MFR_COMMON command contains bits that are common to all L TC digital power and telemetry products. BIT MEANING

7 MODULE NOT DRIVING ALERT LOW

6 MODULE NOT BUSY

5 CALCULATIONS NOT PENDING

4 OUTPUT NOT IN TRANSITION

3 NVM Initialized

1 SHARE_CLK Timeout

0 WP Pin Status

This read-only command has one data byte.

Figure 67. Summary of the Status Registers

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails MFR_INFO The MFR_INFO command contains additional status bits that are LTM4676A-specific and may be common to multiple L TC PSM products. MFR_INFO Data Contents: BIT MEANING 15:6 Reserved. 5 EEPROM ECC status. 0: Corrections have been made in the EEPROM user space. 1: No corrections have been made in the EEPROM user space. 4:0 Reserved EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM bulk read operation. This read-only command has two data bytes. TELEMETR Y COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM DEFAUL T VALUE READ_VIN 0x88 Measured input supply (SV IN) voltage. R Word N L11 V NA READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA READ_IIN 0x89 Calculated input supply current. R Word N L11 A NA MFR_READ_IIN 0xED Calculated input current per channel. R Word Y L11 A NA READ_IOUT 0x8C Measured output current. R Word Y L11 A NA READ_TEMPERATURE_1 0x8D Power stage temperature sensor . This is the value used for all temperature related processing, including IOUT_CAL_GAIN. R Word Y L11 C NA READ_TEMPERATURE_2 0x8E Control IC die temperature. Does not affect any other registers. R Word N L11 C NA READ_DUTY_CYCLE 0x94 Duty cycle of the top gate control signal. R Word Y L11 % NA READ_POUT 0x96 Calculated output power . R Word Y L11 W NA MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since last MFR_CLEAR_PEAKS. R Word Y L16 V NA MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last MFR_CLEAR_PEAKS. R Word N L11 V NA MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of power stage temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. R Word Y L11 C NA MFR_TEMPERATURE_2_PEAK 0xF4 Maximum measured value of control IC die temperature (READ_TEMPERATURE_2) since last MFR_CLEAR_PEAKS. R Word N L11 C NA MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_IOUT since last MFR_CLEAR_PEAKS. R Word Y L11 A NA MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated fast ADC read back. R/W Byte N Reg 0x00 MFR_ADC_TELEMETRY_ STATUS 0xDA ADC telemetry status indicating which parameter is most recently converted when the short round robin ADC loop is enabled R/W Byte N Reg NA

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails READ_VIN The READ_VIN command returns the measured SVIN input voltage, in volts. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_VOUT The READ_VOUT command returns the measured output voltage in the same format as set by the VOUT_MODE command. This read-only command has two data bytes and is formatted in Linear_16u format. READ_IIN The READ_IIN command returns the input current in Amperes. Note : Input current is calculated from READ_IOUT current and the READ_DUTY_CYCLE value from both outputs plus the MFR_IIN_OFFSET. For accurate values at low currents the part must be in continuous conduction mode. The greatest source of error if DCR sensing is used, is the accuracy of the inductor parasitic DC resistance (DCR) at room temperature IOUT_CAL_GAIN. READ_IIN = MFR_READ_IIN_ PAGE0 + MFR_READ_IIN_PAGE1 This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_READ_IIN The MFR_READ_IIN command is a paged reading of the input current that applies the paged MFR_IIN_OFFSET parameter . This calculation is similar to READ_IIN except the paged values are used. MFR_READ_IIN = MFR_IIN_OFFSET + (IOUT

• DUTY_CYCLE) This command has 2 data bytes and is formatted in Linear_5s_11s format. READ_IOUT The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of: a) the differential voltage derived from the power inductor , ∆ISNSn b) the IOUT_CAL_GAIN value c) the MFR_IOUT_CAL_GAIN_TC value, and d) READ_TEMPERATURE_1 value e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_TEMPERATURE_1 The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails READ_TEMPERATURE_2 The READ_TEMPERATURE_2 command returns the temperature, in degrees Celsius, of the internal sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_DUTY_CYCLE The READ_DUTY_CYCLE command returns the duty cycle of controller , in percent. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_POUT The READ_POUT command is a paged reading of the DC/DC converter output power in Watts. The POUT is calculated based on the most recent correlated output voltage and current readings. This command has 2 data bytes and is formatted in Linear_5s_11s format. MFR_VOUT_PEAK The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_16u format. MFR_VIN_PEAK The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_TEMPERATURE_1_PEAK The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_1 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_TEMPERATURE_2_PEAK The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_2 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format.

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails MFR_IOUT_PEAK The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_ADC_CONTROL The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of 90ms. The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms. This command has a latency of up to two ADC conversions or approximately 16ms (power stage temperature conversions may have a latency of up to three ADC conversion or approximately 24ms). Selecting a value of 0x0D will enable a short round robin loop. This commanded value runs a short telemetry loop only selecting VOUT0, IOUT0, VOUT1 and IOUT1 in a round robin manner . The round robin typical latency is 27ms. It is recommended the part remain in standard telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be commanded to monitor the desired parameter for a limited period of time (say, less than a second) then set the com- mand back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all warnings and faults associated with telemetr y other than the selected parameter are effectively disabled and voltage servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled. COMMANDED VALUE TELEMETRY SELECTED 0x00 Standard ADC Round Robin Telemetry 0x01 SVIN 0x02 Reserved 0x03 Reserved 0x04 Internal IC Temperature 0x05 Channel 0 VOUT 0x06 Channel 0 IOUT 0x07 Reserved 0x08 Channel 0 Power Stage-Sensed Temperature 0x09 Channel 1 VOUT 0x0A Channel 1 IOUT 0x0B Reserved 0x0C Channel 1 Power Stage or TSNS1a-Sensed Temperature 0x0D ADC Short Round Robin 0x0E-0xFF Reserved If a reserved command value is entered, the part will default to Internal IC Temperature and issue a CML[6] fault. CML[6] faults will continue to be issued by the LTM4676A until a valid command value is entered. This read/write command has 1 data byte and is formatted in register format.

For more information www.linear .com/L TM4676A MFR_ADC_TELEMETRY_STATUS The MFR_ADC_TELEMETRY_STATUS command provides the user the means to determine the most recent ADC conversion when the MFR_ADC_CONTROL short round robin loop is enabled using command 0xD8 value 0x0D. The bit assignments of this command are as follows: BIT TELEMETRY DATA AVAILABLE

7 Reserved returns 0

6 Reserved returns 0

5 Reserved returns 0

4 Reserved returns 0

3 Channel 1 IOUT readback (IOUT1)

2 Channel 1 VOUT readback (VOUT1)

1 Channel 0 IOUT readback (IOUT0)

0 Channel 0 VOUT readback (VOUT0)

Write to MFR_ADC_TELEMETRY_STATUS with data bits set to 1 clear the respective bits. This read/write command has 1 data byte and is formatted in register format. NVM (EEPROM) MEMOR Y COMMANDS Store/Restore COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM DEFAUL T VALUE STORE_USER_ALL 0x15 Store user operating memory to EEPROM. Send Byte N NA RESTORE_USER_ALL 0x16 Restore user operating memory from EEPROM. Identical to MFR_RESET. Send Byte N NA MFR_COMPARE_USER_ALL 0xF0 Compares current command contents with NVM. Send Byte N NA STORE_USER_ALL The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating Memory to the matching locations in the non-volatile User NVM memory (EEPROM). The 10 year data retention can only be guaranteed when STORE_USER_ALL is executed at 0°C ≤ TJ ≤ 85°C. Executing this command at junction temperatures above 85°C or below 0°C is not recommended because data retention cannot be guaranteed for that condition. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled. The command is re-enabled when the IC temperature drops below 125°C. Communication with the LTM4676A and programming of the EEPROM can be initiated when VDD33 is available and SV IN is not applied. To enable the part in this state, using global address 0x5B write 0x2B followed by 0xC4. The part can now be communicated with, and the project file updated. To write the updated project file to the EEPROM issue a STORE_USER_ALL command. When SV IN is applied, a MFR_RESET or RESTORE_USER_ALL must be issued to allow the PWM to be enabled and valid ADCs to be read. This write-only command has no data bytes.

This write-only command has no data bytes. what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated. temperature drops below 125°C. This write-only command has no data bytes. is similar to a strip chart recorder . When a fault occurs, the contents are written into EEPROM for nonvolatile storage. Figure 68. Fault Log Conceptual Diagram

used to assemble a complete fault log. occurs within the first second of applying power , some of the earlier pages in the fault log may not contain valid data. NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock. This read-only command is in block format. IN - power cycle) in 200µs increments. This is a 48-bit binary counter . This write-only command has no data bytes. Table 30. Fault Logging. This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command. Fault Log Preface [7:0] ASC 0 Returns L Txx beginning at byte 0 if a partial or complete fault log exists.

Fault Source [7:0] Reg 4 Refer to Table 31. MFR_REAL_TIME [7:0] Reg 5 48 bit share-clock counter value when fault occurred (200µs resolution). MFR_VIN_PEAK [15:8] L11 19 Peak READ_VIN since last power-on or CLEAR_PEAKS command. READ_TEMPERATURE1 (PAGE 0) [15:8] L11 21 Channel 0 power stage during last event. READ_TEMPERATURE2 [15:8] L11 25 Internal temperature sensor during last event.

Table 31. Explanation of Position_Fault Values

For more information www.linear .com/L TM4676A appenDix c: pMbus coMManD DeTails MFR_FAULT_LOG_CLEAR The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear . This write-only command is send bytes. Block Memory Write/Read COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access by MFR_EE_ERASE and MFR_EE_DATA commands. R/W Byte N Reg NA MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk programming by MFR_EE_ DATA. R/W Byte N Reg NA MFR_EE_DATA 0xBF Data transferred to and from EEPROM using sequential PMBus word reads or writes. Supports bulk programming. R/W Word N Reg NA All the (EEPROM) commands are disabled if the die temperature exceeds 130°C. (EEPROM) commands are re-enabled when the die temperature drops below 125°C. MFR_EE_xxxx MFR_EE_XXXX commands are used to facilitate bulk programming of the internal EEPROM. Contact the factory for more details.

Table 32. LTM4676A BGA Pinout

For more information www.linear .com/L TM4676A package DescripTion package phoTograph VOUT0 VOUT0 ISNS0b ISNS1b – ISNS1a ISNS1b + ISNS1a + FSWPHCFG ISNS0a GPIO0 GPIO1ISNS0b + ISNS0a 1 2 3 4 5 6 7 TOP VIEW 8 9 10 11 12 M L K J H G F E D C B A VIN0 VIN0 GND GNDGND SW0GND SNUB0 TSNS0b TSNS0a RUN0 ALERT DNC GND COMP0b VOSNS0+ VORB0– DNC SVIN SVIN VORB0+ VOSNS0–COMP0aSYNC SDA SCL RUN1 SGND INTV CC GNDGND GND ASEL V OUT0CFG VTRIM0CFG VTRIM1CFGSHARE_CLK COMP1a VOSNS1 VOUT1CFG GNDGND GND DNC VOUT1 TSNS1a TSNS1b WP DNC SW1 VDD25 VDD33 COMP1b VORB1 VOUT1 SNUB1 VIN1 VIN1

For more information www.linear .com/L TM4676A package DescripTion 144-Lead (16mm × 16mm × 5.01mm) (Reference L TC DWG # 05-08-1920 Rev B) PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES D E b e e b F G BGA 144 0213 REV B TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PIN 1 11 10 9 8 7 6 5 4 3 212 1 A B C D E F G H K J L M SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.630 ±0.025 Ø 144x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL A Øb (144 PLACES) A DETAIL B PACKAGE SIDE VIEW Z M X Y Z ddd M Z eee DETAIL B SUBSTRATE ccc Z MOLD CAP SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 144 // bbb Z Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES Please refer to http://www.linear .com/product/LTM4676A#packaging for the most recent package drawings.

For more information www.linear .com/L TM4676A Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 05/17 Added “with ECC”. Increased input voltage from 17V to 26.5V. Faster turn-on time from 70ms to 40ms tSTART. Changed update rate from 100ms to 90ms. 1, 3, 4 1, 4 7, 8

• SLAVE ADDRESS = 1001111_R/W (0X4F)
• SWITCHING FREQUENCY: 350kHz
• NO GUI CONFIGURATION AND NO PART SPECIFIC PROGRAMMING REQUIRED IN MUL TI-MODULE SYSTEMS, CONFIGURING RAIL_ADDRESS IS RECOMMENDED COUT0 100µF COUT1 100µF VOUT0, 1.0V ADJUSTABLE UP TO 13A V IN0 VIN1 SVIN VDD33 LOAD0SCL SDA ALERT RUN RUN1 GPIO0 GPIO1 SYNC SHARE_CLK ASEL FSWPHCFG VOUT0CFG VTRIM0CFG VOUT1CFG VTRIM1CFG INTVCC VDD25 SW0 SW1 SNUB0 SNUB1 COMP0a COMP0b COMP1a COMP1b GND WP 6.34k ±50ppm/°C L TM4676A 4676A F62 22.6k ±50ppm/°C SMBus INTERFACE WITH PMBus COMMAND SET ON/OFF CONTROL, FAUL T MANAGEMENT , POWER SEQUENCING LOAD1 VOUT0 TSNS0a TSNS0b ISNS0a+ ISNS0b+ ISNS0a– ISNS0b– VORB0+ VOSNS0+ VOSNS0– VORB0– VORB1 VOUT1 TSNS1a TSNS1b ISNS1a+ ISNS1b+ ISNS1a– ISNS1b– VOSNS1 SGND Design resources SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Sear ch parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. PART NUMBER DESCRIPTION COMMENTS LTM4620A Dual 13A or Single 26A Step-Down µModule Regulator 4.5V ≤ V IN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V, 15mm × 15mm × 4.41mm LGA LTM4630 Dual 18A or Single 36A Step-Down µModule Regulator 4.5V ≤ V IN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 4.41mm LGA LTM4677 LTM4675 LTC3880/LTC3883 Dual and Single Output DC/DC Controllers with Power System Management 0.5% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and Supervision LTC2977/LTC2974 8- and 4-Channel PMBus Power System Managers 0.25% TUE 16-Bit ADC, Voltage/Temperature Monitoring and Supervision Licensed under U.S. Patent 7000125 and other related patents worldwide. TUE is total unadjusted error .

Figure 69. 13A, 1V and 13A, 1.8V Output DC/DC µModule Regulator with Serial Interface