LTM4675

Linear Technology

Dual Output PolyPhase Step-Down Controller with Sub-Milliohm DCR Sensing and Digital Power System Management

Manufacturer: Linear Technology

Document: 128 Pages / 3Mb

Request Quote Download Datasheet Read online HTML view

More from Linear Technology Browse L parts

Online Datasheet

Read LTM4675 online.

LTC3884 LINER | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 128

Technical content

3884feFor more information www.linear .com/L TC3884 TYPICAL APPLICATION FEATURES DESCRIPTION Dual Output PolyPhase Step-Down Controller with Sub-Milliohm DCR Sensing and Digital Power System Management The LT C®3884/LTC3884-1 are dual output PolyPhase DC/ DC synchronous step-down switching regulator controllers with an I2C-based PMBus compliant serial interface. The controllers employ a constant-frequency current mode architecture, together with a unique scheme to provide excellent performance for sub-milliohm DCR applica - tions. The LTC3884/LTC3884-1 are supported by the LTpowerPlay ® software development tool with graphical user interface (GUI). Programmable loop compensation allows the controller to be compensated digitally. Switching frequency, channel phasing, output voltage, and device address can be pro- grammed both by the digital interface as well as external configuration resistors. Additionally, parameters can be set via the digital interface or stored in EEPROM. Both outputs have independent power good indicators and FAUL T function. The LTC3884 has integrated gate drivers. The LTC3884-1 has three-state PWM pins to drive power blocks or DrMOS power stages.

APPLICATIONS

n PMBus/I2C Compliant Serial Interface – Telemetry Read-Back Includes VIN, IIN, VOUT, IOUT, Temperature and Faults – Programmable Voltage, Current Limit, Digital Soft- Start/Stop, Sequencing, Margining, OV/UV/OC n Sub-Milliohm DCR Current Sensing n Digitally Adjustable Loop Compensation Parameters n ±0.5% Output Voltage Accuracy Over Temperature n Integrated Input Current Sense Amplifier n Internal EEPROM with ECC and Fault Logging n Integrated N-Channel MOSFET Gate Drivers (LTC3884) Power Conversion n Wide VIN Range: 4.5V to 38V n VOUT Range: 0.5V to 3.5V (with Low DCR Setting); 0.5V to 5.5 V (without Low DCR Setting) n Accurate PolyPhase® Current Sharing for Up to 6 Phases n Available in 48-Lead 7mm × 7mm QFN and 5mm × 6 mm GQFN Packages. n Telecom, Datacom, and Storage Systems n Industrial and Point-of-Load Applications All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 5408150, 7420359, 8648623, 8786265, 8823352, 7000125. Licensed under U.S. Patent 7000125 and other related patents worldwide. Efficiency and Power Loss vs Load Current INTVCC TG0 TG1 BOOST0 BOOST1 SW0 SW1 BG0 FAUL T MANAGEMENT TO/FROM OTHER L TC DEVICES SDA SCL ALERT RUN0 RUN1 V SENSE0+ VSENSE0– TSNS0 ITH0 ITHR0 VSENSE1+ VSENSE1– TSNS1 ITH1 ITHR1 FAUL T0 FAUL T1 PGOOD0 PGOOD1 BG1 EXTV CC SHARE_CLK 0.22µF 1µF220pF 10nF 10nF VOUT1 30A 330µF 330µF

3884 TA01a

1.8V 30A 2200pF *SOME DETAILS OMITTED FOR CLARITY 0.22µF 931/uni03A9 931/uni03A9 ISENSE0+ ISENSE1+ ISENSE0– ISENSE1– PMBus INTERFACE 4.7µF10µF 10µF 2m/uni03A9 1µF 270µF 1/uni03A9 V IN 6V TO 15V 0.1µF0.1µF DCR=0.32m/uni03A9 L = 0.33µH DCR=0.32m/uni03A9 VIN L TC3884* SGNDPGNDVDD33 VDD25 IIN+ IIN– 1µF 220pF L= 0.33µH V IN = 12V V OUT = 1.8V EXTV CC f SW= 350kHz EFFICIENCY POWER LOSS LOAD CURRENT (A) 100 EFFICIENCY (%) POWER LOSS (W)

3884 TA01b

3884fe For more information www.linear .com/L TC3884 TABLE OF CONTENTS T

Description

T Operation M E Pow S Ti V Sh L S P O IN O utput Current Sensing and Sub Milliohm DCR I P E R F S M P C Se C De R Ou O P R R R I E xternal Overtemperature and Re sponses to Input Overcurrent and Output R F B S imilarity Between PMBus, SMBus and P P C I I I L S lope Compensation and Inductor Peak Current ....49 P ower MOSFET and Optional Schottky Diode V ariable Delay Time, Soft-Start and Output D S IN T Un

3884feFor more information www.linear .com/L TC3884 TABLE OF CONTENTS O P hase-Locked Loop and Frequency Min I E xternal Resistor Configuration Pins (RCONFIG) ....58 V F P A E P C P M P PC B D A C onnecting the USB to I2C/SMBus/PMBus L TpowerPlay: An Interactive GUI for P MBus Communication and Command A Ge O P Vo I O O I Te E T T P Fa Fa F F F F F F F F T

3884fe For more information www.linear .com/L TC3884 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS 3V to 46V Switch Transient Voltage (SW0, SW1) (BOOST0-SW0), (BOOST1-SW1) Top Gate Transient Voltage TG0, TG1 Top Gate Transient Voltage PWM0, PWM1 ISENSE0+, ISENSE0–, ISENSE1+, ISENSE1–, (Note 1) LTC3884 LTC3884 TOP VIEW SGND UK PACKAGE 48-LEAD (7mm × 7mm) PLASTIC QFN VSENSE0+ 1 VSENSE0– 2 ISENSE1+ 3 ISENSE1– 4 ITHR0 5 ITH0 6 ISENSE0+ 7 ISENSE0– 8 TSNS1 9 TSNS0 10 SYNC 11 SCL 12

36 BOOST1

35 TG1

34 SW1

33 PGOOD1

31 VSENSE1–

30 ITHR1

29 ITH1

28 VDD33

27 SHARE_CLK

48 PGOOD0

IN–

46 IIN+

45 SW0

44 TG0

43 BOOST0

42 BG0

41 PGND

40 EXTV

39 VIN

38 INTVCC

37 BG1

VOUT0_CFG 21 VOUT1_CFG 22 FREQ_CFG 23 PHASE_CFG 24 TJMAX = 125°C, θJA = 31°C/W , θJC = 3°C/W EXPOSED PAD (PIN 49) IS SGND, MUST BE SOLDERED TO PCB TOP VIEW SGND RHE PACKAGE 48-LEAD (5mm × 6mm) PLASTIC GQFN PGOOD0 1 VSENSE0+ 2 VSENSE0– 3 ISENSE1+ 4 ISENSE1– 5 ITHR0 6 ITH0 7 ISENSE0+ 8 ISENSE0– 9 TSNS1 10 TSNS0 11 SYNC 12 SCL 13 SDA 14

38 BG1

37 BOOST1

36 TG1

35 SW1

34 PGOOD1

32 VSENSE1–

31 ITHR1

30 ITH1

29 VDD33

28 SHARE_CLK

25 PHASE_CFG

48 IIN–

47 IIN+

46 SW0

45 TG0

44 BOOST0

43 BG0

42 PGND

41 EXTV

40 VIN

39 INTVCC

VOUT0_CFG 22 VOUT1_CFG 23 FREQ_CFG 24 TJMAX = 125°C, θJA = 31°C/W , θJC = 3.7°C/W EXPOSED PADS (PIN 49) ARE SGND, MUST BE SOLDERED TO PCB 3V to 3.6V 3V to 5.5V ASEL0, ASEL1, VOUT0_CFG0, VOUT1_CFG, FAULT0, FAULT1, SHARE_CLK, WP , SYNC –0.3 V to 3.6V 3V to 3.6V Operating Junction Temperature Range C to 125°C C to 150°C* *See Derating EEPROM Retention at Temperature in Applications Informa- tion section for junction temperatures in excess of 125°C.

3884feFor more information www.linear .com/L TC3884 PIN CONFIGURATION LTC3884-1 TOP VIEW SGND RHE PACKAGE 48-LEAD (5mm × 6mm) PLASTIC GQFN PGOOD0 1 VSENSE0+ 2 VSENSE0– 3 ISENSE1+ 4 ISENSE1– 5 ITHR0 6 ITH0 7 ISENSE0+ 8 ISENSE0– 9 TSNS1 10 TSNS0 11 SYNC 12 SCL 13 SDA 14 38 NC

37 VCC1

36 PWM1

45 PWM0

44 VCC0

VOUT0_CFG 22 VOUT1_CFG 23 FREQ_CFG 24 TJMAX = 125°C, θJA = 31°C/W , θJC = 3.7°C/W EXPOSED PADS (PIN 49) ARE SGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3884EUK#PBF LTC3884EUK#TRPBF LTC3884 UK 48-Lead (7mm × 7mm) Plastic QFN –40°C to 125°C LTC3884IUK#PBF LTC3884IUK#TRPBF LTC3884 UK 48-Lead (7mm × 7mm) Plastic QFN –40°C to 125°C LTC3884ERHE#PBF LTC3884ERHE#TRPBF LTC3884 48-Lead (5mm × 6mm) Plastic GQFN –40°C to 125°C LTC3884IRHE#PBF LTC3884IRHE#TRPBF LTC3884 48-Lead (5mm × 6mm) Plastic GQFN –40°C to 125°C LTC3884ERHE-1#PBF LTC3884ERHE-1#TRPBF LTC3884-1 48-Lead (5mm × 6mm) Plastic GQFN –40°C to 125°C LTC3884IRHE-1#PBF LTC3884IRHE-1#TRPBF LTC3884-1 48-Lead (5mm × 6mm) Plastic GQFN –40°C to 125°C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. (http://www.linear .com/product/LTC3884#orderinfo)

3884fe For more information www.linear .com/L TC3884 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Notes 2, 3). VIN = 12V, EXTVCC = 0V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified. SYMBOL PARAMETER CONDITION MIN TYP MAX UNITS Input Voltage VIN Input Voltage Range (Note 11) l 4.5 38 V IQ Input Voltage Supply Current V RUN0,1 = 3.3V (Note 16) VRUN0,1 = 0V (Note 16) mA mA VUVLO Undervoltage Lockout Threshold When VIN > 4.3V VINTVCC Falling VINTVCC Rising 3.55 3.90 V V tINIT Initialization Time Time from VIN Applied Until the TON_DELAY Timer Starts 35 ms tOFF(MIN) Short Cycle Retry Time 120 ms Control Loop VOUTRL Full-Scale Voltage Range Set Point Accuracy (0.6V ~ 2.5V) Resolution LSB Step Size VOUT_COMMAND = 2.75V, MFR_PWM_MODE[1] = 1 (Notes 9, 10, 13) l l 2.7 –0.5 0.688 2.8 0.5 V Bits mV V OUTRH Full-Scale Voltage Range Set Point Accuracy (0.6V ~ 5.0V) Resolution LSB Step Size VOUT_COMMAND = 5.5V, MFR_PWM_MODE[1] = 0 (Notes 9, 10, 13) l l 5.40 –0.5 1.375 5.60 0.5 V Bits mV VLINEREG Line Regulation 6V < VIN < 38V l ±0.02 %/V VLOADREG Load Regulation ∆VITH = 1.35V ~ 0.7V ∆VITH = 1.35V ~ 2V l l 0.01 –0.01 0.1 –0.1 IISENSE0,1 Input Pin Bias Current 0V ≤ VPIN ≤ 5.5V l ±1 ±3 µA VSENSERIN0,1 VSENSE Input Resistance to GND 0V ≤ V PIN ≤ 5.5V 50 kΩ VILIMIT (Note 15) 12 Steps VILIM_HIGH VILIM_LOW VREV MFR_PWM_MODE[7],[2]=0, 1, ILIM[3:0]=1100, VOUT ≤ 3.5V MFR_PWM_MODE[7],[2]=0, 1, ILIM[3:0]=0001, VOUT ≤ 3.5V MFR_PWM_MODE[7],[2]=0, 1, VOUT ≥ VOV l 14.5 16.5 9.5 –7.5 18.5 mV mV mV V ILIM_HIGH VILIM_LOW VREV MFR_PWM_MODE[7],[2]=1, 1, ILIM[3:0]=1100,VOUT ≤ 3.5V MFR_PWM_MODE[7],[2]=1, 1, ILIM[3:0]=0001,VOUT ≤ 3.5V MFR_PWM_MODE[7],[2]=1, 1, VOUT ≥ VOV l 27.0 29.5 17.0 –15 31.0 mV mV mV V ILIM_HIGH VILIM_LOW VREV MFR_PWM_MODE[7],[2]=0, 0, ILIM[3:0]=1100 MFR_PWM_MODE[7],[2]=0, 0, ILIM[3:0]=0001 MFR_PWM_MODE[7],[2]=0, 0, VOUT ≥ VOV l 35 41.38 –18.8 49 mV mV mV V ILIM_HIGH VILIM_LOW VREV MFR_PWM_MODE[7],[2]=1, 0, ILIM[3:0]=1100 MFR_PWM_MODE[7],[2]=1, 0, ILIM[3:0]=0001 MFR_PWM_MODE[7],[2]=1, 0, VOUT ≥ VOV l 67.5 74.5 43.5 –37.5 81.5 mV mV mV g m0,1 Resolution Error Amplifier g m(MAX) Error Amplifier gm(MIN) LSB Step Size ITH0,1 = 1.35V, MFR_PWM_COMP[7:5] = 0 to 7 3 5.76 0.68 Bits mmho mmho mmho R TH0, 1 Resolution Compensation Resistor R TH(MAX) Compensation Resistor RTH(MIN) MFR_PWM_COMP[4:0] = 0 to 31 (See Figure 37) 5 Bits kΩ kΩ Gate Drivers (LTC3884) TG R UP TG Pull-Up RDS(ON) TG High 2.6 Ω TG RDOWN TG Pull-Down RDS(ON) TG Low 1.5 Ω BG RUP BG Pull-Up RDS(ON) BG High 2.4 Ω

10 Bits

VIINSTP LSB Step Size Full-Scale Range = 16mV LSB Step Size Full-Scale Range = 32mV LSB Step Size Full-Scale Range = 64mV Gain = 8, 0V ≤ |VIIN+ – VIIN–| ≤ 5mV Gain = 4, 0V ≤ |VIIN+ – VIIN–| ≤ 20mV Gain = 2, 0V ≤ |VIIN+ – VIIN–| ≤ 50mV 15.26 30.52 µV µV µV IIN_TUE Total Unadjusted Error Gain = 8, 2.5mV ≤ |VIIN+ – VIIN–| VIN = 8V (Note 8) Gain = 4, 4mV ≤ |VIIN+ – VIIN–| VIN = 8V (Note 8) Gain = 2, 6mV ≤ |VIIN+ – VIIN–| VIN = 8V (Note 8) l l l ±1.3 ±1.2 V OS Zero-Code Offset Voltage ±50 µV tCONVERT Update Rate (Note 6) 90 ms Supply Current Readback N Resolution (Note 5) 10 Bits VICHIPSTP LSB Step Size Full-Scale Range = 256mV 244 µV ICHIPTUE Total Unadjusted Error |VIIN+ – VIN| ≤ 150mV (Note 19) l ±3 % tCONVERT Update Rate (Note 6) 90 ms Temperature Readback (T0, T1) TRES_T Resolution 0.25 °C T0_TUE External Temperature Total Unadjusted Readback Error TSNS0, TSNS1 ≤ 1.85V (Note 8) MFR_PWM_MODE_[5] = 0 MFR_PWM_MODE_[5] = 1 (Note 14) –10 T1_TUE Internal TSNS TUE V RUN0,1 = 0.0, fSYNC = 0kHz (Note 8) ±1 °C tCONVERT Update Rate (Note 6) 90 ms INTVCC Regulator/EXTVCC VINTVCC Internal VCC Voltage No Load 6V ≤ V IN ≤ 38V 5.25 5.5 5.75 V VLDO_INT INTVCC Load Regulation ICC = 0mA to 20mA, 6V ≤ VIN ≤ 38V 0.5 ±2 % VEXTVCC EXTVCC Switchover Voltage V IN ≥ 7V, EXTVCC Rising 4.5 4.7 V VLDO_HYS EXTVCC Hysteresis 290 mV VLDO_EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5.5V 50 100 mV

3884fe For more information www.linear .com/L TC3884 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Notes 2, 3). VIN = 12V, EXTVCC = 0V, VRUN0,1 = 3.3V, fSYNC = 500kHz (externally driven) and all programmable parameters at factory default, unless otherwise specified. SYMBOL PARAMETER CONDITION MIN TYP MAX UNITS Open-Drain Outputs SCL, SDA, FAUL Tn, ALERT, RUNn, SHARE_CLK, PGOODn VOL Output Low Voltage ISINK = 3mA 0.4 V Digital Inputs SHARE_CLK, WP V IH Input High Threshold Voltage l 1.5 1.8 V VIL Input Low Threshold Voltage l 0.6 1 V Digital Filtering of FAUL Tn I FL TG Input Digital Filtering FAUL Tn 3 µs Digital Filtering of PGOODn I FL TG Output Digital Filtering PGOODn 60 µs Digital Filtering of RUNn I FL TG Input Digital Filtering RUN 10 µs PMBus Interface Timing Characteristics f SCL Serial Bus Operating Frequency l 10 400 kHz tBUF Bus Free Time Between Stop and Start l 1.3 µs tHD(STA) Hold Time After Repeated Start Condition After This Period, the First Clock is Generated l 0.6 µs tSU(STA) Repeated Start Condition Setup Time l 0.6 10000 µs tSU(ST0) Stop Condition Setup Time l 0.6 µs tHD(DAT) Date Hold Time Receiving Data T ransmitting Data l l 0.3 0.9 µs µs t SU(DAT) Data Setup Time Receiving Data l 0.1 µs tTIMEOUT_SMB Stuck PMBus Timer Non-Block Reads Stuck PMBus Timer Block Reads Measured from the Last PMBus Start Event 32 255 ms tLOW Serial Clock Low Period l 1.3 10000 µs tHIGH Serial Clock High Period l 0.6 µs Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3884/LTC3884-1 is tested under pulsed load conditions such that T J ≈ TA. The LTC3884E/LTC3884E-1 is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3884I/LTC3884I-1 is guaranteed over the full –40°C to 125°C operating junction temperature range. TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA) The maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified Note 4: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. C LOAD = 3500pF is guaranteed by design. Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits mantissa (signed). This limits the output resolution to 10 bits though the internal ADC is 16 bits and the calculations use 32-bit words. Note 6: The data conversion is done by default in round robin fashion. All inputs signals are continuously converted for a typical latency of 90ms. Setting MFR_ADC_CONTRL value to be 0 to 12, LTC3884 can do fast data conversion with only 8ms to 10ms. See section PMBus Command for details. Note 7: The IOUT_CAL_GAIN = 1.0mΩ and MFR_IOUT_TC = 0.0. Value as read from READ_IOUT in Amperes.

3884feFor more information www.linear .com/L TC3884

ELECTRICAL CHARACTERISTICS

R TH (kΩ)

3884 F01

Figure 1. Programmable RTH (Zero code Offset + ADC Linearity Error)/Actual Value. feedback loop that servos VOUT to a specified value. operating junction temperature range. and sub milliohm DCR Current Sensing” in Operation Section for details. Only VILIMIT codes 2–8 are supported for DCR sensing. operating junction temperature may impair device reliability. result in a degradation of retention characteristics. sensing voltage within the maximum voltage of 150mV.

3884fe For more information www.linear .com/L TC3884 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 12V, L = 0.33µH, DCR = 0.32mΩ, EXTVCC = 0V unless otherwise noted. Efficiency vs Load Current Efficiency vs Load Current Power Loss vs Load Current f SW = 350KHz V OUT =1.8V V OUT =1.5V V OUT =1.2V V OUT =1.0V LOAD CURRENT (A) EFFICIENCY (%)

3884 G01

f SW = 500KHz V OUT =1.8V V OUT =1.5V V OUT =1.2V V OUT =1.0V LOAD CURRENT (A) EFFICIENCY (%)

3884 G02

f SW = 350KHz V OUT =1.8V V OUT =1.5V V OUT =1.2V V OUT =1.0V LOAD CURRENT (A) POWERLOSS (W)

3884 G03 Power Loss vs Output Current

(Forced Continuous Mode) Load Step (Discontinuous Mode) ILOAD 10A/DIV IL 10A/DIV VOUT 100mV/DIV AC-COUPLED 50µs/DIVVIN = 12V VOUT = 1.8V 0.3A TO 10A STEP

3884 G05

50µs/DIVVIN = 12V VOUT = 1.8V 0.3A TO 10A STEP

3884 G06

f SW = 500KHz V OUT =1.8V V OUT =1.5V V OUT =1.2V V OUT =1.0V LOAD CURRENT (A) POWERLOSS (W)

3884 G04

3884feFor more information www.linear .com/L TC3884 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = 12V, L = 0.33µH, DCR = 0.32mΩ, EXTVCC = 0V unless otherwise noted. Inductor Current at Light Load Soft-Start Ramp Start-Up Into a Prebiased Output FORCED CONTINUOUS MODE 5A/DIV DISCONTINUOUS MODE 5A/DIV 1µs/DIVVOUT = 1.8V ILOAD = 1A

3884 G07

5ms/DIVtRISE = 10ms tDELAY = 5ms VOUT = 1.8V

3884 G08

5ms/DIVtRISE = 10ms VOUT = 1.8V

3884 G09

Dynamic Current Sharing During a Load T ransient in a 2-Phase System Dynamic Current Sharing During a Load Transient in a 2-Phase System RUN 2V/DIV VOUT 1V/DIV 5ms/DIVtFALL = 5ms tDELAY = 10ms

3884 G10

5µs/DIV

3884 G11

5µs/DIV

3884 G12

3884fe For more information www.linear .com/L TC3884 TA = 25°C, VIN = 12V, L = 0.33µH, DCR = 0.32mΩ, EXTVCC = 0V unless otherwise noted. TYPICAL PERFORMANCE CHARACTERISTICS Dynamic Current Sharing During a Load T ransient in a 4-Phase System Phase Current Matching in T wo Phase Systems Dynamic Current Sharing During a Load T ransient in a 4-Phase System INTV CC Line Regulation Current Limit During an Output Short Condition Current Sense Threshold vs Duty Cycle CH0 CH1 OUTPUT CURRENT (A) –0.1 1.9 3.9 6.0 8.0 10.0 12.1 14.1 16.2 18.2 20.2 PHASE CURRENT (A)

3884 G16

V IN (V) 4.0 4.3 4.6 4.9 5.2 5.5 5.8 INTV CC (V)

3884 G17

MFM_PWM_MODE[7][2] = 0,1 IOUT_OC_FAUL T_LIMIT= 32.5A DUTY CYCLE (%) 100 8.0 8.4 8.8 9.2 9.6 10.0 10.4 10.8 11.2 11.6 12.0 OVER CURRENT SENSE THRESHOLD (mV)

3884 G18

5µs/DIV

3884 G13

5µs/DIV

3884 G14

5µs/DIV VOUT GND IL 10A/DIV

3884 G15

OC_FAUL T LIMIT = 40A, IL_PEAK = 42A

3884feFor more information www.linear .com/L TC3884 TA = 25°C, VIN = 12V, L = 0.33µH, DCR = 0.32mΩ, EXTVCC = 0V unless otherwise noted. TYPICAL PERFORMANCE CHARACTERISTICS SHARE_CLK Frequency vs Input Voltage Quiescent Current vs Input Voltage Supply Current Measurement Error vs Supply Current V IN (V) 100 102 105 107 SHARE_CLK FREQUENCY (KHz)

3884 G19

VIN (V) 15.0 17.5 20.0 22.5 25.0 27.5 30.0 QUIESCENT CURRENT (mA)

3884 G20

R VIN = 2Ω SUPPL Y CURRENT (mA) 100 120 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 SUPPL Y CURRENT MEASUREMENT ERROR (%)

3884 G21

VOUT Overvoltage Threshold vs Temperature (Target 2V) VOUT vs Temperature VOUT Overvoltage Threshold vs Temperature (Target 4V) SHARE_CLK vs Temperature VOUT Overvoltage Threshold vs Temperature (Target 1V) TEMPERATURE (°C) –55 –10 125 1.2190 1.2193 1.2195 1.2198 1.2200 1.2203 1.2205 1.2208 1.2210 1.2213 1.2215 1.2218 1.2220 VREF (V)

3884 G22

TEMPERATURE (°C) –55 –10 125 0.995 0.996 0.997 0.998 0.999 1.000 1.001 1.002 1.003 1.004 1.005 VOUT (V)

3884 G23

TEMPERATURE (°C) –55 –10 125 0.985 0.990 0.995 1.000 1.005 1.010 1.015 OV THRESHOLD (V)

3884 G24

TEMPERATURE (°C) –55 –10 125 1.970 1.980 1.990 2.000 2.010 2.020 2.030 OV THRESHOLD (V)

3884 G25

TEMPERATURE (°C) –55 –10 125 3.94 3.96 3.98 4.00 4.02 4.04 4.06 OV THRESHOLD (V)

3884 G26

TEMPERATURE (°C) –55 –10 125 100 101 103 104 106 107 SHARE_CLK (KHz)

3884 G27

3884fe For more information www.linear .com/L TC3884 TYPICAL PERFORMANCE CHARACTERISTICS Underlock Voltage vs Temperature V OUT Command DNL VOUT Command INL VOUT Error vs VOUT IOUT Error vs IOUT Input Current Error vs Input Current RISING FALLING TEMPERATURE (°C) –55 –10 125 3.50 3.55 3.60 3.65 3.70 3.75 3.80 3.85 3.90 3.95 4.00 UNDERLOCK VOL TAGE (V)

3884 G28

VOUT (V) 0.5 1.5 2.5 3.5 4.5 5.5 –0.30 –0.22 –0.15 –0.07 0.00 0.08 0.15 0.23 0.30 DNL (LSB)

3884 G29

VOUT (V) 0.50 1.50 2.50 3.50 4.50 5.50 –1.00 –0.50 0.50 1.00 1.50 2.00 INL (LSB)

3884 G30

VOUT (V) 0.5 1.5 2.5 3.5 4.5 5.5 –0.30 –0.20 –0.10 0.00 0.10 0.20 0.30 0.40 V OUT MEASUREMENT ERROR (mV)

3884 G31

I OUT (A) 0.1 8.0 16.0 24.0 32.0 40.0 –10.00 –7.14 –4.29 –1.43 1.43 4.29 7.14 10.00 I OUT MEASUREMENT ERROR (mA)

3884 G32

R IINSNS = 5mΩ INPUT CURRENT(A) I INPUT MEASUREMENT ERROR (mA)

3884 G33

TA = 25°C, VIN = 12V, L = 0.33µH, DCR = 0.32mΩ, EXTVCC = 0V unless otherwise noted.

3884feFor more information www.linear .com/L TC3884 VSENSE0+/VSENSE1+ (Pin 1/Pin 32, Pin 2/Pin 33): Positive Output Voltage Sense Inputs. VSENSE0–/VSENSE1– (Pin 2/Pin 31, Pin 3/Pin 32): Negative Output Voltage Sense Inputs. I TH0/ITH1 (Pin 6/Pin 29, Pin 7/Pin 30): Current Control Threshold and Error Amplifier Compensation Nodes. Each associated channel’s current comparator tripping threshold increases with its ITH voltage. ITHR0/ITHR1 (Pin 5/Pin 30, Pin 6/Pin 31): Loop Compen- sation Nodes. ISENSE0+/ISENSE1+ (Pin 7/Pin 3, Pin 8/Pin 4): Current sense comparator positive inputs, normally connected to DCR sensing networks or current sensing resistors. ISENSE0–/ISENSE1– (Pin 8/Pin 4, Pin 9/Pin 5): Current sense comparator negative inputs, normally connected to outputs. SYNC (Pin 11, Pin 12): External Clock Synchronization Input and Open-Drain Output Pin. If an external clock is present at this pin, the switching frequency will be syn - chronized to the external clock. If clock master mode is enabled, this pin will pull low at the switching frequency with a 500ns pulse to ground. A resistor pull-up to 3.3V is required in the application if the LTC3884 is the master . SCL (Pin 12, Pin 13): Serial Bus Clock Input. Open-drain output can hold the output low if clock stretching is enabled. A pull-up resistor to 3.3V is required in the application. SDA (Pin 13, Pin 14): Serial Bus Data Input and Output. A pull-up resistor to 3.3V is required in the application. ALERT (Pin 14, Pin 15): Open-Drain Digital Output. Con- nect the SMBALERT signal to this pin. A pull-up resistor to 3.3V is required in the application. F AUL T0/FAUL T1 (Pin 15/Pin 16, Pin 16/Pin 17): Digital Programmable FAUL T Inputs and Outputs. Open-drain out- put. A pull-up resistor to 3.3V is required in the application. RUN0/RUN1 (Pin 17/Pin 18, Pin 18/Pin 19): Enable Run Input and Output. Logic high on these pins enables the controller . An open-drain output holds the pin low until the LTC3884 is out of reset. This pin should be driven by an open-drain digital output. A pull-up resistor to 3.3V is required in the application. PIN FUNCTIONS ASEL0/ASEL1 (Pin 19/Pin 20, Pin 20/Pin 21): Serial Bus Address Select Inputs. Connect optional ±1% resistor dividers between V DD25 and SGND to these pins to select the serial bus interface address. Refer to the Applications Information section for more details. Minimize capacitance when the pin is open to assure accurate detection of the pin state. V OUT0_CFG/VOUT1_CFG (Pin 21/Pin 22, Pin 22/Pin 23): Output Voltage Select Pins. Connect optional ±1% resistor divider between VDD25 VOUT_CFG and SGND in order to select output voltage for each channel. If the pin is left open, the IC will use the value programmed in EEPROM. Refer to the Applications Information section for more details. Minimize capacitance when the pin is open to assure accurate detection of the pin state. FREQ_CFG (Pin 23, Pin 24): Frequency Select Pin. Con- nect optional ±1% resistor divider between V DD25 and FREQ_CFG SGND in order to select PWM switching fre - quency. Refer to the Applications Information section for more details. Minimize capacitance when the pin is open to assure accurate detection of the pin state. PHASE_CFG (Pin 24, Pin 25) : Phase Select Pin. Connect ±1% resistor divider between V DD25 PHASE_CFG SGND to this pin to configure the phase of each PWM channel relative to SYNC. If the pin is left open, the IC will use the value programmed in the NVM. Refer to the Applications Information section for more details. Minimize capacitance when the pin is open to assure accurate detection of the pin state. V DD25 (Pin 25, Pin 26): Internally Generated 2.5V Power Supply Output Pin. Bypass this pin to SGND with a low ESR 1μF capacitor . Do not load this pin with external cur- rent except for the ±1% resistor dividers required for the configuration pins. WP (Pin 26, Pin 27) : Write Protect Pin Active High. An internal 10μA current source pulls the pin to VDD33. If WP is high, the PMBus writes are restricted. SHARE_CLK (Pin 27, Pin 28): Share Clock, Bidirectional Open-Drain Clock Sharing Pin. Nominally 100kHz. Used to synchronize the timing between multiple LTC3884s. Tie all SHARE_CLK pins together . All LTC3884s will synchronize to the fastest clock. A pull-up resistor to 3.3V is required. (UK, RHE)

3884fe For more information www.linear .com/L TC3884 PIN FUNCTIONS VDD33 (Pin 28, Pin 29): Internally Generated 3.3V Power Supply Output Pin. Bypass this pin to SGND with a low ESR 1μF capacitor . Do not load this pin with external cur- rent except for the pull-up resistors required for FAUL Tn, SCLK, SYNC and possibly RUNn , SDA and SCL, PGOODn. INTVCC (Pin 38, Pin 39): Internal Regulator 5.5V Output. The control circuits are powered from this voltage. De - couple this pin to PGND with a minimum of 4.7μF low ESR tantalum or ceramic capacitor . This regulator is mainly designed for internal cir cuits, not to be used as supply for the other ICs. EXTVCC (Pin 40, Pin 41): External Power Input to an Internal Switch Connected to INTVCC. This switch closes and supplies the IC power , bypassing the internal regulator whenever EXTVCC is higher than 4.7V and V IN is higher than 7V. EXTVCC also powers up V DD33 when EXTVCC is higher than 4.7V and INTVCC is lower than 3.8V. Do not exceed 6V on this pin. Decouple this pin to PGND with a minimum of 4.7μF low ESR tantalum or ceramic capacitor . If the EXTV CC pin is not used to power INTVCC, the EXTVCC pin must be tied GND. The EXTVCC pin may be connected to a higher voltage than the VIN pin. VIN (Pin 39, Pin 40): Main Input Supply. Decouple this pin to PGND with a capacitor (1µF to 10µF). For applica- tions where the main input power is 6V or below, tie the V IN and INTVCC pins together . If the input current sense amplifier is not used, this pin must be shorted to the IIN+ and IIN– pins. BG0/BG1 (LTC3884) (Pin 42/Pin 37, Pin 43/Pin 38): Bottom Gate Driver Outputs. These pins drive the gates of the bottom N-channel MOSFETs between PGND and INTV CC. BOOST0/BOOST1 (LTC3884) (Pin 43/Pin 36, Pin 44/Pin 37): Boosted Floating Driver Supplies. The (+) terminal of the booststrap capacitors connect to these pins. These pins swing from a diode voltage drop below INTV CC up to VIN + INTVCC. TG0/TG1 (LTC3884) (Pin 44/Pin 35, Pin 45/Pin 36): Top Gate Driver Outputs. These are the outputs of the floating drivers with a voltage swing equal to INTV CC superimposed on the switch node voltages. SW0/SW1 (LTC3884) (Pin 45/Pin 34, Pin 46/Pin 35): Switch Node Connections to Inductors. Voltage swings at the pins are from a diode (internal body diode) voltage drop below ground to V IN. TSNS0/TSNS1 (Pin 10/Pin 9, Pin 11/Pin 10): External Diode Temperature Sense. Connect to the anode of a diode connected PNP transistor and star-connect the cathode to GND (Pin 49) in order to sense remote temperature. A bypass capacitor between the anode and cathode must be located in close proximity to the transistor . If external temperature sense elements are not installed, short pin to ground and set the UT_FAULT_LIMIT to –275°C and the UT_FAULT_RESPONSE to ignore. I IN+ (Pin 46, Pin 47): Positive Current Sense Comparator Input. If the input current sense amplifier is not used, this pin must be shorted to the IIN– and VIN pins. IIN– (Pin 47, Pin 48): Negative Current Sense Comparator Input. If the input current sense amplifier is not used, this pin must be shorted to the I IN+ and VIN pins. PGOOD0/PGOOD1 (Pin 48/Pin 33, Pin 1/ Pin 34): Power Good Indicator Outputs. Open-drain logic output that is pulled to ground when the output exceeds the UV and OV regulation window. The output is deglitched by an internal 60µs filter . A pull-up resistor to 3.3V is required in the application. PGND (Pin 41/Pin 42): Power Ground. V CC0/VCC1 (LTC3884-1) (Pin 44/Pin 37): Supply to PWM. Connected to INTVCC or V DD33. Bypass to PGND with a 1µF capacitor . PWM0/PWM1 (LTC3884-1) (Pin 45/Pin 36): PWM Outputs. These are the three-state control outputs with a voltage swing of GND to V CC. SGND (Exposed Pad Pin 49): Internal Signal Ground. All small-signal and compensation components should connect to this ground, which in turn connects to PGND at single point. (UK, RHE)

3884 F02

Figure 2. Block Diagram, One of T wo Channels (Channel 0 Shown)

3884fe For more information www.linear .com/L TC3884 OPERATION OVERVIEW The LTC3884-1 has all the features that LTC3884 has, except the LTC3884 includes MOSFET gate drivers while the LTC3884-1 does not. LTC3884 is used in applications where the gate driver is required while the LTC3884-1 is used in applications where the gate driver is external, for example a DrMOS power stage. In the remainder of this document, all the descriptions, features, operation and applications of LTC3884 apply to LTC3884-1, unless otherwise specified. The LTC3884 is a dual channel/dual phase, constant- frequency, analog current mode controller for DC/DC step- down applications with a digital interface. The LTC3884 digital interface is compatible with PMBus which supports bus speeds of up to 400kHz. A Typical Application circuit is shown on the first page of this data sheet. LTC3884 is very similar to LTC3880, but has numerous new features as shown in bold: Major features include: n Sub-Milliohm DCR Sensing n Dedicated Power Good Indicators n Direct Input and Chip Current Sensing n Programmable Loop Compensation Parameters n TINIT Start-Up Time: 35ms n PWM Synchronization Circuit, (See Frequency and Phasing Section for Details) n MFR_ADC_CONTROL for Fast ADC Sampling of One Parameter (as Fast as 8ms) (See PMBus Command for Details) n Fully Differential Output Sensing for Both Channels; VOUT0/1 Both Programmable Up to 5.5V n Power-Up and Program EEPROM with EXTVCC n Input Voltage Up to 38V n Dual Diode Temperature Sensing n SYNC Contention Circuit (Refer to Frequency and Phase Section for Details) n Fault Logging n Programmable Output Voltage n Programmable Input Voltage On and Off Threshold V oltage n Programmable Current Limit n Programmable Switching Frequency n Programmable OV and UV Threshold voltage n Programmable ON and Off Delay Times n Programmable Output Rise/Fall Times n Phase-Locked Loop for Synchronous PolyPhase Operation (2, 3, 4 or 6 Phases). n Integrated Gate Drivers (LTC3884) n Nonvolatile Configuration Memory with ECC n Optional External Configuration Resistors for Key Operating Parameters n Optional Timebase Interconnect for Synchronization Between Multiple Controllers n WP Pin to Protect Internal Configuration n Stand Alone Operation After User Factory Configuration n PMBus, Version 1.2, 400kHz Compliant Interface The PMBus inter face provides access to important power management data during system operation including: n Internal Controller Temperature n External System Temperature via Optional Diode Sense Elements n Average Output Current n Average Output Voltage n Average Input Voltage n Average Input Current n Average Chip Input Current from VIN n Configurable, Latched and Unlatched Individual Fault and Warning Status Individual channels are accessed through the PMBus using the PAGE command, i.e., PAGE 0 or 1.

3884feFor more information www.linear .com/L TC3884 OPERATION Fault reporting and shutdown behavior are fully con- figurable. T wo individual FAUL T0, FAUL T1 outputs are provided, both of which can be masked independently . Three dedicated pins for ALERT, PGOOD0/1 functions are provided. The shutdown operation also allows all faults to be individually masked and can be operated in either unlatched (hiccup) or latched modes. Individual status commands enable fault reporting over the serial bus to identify the specific fault event. Fault or warning detection includes the following: n Output Undervoltage/Over voltage n Input Undervoltage/Over voltage n Input and Output Overcurrent n Internal Overtemperature n External Overtemperature n Communication, Memory or Logic (CML) Fault MAIN CONTROL LOOP The LTC3884 is a constant-frequency, current mode step- down controller containing two channels operating with user-defined relative phasing. During normal operation the top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator , I CMP, resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin which is the output of each er- ror amplifier , EA. The EA negative terminal is equal to the differential voltage between V SENSE+ and VSENSE– divided by 5.5 (or 2.75 if MFR_PWM_MODE[1] = 1). The positive terminal of the EA is connected to the output of a 12-bit DAC with values ranging from 0V to 1.024V. The output voltage, through feedback of the EA, will be regulated to 5.5 times the DAC output (or 2.75 times). The DAC value is calculated by the part to synthesize the user's desired output voltage. The output voltage is programmed by the user either with the resistor configuration pins detailed in Table 3 or by the PMBus V OUT command (either from EEPROM or by PMBus command). Refer to the PMBus command section of the data sheet or the PMBus specifica- tion for more details. The PMBus VOUT_COMMAND can be executed at any time while the device is running. This command will typically have a latency less than 10ms. The user is encouraged to refer to the PMBus Power System Management Protocol Specification to understand how to program the LTC3884. http://www .pmbus.org/specs.html Continuing the basic operation description, the current- mode controller will turn off the top gate when the peak current is reached. If the load current increases, sense voltage will slightly droop with respect to the DAC reference. This causes the I TH voltage to increase until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on. In continuous conduction mode, the bottom MOSFET stays on until the end of the switching cycle. EEPROM The LTC3884 contains internal EEPROM (nonvolatile memory) with Error Correction Coding (ECC) to store user configuration settings and fault log information. EEPROM endurance retention and mass write operation time are specified in the Electrical Characteristics and Absolute Maximum Ratings sections. Write operations above T J = 85°C are possible although the Electrical Characteristics are not guaranteed and the EEPROM will be degraded. Read operations performed at temperatures between –40°C and 125°C will not degrade the EEPROM. Writing to the EEPROM above 85°C will result in a degradation of retention characteristics. The fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log EEPROM locations. If occasional writes to these registers occur above 85°C, the slight degradation in the data retention characteristics of the fault log will not take away from the usefulness of the function. It is recommended that the EEPROM not be written when the die temperature is greater than 85°C. If the die temperature exceeds 130°C, the LTC3884 will disable all EEPROM write operations. All EEPROM write operations will be re-enabled when the die temperature drops below 125°C. (The controller will also disable all the switching when the die temperature exceeds the internal overtem - perature fault limit 160°C with a 10°C hysteresis)

3884fe For more information www.linear .com/L TC3884 OPERATION The degradation in EEPROM retention for temperatures >125°C can be approximated by calculating the dimen - sionless acceleration factor using the following equation: AF = e Ea k ⎝⎜ ⎞ ⎠⎟• 1 TUSE+273– 1 TSTRESS+273 where: AF = acceleration factor Ea = activation energy = 1.4eV K = 8.617 • 10 –5 eV/°K TUSE = 125°C specified junction temperature TSTRESS = actual junction temperature in °C Example: Calculate the effect on retention when operating at a junction temperature of 135°C for 10 hours. TSTRESS = 130°C TUSE = 125°C, The equivalent operating time at 125°C = 16.6 hours. Thus the overall retention of the EEPROM was degraded by 16.6 hours as a result of operating at a junction temperature of 130°C for 10 hours. The effect of the overstress is negligible when compared to the overall EEPROM retention rating of 87,600 hours at a maximum junction temperature of 125°C. The integrity of the entire onboard EEPROM is checked with a CRC calculation each time its data is to be read, such as after a power-on reset or execution of a RESTORE_USER_ ALL command. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC command is set, and the ALERT and RUN pins pulled low (PWM channels off). At that point the device will only respond at special address 0x7C, which is activated only after an invalid CRC has been detected. The chip will also respond at the global addresses 0x5A and 0x5B, but use of these addresses when attempting to recover from a CRC issue is not recommended. All power supply rails associated with either PWM channel of a device reporting an invalid CRC should remain disabled until the issue is resolved. See the application Information section or con- tact the factory for details on efficient in-system EEPROM programming, including bulk EEPROM Programming, which the LTC3884 also supports. POWER-UP AND INITIALIZA TION The LTC3884 is designed to provide standalone supply sequencing and controlled turn-on and turn-off operation. It operates from a single input supply (4.5V to 38V) while three on-chip linear regulators generate internal 2.5V, 3.3V and 5.5V. If V IN does not exceed 6V, and the EXTVCC pin is not driven by an external supply, the INTV CC and V IN pins must be tied together . The controller configuration is initialized by an internal threshold based UVLO where V IN must be approximately 4V and the 5.5V, 3.3V and 2.5V linear regulators must be within approximately 20% of the regulated values. In addition to power supply,a PMBus RESTORE_USER_ALL or MFR_RESET command can initialize the part too. The EXTV CC pin is driven by an external regulator to improve efficiency of the circuit and minimize power loss on the LTC3884 when VIN is high. The EXTVCC pin must exceed approximately 4.7V, and VIN must exceed approximately 7V before the INTVCC LDO operates from the EXTVCC pin. To minimize application power , the EXTVCC pin can be supplied by a switching regulator . During initialization, the external configuration resistors are identified and/or contents of the NVM are read into the controller’s commands and the BGn, TGn pins are held low for LTC3884. The RUNn and FAUL Tn and PGOODn are held low for the LTC3884, or PWM pins are in three-state for the LTC3884-1. The LTC3884 will use the contents of Table 3 to Table 6 to determine the resistor defined parameters. See the Resistor Configuration section for more details. The resistor configuration pins only control some of the preset values of the controller . The remaining values are programmed in NVM either at the factory or by the user . If the configuration resistors are not inserted or if the ignore RCONFIG bit is asserted (bit 6 of the MFR_CONFIG_ALL configuration command), the LTC3884 will use only the contents of NVM to determine the DC/DC characteristics. The ASEL0/1 value read at power-up or reset is always respected unless the pin is open. The ASEL0/1 will set the MSB and the LSB from the detected threshold. See the Applications Information section for more details.

3884feFor more information www.linear .com/L TC3884 OPERATION After the part has initialized, an additional comparator moni- tors VIN. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After VIN is initially applied, the part will typically require 35ms to initialize and begin the TON_DELAY timer . The readback of voltages and currents may require an additional 0ms to 90ms. SOFT-START The method of start-up sequencing described below is time based. The part must enter the run state prior to soft-start. The run pins are released by the LTC3884 after the part is initialized and V IN is greater than the VIN_ON threshold. If multiple LTC3884s are used in an application, they all hold their respective run pins low until all devices are initialized and V IN exceeds the VIN_ON threshold for every device. The SHARE_CLK pin assures all the devices connected to the signal use the same time base. The SHARE_CLK pin is held low until the part has been initialized after V IN is ap- plied. The LTC3884 can be set to turn-off (or remain off) if SHARE_CLK is low (set bit 2 of MFR_CHAN_CONFIG to 1). This allows the user to assure synchronization across numerous ADI ICs even if the RUN pins cannot be con - nected together due to board constraints. In general, if the user cares about synchronization between chips it is best not only to connect all the respective RUN pins together but also to connect all the respective SHARE_CLK pins together and pull up to V DD33 with a 10k resistor . This as- sures all chips begin sequencing at the same time and use the same time base. After the RUN pins release and prior to entering a constant output voltage regulation state, the LTC3884 performs a monotonic initial ramp or “soft-start”. Soft-start is performed by actively regulating the load voltage while digitally ramping the target voltage from 0V to the commanded voltage set- point. Once the LTC3884 is commanded to turn on (after power up and initialization), the controller waits for the user specified turn-on delay (TON_DELAY) prior to initiat- ing this output voltage ramp. The rise time of the voltage ramp can be programmed using the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting the value of TON_RISE to any value less than 0.25ms. The LTC3884 PWM always uses discontinuous mode during the TON_RISE operation. In discontinuous mode, the bottom gate is turned off as soon as reverse current is detected in the inductor . This will allow the regulator to start up into a pre-biased load. When the TON_MAX_FAULT_LIMIT is reached, the part transitions to continuous mode, if so programmed. If TON_MAX_FAULT_LIMIT is set to zero, there is no time limit and the part transitions to the desired conduction mode after TON_RISE completes and V OUT has exceeded the VOUT_UV_FAULT_LIMIT and IOUT_OC is not present. However setting TON_MAX_FAULT_LIMIT to a value of 0 is not recommended. TIME-BASED SEQUENCING The default mode for sequencing the outputs on and off is time based. Each output is enabled after waiting TON_DELAY amount of time following either a RUN pin going high, a PMBus command to turn on or the V IN rising above a preprogrammed voltage. Off sequencing is handled in a similar way. To assure proper sequencing, make sure all ICs connect the SHARE_CLK pin together and RUN pins together . If the RUN pins cannot be connected together for some reasons, set bit 2 of MFR_CHAN_ CONFIG to 1. This bit requires the SHARE_CLK pin to be clocking before the power supply output can start. When the RUN pin is pulled low, the LTC3884 will hold the pin low for the MFR_ RESTART_DELAY. The minimum MFR_RESTART_ DELAY is TOFF_DELAY + TOFF_FALL + 136ms. This delay assures proper sequencing of all rails. The LTC3884 calculates this delay internally and will not process a shorter delay. However , a longer commanded MFR_RESTART_DELAY will be used by the part. The maximum allowed value is 65.52 seconds. VOL TAGE-BASED SEQUENCING The sequence can also be voltage based. As shown in Figure 3, The PGOODn pin is asserted when the UV threshold is exceeded for each output. It is possible to feed the PGOOD pin from one LTC3884 into the RUN pin of the next LTC3884 in the sequence, especially across multiple LTC3884s. The PGOODn has a 60μs filter . If the VOUT voltage bounces around the UV threshold for a long period of time it is possible for the PGOODn output to toggle more than once. To minimize this problem, set the TON_RISE time under 100ms.

capacitance and load current, instead of TOFF_FALL. as toggling RUNn or commanding the part OFF then ON. zero, preventing it from reversing and going negative. light loads is lower than in discontinuous mode operation. the part in discontinuous conduction mode.

3884 F03

Figure 3. Event (Voltage) Based Sequencing

3884feFor more information www.linear .com/L TC3884 OPERATION SWITCHING FREQUENCY AND PHASE The switching frequency of the PWM can be established with an internal oscillator or an external time base. The internal phase-locked loop (PLL) synchronizes PWM control to this timing reference with proper phase relation, whether the clock is provided internally or externally. The device can also be configured to provide the master clock to other ICs through PMBus command, NVM setting, or external configuration resistors as outlined in Table 4. As clock master , the LTC3884 will drive its open-drain SYNC pin at the selected rate with a pulse width of 500ns. An external pull-up resistor between SYNC and V DD33 is required in this case. Only one device connected to SYNC should be designated to drive the pin. But if multiple LTC3884s programmed as clock masters are wired to the same SYNC line with a pull- up resistor , just one of the devices is automatically elected to provide clocking, and the others disable their SYNC outputs. The LTC3884 will automatically revert to an external SYNC input, disabling its own SYNC, as long as the external SYNC frequency is greater than 80% of the programmed SYNC frequency. The external SYNC input shall have a duty cycle between 20% and 80%. Whether configured to drive SYNC or not, the LTC3884 can continue PWM operation using its own internal oscillator if an external clock signal is subsequently lost. The device can also be programmed to always require an external oscillator for PWM operation by setting bit 4 of MFR_CONFIG_ALL. The status of the SYNC driver circuit is indicated by bit 10 of MFR_PADS. The MFR_PWM_CONFIG command can be used to configure the phase of each channel. Desired phase can also be set from EEPROM or external configuration resistors as outlined in Table 5. Designated phase is the relationship between the falling edge of SYNC and the internal clock edge that sets the PWM latch to turn on the top power switch. Additional small propagation delays to the PWM control pins will also apply. Both channels must be off before the FREQUENCY_SWITCH and MFR_PWM_CONFIG commands can be written to the LTC3884. The phase relationships and frequency are independent of each other, providing numerous application options. Multiple LTC3884 ICs can be synchronized to realize a PolyPhase array. In this case the phases should be separated by 360/n degrees, where n is the number of phases driving the output voltage rail. PWM LOOP COMPENSATION The internal PWM loop compensation resistors R ITHn of the LTC3884 can be adjusted using bit[4:0] of the MFR_PWM_COMP command. The transconductance of the LTC3884 PWM error amplifier can be adjusted using bit[7:5] of the MFR_PWM_COMP command. These two loop compensation parameters can be programmed when device is in operation. Refer to the Programmable Loop Compensation subsection in the Applications Information section for further details. OUTPUT VOL TAGE SENSING Both channels in LTC3884 have differential amplifiers, which allow the remote sensing of the load voltage be - tween V SENSEn+ and VSENSEn– pins. The telemetry ADC is also fully differential and makes measurements between V SENSEn+ and VSENSEn– pins respectively. The maximum allowed sense voltages for both channels is 5.5V. INTVCC/EXTVCC POWER Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTV CC pin. When the EXTVCC pin is shorted to GND or tied to a voltage less than 4.7V, an internal 5.5V linear regulator supplies INTVCC power from VIN. If EXTVCC is taken above approxi- mately 4.7V and VIN is higher than 7.0V, the 5.5V regulator is turned off and an internal switch is turned on, connecting EXTV CC to INTVCC. Using the EXTVCC allows the INTVCC power to be derived from a high efficiency external source such as a switching regulator output. EXTV CC can provide power to the internal 3.3V linear regulator even when VIN is not present, which allows the LTC3884 to be initialized and programmed even without main power being applied.

thus represents the current flowing through the inductor . with the MFR_PWM_MODE[2] , MFR_PWM_MODE[7].

3884 F04

Figure 4. Load Sharing Connections for 3-Phase Operation

ing current value is returned by the READ_IOUT command. ply voltage and the drain of the top N-channel MOSFET . The IIN+ and IIN– pins are connected to the sense resistor . is returned by the READ_IIN command. value is returned by the MFR_READ_ICHIP command. section for further details. of the external clock and disable its output. diode-connected PNP transistor such as the MMBT3906. Figure 5. Temperature Sense Circuit

3884 F05

method, but may function better in a noisy application.

3884fe For more information www.linear .com/L TC3884 OPERATION configurations. The calculated temperature is returned by the PMBus READ_TEMPERATURE_1 command. Refer to the Applications Information section for details on proper layout of external temperature sense elements and PMBus commands that can be used to improve the accuracy of calculated temperatures. The READ_TEMPERATURE_2 command returns the internal junction temperature of the LTC3884 using an on-chip diode with a ∆V BE measure- ment and calculation. The slope of the external temperature sensor can be modified with the temperature slope coefficient stored in MFR_TEMP_1_GAIN. T ypical PNPs require temperature slope adjustments slightly less than 1. The MMBT3906 has a recommended value in this command of approximately MFR_TEMP_1_GAIN = 0.991 based on the ideality factor of 1.01. Simply invert the ideality factor to calculate the MFR_TEMP_1_GAIN. Different manufacturers and differ- ent lots may have different ideality factors. Consult with the manufacturer to set this value. The offset of the external temperature sense can be adjusted by MFR_TEMP_1_OFF- SET . A value of 0 in this register sets the temperature offset to –273.15°C. If the PNP cannot be placed in direct contact with the inductor , the slope or offset can be increased to account for temperature mismatches. If the user is adjusting the slope, the intercept point is at absolute zero, –273.15°C, so small adjustments in slope can change the apparent mea- sured temperature significantly. Another way to artificially increase the slope of the temperature term is to increase the MFR_IOUT_CAL_GAIN_TC term. This will modify the temperature slope with respect to room temperature. RCONFIG (RESISTOR CONFIGURATION) PINS There are six input pins utilizing 1% resistor dividers between VDD25 and SGND to select key operating param- eters. The pins are ASEL0, ASEL1, FREQ_CFG, VOUT0_CFG, VOUT1_CFG, PHASE_CFG. If pins are floated, the value stored in the corresponding NVM command is used. If bit 6 of the MFR_CONFIG_ALL configuration command is asserted in NVM, the resistor inputs are ignored upon power-up except for ASEL0 and ASEL1 which are always respected. The resistor configuration pins are only measured during a power-up reset or after a MFR_RESET or after a RESTORE_USER_ALL command is executed. The V OUTn_CFG pin settings are described in Table 3. These pins select the output voltages for the LTC3884’s analog PWM controllers. If the pin is open, the VOUT_COMMAND command is loaded from NVM to determine the output voltage. The default setting is to have the switcher off unless the voltage configuration pins are installed. The following parameters are set as a percentage of the output voltage if the RCONFIG pins are used to determine the output voltage: The FREQ_CFG pin settings are described in Table 4. This pin selects the switching frequency. The phase relationships between the two channels and SYNC pin are determined by the PHASE_CFG pin described in Table 5. To synchronize to an external clock, the part should be put into external clock mode (SYNC output disabled but frequency set to the nominal value). If no external clock is supplied, the part will clock at the programmed frequency. If the application is multiphase and the SYNC signal between chips is lost, the parts will not operate at the designed phase even if they are programmed and trimmed to the same frequency. This may increase the ripple voltage on the output, pos- sibly produce undesirable operation. If the external SYNC signal is being generated internally and external SYNC is not selected, bit 10 of MFR_PADS will be asserted. If no frequency is selected and the external SYNC frequency is not present, a PLL_FAULT will occur . If the user does not wish to see the ALERT from a PLL_FAULT even if there is not a valid synchronization signal at power-up, the ALERT mask for PLL_FAULT must be written. See the description on SMBALERT_MASK for more details. If the SYNC pin is connected between multiple ICs only one of the ICs should have the SYNC pin enabled, and all other ICs should be configured to have the SYNC pin disabled.

3884feFor more information www.linear .com/L TC3884 OPERATION The ASEL0,1 pin settings are described in Table 6. ASEL1 selects the top 3 bits of the slave address for the LTC3884. ASEL0 selects the bottom 4 bits of the slave address for the LTC3884. If ASEL1 is floating, the 3 most significant bits are retrieved from the NVM MFR_ADDRESS com - mand. If ASEL0 is floating, the 4 LSB bits stored in NVM MFR_ADDRESS command are used to determine the 4 LSB bits of the slave address. For more detail, refer to Table 6. Note: Per the PMBus specification, pin programmed parameters can be overridden by commands from the digital interface with the exception of ASEL which is always honored. Do not set any part address to 0x5A or 0x5B because these are global addresses and all parts will respond to them. FAUL T DETECTION AND HANDLING A variety of fault and warning reporting and handling mechanisms are available. Fault and warning detection capabilities include: n Input OV FAUL T Protection and UV Warning n Average Input OC Warn n Output OV/UV Fault and Warn Protection n Output OC Fault and Warn Protection n Internal and External Overtemperature Fault and Warn Protection n External Undertemperature Fault and Warn Protection n CML Fault (Communication, Memory or Logic) n External Fault Detection via the Bidirectional F AUL Tn Pins. In addition, the LTC3884 can map any combination of fault indicators to their respective FAUL Tn pin using the propagate FAUL Tn response commands, MFR_FAULT_ PROPAGATE. Typical usage of a FAUL Tn pin is as a driver for an external crowbar device, overtemperature alert, over- voltage alert or as an interrupt to cause a microcontroller to poll the fault commands. Alternatively, the FAUL Tn pins can be used as inputs to detect external faults downstream of the controller that require an immediate response. Any fault or warning event will always cause the ALERT pin to assert low unless the fault or warning is masked by the SMBALERT_MASK. The pin will remain asserted low until the CLEAR_FAULTS command is issued, the fault bit is written to a 1 or bias power is cycled or a MFR_RESET command is issued, or the RUN pins are toggled OFF/ON or the part is commanded OFF/ON via PMBus or an ARA command operation is performed. The MFR_FAULT_ PROPAGATE command determines if the FAUL T pins are pulled low when a fault is detected. Output and input fault event handling is controlled by the corresponding fault response byte as specified in Tables 7 to 12. Shutdown recovery from these types of faults can either be autonomous or latched. For autonomous recov- ery, the faults are not latched, so if the fault conditions not present after the retr y inter val has elapsed, a new soft-start is attempted. If the fault persists, the controller will continue to retry. The retry interval is specified by the MFR_RETRY_DELAY command and prevents damage to the regulator components by repetitive power cycling, assuming the fault condition itself is not immediately destructive. The MFR_RETRY_DELAY must be greater than 120ms. It can not exceed 83.88 seconds. Status Registers and ALERT Masking Figure 6 summarizes the internal LTC3884 status reg - isters accessible by PMBus command. These contain indication of various faults, warnings and other important operating conditions. As shown, the STATUS_BYTE and STATUS_WORD commands also summarize contents of other status registers. Refer to PMBus Command Details for specific information. NONE OF THE ABOVE in STATUS_BYTE indicates that one or more of the bits in the most-significant nibble of STATUS_WORD are also set. In general, any asserted bit in a STATUS_x register also pulls the ALERT pin low. Once set, ALERT will remain low until one of the following occurs. n A CLEAR_FAULTS or MFR_RESET Command Is Issued n The Related Status Bit Is Written to a One n The Faulted Channel Is Properly Commanded Off and Back On

3884 F06

Figure 6. LTC3884 Status Register Summary

3884feFor more information www.linear .com/L TC3884 OPERATION n The LTC3884 Successfully T ransmits Its Address During a PMBus ARA n Bias Power Is Cycled With some exceptions, the SMBALERT_MASK command can be used to prevent the LTC3884 from asserting ALERT for bits in these registers on a bit-by-bit basis. These mask settings are promoted to STATUS_WORD and STATUS_BYTE in the same fashion as the status bits themselves. For example, if ALERT is masked for all bits in Channel 0 STATUS_VOUT, then ALERT is effectively masked for the VOUT bit in STATUS_WORD for PAGE 0. The BUSY bit in STATUS_BYTE also asserts ALERT low and cannot be masked. This bit can be set as a result of various internal interactions with PMBus communication. This fault occurs when a command is received that cannot be safely executed with one or both channels enabled. As discussed in Application Information, BUSY faults can be avoided by polling MFR_COMMON before executing some commands. If masked faults occur immediately after power up, ALERT may still be pulled low because there has not been time to retrieve all of the programmed masking information from EEPROM. Status information contained in MFR_COMMON and MFR_PADS can be used to further debug or clarify the contents of STATUS_BYTE or STATUS_WORD as shown, but the contents of these registers do not affect the state of the ALERT pin and may not directly influence bits in STATUS_BYTE or STATUS_WORD. Mapping Faults to FAUL T Pins Channel-to-channel fault (including channels from multiple LTC3884s) dependencies can be created by connecting FAUL Tn pins together . In the event of an internal fault, one or more of the channels is configured to pull the bussed FAUL Tn pins low. The other channels are then configured to shut down when the FAUL Tn pins are pulled low. For autonomous group retry, the faulted channel is config - ured to let go of the FAUL Tn pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. If the fault response is LATCH_OFF, the FAUL Tn pin remains asserted low until either the RUN pin is toggled OFF/ON or the part is commanded OFF/ON. The toggling of the RUN either by the pin or OFF/ON command will clear faults associ - ated with the channel. If it is desired to have all faults cleared when either RUN pin is toggled or , set bit 0 of MFR_CONFIG_ALL to a 1. The status of all faults and warnings is summarized in the STATUS_WORD and STATUS_BYTE commands. Additional fault detection and handling capabilities are: Power Good Pins The PGOODn pins of the LTC3884 are connected to the open drains of internal MOSFETs. The MOSFETs turn on and pull the PGOODn pins low when the channel output voltage is not within the channel’s UV and OV voltage thresh- olds. During TON_DELAY and TON_RISE sequencing, the PGOODn pin is held low. The PGOODn pin is also pulled low when the respective RUNn pin is low. The PGOODn pin response is deglitched by an internal 60μs digital filter . The PGOODn pin and PGOOD status may be different at times due to communication latency of up to 10µs. CRC Protection and ECC The LTC3884 contains internal EEPROM with error correc- tion coding (ECC) to store user configuration settings and fault login formation. EEPROM endurance and retention for user space and fault log pages are specified in the Absolute Maximum Ratings and Electrical Characteristics tables. The integrity of the NVM memor y is checked after a power on reset. A CRC error will prevent the controller from leav- ing the inactive state. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT pin will be pulled low. NVM repair can be attempted by writing the desired configura- tion to the controller and executing a STORE_USER_ALL command followed by a CLEAR_FAULTS command. The LTC3884 manufacturing section of the NVM is mir - rored. If both copies are corrupted, the “NVM CRC Fault” in the STATUS_MFR_SPECIFIC command is set. If this bit remains set after being cleared by issuing a CLEAR_FAULTS or writing a 1 to this bit, an irrecoverable internal fault has

3884fe For more information www.linear .com/L TC3884 OPERATION occurred. The user is cautioned to disable both output power supply rails associated with this specific part. There are no provisions for field repair of NVM faults in the manufacturing section. SERIAL INTERFACE The LTC3884 serial interface is a PMBus compliant slave device and can operate at any frequency between 10kHz and 400kHz. The address is configurable using either the NVM or an external resistor divider . In addition the LTC3884 always responds to the global broadcast address of 0x5A (7 bit) or 0x5B (7 bit). The serial interface supports the following protocols de- fined in the PMBus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte, 6) read word and 7) read block. 8) write block. All read operations will return a valid PEC if the PMBus master requests it. If the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL command, the PMBus write operations will not be acted upon until a valid PEC has been received by the LTC3884. Communication Protection PEC write errors (if PEC_REQUIRED is active), attempts to access unsupported commands, or writing invalid data to supported commands will result in a CML fault. The CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the appropriate bit is set in the STATUS_CML command, and the ALERT pin is pulled low. DEVICE ADDRESSING The LTC3884 offers five different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ARA). Global addressing provides a means of the PMBus master to address all LTC3884 devices on the bus. The LTC3884 global address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and cannot be disabled. Commands sent to the global address act the same as if PAGE is set to a value of 0xFF . Com - mands sent are written to both channels simultaneously. Global command 0x 5B (7 bit) or 0xB6 (8 bit) is paged and allows channel specific command of all LTC3884 devices on the bus. Other ADI device types may respond at one or both of these global addresses. Reading from global addresses is strongly discouraged. Device addressing provides the standard means of the PMBus master communicating with a single instance of an LTC3884. The value of the device address is set by a combination of the ASEL0 and ASEL1 configuration pins and the MFR_ ADDRESS command. When this addressing means is used, the PAGE command determines the channel being acted upon. Device addressing can be disabled by writing a value of 0x80 to the MFR_ADDRESS. Rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (PolyPhase). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_ ADDRESS command, allowing for any logical grouping of channels that might be required for reliable system control. Reading from rail addresses is also strongly discouraged. All four means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. Communication to LTC3884 devices at global and rail ad- dresses should be limited to command write operations. RESPONSES TO VOUT, IIN and IOUT FAUL TS VOUT OV and UV conditions are monitored by comparators. The OV and UV limits are set in three ways. n As a Percentage of the V OUT if Using the Resistor Configuration Pins n In NVM if Either Programmed at the Factory or Through the GUI n By PMBus Command The IIN and IOUT overcurrent monitors are performed by ADC readings and calculations. Thus these values are based on average currents and can have a time latency of up to t CONVERT. The IOUT calculation accounts for the DCR or sense resistor and their temperature coefficient. The input current is equal to the voltage measured across the R IINSNS resistor divided by the resistors value as set with the MFR_RVIN command. If this calculated input current exceeds the IN_OC_WARN_LIMIT the ALERT pin

3884feFor more information www.linear .com/L TC3884 OPERATION is pulled low and the IIN_OC_WARN bit is asserted in the STATUS_INPUT command. The digital processor within the LTC3884 provides the ability to ignore the fault, shut down and latch off or shut down and retry indefinitely (hiccup). The retry interval is set in MFR_RETRY_ DELAY and can be from 120ms to 83.88 seconds in 1ms increments. The shutdown for OV/UV and OC can be done immediately or after a user selectable deglitch time. Output Overvoltage Fault Response A programmable overvoltage comparator (OV) guards against transient overshoots as well as long-term over - voltages at the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on. However , the reverse output current is monitored while device is in OV fault. When it reaches the limit, both top and bottom MOSFETs are turned off. The top and bottom MOSFETs will keep their state until the overvoltage condition is cleared regardless of the PMBus VOUT_OV_FAULT_RESPONSE command byte value. This hardware level fault response delay is typically 2μs from the overvoltage condition to BG asserted high. Using the VOUT_OV_FAULT_RESPONSE command, the user can select any of the following behaviors: n OV Pull-Down Only (OV Cannot Be Ignored) n Shut Down (Stop Switching) Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY Either the Latch Off or Retry fault responses can be de - glitched in increments of (0-7) • 10μs. See Table 7. Output Undervoltage Response The response to an under voltage comparator output can be the following: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. The UV responses can be deglitched. See Table 8. Peak Output Overcurrent Fault Response Due to the current mode control algorithm, peak output current across the inductor is always limited on a cycle-by- cycle basis. The value of the peak current limit is specified in sense voltage in the EC table. The current limit circuit operates by limiting the I TH maximum voltage. If DCR sens- ing is used, the ITH maximum voltage has a temperature dependency directly proportional to the TC of the DCR of the inductor . The LTC3884 automatically monitors the external temperature sensors and modifies the maximum allowed I TH to compensate for this term. The overcurrent fault processing circuitry can execute the following behaviors: n Current Limit Indefinitely n Shut Down Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. The overcurrent responses can be deglitched in increments of (0-7) • 16ms. See Table 9 RESPONSES TO TIMING FAUL TS TON_MAX_FAULT_LIMIT is the time allowed for V OUT to rise and settle at start-up. The TON_MAX_FAULT_LIMIT condition is predicated upon detection of the VOUT_UV_ FAULT_LIMIT as the output is undergoing a SOFT_START sequence. The TON_MAX_ FAULT_LIMIT time is started after TON_DELAY has been reached and a SOFT_START sequence is started. The resolution of the TON_MAX_ FAULT_LIMIT is 10μs. If the VOUT_UV_FAULT _LIMIT is not reached within the TON_MAX_FAULT_LIMIT time, the response of this fault is determined by the value of the TON_MAX_FAULT_RESPONSE command value. This response may be one of the following: n Ignore n Shut Down (Stop Switching) Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. This fault response is not deglitched. A value of 0 in TON_MAX_FAULT_LIMIT means the fault is ignored. The

3884fe For more information www.linear .com/L TC3884 OPERATION TON_MAX_FAULT_LIMIT should be set longer than the TON_RISE time. It is recommended TON_MAX_FAULT_ LIMIT always be set to a non-zero value, otherwise the output may never come up and no flag will be set to the user . See Table 11. RESPONSES TO V IN OV FAUL TS VIN overvoltage is measured with the ADC. The response is naturally deglitched by the 90ms typical response time of the ADC. The fault responses are: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. See Table 11. RESPONSES TO OT/UT FAUL TS Internal Overtemperature Fault Response An internal temperature sensor protects against NVM damage. Above 85°C, no writes to NVM are recommended. Above 130°C,the internal overtemperature warn threshold is exceeded and the part disables the NVM and does not re- enable until the temperature has dropped to 125°C. When the die temperature exceed 160°C the internal temperature fault response is enabled and the PWM is disabled until the die temperature drops below 150°C. Temperature is measured by the ADC. Internal temperature faults cannot be ignored. Internal temperature limits cannot be adjusted by the user . See Table 10. External Overtemperature and Undertemperature Fault Response T wo external temperature sensors can be used to sense the temperature of critical circuit elements like inductors and power MOSFETs. The OT_FAULT_ RESPONSE and UT_FAULT_ RESPOSE commands are used to determine the appropriate response to an overtemperature and under temperature condition, respectively. If no external sense elements are used (not recommended) set the UT_FAULT_ RESPONSE to ignore and set the UT_FAULT_LIMIT to –275°C. The fault responses are: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY. See Table 9. RESPONSES TO INPUT OVERCURRENT AND OUTPUT UNDERCURRENT FAUL TS Input overcurrent and output undercurrent are measured with the ADC. The fault responses are: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately—Retry Indefinitely at the Time Inter val Specified in MFR_RETRY_DELAY See Table 11. RESPONSES TO EXTERNAL FAUL TS When either FAUL Tn pin is pulled low, the OTHER bit is set in the STATUS_WORD command, the appropriate bit is set in the STATUS_MFR_SPECIFIC command, and the ALERT pin is pulled low. Responses are not deglitched. Each channel can be configured to ignore or shut down then retry in response to its FAUL Tn pin going low by modifying the MFR_FAULT_RESPONSE command. To avoid the ALERT pin asserting low when FAUL T is pulled low, assert bit 1 of MFR_CHAN_CONFIG, or mask the ALERT using the SMBALERT_MASK command. FAUL T LOGGING The LTC3884 has fault logging capability. Data is logged into memory in the order shown in Table 13. The data is stored in a continuously updated buffer in RAM. When a fault event occurs, the fault log buffer is copied from the RAM buffer into NVM. Fault logging is allowed at tem - peratures above 85°C; however , retention of 10 years is not guaranteed. When the die temperature exceeds 130°C the fault logging is delayed until the die temperature drops below 125°C. The fault log data remains in NVM until a MFR_FAULT _LOG_CLEAR command is issued. Issuing this command re-enables the fault log feature. Before

3884feFor more information www.linear .com/L TC3884 OPERATION re-enabling fault log, be sure no faults are present and a CLEAR_FAULTS command has been issued. When the LTC3884 powers-up or exits its reset state, it checks the NVM for a valid fault log. If a valid fault log exists in NVM, the “Valid Fault Log” bit in the STATUS_ MFR_SPECIFIC command will be set and an ALERT event will be generated. Also, fault logging will be blocked until the LTC3884 has received a MFR_FAULT_LOG_CLEAR command before fault logging will be re-enabled. The information is stored in EEPROM in the event of any fault that disables the controller on either channel. A FAUL Tn being externally pulled low will not trigger a fault logging event. BUS TIMEOUT PROTECTION The LTC3884 implements a timeout feature to avoid per- sistent faults on the serial interface. The data packet timer begins at the first STAR T event before the device address write byte. Data packet information must be completed within 35ms or the LTC3884 will three-state the bus and ignore the given data packet. If more time is required, assert bit 3 of MFR_CONFIG_ALL to allow typical bus timeouts of 255ms. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), all data bytes and the PEC byte if applicable. The LTC3884 allows longer PMBus timeouts for block read data packets. This timeout is proportional to the length of the block read. The additional block read timeout applies primarily to the MFR_FAULT_LOG command. The timeout period defaults to 32ms. The user is encouraged to use as high a clock rate as possible to maintain efficient data packet transfer between all devices sharing the serial bus interface. The LTC3884 supports the full PMBus frequency range from 10kHz to 400kHz. SIMILARITY BETWEEN PMBus, SMBus AND I 2-WIRE INTERFACE The PMBus 2-wire interface is an incremental extension of the SMBus. SMBus is built upon I2C with some minor differences in timing, DC parameters and protocol. The PMBus/SMBus protocols are more robust than simple I 2C byte commands because PMBus/SMBus provide timeouts to prevent persistent bus errors and optional packet error checking (PEC) to ensure data integrity. In general, a master device that can be configured for I communication can be used for PMBus communication with little or no change to hardware or firmware. Repeat start (restart) is not supported by all I 2C controllers but is required for SMBus/PMBus reads. If a general purpose I 2C controller is used, check that repeat start is supported. The LTC3884 supports the maximum SMBus clock speed of 100kHz and is compatible with the higher speed PM - Bus specification (between 100kHz and 400kHz) if MFR_ COMMON polling or clock stretching is enabled. For robust communication and operation refer to the Note section in the PMBus command summary. Clock stretching is enabled by asserting bit 1 of MFR_CONFIG_ALL. For a description of the minor extensions and exceptions PMBus makes to SMBus, refer to PMBus Specification Part 1 Revision 1.2: Paragraph 5: T ransport. For a description of the differences between SMBus and I 2C, refer to System Management Bus (SMBus) Speci - fication Version 2.0: Appendix B—Differences Between SMBus and I 2C. PMBus SERIAL DIGITAL INTERFACE The LTC3884 communicates with a host (master) using the standard PMBus serial bus interface. The Timing Diagram, Figure 7, shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. The LTC3884 is a slave device. The master can communicate with the LTC3884 using the following formats: n Master T ransmitter , Slave Receiver n Master Receiver , Slave T ransmitter The following PMBus protocols are supported: n Write Byte, Write Word, Send Byte n Read Byte, Read Word, Block Read, Block Write n Alert Response Address

Figure 9. Quick Command Protocol Figure 10. Send Byte Protocol Figure 11. Send Byte Protocol with PEC Figure 8. PMBus Packet Protocol Diagram Element Key Figure 13. Write Byte Protocol with PEC Figure 14. Write Word Protocol Figure 15. Write Word Protocol with PEC Figure 12. Write Byte Protocol

3884 F08

3884 F09

3884 F10

3884 F11

3884 F12

3884 F13

3884 F14

3884 F15

Figure 19. Read Word Protocol with PEC Figure 20. Block Read Protocol Figure 18. Read Word Protocol Figure 21. Block Read Protocol with PEC Figure 17. Read Byte Protocol with PEC Figure 16. Read Byte Protocol

3884 F16

3884 F17

3884 F18

3884 F19

3884 F22

3884 F21

Figure 22. Block Write – Block Read Process Call Figure 24. Alert Response Address Protocol Figure 25. Alert Response Address Protocol with PEC Figure 23. Block Write – Block Read Process Call with PEC

3884 F23

3884 F24

3884 F25

protocols supported by this device. Table 2. Summary (Note: The Data Format abbreviations are detailed at the end of this table.) 1.2”. Users are encouraged to reference this specification. tion 7.1) format, whichever is appropriate for the command. of 0x14. This translates to an exponent of 2–12. section for further details.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PAGE VOUT_TRANSITION_ RATE 0X27 Rate the output changes when VOUT commanded to a new value. R/W Word Y L11 V/ms Y 0.25 0xAA00 FREQUENCY_SWITCH 0x33 Switching frequency of the controller . R/W Word N L11 kHz Y 425k 0xFB52 VIN_ON 0x35 Input voltage at which the unit should start power conversion. R/W Word N L11 V Y 6.5 0xCB40 VIN_OFF 0x36 Input voltage at which the unit should stop power conversion. R/W Word N L11 V Y 6.0 0xCB00 IOUT_CAL_GAIN 0x38 The ratio of the voltage at the current sense pins to the sensed current. For devices using a fixed current sense resistor , it is the resistance value in mΩ. R/W Word Y L11 mΩ Y 0.32 0xAA8F VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1 0x119A VOUT_OV_FAULT_ RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0xB8 VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075 0x1133 VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925 0x0ECD VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 0.9 0x0E66 VOUT_UV_FAULT_ RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0xB8 IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A Y 45.0 0xE2D0 IOUT_OC_FAULT_ RESPONSE 0x47 Action to be taken by the device when an output overcurrent fault is detected. R/W Byte Y Reg Y 0x00 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 35.0 0xE230 OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 C Y 100.0 0xEB20 OT_FAULT_RESPONSE 0x50 Action to be taken by the device when an external overtemperature fault is detected, R/W Byte Y Reg Y 0xB8 97 OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 C Y 85.0 0xEAA8 UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 C Y –40.0 0xE580 UT_FAULT_RESPONSE 0x54 Action to be taken by the device when an external undertemperature fault is detected. R/W Byte Y Reg Y 0xB8 97 VIN_OV_FAULT_LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 V Y 15.5 0xD3E0 VIN_OV_FAULT_ RESPONSE 0x56 Action to be taken by the device when an input overvoltage fault is detected. R/W Byte Y Reg Y 0x80 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 6.3 0xCB26 IIN_OC_WARN_LIMIT 0x5D Input supply overcurrent warning limit. R/W Word N L11 A Y 10.0 0xD280 TON_DELAY 0x60 Time from RUN and/or Operation on to output rail turn-on. R/W Word Y L11 ms Y 0.0 0x8000

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PAGE TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value. R/W Word Y L11 ms Y 8.0 0xD200 TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for VOUT to cross the VOUT_UV_FAULT_LIMIT. R/W Word Y L11 ms Y 10.00 0xD280 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_ MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start of TOFF_FALL ramp. R/W Word Y L11 ms Y 0.0 0x8000 TOFF_FALL 0x65 Time from when the output starts to fall until the output reaches zero volts. R/W Word Y L11 ms Y 8.00 0xD200 TOFF_MAX_WARN_ LIMIT 0x66 Maximum allowed time, after TOFF_FALL completed, for the unit to decay below 12.5%. R/W Word Y L11 ms Y 150.0 0xF258 STATUS_BYTE 0x78 One byte summary of the unit’s fault condition. R/W Byte Y Reg NA 104 STATUS_WORD 0x79 T wo byte summary of the unit’s fault condition. R/W Word Y Reg NA 104 STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA 105 STATUS_IOUT 0x7B Output current fault and warning status. R/W Byte Y Reg NA 105 STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg NA 106 STATUS_TEMPERATURE 0x7D External temperature fault and warning status for READ_TEMERATURE_1. R/W Byte Y Reg NA 106 STATUS_CML 0x7E Communication and memory fault and warning status. R/W Byte N Reg NA 107 STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state information. R/W Byte Y Reg NA 107 READ_VIN 0x88 Measured input supply voltage. R Word N L11 V NA 110 READ_IIN 0x89 Measured input supply current. R Word N L11 A NA 110 READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA 110 READ_IOUT 0x8C Measured output current. R Word Y L11 A NA 110 READ_TEMPERATURE_1 0x8D External temperature sensor temperature. This is the value used for all temperature related processing, including IOUT_CAL_GAIN. R Word Y L11 C NA 110 READ_TEMPERATURE_2 0x8E Internal die junction temperature. Does not affect any other commands. R Word N L11 C NA 110 READ_FREQUENCY 0x95 Measured PWM switching frequency. R Word Y L11 Hz NA 110 READ_POUT 0x96 Measured output power R Word Y L11 W N/A 110 READ_PIN 0x97 Calculated input power R Word Y L11 W N/A 111 PMBus_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.2. R Byte N Reg 0x22 101 MFR_ID 0x99 The manufacturer ID of the LTC3884 in ASCII. R String N ASC LT C 101 MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC LTC3884 101 MFR_VOUT_MAX 0xA5 Maximum allowed output voltage including VOUT_OV_FAULT_LIMIT. R Word Y L16 V 5.7 0x5B33 MFR_PIN_ACCURACY 0xAC Returns the accuracy of the READ_PIN command R Byte N % 5.0% 111 USER_DATA_00 0xB0 OEM RESERVED. Typically used for part serialization. R/W Word N Reg Y NA 101

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PAGE USER_DATA_01 0xB1 Manufacturer reserved for L TpowerPlay. R/W Word Y Reg Y NA 101 USER_DATA_02 0xB2 OEM RESERVED. Typically used for part serialization. R/W Word N Reg Y NA 101 USER_DATA_03 0xB3 An NVM word available for the user . R/W Word Y Reg Y 0x0000 101 USER_DATA_04 0xB4 An NVM word available for the user . R/W Word N Reg Y 0x0000 101 MFR_INFO 0xB6 Manufacturing specific information. R Word N Reg 109 MFR_EE_UNLOCK 0xBD Contact factory. 118 MFR_EE_ERASE 0xBE Contact factory. 118 MFR_EE_DATA 0xBF Contact factory. 118 MFR_CHAN_CONFIG 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1D 75 MFR_CONFIG_ALL 0xD1 General configuration bits. R/W Byte N Reg Y 0x21 76 MFR_FAULT_ PROPAGATE 0xD2 Configuration that determines which faults are propagated to the FAUL T pin. R/W Word Y Reg Y 0x6993 98 MFR_PWM_COMP 0xD3 PWM loop compensation configuration R/W Byte Y Reg Y 0xAE 79 MFR_PWM_MODE 0xD4 Configuration for the PWM engine. R/W Byte Y Reg Y 0xC7 78 MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAUL T pin is externally asserted low. R/W Byte Y Reg Y 0xC0 100 MFR_OT_FAULT_ RESPONSE 0xD6 Action to be taken by the device when an internal overtemperature fault is detected. R Byte N Reg 0xC0 MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_ IOUT since last MFR_CLEAR_PEAKS. R Word Y L11 A NA 111 MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated fast ADC read back R/W Byte N Reg 0x00 112 MFR_RETRY_DELAY 0xDB Retry interval during FAUL T retry mode. R/W Word Y L11 ms Y 350.0 0xFABC MFR_RESTART_DELAY 0xDC Minimum time the RUN pin is held low by the LTC3884. R/W Word Y L11 ms Y 500.0 0xFBE8 MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since last MFR_CLEAR_PEAKS. R Word Y L16 V NA 111 MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last MFR_CLEAR_PEAKS. R Word N L11 V NA 111 MFR_TEMPERATURE_1_ PEAK 0xDF Maximum measured value of external Temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. R Word Y L11 C NA 111 MFR_READ_IIN_PEAK 0xE1 Maximum measured value of READ_IIN command since last MFR_CLEAR_PEAKS R Word N L11 A NA 111 MFR_CLEAR_PEAKS 0xE3 Clears all peak values. Send Byte N NA 103 MFR_READ_ICHIP 0xE4 Measured supply current of the LTC3884 R Word N L11 A NA 111 MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg NA 108 MFR_ADDRESS 0xE6 Sets the 7-bit I 2C address byte. R/W Byte N Reg Y 0x4F 75 MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTC3884 and revision R Word N Reg 0x4C0X 101 MFR_IIN_CAL_GAIN 0xE8 The resistance value of the input current sense element in mΩ. R/W Word N L11 mΩ Y 5.0 0xCA80

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND SUMMARY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PAGE MFR_FAULT_LOG_ STORE 0xEA Command a transfer of the fault log from RAM to EEPROM. Send Byte N NA 115 MFR_FAULT_LOG_ CLEAR 0xEC Initialize the EEPROM block reserved for fault logging. Send Byte N NA 118 MFR_FAULT_LOG 0xEE Fault log data bytes. R Block N Reg Y NA 115 MFR_COMMON 0xEF Manufacturer status bits that are common across multiple ADI chips. R Byte N Reg NA 108 MFR_COMPARE_USER_ ALL 0xF0 Compares current command contents with NVM. Send Byte N NA 113 MFR_TEMPERATURE_2_ PEAK 0xF4 Peak internal die temperature since last MFR_ CLEAR_PEAKS. R Word N L11 C NA 112 MFR_PWM_CONFIG 0xF5 Set numerous parameters for the DC/DC controller including phasing. R/W Byte N Reg Y 0x10 80 MFR_IOUT_CAL_GAIN_ TC 0xF6 Temperature coefficient of the current sensing element. R/W Word Y CF ppm/ Y 3900 0x0F3C MFR_RVIN 0xF7 The resistance value of the V IN pin filter element in mΩ. R/W Word N L11 mΩ Y 1000 0x03E8 MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature sensor . R/W Word Y CF Y 1.0 0x4000 MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the external temperature sensor with respect to –273.1°C R/W Word Y L11 C Y 0.0 0x8000 MFR_RAIL_ADDRESS 0xFA Common address for PolyPhase outputs to adjust common parameters. R/W Byte Y Reg Y 0x80 MFR_REAL_TIME 0xFB 48-bit share-clock counter value. R Block N CF NA xx MFR_RESET 0xFD Commanded reset without requiring a power down. Send Byte N NA 77 Note 1: Commands indicated with Y in the NVM column indicate that these commands are stored and restored using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively. Note 2: Commands with a default value of NA indicate “not applicable”. Commands with a default value of FS indicate “factory set on a per part basis”. Note 3: The LTC3884 contains additional commands not listed in this table. Reading these commands is harmless to the operation of the IC; however , the contents and meaning of these commands can change without notice. Note 4: Some of the unpublished commands are read-only and will generate a CML bit 6 fault if written. Note 5: Writing to commands not published in this table is not permitted. Note 6: The user should not assume compatibility of commands between different parts based upon command names. Always refer to the manufacturer’s data sheet for each part for a complete definition of a command’s function. ADI strives to keep command functionality compatible between all ADI devices. Differences may occur to address specific product requirements.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND SUMMARY *DATA FORMAT L11 Linear_5s_11s PMBus data field b[15:0] Value = Y • 2N where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit two’s complement integer Example: For b[15:0] = 0x9807 = ‘b10011_000_0000_0111 V alue = 7 • 2–13 = 854 • 10–6 From “PMBus Spec Part II: Paragraph 7.1” L16 Linear_16u PMBus data field b[15:0] Value = Y • 2N where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s complement exponent that is hardwired to –12 decimal Example: For b[15:0] = 0x9800 = ‘b1001_1000_0000_0000 V alue = 19456 • 2–12 = 4.75 From “PMBus Spec Part II: Paragraph 8.2” Reg Register PMBus data field b[15:0] or b[7:0]. Bit field meaning is defined in detailed PMBus Command Description. I16 Integer Word PMBus data field b[15:0] Value = Y where Y = b[15:0] is a 16 bit unsigned integer Example: For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111 V alue = 38919 (decimal) CF Custom Format V alue is defined in detailed PMBus Command Description. This is often an unsigned or two’s complement integer scaled by an MFR specific constant. ASC ASCII Format A variable length string of text characters conforming to ISO/IEC 8859-1 standard.

power efficient, especially in high current applications. best signal-to-noise ratio of the input sensing voltage. transient response to load changes. using the PMBUS command IOUT_OC_FAULT_LIMIT.

3994 F26

Figure 26. VITH vs VILIMIT the Operation section for more details.

these pins during normal operation. or greater should be placed in parallel with this resistor . the 5x the voltage ripple across the inductor DCR. Figure 27. Sense Lines Placement with Inductor DCR

3884 F28a

3884 F28b

3884fe For more information www.linear .com/L TC3884 APPLICATIONS INFORMATION operation is obtained with a small ripple current, which requires a large inductor . A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that the ripple current does not exceed a specified maxi- mum, the inductor should be chosen according to: L ≥ VOUT VIN – VOUT( ) VIN • fOSC •IRIPPLE INDUCTOR CORE SELECTION Once the inductor value is determined, the type of induc- tor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance. As the inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core materials saturate hard, which means that the induc - tance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! LOW VALUE RESISTOR CURRENT SENSING A typical sensing cir cuit using a discrete resistor is shown in Figure 28b. R SENSE is chosen based on the required output current. The current comparator has a maximum threshold VSENSE(MAX) determined by the I LIMIT setting. The input common mode range of the current comparator is 0V to 5.5V. The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current I MAX equal to the peak value less half the peak- to-peak ripple current ∆IL. To calculate the sense resistor value, use the equation: RSENSE = VSENSE(MAX) IMAX + ΔIL To ensure the load current will be delivered over the full operating temperature range, the temperature coefficient of DCR resistance, approximately 3900ppm/°C, should be taken into consideration. Typically, C is selected in the range of 0.047µF to 0.47µF. This forces R1 to around 2kΩ @ MFR_PWM_MODE[2]=0, 400Ω @ MFR_PWM_MODE[2]=1 reducing error that might have been caused by the I SENSE pins’ ±1µA current (R3 and C2 are for reducing sensing error caused by input current through R1). There will be some power loss in R that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage: PLOSS R( ) = VIN(MAX) – VOUT( ) • VOUT R Ensure that R1 has a power rating higher than this value. However , DCR sensing eliminates the conduction loss of sense resistor; it will provide better efficiency at heavy loads. To maintain a good signal-to-noise ratio for low current sense signals, it is best to enable the LOW DCR sensing network (MFR_PWM_MODE[2] = 1, RC = L/(5 • DCR)). For a DCR sensing application, the ripple voltage will be determined by the equation: ΔVSENSE = VOUT VIN

VIN – VOUT RC• fOSC Low DCR sensing can be used at ∆VSENSE signals as low as 2mV. INDUCTOR VALUE CALCULATION Given the desired input and output voltages, the inductor value and operating frequency, f OSC, directly determine the inductor peak-to-peak ripple current: IRIPPLE = VOUT VIN – VOUT( ) VIN • fOSC •L Lower ripple current reduces core losses in the inductor , ESR losses in the output capacitors, and output voltage ripple. Thus, at a given frequency, the highest efficiency

3884feFor more information www.linear .com/L TC3884 APPLICATIONS INFORMATION Due to possible PCB noise in the current sensing loop, the AC current sensing ripple of ∆VSENSE = ∆IL • RSENSE also needs to be checked in the design to get a good signal-to- noise ratio. In general, for a reasonably good PCB layout, a 15mV minimum ∆V SENSE voltage is recommended as a conservative number to start with for RSENSE applications. For previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mV for the LTC1628/LTC3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error . In the newer and higher current density solutions, the value of the sense resistor can be less than 1mΩ and the peak sense voltage can be less than 20mV. Also, inductor ripple currents greater than 50% with operation up to 750kHz are becoming more common. Under these conditions, the voltage drop across the sense resistor’s parasitic inductance is no longer negligible. A typical sensing circuit using a discrete resistor is shown in Figure 28b. In previous generations of controllers, a small RC filter placed near the IC was commonly used to reduce the effects of the capacitive and inductive noise coupled in the sense traces on the PCB. A typical filter consists of two series 100Ω resistors connected to a parallel 1000pF capacitor , resulting in a time constant of 200ns. This same RC filter , with minor modifications, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. For example, Figure 29a illustrates the voltage waveform across a 2mΩ resistor with a PCB footprint of 2010. The waveform is the superposition of a purely resistive component and a purely inductive component. It was measured using two scope probes and waveform math to obtain a differential measurement. Based on additional measurements of the inductor ripple current and the on-time, t ON, and off-time, tOFF, of the top switch, the value of the parasitic inductance was determined to be 0.5nH using the equation: ESL = VESL(STEP) ΔIL

tON • tOFF tON + tOFF (1) If the RC time constant is chosen to be close to the para- sitic inductance divided by the sense resistor (L/R), the resultant waveform looks resistive, as shown in Figure 29b. For applications using low maximum sense voltages, check the sense resistor manufacturer ’s data sheet for information about parasitic inductance. In the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the ESL step and use Equation 1 to determine the ESL. However , do not overfilter the signal. Keep the RC time constant less than or equal to the inductor time constant to maintain a sufficient ripple voltage on V RSENSE for optimal operation of the current loop controller . SLOPE COMPENSATION AND INDUCTOR PEAK CURRENT Slope compensation provides stability in constant- frequency current-mode architectures by preventing sub-harmonic oscillations at high duty cycles. This is ac- complished internally by adding a compensation ramp to the inductor current signal. The LTC3884 uses a patented current limit technique that counteracts the compensating ramp. This allows the maximum inductor peak current to remain unaffected throughout all duty cycles. Figure 29a. Voltage Measured Directly Across RSENSE Figure 29b. Voltage Measured After the RSENSE Filter 500ns/DIV VSENSE 20mV/DIV

3884 F29a

VESL(STEP) 500ns/DIV VSENSE 20mV/DIV

3884 F29b

3884fe For more information www.linear .com/L TC3884 APPLICATIONS INFORMATION where δ is the temperature dependency of R DS(ON) and RDR (approximately 2Ω) is the effective driver resistance at the MOSFET’s Miller threshold voltage. V TH(MIN) is the typical MOSFET minimum threshold voltage. Both MOSFETs have I 2R losses while the topside N-channel equation includes an additional term for transition losses, which are highest at high input voltages. For V IN < 20V the high current efficiency generally improves with larger MOSFETs, while for V IN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. The term (1 + d) is generally given for a MOSFET in the form of a normalized R DS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. The optional Schottky diodes conduct during the dead time between the conduction of the two power MOSFETs. These prevent the body diodes of the bottom MOSFETs from turning on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in efficiency at high V IN. A 1A to 3A Schottky is generally a good compromise for both regions of opera- tion due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. VARIABLE DELAY TIME, SOFT-START AND OUTPUT VOL TAGE RAMPING The LTC3884 must enter the run state prior to soft-start. The RUNn pin is released after the part initializes and V IN is greater than the VIN_ON threshold. If multiple LTC3884s are used in an application, they should be configured to share the same RUNn pins. They all hold their respective RUNn pins low until all devices initialize and V IN exceeds the VIN_ON threshold for all devices. The SHARE_CLK pin assures all the devices connected to the signal use the same time base. POWER MOSFET AND OPTIONAL SCHOTTKY DIODE SELECTION T wo external power MOSFETs must be selected for each controller in the LTC3884: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bot- tom (synchronous) switch. The peak-to-peak drive levels are set by the INTV CC voltage. This voltage is typically 5.5V. Consequently, logic-level threshold MOSFETs must be used in most applications. The only exception is if low input volt- age is expected (V IN < 5V); then, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close atten- tion to the BVDSS specification for the MOSFETs as well; most of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the on- resistance, R DS(ON), Miller capacitance, C MILLER, input voltage and maximum output current. Miller capacitance, C MILLER, can be approximated from the gate charge curve usually provided on the MOSFET manufacturers’ data sheet. C MILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in V DS. This result is then multiplied by the ratio of the application applied VDS to the gate charge curve specified V DS. When the IC is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN Synchronous Switch Duty Cycle =VIN – VOUT VIN The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT VIN IMAX( ) 2 1+δ( ) •RDS(ON)+ VIN( ) 2 IMAX ⎝⎜ ⎞ ⎠⎟ RDR( ) CMILLER( ) • VINTVCC – VTH(MIN) + 1 VTH(MIN)

fOSC PSYNC = VIN – VOUT VIN IMAX( ) 2 • 1+δ( ) •RDS(ON)

3884feFor more information www.linear .com/L TC3884 APPLICATIONS INFORMATION After the RUNn pin releases, the controller waits for the user-specified turn-on delay (TON_DELAY) prior to ini - tiating an output voltage ramp. Multiple LTC3884s and other ADI parts can be configured to start with variable delay times. T o work correctly, all devices use the same timing clock (SHARE_CLK) and all devices must share the RUNn pin. This allows the relative delay of all parts to be synchronized. The actual variation in the delay will be dependent on the highest clock rate of the devices connected to the SHARE_CLK pin (all Analog Devices ICs are configured to allow the fastest SHARE_CLK signal to control the timing of all devices). The SHARE_CLK signal can be ±10% in frequency, thus the actual time delays will have proportional variance. Soft-start is performed by actively regulating the load volt- age while digitally ramping the target voltage from 0.0V to the commanded voltage set point. The rise time of the voltage ramp can be programmed using the TON_RISE command to minimize inrush currents associated with the start-up voltage ramp. The soft-start feature is disabled by setting TON_RISE to any value less than 0.250ms. The LTC3884 will perform the necessary math internally to assure the voltage ramp is controlled to the desired slope. However , the voltage slope cannot be any faster than the fundamental limits of the power stage. The shorter TON_RISE time is set, the larger the discrete steps in the TON_RISE ramp will appear . The number of steps in the ramp is equal to TON_RISE/0.1ms. The LTC3884 PWM will always use discontinuous mode during the TON_RISE operation. In discontinuous mode, the bottom gate is turned off for LTC3884 or PWM is in three-state for LTC3884-1 as soon as reverse current is detected in the inductor . This will allow the regulator to start up into a pre-biased load. There is no traditional tracking feature in the LTC3884. However , two outputs can be given the same TON_RISE and TON_DELAY times to effectively ramp up at the same time. If the RUN pin is released at the same time and both LTC3884s use the same time base, the outputs will track very closely. If the circuit is in a PolyPhase configuration, all timing parameters must be the same. The method of start-up sequencing described above is time based. For concatenated events it is possible to control the RUNn pins based on the PGOODn pin of a different controller . There is 60µs filtering to the PGOODn inside the device. If unwanted transitions still occur on PGOODn, place a capacitor to ground on the PGOODn pin to filter the waveform. The RC time-constant of the filter should be set sufficiently fast to assure no appreciable delay is incurred. A value of 300μs to 500μs will provide some additional filtering without significantly delaying the trigger event. DIGITAL SERVO MODE For maximum accuracy in the regulated output voltage, enable the digital servo loop by asserting bit 6 of the MFR_PWM_MODE command. In digital servo mode, the LTC3884 will adjust the regulated output voltage based on the ADC voltage reading. Every 90ms the digital servo loop will step the LSB of the DAC (nominally 1.375mV or 0.688mV depending on the voltage range bit) until the output is at the correct ADC reading. At power-up this mode engages after TON_MAX_FAULT_LIMIT unless the limit is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set to 0 (infinite), the servo begins after TON_RISE is complete and V OUT has exceeded the VOUT_UV_FAULT_LIMIT. This same point in time is when the output changes from discontinuous to the programmed mode as indicated in MFR_PWM_MODE bit 0. Refer to Figure 30 for details on the V OUT waveform under time-based sequencing. If the TON_MAX_FAULT_LIMIT is set to a value greater than 0 and the TON_MAX_FAULT_RESPONSE is set to ignore 0x00, the servo begins: 1. After the TON_RISE sequence is complete 2. After the TON_MAX_FAULT_LIMIT time is reached; and 3. After the VOUT_UV_FAULT_LIMIT has been exceed or the IOUT_OC_FAULT_LIMIT is no longer active. If the TON_MAX_FAULT_LIMIT is set to a value greater than 0 and the TON_MAX_FAULT_RESPONSE is not set to ignore 0X00, the servo begins: 1. After the TON_RISE sequence is complete;

After the TON_MAX_FAULT_LIMIT time has expired

The maximum rise time is limited to 1.3 seconds. of the control loops have the digital servo mode enabled. other due to slight differences in the reference circuits. ramp is equal to TOFF_FALL/0.1ms. Figure 31. TOFF_DELAY and TOFF_FALL will three-state rather than exhibiting a controlled ramp.

3884 F30

Figure 30. Timing Controlled VOUT Rise INTVCC/EXTVCC POWER other internal circuitry are derived from the INTV CC pin.

MOSFETs, which is typically 4.5V for logic level devices. CC is set to approximately 4V. external diode DB from INTVCC when the SWn pin is low. recommended to reduce ESL and achieve the best results. Figure 32. Setup for a 5V Input Figure 33. Boost Circuit to Minimize PWM Jitter

3884 F32

3884 F33

3884fe For more information www.linear .com/L TC3884 APPLICATIONS INFORMATION UNDERVOL TAGE LOCKOUT The LTC3884 is initialized by an internal threshold-based UVLO where VIN must be approximately 4V and INTVCC, VDD33, and VDD25 must be within approximately 20% of their regulated values. In addition, VDD33 must be within approximately 7% of the targeted value before the RUN pin is released. After the part has initialized, an additional comparator monitors V IN. The VIN_ON threshold must be exceeded before the power sequencing can begin. When V IN drops below the VIN_OFF threshold, the SHARE_CLK pin will be pulled low and V IN must increase above the VIN_ON threshold before the controller will restart. The normal start-up sequence will be allowed after the VIN_ON threshold is crossed. If FAUL TB is held low when V IN is applied, ALERT will be asserted low even if the part is programmed to not assert ALERT when FAUL TB is held low. If I 2C communication occurs before the LTC3884 is out of reset and only a portion of the command is seen by the part, this can be interpreted as a CML fault. If a CML fault is detected, ALERT is asserted low. It is possible to program the contents of the NVM in the application if the V DD33 supply is externally driven directly to VDD33 or through EXTVCC. This will activate the digital portion of the LTC3884 without engaging the high volt - age sections. PMBus communications are valid in this supply configuration. If V IN has not been applied to the LTC3884, bit 3 (NVM Not Initialized) in MFR_COMMON will be asserted low. If this condition is detected, the part will only respond to addresses 5A and 5B. To initialize the part issue the following set of commands: global ad- dress 0x5B command 0xBD data 0x2B followed by global address 5B command 0xBD and data 0xC4. The part will now respond to the correct address. Configure the part as desired then issue a STORE_USER_ALL. When V IN is ap- plied a MFR_RESET command must be issued to allow the PWM to be enabled and valid ADC conversions to be read. C IN AND COUT SELECTION In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (V OUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≈IMAX VIN VOUT( ) VIN – VOUT( )⎡⎣ ⎤ This formula has a maximum at V IN = 2V OUT, where IRMS = IOUT/2. This simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capaci- tor , or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC3884, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. The benefit of using a LTC3884 in 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. The total RMS power loss is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor’s ESR. This is why the input capacitor’s requirement cal - culated above for the worst-case controller is adequate for the dual controller design. Also, the input protection fuse resistance, batter y resistance, and PC board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. The overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. The sources of the top MOSFETs should be placed within 1cm of each other and share a common C IN(s). Separating the sources and CIN may pro- duce undesirable voltage and current resonances at VIN. A small (0.1μF to 1μF) bypass capacitor between the chip V IN pin and ground, placed close to the LTC3884, is also suggested. A 2.2Ω to 10Ω resistor placed between C IN (C1) and the V IN pin provides further isolation between the two LTC3884s.

3884feFor more information www.linear .com/L TC3884 APPLICATIONS INFORMATION The selection of C OUT is driven by the effective series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆V OUT) is approximated by: ΔVOUT ≈IRIPPLE ESR+ 1 8 • f •COUT where f is the operating frequency, C OUT is the output capacitance and IRIPPLE is the ripple current in the induc- tor . The output ripple is highest at maximum input voltage since IRIPPLE increases with input voltage. FAUL T INDICATION The LTC3884 FAUL T pins are configurable to indicate a variety of faults including OV , UV , OC, OT , timing faults, and peak over current faults. In addition, the FAUL T pins can be pulled low by external sources indicating a fault in some other portion of the system. The fault response is configurable and allows the following options: n Ignore n Shut Down Immediately—Latch Off n Shut Down Immediately— Retry Indefinitely at the Time Interval Specified in MFR_RETRY_DELAY Refer to the PMBus section of the data sheet and the PMBus specification for more details. The OV response is automatic. If an OV condition is de - tected, TGn goes low and BGn is asserted. Fault logging is available on the LTC3884 . The fault log- ging is configurable to automatically store data when a fault occurs that causes the unit to fault off. The header portion of the fault logging table contains peak values. It is possible to read these values at any time. This data will be useful while troubleshooting the fault. If the LTC3884 internal temperature is in excess of 85°C, writes into the NVM (other than fault logging) are not recommended. The data will still be held in RAM, unless the 3.3V supply UVLO threshold is reached. If the die temperature exceeds 130°C all NVM communication is disabled until the die temperature drops below 120°C. OPEN-DRAIN PINS The LTC3884 has the following open-drain pins: 3.3V Pins 1. F AUL T 2. SYNC 3. SHARE_CLK 4. PGOODn Pins (5V pins operate correctly when pulled to 3.3V.) 1. RUNn 2. ALER T 3. SCL 4. SDA All the above pins have on-chip pull-down transistors that can sink 3mA at 0.4V. The low threshold on the pins is 0.8V; thus, there is plenty of margin on the digital signals with 3mA of current. For 3.3V pins, 3mA of current is a 1.1k resistor . Unless there are transient speed issues associated with the RC time constant of the resistor pull- up and parasitic capacitance to ground, a 10k resistor or larger is generally recommended. For high speed signals such as the SDA, SCL and SYNC, a lower value resistor may be required. The RC time con- stant should be set to 1/3 to 1/5 the required rise time to avoid timing issues. For a 100pF load and a 400kHz PMBus communication rate, the rise time must be less than 300ns. The resistor pull-up on the SDA and SCL pins with the time constant set to 1/3 the rise time is: RPULLUP = tRISE 3•100pF = 1k The closest 1% resistor value is 1k. Be careful to minimize parasitic capacitance on the SDA and SCL pins to avoid communication problems. To estimate the loading capaci- tance, monitor the signal in question and measure how long it takes for the desired signal to reach approximately 63% of the output value. This is a one time constant. The SYNC pin has an on-chip pull-down transistor with the

3884fe For more information www.linear .com/L TC3884 APPLICATIONS INFORMATION output held low for nominally 500ns. If the internal oscil- lator is set for 500kHz and the load is 100pF and a 3x time constant is required, the resistor calculation is as follows: RPULLUP = 2µs – 500ns 3•100pF = 5k The closest 1% resistor is 4.99k. If timing errors are occurring or if the SYNC frequency is not as fast as desired, monitor the waveform and determine if the RC time constant is too long for the application. If possible reduce the parasitic capacitance. If not reduce the pull-up resistor sufficiently to assure proper timing. The SHARE_CLK pull-up resistor has a similar equation with a period of 10µs and a pull-down time of 1μs. The RC time constant should be approximately 3μs or faster . PHASE-LOCKED LOOP AND FREQUENCY SYNCHRONIZATION The LTC3884 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector . The PLL is locked to the falling edge of the SYNC pin. The phase relationship between the PWM controller and the falling edge of SYNC is controlled by the lower 3 bits of the MFR_PWM_ CONFIG command. For PolyPhase applications, it is recommended that all the phases be spaced evenly. Thus for a 2-phase system the signals should be 180° out of phase and a 4-phase system should be spaced 90°. The phase detector is an edge-sensitive digital type that provides a known phase shift between the external and internal oscillators. This type of phase detector does not exhibit false lock to harmonics of the external clock. The output of the phase detector is a pair of complemen- tary current sources that charge or discharge the internal filter network. The PLL lock range is guaranteed between 200kHz and 1MHz. Nominal parts will have a range beyond this; however , operation to a wider frequency range is not guaranteed. The PLL has a lock detection circuit. If the PLL should lose lock during operation, bit 4 of the STATUS_MFR_SPECIFIC command is asserted and the ALERT pin is pulled low. The fault can be cleared by writing a 1 to the bit. If the user does not wish to see the ALERT pin assert if a PLL_FAULT occurs, the SMBALERT_MASK command can be used to prevent the alert. If the SYNC signal is not clocking in the application, the nominal programmed frequency will control the internal PWM circuitry. However , if multiple parts share the SYNC pins and the signal is not clocking, the parts will not be synchronized and excess voltage ripple on the output may be present. Bit 10 of MFR_PADS will be asserted low if this condition exists. If the TG/BG (LTC3884) or PWM (LTC3884-1) appear to be running at too high a frequency, monitor the SYNC pin. Extra transitions on the falling edge will result in the PLL trying to lock on to noise versus the intended signal. Review routing of digital control signals and minimize crosstalk to the SYNC signal to avoid this problem. Multiple LTC3884s are required to share one SYNC pin in PolyPhase configurations. For other configurations, connecting the SYNC pins to form a single SYNC signal is optional. If the SYNC pin is shared between LTC3884s, only one LTC3884 can be programmed with a frequency output. All the other LTC3884s should be programmed to disable the SYNC output. However their frequency should be programmed to the nominal desired value. MINIMUM ON-TIME CONSIDERATIONS Minimum on-time, t ON(MIN), is the smallest time duration that the LTC3884 is capable of turning on the top MOSFET . It is determined by internal timing delays and the gate charge required to turn off the top MOSFET . Low duty cycle applications may approach this minimum limit and care should be taken to ensure that: tON(MIN) < VOUT VIN • fOSC If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase.

should be placed in parallel with the diode-connected PNP. between the transistor and capacitor .

3884 F35

3884 F34

Figure 35. 2D+R Temperature Sense Figure 34. External ∆VBE Temperature Sense BE approach with its lower signal levels. the ideality factor to calculate the MFR_TEMP_1_GAIN. the direct p-n junction measurement. IOUT_CAL_GAIN_TC to a value of 0.

later section covering PMBus command details. VIN filter element is used, set MFR_RVIN = 0. sense amplifier inputs and supply. IN, IIN+, and IIN– pins together . Figure 36. Low Noise Input Current Sense Circuit

3884 F36

PMBus interface or purchasing custom programmed parts. clock signals should not be routed near these pins.

Table 3. VOUT_CFGn Resistor Programming The PWM switching frequency is set according to Table 4. Table 4. FREQ_CFG Resistor Programming

of SYNC is set using the values in Table 5. Table 5. PHASE_CFG Resistor Programming is with respect to the falling edge of SYNC. Table 6. ASEL0 programs the bottom four bits of the device stored in EEPROM is used to determine the device address. Table 6. ASELn Resistor Programming

3884feFor more information www.linear .com/L TC3884 APPLICATIONS INFORMATION Table 6A1. MFR_ADDRESS Command Examples Expressing Both 7- or 8-Bit Addressing

0 R/W7 BIT 8 BIT

Rail4 0x5A 0xB4 0 1 0 1 1 0 1 0 0 Global4 0x5B 0xB6 0 1 0 1 1 0 1 1 0 Default 0x4F 0x9E 0 1 0 0 1 1 1 1 0 Example 1 0x60 0xC0 0 1 1 0 0 0 0 0 0 Example 2 0x61 0xC2 0 1 1 0 0 0 0 1 0 Disabled2,3,5 1 0 0 0 0 0 0 0 0 Note 1: This table can be applied to the MFR_CHANNEL_ADDRESS, and MFR_RAIL_ADDRESS commands as well as the MFR_ADDRESS command. Note 2: A disabled value in one command does not disable the device, nor does it disable the Global address. Note 3: A disabled value in one command does not inhibit the device from responding to device addresses specified in other commands. Note 4: It is not recommended to write the value 0x00, 0x0C (7 bit), or 0x5A or 0x5B(7 bit) to the MFR_ADDRESS, MFR_CHANNEL_ ADDRESS or the MFR_RAIL_ADDRESS commands. Note 5: To disable the address enter 0x80 in the MFR_ADDRESS command. The 0x80 is greater than the 7-bit address field, disabling the address. EFFICIENCY CONSIDERATIONS The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percent- age of input power . Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3884 circuits: 1) IC V IN current, 2) INTVCC regulator current, 3) I 2R losses, 4) Topside MOSFET transition losses. 1. The VIN current is the DC supply current given in the Electrical Characteristics table, which excludes MOSFET driver and control currents. V IN current typically results in a small (<0.1%) loss. 2. INT VCC current is the sum of the MOSFET driver and control currents (LTC3884). The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTV CC to ground. The resulting dQ/dt is a cur - rent out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom side MOSFETs. For the LTC3884-1, the gate driver is inside the DrMOS, which is powered by some other supply. Similar power loss occurs with that supply. I2R losses are predicted from the DC resistances of the fuse (if used), MOSFET , inductor , and current sense resistor . In continuous mode, the average output current flows through the inductor and R SENSE, but is “chopped” between the topside MOSFET and the synchronous MOSFET . If the two MOSFETs have approximately the same R DS(ON), then the resistance of one MOSFET can simply be summed with the resistances of the inductor and R SENSE to obtain I2R losses. For example, if each RDS(ON) = 10mΩ, RL = 10mΩ, RSENSE = 5mΩ, then the total resistance is 25mΩ. This results in losses ranging from 2% to 8% as the output current increases from 3A to 15A for a 5V output, or a 3% to 12% loss for a 3.3V output. Efficiency varies as the inverse square of V OUT for the same external components and output power level. The combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but qua - drupling the importance of loss terms in the switching regulator system!

3884 F37

Figure 37. Programmable Loop Compensation Figure 38. Error Amp gm Adjust Figure 39. RTH Adjust

3884 F39

T ransition losses apply only to the topside MOSFET(s),

generally account for less than 2% total additional loss. the typical ratio between CTH and CTHP is 10. location, as shown in Figure 38.

3884 F38

3884feFor more information www.linear .com/L TC3884 APPLICATIONS INFORMATION CHECKING TRANSIENT RESPONSE The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, V OUT shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return V OUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the I TH pin not only allows optimization of control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The I THR external capacitor shown in the Typical Application circuit will provide an adequate starting point for most applications. The programmable parameters that affect loop gain are the voltage range, bit[1] of the MFR_PWM_MODE command, the current range, bit[2] and bit[7] of the MFR_PWM_MODE com - mand, the g m of the PWM channel amplifier bits [7:5] of MFR_PWM_COMP, and the internal R TH compensation resistor , bits[4:0] of MFR_PWM_COMP. Be sure to es - tablish these settings prior to compensation calculation. The I TH series internal R TH external C TH filter sets the dominant pole-zero loop compensation. The internal RTH value can be modified (from 0Ω to 62kΩ) using bits[4:0] of the MFR_PWM_ COMP command. Adjust the value of R TH to optimize transient response once the final PCB layout is done and the particular C TH filter capacitor and output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1μs to 10μs will produce output volt- age and I TH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET with a resistor to ground directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce to a load step. The MOSFET + R SERIES will produce output currents approximately equal to V OUT/RSERIES. R SERIES values from 0.1Ω to 2Ω are valid depending on the current limit settings and the programmed output voltage. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the I TH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing R TH and the bandwidth of the loop will be increased by decreasing CTH. If RTH is increased by the same factor that C TH is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The gain of the loop will be proportional to the transconductance of the error amplifier which is set using bits[7:5] of the MFR_PWM_COMP command. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. A second, more severe transient is caused by switching in loads with large (>1μF ) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of C LOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • C LOAD. Thus a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA.

3884fe For more information www.linear .com/L TC3884 PolyPhase Configuration When configuring a PolyPhase rail with multiple LTC3884s, the user must share the SYNC, I TH, ITHR, SHARE_CLK, FAUL T, and ALERT pins of these parts. Be sure to use pull- up resistors on FAUL T, SHARE_CLK and ALERT. One of the part’s SYNC pins must be set to the desired switching frequency, and all other FREQUENCY_SWITCH commands must be set to External Clock. If an external oscillator is provided, set the FREQUENCY_SWITCH command to External Clock for all parts. The relative phasing of all the channels should be spaced equally. The MFR_RAIL_ ADDRESS of all the devices should be set to the same value. When connecting a PolyPhase rail with LTC3884 s, connect the VIN pins of the LTC3884s directly back to the supply voltage through the VIN pin filter networks. Master Slave Operation LTC3884 (as Master) can work with LTC3874 (as slave) very efficiently to deliver very large output currents. LTC3874 is a very small simple device, which has two current loops, but no PMBus, and no voltage loops. Both LTC3884 and LTC3874 devices are mainly designed for low DCR applications, and with the same relationship between V ITH vs VISENSE (see Figure 40). Figure 40 is the schematic of a 3+1 application using a LTC3884 and a LTC3874. LTC3884 channel 0 provides V OUT0 of 1.5V and 30A output current, and channel 1 together with channel 0 and channel 1 in the LTC3874 to provide VOUT1 of 1.0V, with 90A output current. Both chips are programmed to be LOW DCR configuration, and channel1 of LTC3884 and channel 0/1 of the LTC3874 are programmed to have the same current limit. Connecting I TH1 of LTC3884 with ITH0 and ITH1 of LTC3874 together forms three current loops. The voltage loop inside the LTC3884 regulates I TH1, which then regulates all three current loops with the same gain and current limit, and ultimately delivers the same amount of current per phase. Programming the phase of each channel properly, these three channels form a perfect PolyPhase configuration. APPLICATIONS INFORMATION

Figure 40. Master/Slave 3 +1 High Efficiency, Low DCR Sense, 425kHz, Dual-Output, 1.5V/30A and 1.0V/90A Buck Converter (LTC3884/LTC3874)

3884 TA05

3884fe For more information www.linear .com/L TC3884 APPLICATIONS INFORMATION RL1D1 L1SW1 RSENSE1 VOUT1 COUT1 VIN CIN RIN RL0D0BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. L0SW0

3884 F40b

Figure 41b. Branch Current Waveforms L TC3884 PGND/SGND IIN– ISENSE+ ISENSE– VIN VDD25 VDD33 ITH ITHR VSENSE– VSENSE+ RUN SYNC TSNS TG SW BOOST BG INTVCC IIN+ VIN RIINSNS L 1µF CERAMIC CB

3884 F40a

Figure 41a. Recommended Printed Circuit Layout Diagram, Single Phase Shown

3884feFor more information www.linear .com/L TC3884 APPLICATIONS INFORMATION PC BOARD LAYOUT CHECKLIST When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 41a. Figure 41b illustrates the current waveforms present in the various branches of a synchronous regulator operating in continuous mode. Check the following in your layout: Is the top N-channel MOSFET , M1, located within 1cm of CIN? 2. Are signal ground and power ground kept separate? The ground return of CINTVCC must return to the combined COUT (–) terminals. 3. The ITH trace should be as short as possible. 4. The loop formed by the top N-channel MOSFET, Schottky diode and the C IN capacitor should have short leads and PC trace lengths. 5. Th e output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described in item 4. Are the I SENSE+ and I SENSE– leads routed together with minimum PC trace spacing? The filter capacitor between I SENSE+ and I SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor or inductor, whichever is used for current sensing. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the power ground pins? This capacitor carries the MOSFET driver current peaks. An additional 1µF ceramic capacitor placed immediately next to the INTV CC and GND pins can help improve noise performance substantially. 8. Keep the switching nodes (SWn ), top gate nodes (TGn), and boost nodes (BOOSTn) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” of the LTC3884 and occupy minimum PC trace area. If DCR sensing is used, place the top resistor (Figure 25a, R1) close to the switching node. PC BOARD LAYOUT DEBUGGING It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SWn pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper performance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB implementation. Variation in the duty cycle at a subharmonic rate can sug- gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. Overcompensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Reduce V IN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher out- put currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOSTn , SWn, TGn, and possibly BGn connections and the sensitive volt- age and current pins. The capacitor placed across the cur- rent sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the GND pin of the IC.

3884fe For more information www.linear .com/L TC3884 APPLICATIONS INFORMATION DESIGN EXAMPLE As a design example for a 2-channel medium current regulator , assume VIN = 12V nominal, VIN = 20V maximum, VOUT0 = 3.3V, VOUT1 = 1.5V, IMAX0,1 = 30A and f = 500kHz. The regulated output is established by the VOUT_ COMMAND stored in NVM or placing the following resis- tor divider between V DD25 the RCONFIG pin and SGND: 1. VOUT0_CFG, RTOP = 10k, RBOTTOM = 15.8k 2. VOUT1_CFG, RTOP = 20k, RBOTTOM = 17.8k The frequency and phase are set by NVM or by setting the resistor divider between V DD25 FREQ_CFG and SGND and VDD25 PHASE_CFG and SGND. Frequency RTOP = 24.9kΩ and RBOTTOM = 5.76kΩ Phase RTOP = open and RBOTTOM = 0Ω The address is set to XF where X is the MSB stored in NVM. The following parameters are set as a percentage of the output voltage if the resistor configuration pins are used to determined output voltage: All other user defined parameters must be programmed into the NVM. The GUI can be utilized to quickly set up the part with the desired operating parameters. The inductance values are based on a 28% maximum ripple current assumption (8.4A). The highest value of ripple current occurs at the maximum input voltage: L = VOUT f •ΔIL(MAX) 1– VOUT VIN(MAX) Channel 0 will require 0.68μH and channel 1 will require 0.33μH. respectively. At the nominal input the ripple will be: ΔIL(NOM) = VOUT f •L 1– VOUT VIN(NOM) Channel 0 will have 8.1A (27%) ripple, and channel 1 will have 8.4A (28%) ripple. The peak inductor current will be the maximum DC value plus one-half the ripple current or 34A for channel 0 and 34.2A for channel 1. The minimum on time occurs on channel 1 at the maximum V IN, and should not be less than 60ns: tON(MIN) = VOUT VIN(MAX) • f= 1.5V 20V •500kHz = 150ns The next design focuses on only Channel1. The Würth 744301033 0.33μH (0.32mΩ DCR TYP at 25°C) is used for channel 1. So IOUT_CAL_GAIN = 0.32mΩ. Based on the output current and inductor value, it is con- sidered to be a perfect example of low DCR application. Set: MFR_PWM_MODE[2] = 1 then choose C = 220nF, R1 = L/(DCR • C • 5) = 937Ω Choose R1 = 931Ω. The maximum power loss in R1 is related to the duty cycle, and will occur in continuous mode at the maximum input voltage: PLOSSR1= VIN(MAX) – VOUT( ) • VOUT = 20−1.5( ) •1.5 931 = 29.8mW The current limit will be set 20% higher than the peak value to assure variation in components and noise in the system do not limit the average current. V ILIMIT = IPEAK • RDCR(MAX) = (1 + 20%) • 34.2A • 0.32mΩ = 13.1mV Based on Figure 26, set MFR_PWM_MODE[2], [7] = 1,0 and IOUT_CAL_GAIN = 0.32mΩ in GUI, and enter the value with IOUT_OC_FAULT_LIMIT = 41.04A, the LTC3884 will automatically set the current limit to 40.64A, based on the IOUT_FAULT_LIMIT table, (see PMBus command for details).

3884feFor more information www.linear .com/L TC3884 APPLICATIONS INFORMATION The power dissipation on the topside MOSFET can be eas- ily estimated. Choose a INFINEON BSC050NE2LS topside MOSFET. RDS(ON) = 7.1mΩ, CMILLER = 35pF. At maximum input voltage with T estimated = 75°C and a bottom side MOSFET a INFINEON BSC010NE2LSI, R DS(ON) = 1.1mΩ: PMAIN = 1.5V

0.0071Ω+ 20V 5.5– 2.8 + 1 2.8 ⎝⎜ ⎞ ⎠⎟ 35pF( ) 500kHz( ) = 751 mW The loss in the bottom side MOSFET is: PSYNC = 20V –1.5V 20V • 30A( ) 2 • ⎦•0.001Ω =11.04W Both MOSFETS have I2R losses while the PMAIN equation includes an additional term for transition losses, which are highest at high input voltages. C IN is chosen for an RMS current rating of: CIN Required IRMS = 34.2/12 • (3.3 • (12– 3.3))1/2 = 15A COUT is chosen with an ESR of 0.006Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is: VORIPPLE = RESR • (∆IL) = 0.006Ω • 8.1 ≈ 48.6mV ADDITIONAL DESIGN CHECKS Tie FAUL T0 and FAUL T1 together and pull up to VDD33 with a 10k resistor . Tie RUN0 and RUN1 together and pull up to VDD33 with a 10k resistor . If there are other ADI PSM parts, connect the RUN pins between chips and connect the FAUL T pins between chips. Be sure all PMBus pins have resistor pull-up to V DD33 and connect these inputs across all ADI PSM parts in the application. Tie SHARE_CLK high with a 4.99k resistor to V DD33 and share between all ADI PSM parts in the application. Be sure a unique address for each chip can be decoded with the ASEL0 and ASEL1 pins. Refer to Table 6. For maximum flexibility, allow board space for R TOP and RBOTTOM for any parameter that is set with resistors such as ASEL0 and ASEL1. CONNECTING THE USB TO I2C/SMBus/PMBus CONTROLLER TO THE LTC3884 IN SYSTEM The ADI USB-to-I2C/SMBus/PMBus adapter (DC1613A or equivalent) can be interfaced to the LTC3884 on the user’s board for programming, telemetry and system debug. The adapter , when used in conjunction with L TpowerPlay, provides a powerful way to debug an entire power sys - tem. Faults are quickly diagnosed using telemetry, fault status commands and the fault log. The final configura - tion can be quickly developed and stored to the LTC3884 EEPROM. Figure 42 illustrates the application schematic for powering, programming and communication with one or more LTC3884s via the ADI I2C/SMBus/PMBus adapter regardless of whether or not system power is present. If system power is not present the dongle will power the LTC3884 through the V DD33 supply pin. To initialize the part when VIN is not applied and the VDD33 pin is powered use global address 0x5B command 0xBD data 0x2B fol - lowed by address 0x5B command 0xBD data 0xC4.The LTC3884 can now communicate with, and the project file can be updated. To write the updated project file to the NVM issue a STORE_USER _ALL command. When V IN is applied, a MFR_RESET must be issued to allow the PWM to be enabled and valid ADCs to be read. Because of the adapter’s limited current sourcing capability, only the LTC3884s, their associated pull-up resistors and the I 2C pull-up resistors should be powered from the ORed 3.3V supply. In addition any device sharing the I 2C bus connections with the LTC3884 should not have body diodes between the SDA/SCL pins and their respective V DD node because this will interfere with bus communication in the absence of system power . If V IN is applied, the DC1613A will not supply the power to the LTC3884s on the board. It is recommended the RUNn pins be held low or no voltage configuration resistors inserted to avoid providing power to the load until the part is fully configured.

system or to diagnose power issues when bring up rails. set of device drivers and documentation. as shown in Figure 44, Write Command Data Processing.

3884 F41

Figure 42. Controller Connection

Figure 43. L TpowerPlay Screen Shot

3884 F43

Figure 44. Write Command Data Processing

Figure 45. Example of a Command Write of VOUT_COMMAND for the VOUT_COMMAND register is provided in Figure 45.

will respond to read commands as if PAGE were set to 0x00 (Channel 0 results). This command has one data byte. may be sent with PAGE_PLUS_WRITE. a non-paged command, the Page Number byte is ignored. mand that has two data bytes is shown in Figure 46.

3884 F45

Figure 46. Example of PAGE_PLUS_WRITE the data returned by the command, all in one communication packet .

data from a non-paged command, the Page Number byte is ignored.

3884 F46

Figure 47. Example of PAGE_PLUS_READ fault for Invalid/Unsupported Data. EE_UNLOCK, and STORE_USER_ALL commands. respective bits in the STATUS commands. Enable writes to all commands when WRITE_PROTECT is set to 0x00.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS MFR_ADDRESS The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device. Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B, cannot be deactivated. If RCONFIG is set to ignore, the ASEL0 and ASEL1 pins are still used to determine the LSB and MSB, respectively, of the channel address. If the ASEL0 and ASEL1 pins are both open, the LTC3884 will use the address value stored in NVM. If the ASEL0 pin is open, the LTC3884 will use the lower 4 bits of the MFR_ADDRESS value stored in NVM to construct the effective address of the part. If the ASEL1 pin is open, the LTC3884 will use the upper 4 bits of the MFR_ADDRESS value stored in NVM to construct the effective address of the part. This command has one data byte. MFR_RAIL_ADDRESS The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value of this command should be common to all devices attached to a single power supply rail. The user should only perform command writes to this address. If a read is performed from this address and the rail devices do not respond with EXACTL Y the same value, the LTC3884 will detect bus contention and may set a CML communications fault. Setting this command to a value of 0x80 disables rail device addressing for the channel. This command has one data byte. GENERAL CONFIGURATION COMMANDS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_CHAN_CONFIG 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1D MFR_CONFIG_ALL 0xD1 General configuration bits. R/W Byte N Reg Y 0x21 MFR_CHAN_CONFIG General purpose configuration command common to multiple ADI products. BIT MEANING

7 Reserved

6 Reserved

5 Reserved

4 Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF . 3 Enable Short Cycle recognition if this bit is set to a 1. 2 SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled. 1 No FAUL T ALERT, ALERT is not pulled low if FAUL T is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are propagated on FAUL T.

0 Disables the V

OUT decay value requirement for MFR_RETRY_TIME and tOFF(MIN) processing. When this bit is set to a 0, the output must decay to less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low to high. This command has one data byte.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS A shortCycle event occurs whenever the PWM channel is commanded back ON, or reactivated, after the part has been commanded OFF and is processing either the TOFF_DELAY or the TOFF_FALL states. The PWM channel can be turned ON and OFF through either the RUN pin and or the PMBus OPERATION command. If the PWM channel is reactivated during the TOFF_DELAY, the part will perform the following: 1. Immediately tri-state the PWM channel output; 2. Start the retry delay timer as specified by the tOFF(MIN). 3. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_ MFR_SPECIFIC bit #1 will assert. If the PWM channel is reactivated during the TOFF_FALL, the part will perform the following: 1. Stop ramping down the PWM channel output; 2. Immediately tri-state the PWM channel output; 3. Start the retry delay timer as specified by the tOFF(MIN). 4. After the tOFF(MIN) value has expired, the PWM channel will proceed to the TON_DELAY state and the STATUS_ MFR_SPEFIFIC bit #1 will assert. If the SHORT Cycle event occurs and the ShortCycle MFR_CHAN_CONFIG bit is not set, the PWM channel state machine will complete its TOFF_DELAY and TOFF_FALL operations as previously commanded by the user . MFR_CONFIG_ALL General purpose configuration command common to multiple ADI products. BIT MEANING 7 Enable Fault Logging. 6 Ignore Resistor Configuration Pins. 5 Mask PMBus, PartII, Section 10.9.1 Violations. 4 Disable SYNC output. 3 Enable 255ms PMBus timeout. 2 PMBus command writes require a valid Packet Error Checking, PEC, byte to be accepted.* 1 Enable the use of PMBus clock stretching. 0 Execute CLEAR_FAULTS on rising edge of either RUN pin. *PMBus command writes that have a valid PEC byte are always processed. PMBus command writes that have an invalid PEC byte are not processed and set a CML status fault. This command has one data byte. ON/OFF/MARGIN COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE ON_OFF_CONFIG 0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte Y Reg Y 0x1E OPERATION 0x01 Operating mode control. On/off, margin high and margin low. R/W Byte Y Reg Y 0x80 MFR_RESET 0xFD Commanded reset without requiring a power-down. Send Byte N NA

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS ON_OFF_CONFIG The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to turn the PWM channel on and off. Supported Values: VALUE MEANING 0x1F OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off. 0x1E OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off. 0x17 RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored. 0x16 RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored. Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored. This command has one data byte. OPERATION The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOL TAGEs. The unit stays in the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation command is sequence off. If V IN is applied to a part with factory default programming and the VOUT_CONFIG resistor configuration pins are not installed, the outputs will be commanded off. The part defaults to the Sequence Off state. This command has one data byte. Supported Values: VALUE MEANING 0xA8 Margin high. 0x98 Margin low. 0x80 On (V OUT back to nominal even if bit 3 of ON_OFF_CONFIG is not set). 0x40* Soft off (with sequencing). 0x00* Immediate off (no sequencing). *Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set. Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored. This command has one data byte. MFR_RESET This command provides a means to reset the LTC3884 from the serial bus. This forces the LTC3884 to turn off both PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of both PWM channels, if enabled. This write-only command has no data bytes.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS PWM CONFIGURATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_PWM_COMP 0xD3 PWM loop compensation configuration R/W Byte Y Reg Y 0xAE MFR_PWM_MODE 0xD4 Configuration for the PWM engine. R/W Byte Y Reg Y 0xC7 MFR_PWM_CONFIG 0xF5 Set numerous parameters for the DC/DC controller including phasing. R/W Byte N Reg Y 0x10 FREQUENCY_SWITCH 0x33 Switching frequency of the controller . R/W Word N L11 kHz Y 425 0xFB52 MFR_PWM_MODE The MFR_PWM_MODE command sets important PWM controls for each channel. The MFR_PWM_MODE command allows the user to program the PWM controller to use discontinuous (pulse-skipping mode), or forced continuous conduction mode. BIT MEANING Use High Range of ILIMIT Low Current Range High Current Range

6 Enable Servo Mode

5 External temperature sense:

∆VBE measurement. 1: Direct voltage measurement. [4:3] Reserved

2 Enable ultra-low DCR current sense

V OUT Range The maximum output voltage is 2.75V The maximum output voltage is 5.5V Bit[0] Mode Discontinuous Forced Continuous Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault. Bit [6] The LTC3884 will not servo while the part is OFF , ramping on or ramping off. When set to a one, the output servo is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC and the VOUT_COMMAND (or the appropriate margined value). When Bit[5] is cleared, the LTC3884 computes temperature in °C from ∆V BE measured by the ADC at the TSNSn pin as T = (G • When Bit[5] is set, the LTC3884 computes temperature in °C from TSNSn voltage measured by the ADC as

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS For both equations, G = MFR_TEMP_1_GAIN • 2–14, and O = MFR_TEMP_1_OFFSET Bit[2] determines if the part uses sub-milliohm DCR for sensing the output current. This is a very critical selection in terms of overcurrent limit. It is highly recommend that Bit[2] should not be changed when device is in operation. Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes the PWM loop gain and compensation. This bit value should not be changed when the channel output is active. Writing this bit when the channel is active will generate a CML fault. Bit[0] determines if the PWM mode of operation is discontinuous (pulse-skipping mode), or forced continuous con - duction mode. Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this bit. This command has one data byte. MFR_PWM_COMP The MFR_PWM_COMP command sets the g m of the PWM channel error amplifiers and the value of the internal RITHn compensation resistors. This command affects the loop gain of the PWM output which may require modifications to the external compensation network. BIT MEANING BIT [7:5] Error Amplifier GM Adjust (mS) 000b 1.00 001b 1.68 010b 2.35 011b 3.02 100b 3.69 101b 4.36 110b 5.04 111b 5.73 BIT [4:0] RITH (kΩ) 00000b 0 00001b 0.25 00010b 0.5 00011b 0.75 00100b 1 00101b 1.25 00110b 1.5 00111b 1.75 01000b 2 01001b 2.5 01010b 3 01011b 3.5 01100b 4 01101b 4.5 01110b 5

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS 01111b 5.5 10000b 6 10001b 7 10010b 8 10011b 9 10100b 11 10101b 13 10110b 15 10111b 17 11000b 20 11001b 24 11010b 28 11011b 32 11100b 38 11101b 46 11110b 54 11111b 62 This command has one data byte. MFR_PWM_CONFIG The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the channels must be commanded off. If either channel is in the RUN state and this command is written, the command will be NACK’d and a BUSY fault will be asserted. BIT MEANING [6:5] 00b 01b 10b 11b Input current sense gain. 2x gain. 0mV to 50mV range. 4x gain. 0mV to 20mV range. 8x gain. 0mV to 5mV range. Reserved

4 Share Clock Enable : If this bit is 1, the

SHARE_CLK pin will not be released until V IN > VIN_ON. The SHARE_CLK pin will be pulled low when VIN < VIN_OFF. If this bit is 0, the SHARE_CLK pin will not be pulled low when VIN < VIN_OFF except for the initial application of VIN. BIT [2:0] CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES) 000b 0 180 001b 90 270 010b 0 240 011b 0 120 100b 120 240 101b 60 240 110b 120 300

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS FREQUENCY_SWITCH The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of the LTC3884. Supported Frequencies: VALUE [15:0] RESUL TING FREQUENCY (TYP) 0x0000 External Oscillator 0xF3E8 250kHz 0xFABC 350kHz 0xFB52 425kHz 0xFBE8 500kHz 0x023F 575kHz 0x028A 650kHz 0x02EE 750kHz 0x03E8 1000kHz The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be detected as the PLL locks onto the new frequency. This command has two data bytes and is formatted in Linear_5s_11s format. VOL TAGE Input Voltage and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VIN_OV_FAULT_LIMIT 0x55 Input supply overvoltage fault limit. R/W Word N L11 V Y 15.5 0xD3E0 VIN_UV_WARN_LIMIT 0x58 Input supply undervoltage warning limit. R/W Word N L11 V Y 6.3 0xCB26 VIN_ON 0x35 Input voltage at which the unit should start power conversion. R/W Word N L11 V Y 6.5 0xCB40 VIN_OFF 0x36 Input voltage at which the unit should stop power conversion. R/W Word N L11 V Y 6.0 0xCB00 MFR_RVIN 0xF7 The resistance value of the V IN pin filter element in milliohms R/W Word N L11 mΩ Y 1000 0x03E8 VIN_OV_FAULT_LIMIT The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes an input overvoltage fault. This command has two data bytes in Linear_5s_11s format.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS VIN_UV_WARN_LIMIT The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input under- voltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON command and the unit has been enabled. If the VIN Voltage drops below the VIN_OV_WARN_LIMIT the device:

Sets the INPUT Bit Is the STATUS_WORD
Sets the VIN Undervoltage Warning Bit in the STATUS_INPUT Command
Notifies the Host by Asserting ALER T, unless Masked VIN_ON The VIN_ON command sets the input voltage, in Volts, at which the unit starts power conversion. This command has two data bytes and is formatted in Linear_5s_11s format. VIN_OFF The VIN_OFF command sets the input voltage, in Volts, at which the unit stops power conversion. This command has two data bytes and is formatted in Linear_5s_11s format. MFR_RVIN The MFR_RVIN command is used to set the resistance value of the V IN pin filter element in milliohms. (See also READ_VIN). Set MFR_RVIN equal to 0 if no filter element is used. This command has two data bytes and is formatted in Linear_5s_11s format. Output Voltage and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VOUT_MODE 0x20 Output voltage format and exponent (2–12). R Byte Y Reg 2–12 0x14 VOUT_MAX 0x24 Upper limit on the output voltage the unit can command regardless of any other commands. R/W Word Y L16 V Y 2.75 0x2C00 VOUT_OV_FAULT_ LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1 0x119A VOUT_OV_WARN_ LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075 0x1133 VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. Must be greater than VOUT_ COMMAND. R/W Word Y L16 V Y 1.05 0x10CD VOUT_COMMAND 0x21 Nominal output voltage set point. R/W Word Y L16 V Y 1.0 0x1000 VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. Must be less than VOUT_ COMMAND. R/W Word Y L16 V Y 0.95 0x0F33 VOUT_UV_WARN_ LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925 0x0ECD VOUT_UV_FAULT_ LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 0.9 0x0E66 MFR_VOUT_MAX 0xA5 Maximum allowed output voltage. R Word Y L16 V 5.7 0x5B33

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS VOUT_MODE The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode (only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write commands. This read-only command has one data byte. VOUT_MAX The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can com - mand regardless of any other commands or combinations. The maximum allowed value of this command is 5.8V. The maximum output voltage the LTC3884 can produce is 5.5V including VOUT_MARGIN_HIGH. However , the VOUT_OV_FAULT_LIMIT can be commanded as high as 5.7V. This command has two data bytes and is formatted in Linear_16u format. VOUT_OV_FAULT_LIMIT The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor compara- tor at the sense pins, in volts, which causes an output overvoltage fault. If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modi - fied to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of MFR_COMMON . Either bit is low if the part is busy. If this wait time is not honored and the VOUT_COMMAND is modified above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and possible damage to the switcher . If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAUL T pin will not assert if VOUT_OV_FAULT is propagated. The LTC3884 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected. This command has two data bytes and is formatted in Linear_16u format. VOUT_OV_WARN_LIMIT The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value can be used to determine if this limit has been exceeded. In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:

Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
Sets the VOUT bit in the STATUS_WORD
Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
Notifies the host by asserting ALERT pin, unless masked This condition is detected by the ADC so the response time may be up to t CONVERT. This command has two data bytes and is formatted in Linear_16u format.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS VOUT_MARGIN_HIGH The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in Volts, when the OPERATION command is set to “Margin High”. The value should be greater than VOUT_COMMAND. The maximum guaranteed value on VOUT_MARGIN_HIGH is 5.5V. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_COMMAND The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed value on VOUT is 5.5V. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_MARGIN_LOW The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts, when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND. This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE will be used if this command is modified while the output is active and in a steady-state condition. This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_WARN_LIMIT The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins, in volts, which causes an output voltage low warning. In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:

Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
Sets the VOUT bit in the STATUS_WORD
Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_16u format. VOUT_UV_FAULT_LIMIT The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor com - parator at the sense pins, in volts, which causes an output undervoltage fault. This command has two data bytes and is formatted in Linear_16u format.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS MFR_VOUT_MAX The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_ LIMIT. If the output voltages are set to high range (Bit 1 of MFR_PWM_MODE set to a 0) MFR_VOUT_MAX is 5.5V. If the output voltage is set to low range (Bit 1 of MFR_PWM_MODE set to a 1) the MFR_VOUT_MAX is 2.75V. Entering a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting will be clamped to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT command being set. This read only command has 2 data bytes and is formatted in Linear_16u format. OUTPUT CURRENT AND LIMITS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE IOUT_CAL_GAIN 0x38 The ratio of the voltage at the current sense pins to the sensed current. For devices using a fixed current sense resistor , it is the resistance value in mΩ. R/W Word Y L11 mΩ Y 0.32 0xAA8F MFR_IOUT_CAL_GAIN_TC 0xF6 Temperature coefficient of the current sensing element. R/W Word Y CF Y 3900 0x0F3C IOUT_OC_FAULT_LIMIT 0x 46 Output overcurrent fault limit. R/W Word Y L11 A Y 45.0 0xE2D0 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 34.0 0xE230 IOUT_CAL_GAIN The IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms. (see also MFR_IOUT_CAL_GAIN_TC). This command has two data bytes and is formatted in Linear_5s_11s format. MFR_IOUT_CAL_GAIN_TC The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_GAIN sense resistor or inductor DCR in ppm/°C. This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 • –6. Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by: [1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)]. DCR sensing will have a typical value of 3900. The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT, MFR_IOUT_PEAK, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS IOUT_OC_FAULT_LIMIT The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in Amperes. When the control- ler is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The following table lists the progammable peak output current limit value in mV between I SENSE+ and ISENSE–. The actual value of current limit is (ISENSE+ – ISENSE–)/IOUT_CAL_GAIN in Amperes. CODE MFR_PWM_MODE[2]=1 (Sub-milli Ω DCR) L RC = 5 • DCR MFR_PWM_MODE[2]=0 (Normal Value of DCR) L RC = DCR MFR_PWM_MODE[7]=1 High Current Range (mV) MFR_PWM_MODE[7]=0 Low Current Range (mV) MFR_PWM_MODE[7]=1 High Current Range (mV) MFR_PWM_MODE[7]=0 Low Current Range (mV) 0000 15.45 8.59 38.64 21.46 0001 16.59 9.22 41.48 23.04 0010 17.73 9.85 44.32 24.62 0011 18.86 10.48 47.16 26.20 0100 20.42 11.34 51.04 28.36 0101 21.14 11.74 52.84 29.36 0110 22.27 12.37 55.68 30.93 0111 23.41 13.01 58.52 32.51 1000 24.55 13.64 61.36 34.09 1001 25.68 14.27 64.20 35.67 1010 26.82 14.90 67.05 37.25 1011 27.95 15.53 69.89 38.83 1100 29.50 16.50 74.50 41.38 1101 30.23 16.79 75.57 41.98 1110 31.36 17.42 78.41 43.56 1111 32.50 18.06 81.25 45.14 Note: Only VILIMIT codes 2–8 are supported for DCR sensing. Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation: Peak Current Limit = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)). The LTC3884 automatically convert currents to the appropriate internal bit value. The IOUT range is set with bit 7 of the MFR_PWM_MODE command. The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL. If the IOUT_OC_FAULT_LIMIT is exceeded, the device:

Sets the IOUT bit in the STATUS word
Sets the IOUT Overcurrent fault bit in the STATUS_IOUT
Notifies the host by asserting ALERT, unless masked This command has two data bytes and is formatted in Linear_5s_11s format.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS IOUT_OC_WARN_LIMIT This command sets the value of the output current measured by the ADC that causes an output overcurrent warning in Amperes. The READ_IOUT value will be used to determine if this limit has been exceeded. In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:

Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
Sets the IOUT bit in the STATUS_WORD
Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
Notifies the host by asserting ALERT pin, unless masked The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL. This command has two data bytes and is formatted in Linear_5s_11s format Input Current and Limits COMMAND NAME CMD CODE DESCRIPTION TYPE DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_IIN_CAL_GAIN 0xE8 The resistance value of the input current sense element in mΩ. R/W Word L11 mΩ Y 5.000 0xCA80 MFR_IIN_CAL_GAIN The MFR_IIN_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms. (see also READ_IIN). This command has two data bytes and is formatted in Linear_5s_11s format. COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE IIN_OC_WARN_LIMIT 0x5D Input overcurrent warning limit. R/W Word N L11 A Y 10.0 0xD280 IIN_OC_WARN_LIMIT The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded. In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
Sets the OTHER bit in the STATUS_BYTE
Sets the INPUT bit in the upper byte of the STATUS_WORD
Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command, and
Notifies the host by asserting ALERT pin This command has two data bytes and is formatted in Linear_5s_11s format.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS TEMPERATURE External Temperature Calibration COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_TEMP_1_GAIN 0xF8 Sets the slope of the external temperature sensor . R/W Word Y CF Y 1.0 0x4000 MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the external temperature sensor . R/W Word Y L11 C Y 0.0 0x8000 MFR_TEMP_1_GAIN The MFR_TEMP_1_GAIN command will modify the slope of the external temperature sensor to account for non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor . This command has two data bytes and is formatted in 16-bit 2’s complement integer . The effective gain adjustment is N • 2–14. The nominal value is 1. MFR_TEMP_1_OFFSET The MFR_TEMP_1_OFFSET command will modify the offset of the external temperature sensor to account for non- idealities in the element and errors associated with the remote sensing of the temperature in the inductor . This command has two data bytes and is formatted in Linear_5s_11s format. External Temperature Limits COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 C Y 100.0 0xEB20 OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 C Y 85.0 0xEAA8 UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 C Y –40.0 0xE580 OT_FAULT_LIMIT The OT_FAULT_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. This command has two data bytes and is formatted in Linear_5s_11s format. OT_WARN_LIMIT The OT_WARN_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS In response to the OT_WARN_LIMIT being exceeded, the device:

Sets the TEMPERATURE bit in the STATUS_BYTE
Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
Notifies the host by asserting ALERT pin, unless masked This command has two data bytes and is formatted in Linear_5s_11s format. UT_FAULT_LIMIT The UT_FAULT_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees Celsius, which causes an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded. Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response set to ignore to avoid ALERT being asserted. This command has two data bytes and is formatted in Linear_5s_11s format. TIMING Timing—On Sequence/Ramp COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE TON_DELAY 0x60 Time from RUN and/or Operation on to output rail turn-on. R/W Word Y L11 ms Y 0.0 0x8000 TON_RISE 0x61 Time from when the output starts to rise until the output voltage reaches the VOUT commanded value. R/W Word Y L11 ms Y 8.0 0xD200 TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_ RISE for VOUT to cross the VOUT_UV_ FAULT_LIMIT. R/W Word Y L11 ms Y 10.0 0xD280 VOUT_TRANSITION_RATE 0x27 Rate the output changes when VOUT commanded to a new value. R/W Word Y L11 V/ms Y 0.25 0xAA00 TON_DELAY The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of 270µs for TON_DELAY = 0 and an uncertainty of ±50µs for all values of TON_DELAY. This command has two data bytes and is formatted in Linear_5s_11s format. TON_RISE The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during TON_RISE events. If TON_RISE is less than 0.25ms, the LTC3884 digital slope will be bypassed and the output voltage transition will only be controlled by the analog performance of the PWM switcher . The number of steps in TON_RISE is equal to TON_RISE (in ms)/0.1ms with an uncertainty of ±0.1ms. This command has two data bytes and is formatted in Linear_5s_11s format.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS TON_MAX_FAULT_LIMIT The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely. The maximum limit is 83 seconds. This command has two data bytes and is formatted in Linear_5s_11s format. VOUT_TRANSITION_RATE When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the output voltage to change this command set the rate in V/ms at which the output voltage changes. The commanded rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms. This command has two data bytes and is formatted in Linear_5s_11s format. Timing—Off Sequence/Ramp COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start of TOFF_FALL ramp. R/W Word Y L11 ms Y 0.0 0x8000 TOFF_FALL 0x65 Time from when the output starts to fall until the output reaches zero volts. R/W Word Y L11 ms Y 8.0 0xD200 TOFF_MAX_WARN_LIMIT 0x 66 Maximum allowed time, after TOFF_FALL completed, for the unit to decay below 12.5%. R/W Word Y L11 ms Y 150 0xF258 TOFF_DELAY The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of 270µs for TOFF_DELAY = 0 and an uncertainty of ±50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied when a fault event occurs This command has two data bytes and is formatted in Linear_5s_11s format. TOFF_FALL The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt- age is commanded to zero. It is the ramp time of the V OUT DAC. When the VOUT DAC is zero, the PWM output will be set to high impedance state. The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate. fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty of ±0.1ms. In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by the output capacitance and load current. This command has two data bytes and is formatted in Linear_5s_11s format.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS TOFF_MAX_WARN_LIMIT The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the output voltage exceeds 12.5% of the programmed voltage before a warning is asserted. The output is considered off when the V OUT voltage is less than 12.5% of the programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete. A data value of 0ms means that there is no limit and that the output voltage exceeds 12.5% of the programmed voltage indefinitely. Other than 0, values from 120ms to 524 seconds are valid. This command has two data bytes and is formatted in Linear_5s_11s format. Precondition for Restart COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_RESTART_ DELAY 0xDC Minimum time the RUN pin is held low by the LTC3884. R/W Word Y L11 ms Y 500 0xFBE8 MFR_RESTART_DELAY This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms. Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_ FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time, set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_ RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG and the output takes a long time to decay below 12.5% of the programmed value. This command has two data bytes and is formatted in Linear_5s_11s format. FAUL T RESPONSE Fault Responses All Faults COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_RETRY_ DELAY 0xDB Retry interval during FAUL T retry mode. R/W Word Y L11 ms Y 350 0xFABC MFR_RETRY_DELAY This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 10µs increments. Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of MFR_CHAN_CONFIG. This command has two data bytes and is formatted in Linear_5s_11s format.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS Fault Responses Input Voltage COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VIN_OV_FAULT_RESPONSE 0x56 Action to be taken by the device when an input supply overvoltage fault is detected. R/W Byte Y Reg Y 0x80 VIN_OV_FAULT_RESPONSE The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input over - voltage fault. The data byte is in the format given in Table 11. The device also:

Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
Set the INPUT bit in the upper byte of the STATUS_WORD
Sets the VIN Over voltage Fault bit in the STATUS_INPUT command, and
Notifies the host by asserting ALERT pin, unless masked This command has one data byte. Fault Responses Output Voltage COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an output overvoltage fault is detected. R/W Byte Y Reg Y 0xB8 VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an output undervoltage fault is detected. R/W Byte Y Reg Y 0xB8 TON_MAX_FAULT_ RESPONSE 0x63 Action to be taken by the device when a TON_MAX_FAULT event is detected. R/W Byte Y Reg Y 0xB8 VOUT_OV_FAULT_RESPONSE The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output overvoltage fault. The data byte is in the format given in Table 7. The device also:
Sets the VOUT_OV bit in the STATUS_BYTE
Sets the VOUT bit in the STATUS_WORD
Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
Notifies the host by asserting ALERT pin, unless masked The only values recognized for this command are: 0x00–Part performs OV pull down only, or OV_PULLDOWN. 0x80–The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7).

condition causes the unit to shut down. manded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7. removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7. Any other value will result in a CML fault and the write will be ignored. This command has one data byte. Table 7. VOUT_OV_FAULT_RESPONSE Data Byte Contents

Sets the corresponding fault bit in the status commands and
Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
The device receives a CLEAR_FAULTS command.
The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
Bias power is removed and reapplied to the LTC3884.

00 Part performs OV pull down only or OV_PULLDOWN

01 The PMBus device continues operation for the delay time

10 The device shuts down immediately (disables the output) and

responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault.

111 The PMBus device attempts to restart continuously, without

detected. Only valid for deglitched off state. undervoltage fault. The data byte is in the format given in Table 8.

Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
Sets the VOUT bit in the STATUS_WORD

Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
Notifies the host by asserting ALERT pin, unless masked The UV fault and warn are masked until the following criteria are achieved: 1) The TON_MAX_FAULT_LIMIT has been reached 2) The TON_DELAY sequence has completed 3) The TON_RISE sequence has completed 4) The VOUT_UV_FAULT_LIMIT threshold has been reached 5) The IOUT_OC_FAULT_LIMIT is not present The UV fault and warn are masked whenever the channel is not active. The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing. This command has one data byte.

Table 8. VOUT_UV_FAULT_RESPONSE Data Byte Contents

Sets the corresponding fault bit in the status commands and
Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
The device receives a CLEAR_FAULTS command.
The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
The device receives a RESTORE_USER_ALL command.
The device receives a MFR_RESET command.
The device supply power is cycled. 00 The PMBus device continues operation without interruption. (Ignores the fault functionally)

10 The device shuts down (disables the output) and responds

according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. detected. Only valid for deglitched off state.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS TON_MAX_FAULT_RESPONSE The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX fault. The data byte is in the format given in Table 11. The device also:

Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
Sets the VOUT bit in the STATUS_WORD
Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
Notifies the host by asserting ALERT pin, unless masked A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0. Note: The PWM channel remains in discontinues mode until the TON_MAX_FAULT_LIMIT has been exceeded. This command has one data byte. Fault Responses Output Current COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE IOUT_OC_FAULT_RESPONSE 0x47 Action to be taken by the device when an output overcurrent fault is detected. R/W Byte Y Reg Y 0x00 IOUT_OC_FAULT_RESPONSE The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output overcurrent fault. The data byte is in the format given in Table 9. The device also:
Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
Sets the IOUT_OC bit in the STATUS_BYTE
Sets the IOUT bit in the STATUS_WORD
Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
Notifies the host by asserting ALERT pin, unless masked This command has one data byte.

Table 9. IOUT_OC_FAULT_RESPONSE Data Byte Contents

Sets the corresponding fault bit in the status commands and
Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
The device receives a CLEAR_FAULTS command.
The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
The device receives a RESTORE_USER_ALL command.
The device receives a MFR_RESET command.
The device supply power is cycled.

00 The LTC3884 continues to operate indefinitely while maintaining

current or brick-wall limiting).

10 The LTC3884 continues to operate, maintaining the output

regard to the output voltage, for the delay time set by bits [2:0].

11 The LTC3884 shuts down immediately and responds as

programmed by the Retry Setting in bits [5:3].

111 The device attempts to restart continuously, without limitation,

is set by the MFR_RETRY_DELAY command. down. Only valid for deglitched off response. internal overtemperature fault is detected. overtemperature fault. The data byte is in the format given in Table 10.

Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
Sets the MFR bit in the STATUS_WORD, and
Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
Notifies the host by asserting ALERT pin, unless masked This command has one data byte.

Table 10. Data Byte Contents MFR_OT_FAULT_RESPONSE

Sets the corresponding fault bit in the status commands and
Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
The device receives a CLEAR_FAULTS command.
The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
Bias power is removed and reapplied to the LTC3884. 00 Not supported. Writing this value will generate a CML fault. 01 Not supported. Writing this value will generate a CML fault

responds according to the retry setting in bits [5:3]. 11 The device’s output is disabled while the fault is present. disabled until the fault is cleared. 001-111 Not supported. Writing this value will generate CML fault. external undertemperature fault is detected. perature fault on the external temp sensors. The data byte is in the format given in Table 11.

Sets the TEMPERA TURE bit in the STATUS_BYTE
Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
Notifies the host by asserting ALERT pin, unless masked This command has one data byte. UT_FAULT_RESPONSE The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external under - temperature fault on the external temp sensors. The data byte is in the format given in Table 11. The device also:
Sets the TEMPERA TURE bit in the STATUS_BYTE
Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
Notifies the host by asserting ALERT pin, unless masked

This condition is detected by the ADC so the response time may be up to tCONVERT. This command has one data byte. Table 11. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,

Sets the corresponding fault bit in the status commands, and
Notifies the host by asserting ALERT pin, unless masked. The fault bit, once set, is cleared only when one or more of the following events occurs:
The device receives a CLEAR_FAULTS command.
The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERATION command, to turn off and then to turn back on, or
The device receives a RESTORE_USER_ALL command.
The device receives a MFR_RESET command.
The device supply power is cycled. 00 The PMBus device continues operation without interruption. 01 Not supported. Writing this value will generate a CML fault.

responds according to the retry setting in bits [5:3]. 11 Not supported. Writing this value will generate a CML fault. are propagated to the FAUL T pins. This command has two data bytes.

3884feFor more information www.linear .com/L TC3884 Table 12: FAUL Tn Propagate Fault Configuration The FAUL T0 and FAUL T1 pins are designed to provide electrical notification of selected events to the user . Some of these events are common to both output channels. Others are specific to an output channel. They can also be used to share faults between channels. BIT(S) SYMBOL OPERATION B[15] VOUT disabled while not decayed. This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTC3884 is a zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF , and then the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT will not restart until the 12.5% decay is honored. The FAUL T pin is asserted during this condition if bit 15 is asserted. B[14] Mfr_fault_propagate_short_CMD_cycle 0: No action 1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high t OFF(MIN) after sequence off. b[13] Mfr_fault_propagate_ton_max_fault 0: No action if a TON_MAX_FAULT fault is asserted 1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted FAUL T0 is associated with page 0 TON_MAX_FAULT faults FAUL T1 is associated with page 1 TON_MAX_FAULT faults b[12] Reserved b[11] Mfr_fault0_propagate_int_ot, Mfr_fault1_propagate_int_ot 0: No action if the MFR_OT_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted b[10] Reserved b[9] Reserved b[8] Mfr_fault0_propagate_ut, Mfr_fault1_propagate_ut 0: No action if the UT_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted FAUL T0 is associated with page 0 UT faults FAUL T1 is associated with page 1 UT faults b[7] Mfr_fault0_propagate_ot, Mfr_fault1_propagate_ot 0: No action if the OT_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted FAUL T0 is associated with page 0 OT faults FAUL T1 is associated with page 1 OT faults b[6] Reserved b[5] Reserved b[4] Mfr_fault0_propagate_input_ov, Mfr_fault1_propagate_input_ov 0: No action if the VIN_OV_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted b[3] Reserved b[2] Mfr_fault0_propagate_iout_oc, Mfr_fault1_propagate_iout_oc 0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted FAUL T0 is associated with page 0 OC faults FAUL T1 is associated with page 1 OC faults b[1] Mfr_fault0_propagate_vout_uv, Mfr_fault1_propagate_vout_uv 0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted FAUL T0 is associated with page 0 UV faults FAUL T1 is associated with page 1 UV faults b[0] Mfr_fault0_propagate_vout_ov, Mfr_fault1_propagate_vout_ov 0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted 1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted FAUL T0 is associated with page 0 OV faults FAUL T1 is associated with page 1 OV faults PMBus COMMAND DETAILS

3884fe For more information www.linear .com/L TC3884 Fault Sharing Response COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the FAUL T pin is asserted low. R/W Byte Y Reg Y 0xC0 MFR_FAULT_RESPONSE The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAUL Tn pin being pulled low by an external source. Supported Values: VALUE MEANING 0xC0 FAULT_INHIBIT The LTC3884 will three-state the output in response to the FAUL T pin pulled low. 0x00 FAULT_IGNORE The LTC3884 continues operation without interruption. The device also: Sets the MFR Bit in the STATUS_WORD.

Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAUL Tn Is Being Pulled Low
Notifies the Host by Asserting ALER T, Unless Masked This command has one data byte. SCRATCHPAD COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE USER_DATA_00 0xB0 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA USER_DATA_01 0xB1 Manufacturer reserved for L TpowerPlay. R/W Word Y Reg Y NA USER_DATA_02 0xB2 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA USER_DATA_03 0xB3 A NVM word available for the user . R/W Word Y Reg Y 0x0000 USER_DATA_04 0xB4 A NVM word available for the user . R/W Word N Reg Y 0x0000 PMBus COMMAND DETAILS

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS USER_DATA_00 through USER_DATA_04 These commands are non-volatile memory locations for customer storage. The customer has the option to write any value to the USER_DATA_nn at any time. However , the L TpowerPlay software and contract manufacturers use some of these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable inventory control and incompatibility with these products. These commands have 2 data bytes and are in register format. IDENTIFICATION COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE PMBus_REVISION 0x98 PMBus revision supported by this device. Current revision is 1.2. R Byte N Reg FS 0x22 CAPABILITY 0x19 Summary of PMBus optional communication protocols supported by this device. R Byte N Reg 0xB0 MFR_ID 0x99 The manufacturer ID of the LTC3884 in ASCII. R String N ASC LT C MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC LTC3884 MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTC3884. R Word N Reg 0x4C0X PMBus_REVISION The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTC3884 is PMBus Version 1.2 compliant in both Part I and Part II. This read-only command has one data byte. CAPABILITY This command provides a way for a host system to determine some key capabilities of a PMBus device. The LTC3884 supports packet error checking, 400kHz bus speeds, and ALERT pin. This read-only command has one data byte. MFR_ID The MFR_ID command indicates the manufacturer ID of the LTC3884 using ASCII characters. This read-only command is in block format. MFR_MODEL The MFR_MODEL command indicates the manufacturer’s part number of the LTC3884 using ASCII characters. This read-only command is in block format. MFR_SPECIAL_ID The 16-bit word representing the part name and revision. 0x4C denotes the part is an LTC3884, XX is adjustable by the manufacturer . This read-only command has two data bytes.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS FAUL T WARNING AND STATUS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM DEFAUL T VALUE CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte N NA SMBALERT_MASK 0x1B Mask activity. Block R/W Y Reg Y See CMD Details MFR_CLEAR_PEAKS 0xE3 Clears all peak values. Send Byte Y NA STATUS_BYTE 0x78 One byte summary of the unit’s fault condition. R/W Byte Y Reg NA STATUS_WORD 0x79 T wo byte summary of the unit’s fault condition. R/W Word Y Reg NA STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA STATUS_IOUT 0x7B Output current fault and warning status. R/W Byte Y Reg NA STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg NA STATUS_ TEMPERATURE 0x7D External temperature fault and warning status for READ_TEMERATURE_1. R/W Byte Y Reg NA STATUS_CML 0x7E Communication and memory fault and warning status. R/W Byte N Reg NA STATUS_MFR_ SPECIFIC 0x80 Manufacturer specific fault and state information. R/W Byte Y Reg NA MFR_INFO 0xB6 Manufacturing specific information. R Word N Reg NA MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg NA MFR_COMMON 0xEF Manufacturer status bits that are common across multiple ADI chips. R Byte N Reg NA CLEAR_FAULTS The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault occurs within that time frame it may be cleared before the status register is set. This write-only command has no data bytes. The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut down for a fault condition are restarted when: The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin and OPERA TION command, to turn off and then to turn back on, or

MFR_RESET command is issued.
Bias power is removed and reapplied to the integrated circuit

bits would continue to assert ALERT if set. of any supported status register , again without PEC. SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS_LTC3884. SMBALERT_MASK will generate a CML for Invalid/Unsupported Data.

3884 F48

3884 F47

Figure 48. Example of Writing SMBALERT_MASK Figure 49. Example of Reading SMBALERT_MASK This write-only command has no data bytes.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS STATUS_BYTE The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the lower byte of the status word. STATUS_BYTE Message Contents: BIT STATUS BIT NAME MEANING 7* BUSY A fault was declared because the LTC3884 was unable to respond. 6 OFF This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not being enabled. 5 VOUT_OV An output overvoltage fault has occurred. 4 IOUT_OC An output overcurrent fault has occurred. 3 VIN_UV Not supported (LTC3884 returns 0). 2 TEMPERATURE A temperature fault or warning has occurred. 1 CML A communications, memory or logic fault has occurred. 0 NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred. This command has one data byte. STATUS_WORD The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the STATUS_WORD is the same as the STATUS_BYTE command. STATUS_WORD High Byte Message Contents: BIT STATUS BIT NAME MEANING 15 VOUT An output voltage fault or warning has occurred. 14 IOUT An output current fault or warning has occurred. 13 INPUT An input voltage fault or warning has occurred. 12 MFR_SPECIFIC A fault or warning specific to the LTC3884 has occurred. 11 POWER_GOOD# The POWER_GOOD state is false if this bit is set. 10 FANS Not supported (LTC3884 returns 0). 9 OTHER Not supported (LTC3884 returns 0). 8* UNKNOWN Not supported (LTC3884 returns 0). *ALERT can be asserted if either of these bits is set. It may be cleared by writing a 1 to its bit position in the STATUS_BYTE, in lieu of a CLEAR_FAULTS command. If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted. This command has two data bytes.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS STATUS_VOUT The STATUS_VOUT command returns one byte of VOUT status information. STATUS_VOUT Message Contents: BIT MEANING 7 V OUT overvoltage fault. 6 V OUT overvoltage warning. 5 V OUT undervoltage warning. 4 V OUT undervoltage fault. 3 V OUT max warning. 2 TON max fault. 1 TOFF max fault. 0 Not supported (LTC3884 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. STATUS_IOUT The STATUS_IOUT command returns one byte of IOUT status information. STATUS_IOUT Message Contents: BIT MEANING 7 I OUT overcurrent fault. 6 Not supported (LTC3884 returns 0). 5 I OUT overcurrent warning. 4:0 Not supported (LTC3884 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS STATUS_INPUT The STATUS_INPUT command returns one byte of VIN (VINSNS) status information. STATUS_INPUT Message Contents: BIT MEANING 7 V IN overvoltage fault. 6 Not supported (LTC3884 returns 0). 5 V IN undervoltage warning. 4 Not supported (LTC3884 returns 0).

3 Unit off for insufficient V

IN. 2 Not supported (LTC3884 returns 0). 1 I IN overcurrent warning. 0 Not supported (LTC3884 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not generate an ALERT even if it is set. This command has one data byte. STATUS_TEMPERATURE The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged command and is related to the respective READ_TEMPERATURE_1 value. STATUS_TEMPERATURE Message Contents: BIT MEANING 7 External overtemperature fault. 6 External overtemperature warning. 5 Not supported (LTC3884 returns 0). 4 External undertemperature fault. 3:0 Not supported (LTC3884 returns 0). The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. This command has one data byte.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS STATUS_CML The STATUS_CML command returns one byte of status information on received commands, internal memory and logic. STATUS_CML Message Contents: BIT MEANING 7 Invalid or unsupported command received. 6 Invalid or unsupported data received. 5 Packet error check failed. 4 Memory fault detected. 3 Processor fault detected. 2 Reserved (LTC3884 returns 0). 1 Other communication fault. 0 Other memory or logic fault. If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued operation of the part is not recommended if these bits are continuously set. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte. STATUS_MFR_SPECIFIC The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information. The format for this byte is: BIT MEANING 7 Internal Temperature Fault Limit Exceeded. 6 Internal Temperature Warn Limit Exceeded. 5 Factory T rim Area NVM CRC Fault.

4 PLL is Unlocked

3 Fault Log Present

1 ShortCycle Event Detected

0 FAUL T Pin Asserted Low by External Device

If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted. The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear status by means other than using the CLEAR_FAULTS command. However , the fault log present bit can only be cleared by issuing the MFR_FAULT_LOG_CLEAR command. Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS MFR_PADS This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit assignments of this command are as follows: BIT ASSIGNED DIGITAL PIN

15 V DD33 OV Fault

14 V DD33 UV Fault

13 Reserved

12 Reserved

11 ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation

10 SYNC clocked by external device (when LTC3884 configured to drive SYNC pin)

9 Channel 1 Power Good

8 Channel 0 Power Good

7 LTC3884 Driving RUN1 Low

6 LTC3884 Driving RUN0 Low

5 RUN1 Pin State

4 RUN0 Pin State

3 LTC3884 Driving FAUL T1 Low

2 LTC3884 Driving FAUL T0 Low

1 FAUL T1 Pin State

0 FAUL T0 Pin State

A 1 indicates the condition is true. This read-only command has two data bytes. MFR_COMMON The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products. BIT MEANING

7 Chip Not Driving ALERT Low

6 LTC3884 Not Busy

5 Calculations Not Pending

4 LTC3884 Outputs Not in T ransition

3 NVM Initialized

2 Reserved

1 SHARE_CLK Timeout

0 WP Pin Status

This read-only command has one data byte.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS MFR_INFO The MFR_INFO command contains additional status bits that are LTC3884-specific and may be common to multiple ADI PSM products. MFR_INFO Data Contents: BIT MEANING 15:5 Reserved. 4 EEPROM ECC status. 0: Corrections made in the EEPROM user space. 1: No corrections made in the EEPROM user space. 3:0 Reserved EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM bulk read operation. This read-only command has two data bytes. TELEMETRY COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM DEFAUL T VALUE READ_VIN 0x88 Measured input supply voltage. R Word N L11 V NA READ_IIN 0x89 Measured input supply current. R Word N L11 A NA READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA READ_IOUT 0x8C Measured output current. R Word Y L11 A NA READ_TEMPERATURE_1 0x8D External diode junction temperature. This is the value used for all temperature related processing, including IOUT_CAL_GAIN. R Word Y L11 C NA READ_TEMPERATURE_2 0x8E Internal junction temperature. Does not affect any other commands. R Word N L11 C NA READ_FREQUENCY 0x95 Measured PWM switching frequency. R Word Y L11 Hz NA READ_POUT 0x96 Calculated output power . R Word Y L11 W NA READ_PIN 0x97 Calculated input power . R Word N L11 W NA MFR_PIN_ACCURACY 0xAC Returns the accuracy of the READ_PIN command R Byte N % 5.0% MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_IOUT since last MFR_CLEAR_PEAKS. R Word Y L11 A NA MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since last MFR_CLEAR_PEAKS. R Word Y L16 V NA MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last MFR_CLEAR_PEAKS. R Word N L11 V NA MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external Temperature (READ_TEMPERATURE_1) since last MFR_CLEAR_PEAKS. R Word Y L11 C NA MFR_READ_IIN_PEAK 0xE1 Maximum measured value of READ_IIN command since last MFR_CLEAR_PEAKS. R Word N L11 A NA MFR_READ_ICHIP 0xE4 Measured current used by the LTC3884. R Word N L11 A NA MFR_TEMPERATURE_2_PEAK 0xF4 Peak internal die temperature since last MFR_CLEAR_PEAKS. R Word N L11 C NA MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated fast ADC read back. R/W Byte N N Reg NA

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS READ_VIN The READ_VIN command returns the measured V IN pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This compensates for the IR voltage drop across the VIN filter element due to the supply current of the LTC3884. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_VOUT The READ_VOUT command returns the measured output voltage by the VOUT_MODE command. This read-only command has two data bytes and is formatted in Linear_16u format. READ_IIN The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor (see also MFR_IIN_CAL_GAIN). This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_IOUT The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of: a) the differential voltage measured across the I SENSE pins b) the IOUT_CAL_GAIN value c) the MFR_IOUT_CAL_GAIN_TC value, and d) READ_TEMPERATURE_1 value e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_TEMPERATURE_1 The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_TEMPERATURE_2 The READ_TEMPERATURE_2 command returns the LTC3884’s die temperature, in degrees Celsius, of the internal sense element. This read-only command has two data bytes and is formatted in Linear_5s_11s format. READ_FREQUENCY The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. READ_POUT The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on the most recent correlated output voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS READ_PIN The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the most recent input voltage and current reading. This read-only command has 2 data bytes and is formatted in Linear_5s_11s format. MFR_PIN_ACCURACY The MFR_PIN_ACCURACY command returns the accuracy, in percent, of the value returned by the READ_PIN command. This read-only command has one data byte and is formatted as an unsigned integer . MFR_IOUT_PEAK The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_VOUT_PEAK The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_16u format. MFR_VIN_PEAK The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_TEMPERATURE_1_PEAK The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_1 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_READ_IIN_PEAK The MFR_READ_IIN_PEAK command reports the highest current, in Amperes, reported by the READ_IIN measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This command has two data bytes and is formatted in Linear_5s_11s format. MFR_READ_ICHIP The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTC3884. This command has two data bytes and is formatted in Linear_5s_11s format.

3884fe For more information www.linear .com/L TC3884 PMBus COMMAND DETAILS MFR_TEMPERATURE_2_PEAK The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_2 measurement. This command is cleared using the MFR_CLEAR_PEAKS command. This read-only command has two data bytes and is formatted in Linear_5s_11s format. MFR_ADC_CONTROL The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of t CONVERT. The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms. This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled. COMMANDED VALUE TELEMETRY COMMAND NAME DESCRIPTION 0x0F Reserved 0x0E Reserved 0x0D Reserved 0x0C READ_TEMPERATURE_1 Channel 1 external temperature 0x0B Reserved 0x0A READ_IOUT Channel 1 measured output current 0x09 READ_VOUT Channel 1 measured output voltage 0x08 READ_TEMPERATURE_1 Channel 0 external temperature 0x07 Reserved 0x06 READ_IOUT Channel 0 measured output current 0x05 READ_VOUT Channel 0 measured output voltage 0x04 READ_TEMPERATURE_2 Internal junction temperature 0x03 READ_IIN Measured input supply current 0x02 MFR_READ_ICHIP Measured supply current of the LTC3884 0x01 READ_VIN Measured input supply voltage 0x00 Standard ADC Round Robin Telemetry If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault. CML faults will continue to be issued by the LTC3884 until a valid command value is entered. The accuracy of the measured input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round robin telemetry. This write-only command has 1 data byte and is formatted in register format.

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS NVM MEMORY COMMANDS Store/Restore COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM DEFAUL T VALUE STORE_USER_ALL 0x15 Store user operating memory to EEPROM. Send Byte N NA RESTORE_USER_ALL 0x16 Restore user operating memory from EEPROM. Send Byte N NA MFR_COMPARE_USER_ALL 0xF0 Compares current command contents with NVM. Send Byte N NA STORE_USER_ALL The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating Memory to the matching locations in the non-volatile User NVM memory. Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data reten- tion of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled. The command is re-enabled when the IC temperature drops below 125°C. Communication with the LTC3884 and programming of the NVM can be initiated when EXTVCC or VDD33 is available and VIN is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B followed by 0xC4. The LTC3884 will now communicate normally, and the project file can be updated. To write the updated project file to the NVM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be issued to allow the PWM to be enabled and valid ADCs to be read. This write-only command has no data bytes. RESTORE_USER_ALL The RESTORE_USER_ALL command instructs the LTC3884 to copy the contents of the non-volatile User memory to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value retrieved from the User commands. The LTC3884 ensures both channels are off, loads the operating memory from the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both PWM channels if applicable. STORE_USER_ALL, MFR_COMPARE_USER_ALL and RESTORE_USER_ALL commands are disabled if the die exceeds 130°C and are not re-enabled until the die temperature drops below 125°C. This write-only command has no data bytes. MFR_COMPARE_USER_ALL The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated. This write-only command has no data bytes.

for reading at a later time. As a consequence of adding ECC, the area in the EEPROM available for fault log is reduced. sixth events are a repeat of the fourth event.

3884 F49

Figure 50. Fault Log Conceptual Diagram

NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock. This read-only command is in block format. This write-only command has no data bytes. Table 13. Fault Logging This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command. Fault Log Preface [7:0] ASC 0 Returns L Txx beginning at byte 0 if a partial or complete fault log exists. Fault Source [7:0] Reg 4 Refer to Table 13a. MFR_REAL_TIME [7:0] Reg 5 48 bit share-clock counter value when fault occurred (200µs resolution).

3884fe For more information www.linear .com/L TC3884 MFR_VOUT_PEAK (PAGE 0) [15:8] L16 11 Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS command. [7:0] 12 MFR_VOUT_PEAK (PAGE 1) [15:8] L16 13 Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS command. [7:0] 14 MFR_IOUT_PEAK (PAGE 0) [15:8] L11 15 Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS command. [7:0] 16 MFR_IOUT_PEAK (PAGE 1) [15:8] L11 17 Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS command. [7:0] 18 MFR_VIN_PEAK [15:8] L11 19 Peak READ_VIN since last power-on or CLEAR_PEAKS command. [7:0] 20 READ_TEMPERATURE1 (PAGE 0) [15:8] L11 21 External temperature sensor 0 during last event. [7:0] 22 READ_TEMPERATURE1 (PAGE 1) [15:8] L11 23 External temperature sensor 1 during last event. [7:0] 24 READ_TEMPERATURE2 [15:8] L11 25 LTC3884 die temperature sensor during last event. [7:0] 26 CYCLICAL DATA EVENT n (Data at Which Fault Occurred; Most Recent Data) Event “n” represents one complete cycle of ADC reads through the MUX at time of fault. Example: If the fault occurs when the ADC is processing step 15, it will continue to take readings through step 25 and then store the header and all 6 event pages to EEPROM READ_VOUT (PAGE 0) [15:8] LIN 16 27 [7:0] LIN 16 28 READ_VOUT (PAGE 1) [15:8] LIN 16 29 [7:0] LIN 16 30 READ_IOUT (PAGE 0) [15:8] LIN 11 31 [7:0] LIN 11 32 READ_IOUT (PAGE 1) [15:8] LIN 11 33 [7:0] LIN 11 34 READ_VIN [15:8] LIN 11 35 [7:0] LIN 11 36 READ_IIN [15:8] LIN 11 37 [7:0] LIN 11 38 STATUS_VOUT (PAGE 0) BYTE 39 STATUS_VOUT (PAGE 1) BYTE 40 STATUS_WORD (PAGE 0) [15:8] WORD 41 [7:0] WORD 42 STATUS_WORD (PAGE 1) [15:8] WORD 43 [7:0] WORD 44 STATUS_MFR_SPECIFIC (PAGE 0) BYTE 45 STATUS_MFR_SPECIFIC (PAGE 1) BYTE 46 PMBus COMMAND DETAILS

3884feFor more information www.linear .com/L TC3884 PMBus COMMAND DETAILS EVENT n-1 (data measured before fault was detected) READ_VOUT (PAGE 0) [15:8] LIN 16 47 [7:0] LIN 16 48 READ_VOUT (PAGE 1) [15:8] LIN 16 49 [7:0] LIN 16 50 READ_IOUT (PAGE 0) [15:8] LIN 11 51 [7:0] LIN 11 52 READ_IOUT (PAGE 1) [15:8] LIN 11 53 [7:0] LIN 11 54 READ_VIN [15:8] LIN 11 55 [7:0] LIN 11 56 READ_IIN [15:8] LIN 11 57 [7:0] LIN 11 58 STATUS_VOUT (PAGE 0) BYTE 59 STATUS_VOUT (PAGE 1) BYTE 60 STATUS_WORD (PAGE 0) [15:8] WORD 61 [7:0] WORD 62 STATUS_WORD (PAGE 1) [15:8] WORD 63 [7:0] WORD 64 STATUS_MFR_SPECIFIC (PAGE 0) BYTE 65 STATUS_MFR_SPECIFIC (PAGE 1) BYTE 66 EVENT n-5 (Oldest Recorded Data) READ_VOUT (PAGE 0) [15:8] LIN 16 127 [7:0] LIN 16 128 READ_VOUT (PAGE 1) [15:8] LIN 16 129 [7:0] LIN 16 130 READ_IOUT (PAGE 0) [15:8] LIN 11 131 [7:0] LIN 11 132 READ_IOUT (PAGE 1) [15:8] LIN 11 133 [7:0] LIN 11 134 READ_VIN [15:8] LIN 11 135 [7:0] LIN 11 136 READ_IIN [15:8] LIN 11 137 [7:0] LIN 11 138 STATUS_VOUT (PAGE 0) BYTE 139 STATUS_VOUT (PAGE 1) BYTE 140 STATUS_WORD (PAGE 0) [15:8] WORD 141 [7:0] WORD 142 STATUS_WORD (PAGE 1) [15:8] WORD 143 [7:0] WORD 144 STATUS_MFR_SPECIFIC (PAGE 0) BYTE 145 STATUS_MFR_SPECIFIC (PAGE 1) BYTE 146

3884fe For more information www.linear .com/L TC3884 Table 13a: Explanation of Position_Fault Values POSITION_FAULT VALUE SOURCE OF FAUL T LOG 0xFF MFR_FAULT_LOG_STORE 0x00 TON_MAX_FAULT Channel 0 0x01 VOUT_OV_FAULT Channel 0 0x02 VOUT_UV_FAULT Channel 0 0x03 IOUT_OC_FAULT Channel 0 0x05 TEMP_OT_FAULT Channel 0 0x06 TEMP_UT_FAULT Channel 0 0x07 VIN_OV_FAULT 0x0A MFR_TEMPERATURE_2_OT_FAULT 0x10 TON_MAX_FAULT Channel 1 0x11 VOUT_OV_FAULT Channel 1 MFR_FAULT_LOG_CLEAR The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear . This write-only command is send bytes. Block Memory Write/Read COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAUL T VALUE MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access by MFR_EE_ERASE and MFR_EE_DATA commands. R/W Byte N Reg NA MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk programming by MFR_EE_DATA. R/W Byte N Reg NA MFR_EE_DATA 0xBF Data transferred to and from EEPROM using sequential PMBus word reads or writes. Supports bulk programming. R/W Word N Reg NA All the NVM commands are disabled if the die temperature exceeds 130°C. NVM commands are re-enabled when the die temperature drops below 125°C. MFR_EE_xxxx The MFR_EE_xxxx commands facilitate bulk programming of the LTC3884 internal EEPROM. Contact the factory for details. PMBus COMMAND DETAILS

3884feFor more information www.linear .com/L TC3884 TYPICAL APPLICATIONS Low DCR Sensing, 425kHz, High Efficiency, Dual-Output 1.5V/30A and 1.0V/30A, Buck Converter 10nF 150pF 1/uni03A9 0.1µF BSC050NE2LS 0.1µF BSC010NE2LSI BSC050NE2LS BSC010NE2LSI 2m/uni03A9 1µF 270µF 16V 4.99k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 0.33µH 931/uni03A9 220nF 330µF 6.3V 100µF 6.3V 1500pF 2.2µF 1µF 10nF 150pF 1500pF 10µF 4.7µF 0.25µH 715/uni03A9 220nF 330µF 6.3V 100µF 6.3V 20k 17.8k 24.9k 5.76k 10µF INTVCC L TC3884 VIN VDD33 VDD33 IIN+ IIN– TG0 BOOST0 SW0 BG0 SYNC PGOOD0 PGOOD1 SDA SCL ALERT FAUL T0 FAUL T1 SHARE_CLK RUN0 RUN1 WP TSNS0 ISENSE0+ ISENSE0– VSENSE0+ VSENSE0– ITH0 ITHR0 PGND GND VDD25 VDD25 TG1 BOOST1 SW1 BG1 VOUT0_CFG VOUT1_CFG ASEL0 ASEL1 FREQ_CFG PHASE_CFG TSNS1 ISENSE1– ISENSE1+ VSENSE1+ VSENSE1– ITH1 ITHR1 EXTVCC VIN 6V to 14V VDD33 744301033 DCR=0.32 m/uni03A9 VOUT0 1.5V/30A MMBT3906-AL3-R MMBT3906-AL3-R D1, D2: CMDSH3-TR 744301025 DCR=0.32 m/uni03A9 V DD25 VOUT1 1.0V/30A

3884 TA02

3884fe For more information www.linear .com/L TC3884 TYPICAL APPLICATIONS 10nF 100pF 0.1µF BSC050NE2LS 0.1µF BSC010NE2LSI BSC050NE2LS BSC010NE2LSI 2m/uni03A9 1µF 270µF 16V 10k 10k 10k 10k 4.99k 10k 10k 10k 0.25µH 0.25µH 715/uni03A9 220nF 330µF 6.3V 100µF 6.3V 100µF 6.3V 100µF 6.3V 4.7nF 2.2µF 1µF 10nF 10µF 10µF 715/uni03A9 220nF 330µF 6.3V 24.9k 4.32k 330µF 6.3V 4.7µF 24.9k 5.76k INTVCC L TC3884 VIN VDD33 IIN+ IIN– TG0 BOOST0 SW0 BG0 SYNC PGOOD0 PGOOD1 SDA SCL ALERT FAUL T0 FAUL T1 SHARE_CLK RUN0 RUN1 WP SYNC PGOOD SDA SCL ALERT FAUL T SHARECLK RUN PGND SGND V DD25 TG1 BOOST1 SW1 BG1 V OUT0 _CFG V OUT1 _CFG ASEL1 ASEL0 FREQ_CFG PHASE_CFG TSNS1 I SENSE1– I SENSE1+ VSENSE1+ VSENSE1– ITH1 ITHR1 EXTVCC 1/uni03A9 VDD33 744301025 DCR = 0.32m/uni03A9 DCR = 0.32m/uni03A9 MMBT3906-AL3-R MMBT3906-AL3-R 744301025 VDD33 VDD25 D1, D2, D3, D4: CMDSH3-TR

3889 F40

1.0V/120A ISENSE0+ ISENSE0– 10nF 0.1µF BSC050NE2LS 0.1µF BSC010NE2LSI BSC050NE2LS Q10 BSC010NE2LSI 2m/uni03A9 1µF 270µF 16V 0.25µH 0.25µH 715/uni03A9 220nF 100µF 6.3V 2.2µF 1µF 10nF 10µF 10µF 715/uni03A9 220nF 330µF 6.3V 24.9k 5.76k 4.7µF 20k 11k 24.9k 5.76k INTVCC L TC3884 VIN VDD33 IIN+ IIN– TG0 BOOST0 SW0 BG0 SYNC PGOOD0 PGOOD1 SDA SCL ALERT FAUL T0 FAUL T1 SHARE_CLK RUN0 RUN1 WP SYNC PGOOD SDA SCL ALERT FAUL T SHARECLK RUN PGND SGND V DD25 TG1 BOOST1 SW1 BG1 V OUT0 _CFG V OUT1 _CFG ASEL1 ASEL0 FREQ_CFG PHASE_CFG TSNS1 I SENSE1– I SENSE1+ VSENSE1+ VSENSE1– ITH1 ITHR1 EXTVCC 1/uni03A9 744301025 DCR = 0.32m/uni03A9 DCR = 0.32m/uni03A9 MMBT3906-AL3-R MMBT3906-AL3-R 744301025 VDD33_1 VDD25_1 VDD25_1 ISENSE0+ ISENSE0– VIN 6V TO 14V VSENSE0+ VSENSE0– TSNS0 ITH0 ITHR0 VSENSE0+ VSENSE0– TSNS0 I TH0 ITHR0 4 Phase, 500kHz, High Efficiency, Single-Output, 1.0V/120A Buck Converter

3884feFor more information www.linear .com/L TC3884 High Efficiency, 425kHz, Dual-Output, 2.5V/25A and 3.3V/25A Buck Converter TYPICAL APPLICATIONS 10nF 150pF 1/uni03A9 0.1µF BSC032NE2LS 0.1µF BSC010NE2LSI BSC024NE2LS BSC010NE2LSI 2m/uni03A9 1µF 270µF 16V 4.99k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 0.68µH 976/uni03A9 220nF 330µF 6.3V 1500pF 2.2µF 1µF 10nF 150pF 1500pF 10µF 4.7µF 0.9µH 4.52k 220nF 330µF 6.3V 10µF 16.2k 20.5k 10k 15.8k 24.9k 5.76k 2m/uni03A9 100µF 6.3V 100µF 6.3V INTVCC L TC3884 VIN VDD33 VDD33 VDD25 IIN+ IIN– TG0 BOOST0 SW0 BG0 SYNC PGOOD0 PGOOD1 SDA SCL ALERT FAUL T0 FAUL T1 SHARE_CLK RUN0 RUN1 WP TSNS0 ISENSE0+ ISENSE0– VSENSE0+ VSENSE0– ITH0 ITHR0 PGND SGND V DD25 TG1 BOOST1 SW1 BG1 VOUT0_CFG VOUT1_CFG ASEL0 ASEL1 FREQ_CFG PHASE_CFG TSNS1 ISENSE1– ISENSE1+ VSENSE1+ VSENSE1– ITH1 ITHR1 EXTVCC VIN 7V to 14V VDD33 SER2009-681ML DCR=0.63 m/uni03A9 VOUT0 2.5V/25A MMBT3906-AL3-R MMBT3906-AL3-R SER2010-901ML DCR=0.9 m/uni03A9 VDD25 VOUT1 3.3V/25A D1, D2: CMDSH3-TR

3884 TA06

3884fe For more information www.linear .com/L TC3884 Low DCR Sensing, 250kHz, Single-Output, 5V/60A Buck Converter TYPICAL APPLICATIONS 10nF 150pF 1/uni03A9 0.1µF BSC024NE2LS 0.1µF BSC010NE2LSI BSC024NE2LS BSC010NE2LSI 2m/uni03A9 1µF 270µF 16V 4.99k 10k 10k 10k 10k 10k 10k 10k 1µH 3.74k 220nF 330µF 6.3V 100µF 6.3V 3.3nF 2.2µF 1µF 10nF 10µF 4.7µF 1µH 3.74k 220nF 330µF 6.3V 100µF 6.3V 10k 23.2k 30.1k 1.96k 10µF 2m/uni03A9 INTVCC L TC3884 VIN VDD33 VDD33 IIN+ IIN– TG0 BOOST0 SW0 BG0 SYNC PGOOD0 PGOOD1 SDA SCL ALERT FAUL T0 FAUL T1 SHARE_CLK RUN0 RUN1 WP TSNS0 ISENSE0+ ISENSE0– VSENSE0+ VSENSE0– ITH0 ITHR0 PGND SGND V DD25 TG1 BOOST1 SW1 BG1 VOUT0_CFG VOUT1_CFG ASEL0 ASEL1 FREQ_CFG PHASE_CFG TSNS1 ISENSE1– ISENSE1+ VSENSE1+ VSENSE1– ITH1 ITHR1 EXTVCC VIN 10V to 14V VDD33 SER2011-102ML DCR=1.2 m/uni03A9 MMBT3906-AL3-R MMBT3906-AL3-R D1, D2: CMDSH3-TR

3884 TA08

DCR=1.2 m/uni03A9 V DD25 VOUT 5.0V/60A SER2011-102ML 24.9k 5.76k V DD25

3884feFor more information www.linear .com/L TC3884 TYPICAL APPLICATIONS High Efficiency, 425kHz, Single-Output 1.0V/80A Buck Converter with Power Blocks INTVCC INTVCC 1/uni03A9 1µF 270µF 16V 4.99k 10k 10k 10k 10k 10k 10k 10k 47nF 330µF 6.3V 100µF 6.3V 3.3nF 150pF 2.2µF 1µF 4.7µF 47nF 24.9k 24.9k 4.32k 2m/uni03A9 0.1µF 0.1µF 10µF 10µF INTVCC L TC3884 VIN VDD33 IIN+ IIN– TG0 BOOST0 SW0 BG0 SYNC PGOOD0 PGOOD1 SDA SCL ALERT FAUL T0 FAUL T1 SHARE_CLK RUN0 RUN1 WP TSNS0 ISENSE0+ ISENSE0– VSENSE0+ VSENSE0– ITH0 ITHR0 PGND SGND VDD25 VDD25 TG1 BOOST1 SW1 BG1 V OUT0 _CFG V OUT1 _CFG ASEL1 ASEL0 FREQ_CFG PHASE_CFG TSNS1 ISENSE1– ISENSE1+ VSENSE1+ VSENSE1– ITH1 ITHR1 EXTVCC VIN 7V to 13V VDD33 V DD25 V IN1 V IN2 PWMH PWML VGATE GND GND GND GND TEMP_P TEMP_N C_N C_P V OUT1 V OUT2 VRA001-4C3G V IN1 V IN2 PWMH PWML VGATE GND GND GND GND TEMP_P TEMP_N C_N C_P V OUT1 V OUT2 VRA001-4C3G VOUT 1.0V/80A INTVCC VDD33 5.76k 330µF 6.3V 100µF 6.3V

3884 TA09

3884fe For more information www.linear .com/L TC3884 Low DCR Sensing, 500kHz 4-Phase 1.05 Step-Down Converter TYPICAL APPLICATIONS

3884 TA10

4.7µF FREQ L TC3874-1 ITH0 ITH1 ITH RUN0 RUN1 FAUL T0 FAUL T1 SYNC MODE1 MODE0 PHASM0 ILIM LOWDCR PWM0 VCC0 VCC1VDD33_1 GND VIN VIN 7V TO 14V VIN 7V TO 14V INTVCC 47pF VIN IIN+ IIN– INTVCC PWM0 PWM1 WP TSNS0 TSNS1 SDA VCC1 SCL SHARE_CLK ALERT FAUL T0 VDD33 VSENSE0+VOUT VSENSE1+ VSENSE0– VSENSE1– ISENSE0+ ISENSE0– ISENSE1– ISENSE1+ VDD33 VCC0 FAUL T1 RUN0 RUN1 PGOOD0 EXTVCC PHASE_CFGPGOOD1 SYNC L TC3884-1 PINS NOT USED IN CIRCUITS TDA21470: REFIN , GATEL, IOUT, OCSET COUT1, 3, 5, 7: COUT2, 4, 6, 8: L1, L2, L3, L4: MURATA GRM32ER60J107ME20L (100µF , 6.3V , X5R, 1210) PANASONIC ETPF470M5H (470µF , 2.5V) EATON FP1007R3-R22-R (0.215µH, DCR = 0.29m/uni03A9) V DR FROM EXTERNAL 5V POWER SUPPL Y GND BOOT PHASEVIN EN SW VOSPWM VDRV TOUT/FL T PGND LGND VCC TDA2147022µF VIN1 4.7µF 4.7µF VDR 0.47µF 0/uni03A9 COUT5 100µF 6.3V C OUT6 470µF 2.5V 0.215µH, L3330pF BOOT PHASEVIN EN SW VOSPWM VDRV TOUT/FL T PGND LGND VCC TDA2147022µF VIN1 4.7µF 4.7µF VDR 0.47µF 0/uni03A9 COUT7 100µF 6.3V C OUT8 470µF 2.5V 0.215µH, L4330pF BOOT PHASEVIN EN SW VOSPWM VDRV TOUT/FL T PGND LGND VCC TDA2147022µF VIN1 4.7µF 4.7µF VDR 0.47µF 0/uni03A9 COUT3 100µF 6.3V C OUT4 470µF 2.5V 0.215µH, L2330pF 665/uni03A9 BOOT PHASEVIN EN SW VOSPWM VDRV TOUT/FL T PGND LGND VCC TDA2147022µF VIN1 4.7µF 4.7µF VDR 0.47µF 0/uni03A9 COUT1 100µF 6.3V C OUT2 470µF 2.5V V OUT 1.05V 120A 0.215µH, L1 330pF 665/uni03A9 ISENSE1+ ISENSE1– ISENSE0+ ISENSE0– PWM1 0.1µF 2/uni03A9 4.7µF 10nF 10nF 2.2µF 1/uni03A9 1m/uni03A9 VIN1 ITH0 ITH1 ITH ITHR0 ITHR1 VDD25 VOUT 0_CFG VOUT 1_CFG ASEL1 FREQ_CFG ASEL0 6.8nF 330pF 24.9k 24.9k 24.9k 7.32k 5.76k 5.76k 1µF 220nF 1µF 4.7µF 220nF 220nF 220nF 665/uni03A9 665/uni03A9 EXTVCC

3884feFor more information www.linear .com/L TC3884 PACKAGE DESCRIPTION 7.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 6) PIN 1 CHAMFER C = 0.35 0.40 ±0.10 48 47 BOTTOM VIEW—EXPOSED PAD

5.50 REF

(4-SIDES) 0.75 ±0.05 R = 0.115 TYP 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UK48) QFN 0406 REV C RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 5.15 ±0.10 5.15 ±0.10 5.15 ±0.05 5.15 ±0.05 R = 0.10 TYP 48-Lead Plastic QFN (7mm × 7mm) (Reference LTC DWG # 05-08-1704 Rev C) Please refer to http://www.linear .com/product/LTC3884#packaging for the most recent package drawings.

3884fe For more information www.linear .com/L TC3884 PACKAGE DESCRIPTION 5.00 ±0.10 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) 6.00 ±0.10 0.65 ±0.05 RECOMMENDED SOLDER PAD LAYOUT APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.25mm ON ANY SIDE 5. EXPOSED PAD SHALL BE Pd Ni Au PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 1524 4839 BOTTOM VIEW—EXPOSED PAD 1.90 ±0.10 2.60 ±0.10 (RHE48) GQFN 0617 REV B PIN 1 NOTCH 0.35 × 45° CHAMFER 0.20 ±0.05 0.85 ±0.10 1.10 ±0.10 1.10 × 0.85 (×4) 0.85 × 1.10 (×4) 0.40 ±0.10 0.40 BSC 0.55 REF 1.00 REF 0.80 REF

0.25 REF

1.00 REF

0.80 REF

0.25 REF 48-Lead Plastic GQFN (5mm × 6mm) (Reference LTC DWG # 05-08-1527 Rev B) 3.60 ±0.05 5.20 ±0.05 1.90 ±0.10 0.25 2.60 ±0.10 0.80 PACKAGE OUTLINE 0.20 ±0.05

0.40 BSC

0.600.55 Please refer to http://www.linear .com/product/LTC3884#packaging for the most recent package drawings.

3884feFor more information www.linear .com/L TC3884 Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 11/15 Added Note 19. Changed operation default value. 38, 73 B 2/16 Corrected top mark. Modified IIN– switch circuitry. C 5/17 Added ECC. All D 9/17 Added LTC3884-1 part numbers and RHE package option. Added conditions and change limits for PWM. Temp dotted tSU(DAT). 1, 4, 5, 7, 11, 17, 18, 20, 22, 51, 56, 61, 124, 126 E 11/17 Changed package type description from QFN to GQFN. 1, 5

3884fe For more information www.linear .com/L TC3884 LT 1117 REV E • PRINTED IN USA www.linear .com/L TC3884  ANALOG DEVICES, INC. 2017 RELATED PARTS TYPICAL APPLICATION Licensed under U.S. Patent 7000125 and other related patents worldwide. PART NUMBER DESCRIPTION COMMENTS LTM4676A Dual 13A or Single 26A Step-Down DC/DC µModule Regulator with Digital Power System Management 4.5V ≤ VIN ≤17V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface, 16mm × 16mm × 5mm , BGA Package LTM4675 Dual 9A or Single 18A μModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤17V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface, 11.9mm × 16mm × 5mm, BGA Package LTM4677 Dual 18A or Single 36A µModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤ 16V; 0.5V ≤ VOUT (±0.5%) ≤ 1.8V, I2C/PMBus Interface, 16mm × 16mm × 5.01mm, BGA Package LTC3874/ LTC3874-1 Multiphase Step-Down Synchronous Slave Controller with Sub MilliOhm DCR Sensing 4.5V ≤ V IN ≤ 38V, VOUT up to 5.5V, Very High Output Current, Accurate Current Sharing, Current Mode Applications LTC3887/ LTC3887-1 Dual Output Multiphase Step-Down DC/DC Controller with Digital Power System Management, 30mS Start-Up 4.5V ≤ V IN ≤ 24V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 5.5V, I2C/PMBus Interface, –1 Version uses DrMOS or Power Blocks LTC3882/ LTC3882-1 Dual Output Multiphase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management 3V ≤ V IN ≤ 38V, 0.5V ≤ VOUT1,2 ≤ 5.25V, (±0.5%) VOUT Accuracy I2C/ PMBus Interface, uses DrMOS or Power Blocks LTC3886 60V Dual Output Step-Down Controller with Digital Power System Management 4.5V ≤ V IN ≤ 60V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 13.8V, I2C/PMBus Interface, Input Current Sense LTC3815 6A Monolithic Synchronous DC/DC Step-Down Converter with Digital Power System Management 2.25V ≤ V IN ≤ 5.5V, 0.4V ≤ VOUT ≤ 0.72VIN, Programmable VOUT Range ±25% with 0.1% Resolution, Up to 3MHz Operation with 13-Bit ADC Low DCR Sensing, 425kHz, Single-Output, 1.2V/60A Buck Converter 1/uni03A9 0.1µF BSC050NE2LS 0.1µF BSC010NE2LSI BSC050NE2LS BSC010NE2LSI 270µF 16V 4.99k 10k 10k 0.25µH 715/uni03A9 10µF 4.7µF 0.25µH 715/uni03A9 20k 11k 24.9k 4.32k 24.9k 5.76k 10µF INTVCC L TC3884 VIN IIN+ IIN– TG0 BOOST0 SW0 BG0 SYNC PGOOD0 PGOOD1 SDA SCL ALERT FAUL T0 FAUL T1 SHARE_CLK RUN0 RUN1 WP TG1 BOOST1 SW1 BG1 V OUT0 _CFG V OUT1 _CFG ASEL0 ASEL1 FREQ_CFG PHASE_CFG EXTVCC VIN 6V TO 14V VDD33 744301025 DCR=0.32m/uni03A9 D1, D2: CMDSH3-TR

3884 TA11

DCR=0.32m/uni03A9 V DD25 10k 10k 10k 10k 10k 220nF 330µF 6.3V 100µF 6.3V 3.3nF 2.2µF 1µF 220nF VDD33 VDD25 VDD33 PGND SGND V DD25 ISENSE1+ ISENSE0+ ISENSE0– VSENSE0+ VSENSE0– TSNS0 ITH0 ITHR0 MMBT3906-AL3-R VOUT 1.2V/60A 150pF 10nF 10nF MMBT3906-AL3-R ISENSE1– VSENSE1+ VSENSE1– TSNS1 ITH1 ITHR1 330µF 6.3V 100µF 6.3V 2m/uni03A9 1µF

Product Information

LTM4675 specifications and overview.

Summary

Dual Output PolyPhase Step-Down Controller with Sub-Milliohm DCR Sensing and Digital Power System Management

Description

Dual Output PolyPhase Step-Down Controller with Sub-Milliohm DCR Sensing and Digital Power System Management

Source title LTM4675 Datasheet(PDF) - Linear Technology

Related Parts

More parts from the same family.

Browse manufacturer