LTM4677

LTC3874-1 LINER | Alldatasheet

Document overview

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Technical content

38741fFor more information www.linear/L TC3874-1 PWM0 PWM1 L TC3874-1 INTVCC 0.22µF VCC0 VCC1 PHASMD LDWDCR ILIM FREQ GND RUN0 SYNC RUN1 FAUL T0 FAUL T1 RUN0 649/uni03A9 (0.29m/uni03A9 DCR) 0.215µH (0.29m/uni03A9 DCR) 0.215µH FAUL T0 FAUL T1 RUN1 SYNC REFER TO L TC3884-1 DATA SHEET FOR MASTER SETUP PIN NOT USED IN THIS CIRCUIT : EXTV CC ITH0 ITH1 VSENSE0+1.8V 100µF 100µF 470µF 470µF L TC3884-1 I SENSE0+ ISENSE0– ISENSE1+ ISENSE1– ITH0 ITH1 VSENSE1+ VIN 7V TO 14V VOUT 1.8V 120A V IN PGOOD0 PGOOD1 MODE0 MODE1

38741 TA01a

+ 0.22µF 4.7µF 649/uni03A9 V IN = 12V V OUT = 1.8V fSW = 425kHz CCM EFFICIENCY POWER LOSS 0.29mΩ 1.5mΩ 0.29mΩ 1.5mΩ LOAD CURRENT (A) 100 110 120 100 EFFICIENCY (%) POWER LOSS (W)

38741 TA01b

Synchronous Slave Controller with Sub-Milliohm DCR Sensing The LT C®3874-1 is a dual PolyPhase® current mode syn- chronous step-down slave controller . It enables high cur- rent, multiphase applications when paired with a companion master controller by extending the phase count. Compat- ible master controllers include the LTC3884-1, LTC3774, LT C3875, LTC3877 and LTC3866. The LTC3874-1 employs a unique architecture that enhances the signal-to-noise ratio of the current sense signal, allowing the use of sub- milliohm DC resistance power inductors to maximize efficiency while reducing switching jitter . Its peak current mode architecture allows for accurate phase-to-phase current sharing even for dynamic loads. Effectively working with a master controller , the LTC3874-1 supports all the programmable features as well as fault protection. L, L T , L TC, L TM, Linear Technology, the Linear logo, PolyPhase and µModule are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 5408150.

applicaTions

n High Current Distributed Power Systems n Telecom, Datacom and Storage Systems n Intelligent Energy Efficient Power Regulation High Efficiency, 4-Phase 1.8V/120A Step-Down Supply n Phase Extender for High Phase Count Voltage Rails n Operates with Power Blocks, DrMOS or External Gate Drivers and MOSFET s n Accurate Phase-to-Phase Current Sharing n Sub-Milliohm DCR Current Sensing n Phase-Lockable Fixed Frequency 250kHz to 1MHz n Immediate Response to Master IC's Fault n Up to 12-Phase Operation n Wide VIN Range: 4.5 to 38V n VOUT Range : Up to 3.5V (LOWDCR Pin High) Up to 5.5V (LOWDCR Pin Low) n Proprietary Current Mode Control Loop n Programmable CCM/DCM Operation n Programmable Phase Shift Control n 24-Lead (4mm × 4mm) QFN Package 4-Phase Efficiency and Power Loss vs Output Current, Sub- Milliohm DCR vs T raditional DCR

38741f For more information www.linear .com/L TC3874-1 pin conFiguraTionabsoluTe MaxiMuM raTings MODE0, MODE1, ILIM, LOWDCR, 3V to INTVcc Operating Junction Temperature Range C to 125°C C to 150°C (Note 1) 24 23 22 21 20 19 7 8 9 TOP VIEW UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN GND 10 11 12 18ISENSE0+ ISENSE0– RUN0 RUN1 ISENSE1– ISENSE1+ VCC0 VIN INTVCC EXTVCC VCC1 PWM1 MODE0 I TH0 LOWDCR FAULT0 FAULT1 PWM0 MODE1 I TH1 FREQ ILIM SYNC PHASMD TJMAX = 125°C, θJA = 46.9°C/W , θJC_BOT = 4.5°C/W EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3874EUF-1#PBF LTC3874EUF-1#TRPBF 38741 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C LTC3874IUF-1#PBF LTC3874IUF-1#TRPBF 38741 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. orDer inForMaTion http://www.linear .com/product/LTC3874-1#orderinfo

38741fFor more information www.linear/L TC3874-1

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input Voltage Range 4.5 38 V VOUT Output Voltage Range LOWDCR = INTVCC (Note 3) LOWDCR = 0V 3.5 5.5 V V I Q Input DC Supply Current Normal Operation Shutdown V RUN0,1 = 3.3V VRUN0,1 = 0V 4.6 1.8 mA mA V UVLO Undervoltage Lockout Threshold VINTVCC Falling VINTVCC Rising 3.5 3.8 V V Control Loop I ISENSE0,1 ISENSE Pins Bias Current VISENSE0,1 < (VINTVCC – 3.3V) VISENSE0,1 > (VINTVCC – 3.3V) l ±0.15 ±0.4 µA µA VISENSE(MAX) Maximum Current Sense Threshold (Table 3) ILIM = INTVCC, LOWDCR = INTVCC, VISENSE0,1 = 1.2V, VITH = 2.18V l 26.8 28.8 30.8 mV ILIM = 0V, LOWDCR = INT VCC, VISENSE0,1 = 1.2V, VITH = 2.18V l 14.5 16 17.5 mV ILIM = INTVCC, LOWDCR = 0V, VISENSE0,1 = 1.2V, VITH = 2.18V l 65 72 79 mV ILIM = 0V, LOWDCR = 0V, V ISENSE0,1 = 1.2V, VITH = 2.18V l 33 40 47 mV PWM Outputs PWM PWM Output High Voltage PWM Output Low Voltage PWM Output Current in Hi-Z State ILOAD = 500µA ILOAD = –500µA l l VCC – 0.2 0.2 V V µA tON(MIN) Minimum On-Time (Note 4) 60 ns INTVCC Regulator VINTVCC Internal VCC Voltage No Load 6V < VIN < 38V 5.25 5.5 5.75 V VLDO INT INTV CC Load Regulation ICC = 0mA to 20mA 0.5 2 % VEXTVCC EXTVCC Switchover Voltage VEXTVCC Ramping Positive (Note 5) l 4.5 4.7 V VLDO EXT EXTV CC Voltage Drop ICC = 20mA, VEXTVCC = 5V 50 100 mV VLDOHYS EXTVCC Hysteresis 300 mV Oscillator and Phase-Locked Loop fRANGE PLL SYNC Range l 250 1000 kHz fNOM Nominal Frequency VFREQ = 0.9V 500 kHz IFREQ Frequency Setting Current 9 10 11 µA θ SYNC- θ0 SYNC to Ch0 Phase Relationship Based on the Falling Edge of SYNC and Rising Edge of PWM0 PHASMD = 0 PHASMD = 1/3 • INTV CC PHASMD = 2/3 • INTVCC PHASMD = INTVCC 180 120 Deg Deg Deg Deg θ SYNC- θ1 SYNC to Ch1 Phase Relationship Based on the Falling Edge of SYNC and Rising Edge of PWM1 PHASMD = 0 PHASMD = 1/3 • INTV CC PHASMD = 2/3 • INTVCC PHASMD = INTVCC 300 240 270 Deg Deg Deg Deg Digital Inputs RUN0, RUN1, MODE0, MODE1, FAUL T0, FAUL T1, LOWDCR VIH Input High Threshold Voltage l 2.0 V VIL Input Low Threshold Voltage l 1.4 V The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN0,1 = 3.3V unless otherwise specified.

38741f For more information www.linear .com/L TC3874-1 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3874-1 is tested under pulsed load conditions such that T J ≈ TA. The LTC3874E-1 is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°Ç to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3874I-1 is guaranteed over the –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the related package thermal impedance and other environmental factors. The junction temperature T J is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • 46.9°C/W) Note 3: Output voltage is set and controlled by master controller in multiphase operations. Note 4: The minimum on-time condition corresponds to an inductor peak-to-peak ripple current ≥40% of I MAX (see Minimum On-Time Considerations in the Applications Information section). Note 5: EXTVCC is enabled only if VIN is higher than 6.5V. Typical perForMance characTerisTics Load Step (Discontinuous Conduction Mode) 4-Phase with Master Controller LTC3884-1 Efficiency and Power Loss vs Output Current (4-Phase with Master Controller LTC3884-1) Load Step (Forced Continuous Mode) 4-Phase with Master Controller LTC3884-1 Efficiency vs Output Current and Mode (4-Phase with Master Controller LTC3884-1) Efficiency vs Output Current and Mode (4-Phase with Master Controller LTC3884-1) A = 25°C unless otherwise specified) V IN = 12V V OUT = 1.8V f SW = 425kHz CCM DCM LOAD CURRENT (A) 100 110 120 100 EFFICIENCY (%) 38741 G1 V IN = 12V V OUT = 1.2V f SW = 425kHz CCM DCM LOAD CURRENT (A) 100 110 120 100 EFFICIENCY (%) 38741 G2 V IN = 12V V OUT = 1.8V fSW = 425kHz CCM EFFICIENCY POWER LOSS 0.29mΩ 1.5mΩ 0.29mΩ 1.5mΩ LOAD CURRENT (A) 100 110 120 100 EFFICIENCY (%) POWER LOSS (W) 38741 G3 V IN = 12V V OUT = 1.2V I LOAD 0A TO 20A 50µs/DIV I LOAD 50A/DIV V OUT AC-COUPLED 50mV/DIV I L(SLAVE0) 10A/DIV I L(MASTER0) 10A/DIV

38741 G04

V IN = 12V V OUT = 1.2V I LOAD 0A TO 20A 50µs/DIV I LOAD 50A/DIV V OUT AC-COUPLED 50mV/DIV I (SLAVE0) 10A/DIV I (MASTER0) 10A/DIV

38741 G05

38741fFor more information www.linear/L TC3874-1 Typical perForMance characTerisTics INTVCC Line Regulation Undervoltage Lockout Threshold (INTVCC vs Threshold) Current Sense Threshold vs I TH Voltage Quiescent Current vs Input Voltage without EXTV CC Maximum Current Sense Threshold vs Common Mode Voltage (LOWDCR = INTV CC, VITH = 2.18V) Quiescent Current vs Temperature without EXTV CC Inductor Current at Light Load Start-Up Into a Prebiased Load 2-Phase Operation LTC3884-1 and LTC3874-1 A = 25°C unless otherwise specified) VITH (V) –40 VISENSE (mV) –20 100 0.5 1 2.51.5 32

38741 G10

LOWDCR = L, RANGE = H LOWDCR = H, RANGE = L LOWDCR = H, RANGE = H LOWDCR = L, RANGE = L VISENSE COMMON MODE VOLTAGE (V) CURRENT SENSE THRESHOLD (mV) 3.5

38741 G11

ILIM = GND ILIM = INTVCC TEMPERATURE (°C) –50 4.1 3.9 2.9 3.7 2.7 3.1 3.5 2.5 3.3

38741 G12

–5 45 125 UVLO THRESHOLD (V) FALLING RISING V IN = 12V V OUT = 1.2V 1µs/DIV DISCONTINUOUS CONDUCTION MODE 5A/DIV FORCED CONTINUOUS MODE 5A/DIV

38741 G06

V IN 12V V OUT = 1.2V 2ms/DIV RUN ALL RUN PINS TIED TOGETHER 2V/DIV V OUT IN CCM 500mV/DIV

38741 G07

TEMPERATURE (°C) –50 100 150 SUPPL Y CURRENT (mA) 38741 G8 INPUT VOL TAGE (V) INTV CC VOL TAGE (V) 38741 G9 INPUT VOL TAGE (V) SUPPL Y CURRENT (mA)

38741 G13

38741f For more information www.linear .com/L TC3874-1 pin FuncTions ISENSE0 +/ISENSE1 (Pin 1/Pin 6): Current Sense Compara- tor Inputs. The (+) inputs to the current comparators are normally connected to DCR sensing networks. ISENSE0 −/ISENSE1 −(Pin 2/Pin 5): Current Sense Compara- tor Inputs. The (−) inputs to the current comparators are connected to the outputs. RUN0/RUN1 (Pin 3/Pin 4): Enable Run Inputs. Logic high on the RUN pin enables the corresponding channel. MODE0/MODE1(Pin 24/Pin 7): DCM/CCM Mode Control Pins. Each channel runs in forced continuous mode if the mode pin is logic high. There is an internal 500k pull-down resistor on the mode pin. To select discontinuous conduc- tion mode, float or pull down the mode pin. I TH0/ITH1(Pin 23/Pin 8): Current Control Threshold. Each associated channel’s current comparator tripping threshold increases with its I TH voltage. These pins must be con- nected to the master controller’s ITH pins. FREQ(Pin 9): Frequency Set Pin. There is a precision 10µA current flowing out of this pin. A resistor to ground sets a voltage which in turn programs the frequency. This pin sets the default switching frequency when there is no external clock on the SYNC pin. See the application section for detailed information. ILIM(Pin 10): Current Comparators Sense Voltage Limit. Program a DC voltage at this pin to set the maximum cur- rent sense threshold for the current comparators. SYNC (Pin 11): External Clock Synchronization Input. If an external clock is present at this pin, the switching frequency will be synchronized to the falling edge of external clock. Tie this pin to GND if not used. PHASMD (Pin 12): Phase Set Pin. This pin determines the relative phases between the external clock on pin SYNC and the internal controllers. See Table 1 in the Operation section for details. PWM0/PWM1(Pin 19/Pin 13): (Top) Gate Signal Outputs. This signal goes to the PWM or top gate input of the exter- nal driver , integrated driver MOSFET or power block. This is a three-state compatible output. To support three-state mode, an external resistor divider is typically used from V CC0/VCC1 to ground. VCC0/VCC1(Pin 18/Pin 14): PWM Pin Driver Supplies. Decouple this pin to GND with a capacitor (0.1μF) to an external supply or tie this pin to the INTV CC pin. PWM0/ PWM1 signal swing is from ground to VCC0/VCC1. EXTVCC(Pin 15): External Power Input to an Internal Switch Connected to INTVCC. The switch closes and supplies the IC power , bypassing the internal low dropout regulator , whenever EXTV CC is higher than 4.7V and V IN is greater than 7V. Do not exceed 6V on this pin. INTVCC(Pin 16): Internal 5.5V Regulator Output. The control circuits are powered from this voltage. Decouple this pin to GND with a minimum of 4.7μF low ESR tantalum or ceramic capacitor . V IN (Pin 17): Main Input Supply. Decouple this pin to GND with a capacitor (0.1μF to 1μF). FAUL T0/FAUL T1 (Pin 21/Pin 20): Master Controller Fault Inputs. Connect these pins to the master chip fault indica- tor pins to respond to the fault signals from the master controller. When a FAUL T pin is floating or low, the PWM pin of the corresponding channel is in three-state. There is an internal 500k pull-down resistor on each FAUL T pin. LOWDCR(Pin 22): Sub-milliohm DCR Current Sensing Enable Pin. There is an internal 500k pull-up resistor between the LOWDCR pin and INTV CC. Floating or pull - ing this pin logic high will enable the sub-milliohm DCR current sensing. Pulling this pin logic low will disable the sub-milliohm DCR current sensing. GND(Exposed Pad Pin 25) : Ground. Connect this pad, through vias, to a solid ground plane under the circuit. The sources of the bottom N-channel MOSFETs, the (–) terminal of C INTVCC, and the (–) terminal of C IN should connect to this ground plane as closely as possible to the IC. All small-signal components and compensation components should also connect to this ground plane.

38741fFor more information www.linear/L TC3874-1 FuncTional block DiagraM One of Two Channels (CH0) Shown 10µA EXTVCC INTVCC INTVCC IREVICMP INTVCC ITH0 ILIM ISENSE0+ ISENSE0– ON REV UVLO FCNT RUN FAUL TB 1.7V RUN0 SGNDMODE0 FAUL T0 VIN VIN COUT0 CIN 4.7V FREQ SYNC PHASMD SYNC/PHASE DETECT OSC PLL-SYNC UVLO DC AMP SLOPE COMPENSATION ILIM RANGE SELECT HI: 1:1 LO: 1:1.8 SWITCH LOGIC AND ANTI- SHOOT- THROUGH S R Q 5.5V REG REF LOWDCR 38741 BD 60k DrMOS VCC0 PWM0

38741f For more information www.linear .com/L TC3874-1 operaTion Main Control Loop The LTC3874-1 is a constant frequency, L TC proprietary current mode step-down slave controller for parallel opera- tion with master controllers. During normal operation, each top MOSFET is turned on when the clock for that channel sets the RS latch, and turned off when the main current comparator , I CMP, resets the RS latch. The peak inductor current at which ICMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the master controller . When the load current increases, the master controller increases the I TH voltage, which in turn causes the peak current in the corresponding slave channels to increase, until the average inductor current matches the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until the beginning of the next cycle in Continuous Conduction Mode (CCM) or until the inductor current starts to reverse, as indicated by the reverse current comparator I REV, in Discontinuous Conduction Mode (DCM). The LTC3874-1 slave controllers DO NOT regulate the output voltage but regulate the cur- rent in each channel for current sharing with the master controllers. Output voltage regulation is achieved through the voltage feedback control loop in the master controllers. Sub-Milliohm DCR Current Sensing The LTC3874 -1 employs a unique architecture to enhance the signal-to-noise ratio that enables it to operate with a small sense signal of a sub-milliohm value inductor DCR to improve power efficiency and reduce jitter due to switching noise. Floating or pulling the LOWDCR pin high will enable sub- milliohm DCR current sensing. The LTC3874-1 can sense a DCR value as low as 0.2mΩ with careful PCB layout. The proprietary signal processing circuit provides a 14dB signal-to-noise ratio improvement. As with conventional current mode architectures, the current limit threshold is still a function of the inductor peak current and the DCR value, and can be accurately set with the ILIM and I TH pins. INTVCC/EXTVCC Power Power for most internal circuitry is derived from the INTVCC pin. When the EXTVCC pin is left open or tied to a voltage less than 4.7V, an internal 5.5V linear regulator supplies INTV CC power from V IN. If EXTV CC is taken above 4.7V and VIN is higher than 7V, the 5.5V regulator is turned off and an internal switch is turned on connecting EXTV CC. EXTVCC can be applied before VIN. Using the EXTVCC allows the INTVCC power to be drawn from an external source. Start-Up and Shutdown (RUN0, RUN1) The two channels of the LTC3874-1 can be independently shut down using the RUN0 and RUN1 pins. Pulling either of these pins below 1.4V shuts down the main control circuits for that channel. During shutdown, the PWM pin is in three-state mode. Pulling either of these pins above 2V enables the controller . The RUN0/1 pins are actively pulled down until the INTV CC voltage passes the undervoltage lockout threshold of 3.8V. For multiphase operation, the RUN0/1 pins must be connected together and driven by the RUN pins on the master controller . Because a large RC filter in the LTC3874-1 needs to settle during initializa- tion, the RUN pins can only be pulled up 4ms after V IN is ready. Do not exceed the Absolute Maximum Rating of 6V on these pins. The start-up of each channel’s output voltage V OUT is controlled by the master controller . After the RUN pins are released, the master controller drives the output based on the programmed delay time and rise time. The slave con- troller LTC3874-1 follows the I TH voltage set by the master to supply the same current to the output during startup.

38741fFor more information www.linear/L TC3874-1 operaTion Light Load Current Operation (Discontinuous Conduction Mode, Continuous Conduction Mode) The LTC3874-1 can operate either in discontinuous con- duction mode or forced continuous conduction mode. To select forced continuous mode, tie the MODE pin to a DC voltage above 2V (e.g., INTVCC). To select discontinu- ous conduction mode, tie the MODE pin to a DC voltage be low 1.4V (e.g., GND).In forced continuous mode, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the I TH pin. In this mode, the efficiency at light loads is lower than in discontinuous mode. However , continuous mode has the advantages of lower output ripple and less interference with audio circuitry. When the MODE pin is connected to GND, the LTC3874-1 operates in discontinuous mode at light loads. At very light loads, the current comparator I CMP may remain tripped for several cycles and force the external top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). This mode provides higher light load efficiency than forced continuous mode and the inductor current is not allowed to reverse. There is a 500k pull-down resistor internally connected to the MODE pin. If the MODE0/1 pins are left floating, both channels are in discontinuous conduction mode by default. Multichip Operations (PHASMD and SYNC Pins) The PHASMD pin determines the relative phases between the internal channels as well as the external clock signal on SYNC pin as shown in Table 1. The phases tabulated are relative to zero degree phase being defined as the falling edge of the clock on SYNC pin. Table 1 PHASMD CHANNEL 0 PHASE CHANNEL 1 PHASE GND 180° 0° 1/3 INTVCC 60° 300° 2/3 INTVCC or Float 120° 240° INTVCC 90° 270° The SYNC pin is used to synchronize switching frequency between the master and slave controllers. Input capacitance ESR requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the RMS current squared. A two stage, single output voltage implementa- tion can reduce input path power loss by 75% and radi - cally reduce the required RMS current rating of the input capacitor(s). Single Output Multiphase Operation The LTC3874 -1 is configured for single output multiphase converters with a master controller by making these con- nections Tie all the ITH pins of paralleled channels together for current sharing between masters and slaves;

Tie all SYNC or PLLIN pins of paralleled channels to - gether or tie the master chip’s CLKOUT pin to the slave chip’s SYNC pin for switching frequency synchronization among channels.
Tie all the RUN pins of paralleled channels together for startup and shutdown at the same time. Tie the fault indictor pin of the master controller if avail- able to the FAUL T pin of the slave controller for fault protection. The LTC3874-1 MODE pin can be tied to the master chip PGOOD pin for start-up control. During soft-start, the LTC3874-1 operates in DCM mode. When the soft-start interval is done, the LTC3874-1 operates in CCM mode. Examples of single output multiphase converters are shown in Figure 1. The Typical Application on the first page of this data sheet is a basic LTC3874-1 application circuit configured as a slave controller . In paralleled operation, the current sensing scheme and circuit parameters in the LTC3874-1 have to be the same as the master controller to achieve balanced current sharing between masters and slaves. Input and output capacitors are selected based on RMS current rating, ripple and transient specs.

Figure 1. Multiphase Operation ing to any frequency within the range of 250kHz to 1MHz. locking to the external clock.

3 PHASE OPERATION

6 PHASE OPERATION

4 PHASE OPERATION

38741 F01

3 PHASE + 1 PHASE OPERATION

grounded, both channels are set to be low current range. TH voltage can be found in Table 3. Table 2. ILIM vs Range Table 3. Current Sense Threshold vs ITH Voltage Table 3. Current Sense Threshold vs ITH Voltage (continued) be connected directly to V OUT of the master controller . the IC pins to prevent noise coupling to the sense signal. SENSE+, ISENSE– is from 0V to 5.5V. Table 4. Output Voltage Range vs LOWDCR Pin

38741f For more information www.linear .com/L TC3874-1 applicaTions inForMaTion To ensure that the load current will be delivered over the full operating temperature range, the temperature coefficient of the DCR resistance, approximately 0.4%/°C, should be taken into consideration. Typically, C is selected in the range of 0.047µF to 0.47µF. This forces R to around 2kΩ, reducing error that might have been caused by the I SENSE pins’ ±1uA current. There will be some power loss in R that relates to the duty cycle. It will be highest in continuous mode at maximum input voltage: PLOSS (R)= VIN(MAX) −VOUT( ) •VOUT R Ensure that R has a power rating higher than this value. However , DCR sensing eliminates the conduction loss of a sense resistor; it will provide a better efficiency at heavy loads. To maintain a good signal-to-noise ratio for the current sense signal, using a minimum ∆V ISENSE of 2mV for duty cycles less than 40% is desirable when the LOWDCR pin is high; use a minimum ∆V ISENSE of 10mV for duty cycles less than 40% when the LOWDCR pin is low. The actual ripple voltage will be determined by the following equation: ΔVISENSE = VOUT VIN VIN −VOUT R C•fOSC Inductor Value Calculation Given the desired input and output voltages, the inductor value and operating frequency, f OSC, directly determine the inductor’s peak-to-peak ripple current: IRIPPLE = VOUT VIN VIN – VOUT fOSC •L Lower ripple current reduces core losses in the inductor , ESR losses in the output capacitors, and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however , requires a large inductor . A reasonable starting point is to choose a ripple current that is about 40% of I OUT(MAX). Note that the largest ripple Figure 2 Inductor DCR Current Sensing VIN VIN PWM ISENSE+ ISENSE– LTC3874-1 VOUT

38741 F02

L C R DrMOS DCR Inductor DCR Current Sensing The LTC3874-1 is specifically designed for high load current applications requiring the highest possible efficiency; it is capable of sensing the signal of an inductor DCR in the sub-milliohm range (Figure 2). The DCR is the DC winding resistance of the inductor’s copper , which is often less than 1mΩ for high current inductors. In high current and low output voltage applications, conduction loss of a high DCR or a sense resistor will cause a significant reduction in power efficiency. For a specific output requirement, choose the inductor with the DCR that satisfies the maxi- mum desirable sense voltage, and use the relationship of the sense pin filters to output inductor characteristics as depicted below. DCR= VISENSE(MAX) IMAX + ΔIL RC = L/(5 • DCR) when the LOWDCR pin is high RC = L/DCR when the LOWDCR pin is low where: VISENSE(MAX): Maximum sense voltage for a given I TH voltage IMAX: Maximum load current ∆ IL: Inductor ripple current L, DCR: Output inductor characteristics R, C: Filter time constant

VOUT VIN Inductor Core Selection Once the inductance value is determined, the type of in - ductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately , increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET and Schottky Diode (Optional) Selection When we use discrete gate driver and MOSFETs, at least two external power MOSFET s need to be selected: One N-channel MOSFET for the top (main) switch and one or more N-channel MOSFET(s) for the bottom (synchronous) switch. The number , type and on-resistance of all MOSFETs selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the MOSFET will be used. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than one-third of the input voltage. In applica- tions where V IN >> VOUT , the top MOSFETs’ on-resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low on-resistance with significantly reduced input capacitance for the main switch application in switching regulators. The peak-to-peak MOSFET gate drive levels are set by the internal regulator voltage, V INTVCC, requiring the use of logic-level threshold MOSFETs in most applications. Pay close attention to the BV DSS specification for the MOSFETs as well; many of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the on-resistance, R DS(ON), input capacitance, input voltage and maximum output current. MOSFET input capacitance is a combination of several components but can be taken from the typical gate charge cur ve included on most data sheets (Figure 3). The curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. VDS VIN

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Figure 3. Gate Charge Characteristic

38741f For more information www.linear .com/L TC3874-1 definitions of these parameters are not included. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle= VOUT VIN Synchronous Switch Duty Cycle= VIN – VOUT VIN The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: PMAIN = VOUT VIN IMAX( ) 1+ δ( ) RDS(ON) + VIN( ) 2 IMAX ⎠⎟ RDR( ) CMILLER( ) • VINTVCC – VTH(MIN) + 1 VTH(MIN) PSYNC = VIN – VOUT VIN IMAX( ) 1+ δ( ) RDS(ON) where δ is the temperature dependency of R DS(ON), RDR is the effective top driver resistance (approximately 2Ω at VGS = VMILLER), VIN is the drain potential and the change in drain potential in the particular application. V TH(MIN) is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current. C MILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above. Both MOSFETs have I 2R losses while the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For V IN < 20V, the high current efficiency generally improves with larger MOSFETs, while for V IN > 20V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. applicaTions inForMaTion The term (1 + δ ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. An optional Schottky diode across the synchronous MOSFET conducts during the dead time between the con- duction of the two large power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead time and requiring a reverse-recov- er y period which could cost as much as several percent in ef ficiency. A 2A to 8A Schottky is generally a good com- promise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition loss due to their larger junction capacitance. INT VCC Regulators and EXTVCC The LTC3874-1 features a PMOS LDO that supplies power to INTVCC from the V IN supply. INTVCC powers most of the LTC3874-1’s internal circuitry. The linear regulator regulates the voltage at the INTV CC pin to 5.5V when VIN is greater than 6V. EXTV CC connects to INTVCC through another P-channel MOSFET and can supply the needed power when its voltage is higher than 4.7V and V IN is higher than 7V. Each of these can supply a peak current of 100mA and must be bypassed to ground with a minimum value of 4.7µF ceramic capacitor or low ESR electrolytic capacitor . No matter what type of bulk capacitor is used, an additional 0.1µF ceramic capacitor placed directly adja- cent to the INTV CC and GND pins is highly recommended. Good bypassing is needed to prevent interaction between the channels. When the voltage applied to EXTV CC rises above 4.7V and VIN above 7V, the INTVCC linear regulator is turned off and the EXTVCC is connected to INTVCC. Using the EXTVCC al- lows the MOSFET driver and control power to be derived from other high efficiency sources such as +5V rails in the system. Do not apply more than 6V to the EXTVCC pin. For applications where the main input power is 5V, tie the V IN and INTVCC pins together and tie the combined pins to the 5V input with a 1Ω or 2.2Ω resistor as shown in Figure 4 to minimize the voltage drop caused by the gate charge current. This will override the INTV CC linear

which is typically 4.5V for logic-level devices.

38741 F04

Figure 4. Setup for a 5V Input comparator has 300mV of precision hysteresis. or out-of-phase with the falling edge of external clock. not exhibit false lock to harmonics of the external clock. charged to the same voltage potential as the FREQ pin. Figure 5. Relationship Between Oscillator Frequency

38741 F05

38741 F06

Figure 6. Phase-Locked Loop Block Diagram

38741f For more information www.linear .com/L TC3874-1 applicaTions inForMaTion If the external clock frequency is greater than the inter - nal oscillator’s frequency, f OSC, then current is sourced continuously from the phase detector output, pulling up the filter network. When the external clock frequency is less than f OSC, current is sunk continuously, pulling down the filter network. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. The voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the phase detector output is high impedance and the filter capacitor holds the voltage. Typically, the external clock (on the SYNC pin) input high threshold is 2V, while the input low threshold is 1.4V. Fault Protection and Response Master controllers monitor system voltage, current, tem- perature and provide many protection features during all kinds of fault conditions. The LTC3874-1 slave control - lers do not provide as many fault protections as master controllers but respond to the fault signal from the master controller. F AUL T0 and FAUL T1 pins are designed to share the fault signal between masters and slaves. In a typical parallel application, connect the fault pins on LTC3874-1 to the master fault indictor pins, so that the slave control- ler can respond to all fault signals from the master . When the FAUL T pin is pulled below 1.4V, the PWM pin in the corresponding channel is in three-state. When the FAUL T pin voltage is above 2V, the corresponding channel is back to normal operation. During fault conditions, all internal circuits in the LTC3874-1 are still running so the slave controllers can immediately return to normal operation when the FAUL T pin is released. The LTC3874-1 has internal thermal shutdown protection which forces the PWM pin three-state when the junction temperature is higher than 160°C. The thermal shutdown has 10°C of hysteresis. In thermal shutdown, the FAUL T0 and FAUL T1 pins are also pulled low. The RUN pins are not internally pulled low. There is a 500k pull-down resistor on each FAUL T pin which sets the default voltage on the FAUL T pins low if the FAUL T pins are floating. T ransient Response and Loop Stability In a typical parallel operation, the LTC3874-1 cooperates with master controllers to supply more current. To achieve balanced current sharing between master and slave, it is recommended that each slave channel copies the power stage design from the master channel. Select the same inductors, same MOSFET driver , same power MOSFETs, and same output capacitors between the master and slave channels. Control loop and compensation design on the I TH pin should start with the single phase operation of the master controller . The multiphase transient response and loop stability is almost the same as the single phase opera- tion of the master by tying the I TH pins together between master and slaves. For example, design the compensation for a single phase 1.8V/20A output using LTC3884-1 with a 0.33μH inductor and 530μF output capacitors. To extend the output to 1.8V/40A, simply parallel one channel of LTC3874-1 with the same inductor and output capacitors (total output capacitors are 1060μF) and tie the I TH pin of LTC3874-1 to the master ITH. The loop stability and transient responses of the two phase converter are very similar to the single phase design without any extra compensator on the I TH pin of the slave controller . Furthermore, L Tpow- erCAD is provided on the L TC website as a free download for transient and stability analysis. To minimize the high frequency noise on the I TH trace between master and slave ITH pins, a small filter capacitor in the range of tens of pF can be placed closely at each ITH pin of the slave controller . This small capacitor normally does not significantly affect the closed-loop bandwidth but increases the gain margin at high frequency. Mode Selection and Pre-Biased Startup There may be situations that require the power supply to start up with a pre-bias on the output capacitors. In this case, it is desirable to start up without discharging the output capacitors. The LTC3874-1 can be configured to operate in DCM mode for pre-biased start-up. The master chip’s PGOOD pin can be connected to the MODE pins of the LTC3874-1 to ensure the DCM operation at startup and CCM operation in steady state.

38741fFor more information www.linear/L TC3874-1 applicaTions inForMaTion Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC3874-1 is capable of turning on the top MOSFET . It is determined by internal timing delays and the gate charge required to turn on the top MOSFET . Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT VIN •f If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC3874-1 is approximately 60ns, with reasonably good PCB layout, minimum 30% inductor cur- rent ripple and at least 2mV – 3mV (10mV – 15mV when the LOWDCR pin is low) ripple on the current sense signal. The minimum on-time can be affected by PCB switch - ing noise in the current loop. As the peak sense voltage decreases the minimum on-time gradually increases to 100ns. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. PWM Pins The PWM output pins are three-state compatible outputs, designed to drive MOSFET drivers, DrMOSs, etc. which do not represent a heavy capacitive load. An external resistor divider may be used on the PWM pins to set the voltage to mid-rail while in the high impedance state. The V CC pin is the corresponding PWM pin driver supply. Decouple this pin to GND with a capacitor (0.1μF) or tie this pin to the INTVCC pin. If the VCC pin is connected to an external supply, make sure it comes first before the RUN pin goes high. MOSFET Driver Selection Gate driver ICs, DrMOSs and power blocks with an inter- face compatible with the LTC3874-1’s three-state PWM outputs should be used. PC Board Layout Checklist When laying out the printed cir cuit board, the following checklist should be used to ensure proper operation of the IC. Figure 7 illustrates the current waveforms pres - ent in the various branches of the 2-phase synchronous regulators operating in the continuous mode. Check the following in the PC layout: Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined C OUT (–) ter- minals. The ITH traces should be as short as possible. The CIN capacitor should have short leads and PC trace lengths. The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other . Are the ISENSE+ and ISENSE– leads routed together with minimum PC trace spacing? The filter capacitor between ISENSE+ and ISENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor or inductor , whichever is used for current sensing. Is the INTVCC decoupling capacitor connected close to the IC, between the INTVCC and the ground pins? This capacitor carries the MOSFET drivers current peaks. An additional 1μF ceramic capacitor placed immediately next to the INTV CC and GND pins can help improve noise performance substantially. 4. Keep the switching nodes (SW1, SW0), away from sensitive small-signal nodes, especially from the op - posite channel’s current sensing feedback pins. All of these nodes have ver y large and fast moving signals and therefore should be kept on the output side of the LTC3874 -1 and occupy minimum PC trace area. If DCR sensing is used, place the resistor (Figure 2, “R”) close to the switching node.

Use a modified star ground technique: a low impedance,

divider and the GND pin of the IC. drops below the low current operation threshold. to cycle in a well-designed, low noise PCB implementation. Figure 7. Recommended Printed Circuit Layout Diagram

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38741fFor more information www.linear/L TC3874-1 applicaTions inForMaTion both controllers be turned on at the same time. A particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top MOSFET . This occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter . Reduce V IN from its nominal level to verify operation of the regulator in dropout. Check the operation of the un- dervoltage lockout circuit by further lowering V IN while monitoring the outputs to verify operation. Investigate whether any problems exist only at higher out- put currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST , SW , TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between C IN, Schottky and the top MOSFET components to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the GND pin of the IC. Design Example Using master controller LTC3884-1 and slave controller LTC3874-1 for a single-output, 4-phase high current regulator , assume V IN = 12V (nominal), and V IN = 15V (maximum), VOUT = 1.05V, IMAX = 120A, and f = 500kHz (see Figure 8). The master chip LTC3884-1 design can be found in the LTC3884-1 data sheet (Design Example section). The LTC3884-1 SYNC pin is connected to the LTC3874-1 SYNC pin for switching frequency synchronization. The LTC3874 -1 PHASMD pin is tied to INTV CC to form a PolyPhase configuration. The slave chip LTC3874 -1 should use the same inductor , DrMOS, CIN, and COUT as the master chip. DCR sensing is also used for the slave chip. The LTC3884-1 I TH pins and the LTC3874-1 ITH pins are connected together . The LTC3874-1 LOWDCR pin is pulled high and the ILIM pin is forced to INTV CC to obtain the same current limit as LTC3884-1. The LTC3884-1 RUN pins and the LTC3874-1 RUN pins are connected together . The LTC3884-1 FAUL T pins are connected to LTC3874-1 FAUL T pins so the LTC3874-1 will be disabled if the LTC3884-1 is under any fault event. The LTC3874-1 MODE pins are tied to the LTC3884-1 PGOOD pins for start-up control. During soft-start, the LTC3874-1 operates in DCM mode. When the soft-start interval is done, the LTC3874-1 operates in CCM mode.

Figure 8. High Efficiency 500kHz 4-Phase 1.05V Step-Down Converter

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38741fFor more information www.linear/L TC3874-1 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 4.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 24 23 BOTTOM VIEW—EXPOSED PAD 2.45 ±0.10 (4-SIDES) 0.75 ±0.05 R = 0.115 TYP 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UF24) QFN 0105 REV B RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.70 ±0.05 0.25 ±0.05 2.45 ±0.05 (4 SIDES)3.10 ±0.05 4.50 ±0.05 PACKAGE OUTLINE PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697 Rev B) package DescripTion Please refer to http://www.linear .com/product/LTC3874-1#packaging for the most recent package drawings.

38741f For more information www.linear .com/L TC3874-1 LT 0917 • PRINTED IN USA www.linear.com/LTC3874-1  LINEAR TECHNOLOGY CORPORATION 2017 relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS LTM4676A Dual 13A or Single 26A Step-Down DC/DC µModule® Regulator with Digital Power System Management 4.5V ≤ VIN ≤17V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface, 16mm × 16mm × 5mm, BGA Package LTM4675 Dual 9A or Single 18A μModule Regulator with Digital Power System Management 4.5V ≤ VIN ≤17V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface, 11.9mm × 16mm × 5mm, BGA Package LTM4677 Dual 18A or Single 36A μModule Regulator with Digital Power System Management 4.5V ≤ V IN ≤16V; 0.5V ≤ VOUT (±0.5%) ≤ 1.8V, I2C/PMBus Interface, 16mm × 16mm × 5.01mm, BGA Package LTC3884/ LTC3884-1 Dual Output Multiphase Step-Down Controller with Sub mΩ DCR Sensing Current Mode Control and Digital Power System Management 4.5V ≤ V IN ≤ 38V, 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, 70ms Start-Up, I2C/ PMBus Interface, Programmable Analog Loop Compensation, Input Current Sense LTC3887/ LTC3887-1 Dual Output Multiphase Step-Down DC/DC Controller with Digital Power System Management, 70ms Start-Up 4.5V ≤ V IN ≤ 24V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 5.5V, 70ms Start-Up, I2C/ PMBus Interface, -1 Version Uses DrMOS or Power Blocks LTC3882/ LTC3882-1 Dual Output Multiphase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management 3V ≤ V IN ≤ 38V, 0.5V ≤ VOUT1,2 ≤ 5.25V, ±0.5% VOUT Accuracy I2C/ PMBus Interface, Uses DrMOS or Power Blocks LTC3866 Single Output Current Mode Synchronous Step-Down Controller with Sub-Milliohm DCR Sensing 4.5V ≤ V IN ≤ 38V, 0.6V ≤ VOUT ≤ 3.5V, with Remote VOUT Sense, 4mm × 4mm, QFN-24, TSSOP-24 Packages LTC3883/ LTC3883-1 Single Phase Step-Down DC/DC Controller with Digital Power System Management V IN Up to 24V, 0.5V ≤ VOUT ≤ 5.5V, Input Current Sense Amplifier , I2C/ PMBus Interface with EEPROM and 16-Bit ADC, ±0.5% VOUT Accuracy LTC3875 Dual, Multiphase Current Mode Synchronous Step-Down Controller with Sub-Milliohm DCR Sensing, Up to 12 Phases 4.5V ≤ V IN ≤ 38V, 0.6V ≤ VOUT ≤ 3.5V, with Remote Sense LTC3774 Dual, Multiphase Current Mode Synchronous Step-Down Controller with Sub-Milliohm DCR Sensing, Up to 12 Phases V IN Up to 40V, 0.6V ≤ VOUT ≤ 3.5V, Very High Output Current Applications with Accurate Current Share Between Phases Supporting LTC3880/-1, LTC3883/-1, LTC3886, LTC3887/-1 LTC3877 Dual Phase Step-Down Synchronous Controller with 6-Bit V ID Output Voltage Programming and Low Value DCR Sensing 4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 1.23V with VID in 10mV Steps, 0.6V ≤ VOUT ≤ 5V without VID, Up to 12-Phase Operation High Efficiency Dual 1.0V/1.5V Step-Down Converter PWM0 PWM1 L TC3874-1 INTVCC 0.22µF VCC0 VCC1 PHASMD LDWDCR ILIM FREQ GND RUN0 SYNC RUN1 FAUL T0 FAUL T1 RUN0 649/uni03A9 (0.29m/uni03A9 DCR) 0.215µH (0.29m/uni03A9 DCR) 0.215µH FAUL T0 FAUL T1 RUN1 SYNC REFER TO L TC3884-1 DATA SHEET FOR MASTER SETUP PIN NOT USED IN THIS CIRCUIT : EXTV CC ITH0 ITH1 VSENSE0+1V 1.5VVOUT1 100µF 100µF 470µF V OUT0 60A 470µF L TC3884-1 I SENSE0+ ISENSE0– ISENSE1+ ISENSE1– ITH0 ITH1 VSENSE1+ VIN 7V TO 14V VOUT1 1.5V 60A V IN PGOOD0 PGOOD1 MODE0 MODE1

3874 TA02

0.22µF 4.7µF 649/uni03A9

Summary

PolyPhase Step-Down Synchronous Slave Controller with Sub-Milliohm DCR Sensing

Description