LTM4677

LTM4650A-1 LINER | Alldatasheet

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4650a1fFor more information www.linear.com/LTM4650A-1 TYPICAL APPLICATION FEATURES DESCRIPTION Dual 25A or Single 50A DC/DC µModule Regulator with 1% DC Accuracy The LT M®4650A-1 is a dual 25A or single 50A output switching mode step-down DC/DC µModule® (micromod- ule) regulator with ±1% total DC output error . Included in the package are the switching controllers, power FET s, inductors and all supporting components. Operating from an input voltage range of 4.5V to 16V, the LTM4650A-1 supports two outputs with an output voltage range of 0.6V to 5.5V, each set by a single external resistor . Its high ef- ficiency design delivers up to 25A continuous current for each output. Only a few input and output capacitors are needed. Adjustable control loop compensation allows for fast transient response to minimize output capacitance when powering FPGAs, ASICs, and processors. Fault protection features include overvoltage and overcur- rent protection. The LTM4650A-1 is offered in 16mm × 16mm × 5.01mm BGA package. 50A, 3.3V Output DC/DC µModule Regulator

APPLICATIONS

n Dual 25A or Single 50A Output n Input Voltage Range: 4.5V to 16V n Output Voltage Range: 0.6V to 5.5V n ±1% Maximum Total DC Output Error Over Line, Load and Temperature n Higher Light Load Efficiency and Wider VOUT Range Than LTM4650-1 n Adjustable Control Loop Compensation n Differential Remote Sense Amplifier n Current Mode Control/Fast T ransient Response n Multiphase Parallel Current Sharing Up to 300A n Internal Temperature Monitor n Adjustable Switching Frequency or Synchronization n Overcurrent Foldback Protection n Selectable Burst Mode® Operation, Pulse-Skipping Mode Operation n Soft-Start/Voltage T racking n Output Overvoltage Protection n 16mm × 16mm × 5.01mm BGA Package n Telecom and Networking Equipment n Storage and ATCA Cards n Industrial Equipment L, L T , L TC, L TM, Linear Technology, the Linear logo, µModule, Burst Mode, PolyPhase and L TpowerCAD are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066 and 6580258. Other patents pending. 3.3VOUT Efficiency vs IOUT LOAD CURRENT (A) EFFICIENCY (%) 100 20 30 40 5010 4650a1 TA01b 5 VIN, 3.3VOUT, 600kHz 12 VIN, 3.3VOUT, 600kHz LTM4650 Product Family Selection Table VIN RANGE VOUT RANGE I OUT COMPEN- SATION DC VOUT ACCURACY LTM4650 4.5V to 15V 0.6V to 1.8V 25A × 2 Internal 1.5% LTM4650-1B External LTM6450-1A 0.8% LTM4650A 4.5V to 16V 0.6V to 5.5V Internal LTM4650A-1 External 4650a1 TA01a L TM4650A-1 VIN TEMP RUN1 RUN2 TRACK1 TRACK2 fSET 470µF 6.3V 13.3k 100µF 6.3V PHASMD V OUT1 VOUT 3.3V/50AVOUTS1 VFB1 VFB2 COMP1 COMP2 VOUT2 PGOOD2 MODE_PLLIN PINS UNUSED IN THIS APPLICATION: CLKOUT EXTV CC SW1 SW2 V OUTS2 INTVCC INTVCC PGOOD1 PGOOD 10k SGND GND DIFFP DIFFN DIFFOUT RTH CTH 470µF 6.3V 100µF 6.3V 120k 0.1µF 22µF 25V VIN 4.5V TO 16V 4.7µF INTVCC

4650a1f For more information www.linear.com/LTM4650A-1 PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS PGOOD1, PGOOD2, RUN1, RUN2, MODE_PLLIN, fSET, TRACK1, TRACK2, 3V to INTVCC V to INTVCC Internal Operating Temperature Range C to 125°C 5°C (Note 1) ORDER INFORMATION BGA PACKAGE 144-LEAD (16mm × 16mm × 5.01mm) TOP VIEW TEMP CLKOUT SW1 PHASMD EXTVCC 1 2 3 4 5 6 7 8 10 9 11 12 L K J H G F E D C B M A SW2 PGOOD1 PGOOD2 RUN2 TRACK2 INTVCC VOUTS2 DIFFP DIFFOUT DIFFN RUN1 TRACK1 MODE_PLLIN VFB1 VOUTS1 fSET SGND COMP1 COMP2 SGND VFB2 VIN VOUT2GND GND VOUT1 SGND GND TJMAX = 125°C, θJA = 7°C/W , θJCbottom = 1.5°C/W , θJCtop = 3.7°C/W , θJB + θJBA ≅ 7°C/W θ VALUES DEFINED PER JESD 51-12 WEIGHT = 3.8g PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TOTAL DC ACCURACY TEMPERATURE RANGE (Note 2)DEVICE FINISH CODE LTM4650AEY-1#PBF SAC305 (RoHS) LTM4650AY-1 e1 BGA 3 ±1% –40°C to 125°C LTM4650AIY-1#PBF SAC305 (RoHS) LTM4650AY-1 e1 BGA 3 ±1% –40°C to 125°C LTM4650AIY-1 SnPb (63/37) LTM4650AY-1 e0 BGA 3 ±1% –40°C to 125°C Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container . Pad or ball finish code is per IPC/JEDEC J-STD-609.

Terminal Finish Part Marking: www.linear .com/leadfree
Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www .linear .com/umodule/pcbassembly
LGA and BGA Package and T ray Drawings: www.linear .com/packaging http://www.linear .com/product/LTM4650A-1#orderinfo SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage l 4.5 16 V VOUT Output Voltage l 0.6 5.5 V VOUT1(DC), VOUT2(DC) Output Voltage, Total DC Variation with Line and Load (Note 7) C IN = 22µF × 3, COUT = 100µF × 1 Ceramic, 470µF POSCAP V IN = 4.5V to 16V, VOUT = 1.2V, IOUT = 0A to 25A l 1.188 1.2 1.212 V ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 34.

4650a1fFor more information www.linear.com/LTM4650A-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 34. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Specifications VRUN1, VRUN2 RUN Pin On/Off Threshold RUN Rising 1.1 1.25 1.40 V VRUN1HYS, VRUN2HYS RUN Pin On Hysteresis 150 mV IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A, CIN = 22µF ×3, CSS = 0.01µF, COUT = 100µF ×3, VOUT1 = 1.2V, VOUT2 = 1.2V, VIN = 12V 1 A IQ(VIN) Input Supply Bias Current (Both Channels On) VIN = 12V, VOUT = 1.2V, Burst Mode Operation VIN = 12V, VOUT = 1.2V, Pulse-Skipping Mode VIN = 12V, VOUT= 1.2V, Switching Continuous Shutdown, RUN = 0, VIN = 12V 4.5 115 mA mA mA µA I S(VIN) Input Supply Current VIN = 5V, VOUT = 1.2V, IOUT = 25A VIN = 12V, VOUT = 1.2V, IOUT = 25A 8.2 3.1 A A Output Specifications I OUT1(DC), IOUT2(DC) Output Continuous Current Range V IN = 12V, VOUT = 1.2V (Note 6) 0 25 A ΔVOUT1(LINE)/VOUT1 ΔVOUT2(LINE)/VOUT2 Line Regulation Accuracy For Each Output, V OUT = 1.2V, IOUT = 0A, VIN from 4.5V to 16V l 0.02 0.1 %/V ΔVOUT1/VOUT1 ΔVOUT2/VOUT2 Load Regulation Accuracy For Each Output, V IN = 12V, VOUT = 1.2V, IOUT from 0A to 25A l 0.1 0.4 % VOUT1(AC), VOUT2(AC) Output Ripple Voltage For Each Output, VIN = 12V, VOUT = 1.2V, Frequency = 450kHz, IOUT = 0A, COUT = 100µF ×3 Ceramic, 470µF POSCAP 15 mVP-P fS (Each Channel) Output Ripple Voltage Frequency V IN = 12V, VOUT = 1.2V, fSET = 1.25V (Note 4) 500 kHz fSYNC (Each Channel) SYNC Capture Range 250 780 kHz ΔVOUTSTART (Each Channel) Turn-On Overshoot COUT = 100µF ×3 Ceramic, 470µF POSCAP , VIN = 12V , VOUT = 1.2V, IOUT = 0A 10 mV tSTART (Each Channel) Turn-On T ime COUT = 100µF ×3 Ceramic, 470µF POSCAP , VIN = 12V, No Load, TRACK/SS with 0.01µF to GND 5 ms ΔVOUT(LS) (Each Channel) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 100µF ×3 Ceramic, 470µF POSCAP , VIN = 12V, VOUT = 1.2V 30 mV tSETTLE (Each Channel) Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, V IN = 12V, COUT = 100µF ×3 Ceramic, 470µF POSCAP 20 µs IOUT(PK) (Each Channel) Output Current Limit VIN = 12V, VOUT = 1.2V 30 A Control Section VFB1, VFB2 Voltage at VFB Pins IOUT = 0A, VOUT = 1.2V l 0.595 0.600 0.605 V IFB (Note 5) –5 –20 nA VOVL Feedback Overvoltage Lockout l 0.64 0.66 0.68 V ITRACK1, ITRACK2 T rack Pin Soft-Start Pull-Up CurrentTRACK1,TRACK2 Start at 0V 1 1.25 1.5 µA UVLO Undervoltage Lockout (Falling) 3.3 V UVLO Hysteresis 0.6 V tON(MIN) Minimum On-Time (Note 5) 90 ns RFBHI1, RFBHI2 Resistor Between VOUTS1, VOUTS2 and VFB1, VFB2 Pins for Each Output 60.05 60.4 60.75 kΩ VPGOOD1, VPGOOD2 Low PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V

4650a1f For more information www.linear.com/LTM4650A-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 34. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IPGOOD PGOOD Leakage Current V PGOOD = 5V ±5 µA VPGOOD PGOOD T rip Level VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive –10 INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6V < VIN < 16V 4.8 5 5.2 V VINTVCC Load Regulation INTVCC Load Regulation I CC = 0mA to 50mA 0.5 2 % VEXTVCC EXTVCC Switchover Voltage EXTV CC Ramping Positive 4.5 4.7 V VEXTVCC(DROP) EXTVCC Dropout ICC = 20mA, VEXTVCC = 5V 50 100 mV VEXTVCC(HYST) EXTVCC Hysteresis 220 mV Oscillator and Phase-Locked Loop Frequency Nominal Nominal Frequency fSET = 1.2V 450 500 550 kHz Frequency Low Lowest Frequency fSET = 0V 210 250 290 kHz Frequency High Highest Frequency fSET > 2.4V , Up to INTVCC 700 780 860 kHz fSET Frequency Set Current 9 10 11 µA RMODE_PLLIN MODE_PLLIN Input Resistance 250 kΩ CLKOUT Phase (Relative to VOUT1) PHASMD = GND PHASMD = Float PHASMD = INTVCC 120 Deg Deg Deg CLK High CLK Low Clock High Output Voltage Clock Low Output V oltage 0.2 V V Differential Amplifier A V Differential Amp Gain 1 V/V RIN Input Resistance Measured at DIFFP Input 80 kΩ VOS Input Offset Voltage VDIFFP = VDIFFOUT = 1.2V, IDIFFOUT = 100µA 3 mV PSRR Differential Amp Power Supply Rejection Ratio 4.5V < V IN < 16V 90 dB ICL Maximum Output Current 3 mA VOUT(MAX) Maximum Output Voltage I DIFFOUT = 300µA INTVCC – 1.4 V GBW Gain Bandwidth Product 3 MHz VTEMP Diode Connected PNP I = 100µA 0.6 V TC Temperature Coefficient l –2.2 mV/C Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4650A-1 is tested under pulsed load conditions such that T J ≈ TA. The LTM4650AE-1 is guaranteed to meet specifications from 0°C to 125°C internal temperature. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4650AI-1 is guaranteed over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: T wo outputs are tested separately and the same testing condition is applied to each output. Note 4: The switching frequency is programmable from 250kHz to 780kHz. Note 5: These parameters are tested at wafer sort. Note 6: See output current derating curve for different ambient temperature. Note 7: Total DC output voltage error includes all errors over temperature – reference, line and load regulation as well as the tolerance of the integrated top feedback resistor .

4650a1fFor more information www.linear.com/LTM4650A-1 TYPICAL PERFORMANCE CHARACTERISTICS Burst Mode and Pulse-Skip Mode Efficiency VIN=12V, VOUT = 1.2V, fS = 400kHz 1V Dual Phase Single Output Load T ransient Response (Ceramic Output Capacitor Only) Efficiency vs Output Current, V IN = 5V Efficiency vs Output Current, V IN = 12V LOAD CURRENT (A) EFFICIENCY (%) 100 10 15 20 255 4650a1 G01 2.5VOUT, 500kHz 3.3VOUT, 600kHz 1.8VOUT, 500kHz 1.5VOUT, 400kHz 1.2VOUT, 400kHz 1.0VOUT, 300kHz LOAD CURRENT (A) EFFICIENCY (%) 100 10 15 20 255 4650a1 G02 2.5VOUT, 500kHz 3.3VOUT, 600kHz 1.8VOUT, 500kHz 5.0VOUT, 750kHz 1.5VOUT, 400kHz 1.2VOUT, 400kHz 1.0VOUT, 300kHz LOAD CURRENT (mA) 0.01 0.1 100 EFFICIENCY (%) 4650a1 G03 CCM PULSE-SKIP MODE Burst Mode OPERATION VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G04 12VIN, 1VOUT , 300kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 8× 220/uni03BCF CERAMIC CAP RTH = 3.32k, CTH = 6800pF , CFF = 68pF 1.2V Dual Phase Single Output Load Transient Response (Ceramic Output Capacitor Only) 1.5V Dual Phase Single Output Load Transient Response (Ceramic Output Capacitor Only) VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G05 12VIN, 1.2VOUT , 400kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 8× 220/uni03BCF CERAMIC CAP RTH = 3.32k, CTH = 6800pF , CFF = 68pF VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G06 12VIN, 1.5VOUT , 400kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 8× 220/uni03BCF CERAMIC CAP RTH = 3.32k, CTH = 6800pF , CFF = 68pF 1.8V Dual Phase Single Output Load Transient Response (Ceramic Output Capacitor Only) 2.5V Dual Phase Single Output Load Transient Response (Ceramic Output Capacitor Only) VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G07 12VIN, 1.8VOUT , 500kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 8× 220/uni03BCF CERAMIC CAP RTH = 3.32k, CTH = 6800pF , CFF = 68pF VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G08 12VIN, 2.5VOUT , 500kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 8× 220/uni03BCF CERAMIC CAP RTH = 3.32k, CTH = 6800pF , CFF = 68pF 3.3V Dual Phase Single Output Load Transient Response (Ceramic Output Capacitor Only) VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G09 12VIN, 3.3VOUT , 600kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 8× 220/uni03BCF CERAMIC CAP RTH = 3.32k, CTH = 6800pF , CFF = 68pF

4650a1f For more information www.linear.com/LTM4650A-1 TYPICAL PERFORMANCE CHARACTERISTICS 2.5V Dual Phase Single Output Load Transient Response (Bulk Output Capacitor) 1.5V Dual Phase Single Output Load Transient Response (Bulk Output Capacitor) 1.8V Dual Phase Single Output Load Transient Response (Bulk Output Capacitor) 1.2V Dual Phase Single Output Load Transient Response (Bulk Output Capacitor) 1V Dual Phase Single Output Load Transient Response (Bulk Output Capacitor) VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G10 12VIN, 1VOUT , 300kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 4× 220/uni03BCF CERAMIC CAP + 2× 470/uni03BCF 2.5V SPCAP CTHP = 10pF , RTH = 4.65k, CTH = 4700pF , CFF = 10pF VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G11 12VIN, 1.2VOUT , 400kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 4× 220/uni03BCF CERAMIC CAP + 2× 470/uni03BCF 2.5V SPCAP CTHP = 10pF , RTH = 4.65k, CTH = 4700pF , CFF = 10pF VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G12 12VIN, 1.5VOUT , 400kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 4× 220/uni03BCF CERAMIC CAP + 2× 470/uni03BCF 2.5V SPCAP CTHP = 10pF , RTH = 4.65k, CTH = 4700pF , CFF = 10pF VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G13 12VIN, 1.8VOUT , 500kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 4× 220/uni03BCF CERAMIC CAP + 2× 470/uni03BCF 2.5V SPCAP CTHP = 10pF , RTH = 4.65k, CTH = 4700pF , CFF = 10pF VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G14 12VIN, 2.5VOUT , 500kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 4× 220/uni03BCF CERAMIC CAP + 2× 470/uni03BCF 2.5V SPCAP CTHP = 10pF , RTH = 4.65k, CTH = 4700pF , CFF = 10pF 5V Dual Phase Single Output Load Transient Response (Bulk Output Capacitor) 3.3V Dual Phase Single Output Load Transient Response (Bulk Output Capacitor) VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G15 12VIN, 3.3VOUT , 600kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 4× 220/uni03BCF CERAMIC CAP + 2× 470/uni03BCF 6.3V POSCAP CTHP = 10pF , RTH = 9.09k, CTH = 4700pF , CFF = NONE VOUT(AC) 50mV/DIV LOAD STEP 10A/DIV 100µs/DIV 4650a1 G16 12VIN, 5VOUT , 750kHz, DUAL PHASE SINGLE OUTPUT 25%, 12.5A LOAD STEP-UP AND STEP-DOWN, 10A/ /uni03BCs SLEW RATE COUT = 4× 220/uni03BCF CERAMIC CAP + 2× 470/uni03BCF 6.3V POSCAP CTHP = 10pF , RTH = 9.09k, CTH = 4700pF , CFF = NONE

4650a1fFor more information www.linear.com/LTM4650A-1 Single Phase Short Circuit Protection with 25A Load Single Phase Start-up with 25A Load Single Phase Short Circuit Protection with No Load Single Phase Start-Up with No Load SW 10V/DIV VOUT 0.5V/DIV INPUT CURRENT 0.2A/DIV 20ms/DIV 4650a1 G17 12VIN, 1.2VOUT , 400kHz COUT = 2× 470/uni03BCF SPCAP + 4× 100µF CERAMIC CAP CSS = 0.1µF SW 10V/DIV VOUT 0.5V/DIV INPUT CURRENT 2A/DIV 20ms/DIV 4650a1 G18 12VIN, 1.2VOUT , 400kHz COUT = 2× 470/uni03BCF SPCAP + 4× 100µF CERAMIC CAP CSS = 0.1µF SW 10V/DIV VOUT 0.5V/DIV INPUT CURRENT 5A/DIV 100/uni03BCs/DIV 4650a1 G19 12VIN, 1.2VOUT , 400kHz COUT = 2× 470/uni03BCF SPCAP + 4× 100µF CERAMIC CAP SW 10V/DIV VOUT 0.5V/DIV INPUT CURRENT 2A/DIV 100/uni03BCs/DIV 4650a1 G20 12VIN, 1.2VOUT , 400kHz COUT = 2× 470/uni03BCF SPCAP + 4× 100µF CERAMIC CAP TYPICAL PERFORMANCE CHARACTERISTICS

4650a1f For more information www.linear.com/LTM4650A-1 PIN FUNCTIONS VOUT1 (A1–A5, B1–B5, C1–C4): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 6. GND (A6–A7, B6–B7, D1–D4, D9–D12, E1–E4, E10–E12, F1–F3, F10–F12, G1, G3, G10, G12, H1–H7, H9–H12, J1, J5, J8, J12, K1, K5–K8, K12, L1, L12, M1 , M12): Power Ground Pins for Both Input and Output Returns. V OUT2 (A8–A12, B8–B12, C9–C12): Power Output Pins. Apply output load between these pins and GND pins. Rec- ommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 6. VOUTS1, VOUTS2 (C5, C8): This pin is connected to the top of the internal top feedback resistor for each output. The pin can be directly connected to its specific output, or connected to DIFFOUT when the remote sense amplifier is used. In paralleling modules, one of the V OUTS pins is connected to the DIFFOUT pin in remote sensing or directly to V OUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or V OUT since this is the feedback path, and cannot be left open. See the Applications Information section. f SET (C6): Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. SGND (C7, D6, G6–G7, F6–F7): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the ap- plication. See layout guidelines in Figure 14. V FB1, VFB2 (D5, D7): The Negative Input of the Error Am- plifier for Each Channel. Internally, this pin is connected to V OUTS1 or V OUTS2 with a 60.4kΩ precision resistor . Different output voltages can be programmed with an ad- ditional resistor between VFB and GND pins. In PolyPhase® operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. Do not drive this pin. TRACK1, TRACK2 (E5, D8): Output Voltage T racking Pin and Soft-Start Inputs. Each channel has a 1.3µA pull-up current source. When one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. The remaining channel can be set up as the slave, and have the master’s output applied through a voltage divider to the slave out- put’s track pin. This voltage divider is equal to the slave output’ s feedback divider for coincidental tracking. See the Applications Information section. COMP1, COMP2 (E6, E7): Current control threshold and error amplifier compensation point for each channel. The current comparator threshold increases with this control voltage. COMP pin internal has 10pF filter cap to SGND. An external RC filter circuit is required for control loop compensation. See Applications Information section. Tie the COMP pins together for parallel operation. Do not drive this pin. DIFFP (E8): Positive input of the remote sense amplifier . This pin is connected to the remote sense point of the output voltage. Diffamp can be used for ≤3.3V outputs. See the Applications Information section. DIFFN (E9): Negative input of the remote sense amplifier . This pin is connected to the remote sense point of the output GND. Diffamp can be used for ≤3.3V outputs. See the Applications Information section. MODE_PLLIN (F4): Force Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into force continuous mode of operation. Connect to INTV CC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. (Recommended to Use Test Points to Monitor Signal Pin Connections.) PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y .

4650a1fFor more information www.linear.com/LTM4650A-1 PIN FUNCTIONS RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above 1.25V will turn on each channel in the module. A voltage below 1.25V on the RUN pin will turn off the related chan- nel. Each RUN pin has a 1µA pull-up current, once the RUN pin reaches 1.2V an additional 4.5µA pull-up current is added to this pin. DIFFOUT (F8): Internal Remote Sense Amplifier Output. Connect this pin to VOUTS1 or VOUTS2 depending on which output is using remote sense. In parallel operation con - nect one of the VOUTS pin to DIFFOUT for remote sensing. SW1, SW2 (G2, G11): Switching node of each channel that is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information section. PHASMD (G4): Connect this pin to SGND, INTV CC, or float- ing this pin to select the phase of CLKOUT to 60 degrees, 120 degrees, and 90 degrees respectively. CLKOUT ( G5): Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. PGOOD1, PGOOD2 ( G9, G8): Output Voltage Power Good Indicator . Open drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. INTV CC (H8): Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from this voltage. Decouple this pin to PGND with a 4.7µF low ESR tantalum or ceramic. INTV CC is activated when either RUN1 or RUN2 is activated. TEMP (J6): Temperature Monitor . An internal diode con- nected NPN transistor connected between TEMP and SGND pins. See the Applications Information section. EXTVCC (J7): External power input that is enabled through a switch to INTVCC whenever EXTVCC is greater than 4.7V. Do not exceed 6V on this input, and connect this pin to VIN when operating VIN on 5V. An efficiency increase will occur that is a function of the (VIN – INTVCC) multiplied by power MOSFET driver current. Typical current requirement is 30mA. V IN must be applied before EXTVCC, and EXTVCC must be removed before VIN. VIN (M2–M11, L2–L11, J2–J4, J9–J11, K2–K4, K9–K11): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between V IN pins and GND pins. Heat Sink (Top Exposed Metal): The top exposed metal is electrically unconnected. (Recommended to Use Test Points to Monitor Signal Pin Connections.)

TA = 25°C. Use Figure 1 configuration. Figure 1. Simplified LTM4650A-1 Block Diagram

4650a1fFor more information www.linear.com/LTM4650A-1 OPERATION Power Module Description The LTM4650A-1 is a dual-output standalone nonisolated switching mode DC/DC power supply with ±1% total DC output error over line, load and temperature variation. It can provide two 25A outputs or single 50A output with few external input and output capacitors and setup com- ponents. This module provides precisely regulated output voltages programmable via external resistors from 0.6V DC to 5.5VDC over 4.5V to 16V input voltages. The typical application schematic is shown in Figure 34. The LTM4650A-1 has dual integrated constant-frequency current mode regulators and built-in power MOSFET devices with fast switching speed. The typical switching frequency is 300kHz to 750kHz depending on different input and output conditions. For switching-noise sensi - tive applications, it can be externally synchronized from 250kHz to 780kHz. A resistor can be used to program a free run frequency on the f SET pin. See the Applications Information section. With current mode control, multi LTM4650A-1s can be easily paralleled to provide up to 300A current with guaranteed perfect current sharing. Also, with current mode control, the LTM4650A-1 module is able to achieve sufficient stability margins and a very fast ±3% output transient response with a minimum number of output capacitors, even with all ceramic output capacitors. This makes LTM4650A-1 the best candidate when powering FPGAs, ASICs and processors in terms of DC accuracy, AC transient response, high output current and accuracy current sharing. See Applications Information section. Current mode control provides cycle-by-cycle fast current limit and foldback current limit in an overcurrent condition. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD outputs low if the output feedback voltage exits a ±10% window around the regulation point. As the output voltage exceeds 10% above regulation, the bottom MOSFET will turn on to clamp the output voltage. The top MOSFET will be turned off. This overvoltage protect is feedback voltage referred. Pulling the RUN pins below 1.1V forces the regulators into a shutdown state, by turning off both MOSFETs. The TRACK pins are used for programming the output voltage ramp and voltage tracking during start-up or used for soft-starting the regulator . See the Applications Information section. The LTM4650A-1 has a built-in 10pF high frequency filter cap from COMP to SGND for each output. An external RC filtering circuit is required to achieve fast Type II control loop compensation. Table 6 provides a guide line for input, output capacitances and R-C values on COMP pin for several operating conditions. The Linear Technology µModule Power Design Tool (L TpowerCAD ®) will be pro- vided for transient and stability analysis. The V FB pin is used to program the output voltage with a single external resistor to ground. A differential remote sense amplifier is available for sensing the output voltage accurately on one of the outputs at the load point, or in parallel operation sensing the output voltage at the load point. High efficiency at light loads can be accomplished with selectable Burst Mode operation or pulse-skipping opera- tion using the MODE_PLLIN pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the T ypical Performance Characteristics section. See the Applications Information section for details. A general purpose temperature diode is included inside the module to monitor the temperature of the module. See the Applications Information section for details. The switch pins are available for functional operation monitoring and a resistor-capacitor snubber circuit can be careful placed on the switch pin to ground to dampen any high frequency ringing on the transition edges. See the Applications Information section for details.

Figure 4. 4-Phase Parallel Configurations Table 1. VFB Resistor Table vs Various Output Voltages back setting resistor can be used for the parallel design. one programming resistor as shown in Figure 4. input ceramic capacitors are used for RMS ripple current. capacitor can be used for more input bulk capacitance. planes are used, then this bulk capacitor is not needed.

4650a1f For more information www.linear.com/LTM4650A-1 APPLICATIONS INFORMATION Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) η% • D • 1 − D( ) In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher- rated electrolytic aluminum capacitor , Polymer capacitor . Output Capacitors The LTM4650A-1 is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as C OUT are chosen with low enough effective series resistance (ESR) to meet the output volt- age ripple and transient requirements. COUT can be a low ESR tantalum capacitor , the low ESR polymer capacitor or ceramic capacitor . The typical output capacitance range for each output is from 300µF to 800µF per output channel. Additional output filtering may be required by the system designer , if further reduction of output ripples or dynamic transient spikes is required. Table 6 shows a matrix of dif- ferent output voltages and output capacitors to minimize the voltage droop and overshoot during a 25% load step. In multi LTM4650 A-1 paralleling applications, Table 6 RC compensation value is still valid in terms of having one set of RC filters on each of the paralleling modules while connecting all the COMP , FB and V OUT pins together . See Figure 37 and Multiphase Operation section. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 6 matrix, and the Linear Technol- ogy L TpowerCAD Design Tool will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology µModule Power Design Tool can calculate the output ripple reduc- tion as the number of implemented phases increases by N times. A small value 10Ω to 50Ω resistor can be place in series from VOUT to the VOUTS pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The same resistor could be place in series from V OUT to DIFFP and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. Burst Mode Operation The LTM4650A-1 is capable of Burst Mode operation on each regulator in which the power MOSFETs operate in - termittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at ver y light loads is a high priority, Burst Mode operation should be applied. Burst Mode operation is enabled with the MODE_PLLIN pin floating. During this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal opera- tion even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor ’ s average current is greater than the load requirement. As the COMP voltage drops below 0.5V, the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMP to rise above 0.5V, the internal sleep line goes low, and the LTM4650A-1 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4650A-1 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTV CC enables pulse-skipping operation. At light loads the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles.

Figure 5. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table

180 PHASE0 PHASE

90 DEGREE

270 PHASE90 PHASE

60 DEGREE 60 DEGREE

240 PHASE60 PHASE

300 PHASE120 PHASE

output ripple and lower noise than Burst Mode operation. current without increasing input and output voltage ripples. for clock phasing with the PHASMD table.

Figure 7. Operating Frequency vs fSET Pin Voltage and inductor current ripple. in continuous mode while being externally clock. set resistor for free run operation. and the gate charge required turning on the top MOSFET . good rule of thumb is to keep on-time longer than 110ns. during the soft-start process.

proportional to the master’s. the slave regulator , as shown in Figure 9. combination for the ratiometric tracking. pin offset to a negligible value. (SR), waveform as shown in Figure 10. = 1.5V and VOUT(SL) = 3.3V application. Figure 8. Output Ratiometric T racking Waveform

4650a1f For more information www.linear.com/LTM4650A-1 APPLICATIONS INFORMATION Power Good The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a 10% window around the regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. Stability Compensation The LTM4650A-1 has a built-in 10pF high frequency filter capacitor from COMP to SGND on each output channel. An external R-C filtering circuit is required to add from COMP to SGND to achieve fast Type II control loop compensation. Table 6 is provided for most application requirements. The Linear Technology µModule Power Design Tool (L Tpower- CAD) will be provided for other control loop optimization. Run Enable The RUN pins have an enable threshold of 1.4V maximum, typically 1.25V with 150mV of hysteresis. They control the turn on each of the channels and INTVCC. These pins can be pulled up to V IN for 5V operation, or a 5V Zener diode can be placed on the pins and a 10k to 100k resis- tor can be placed up to higher than 5V input for enabling the channels. There is 1µA pull-up current for each RUN pin. The LTM4650A-1 will turn on with RUN floating. Please note RUN has a 6V Abs Max voltage rating. The RUN pins can also be used for output voltage sequencing. In parallel operation the RUN pins can be tie together and controlled from a single control. See the Typical Applica- tion cir cuits in Figure 34. INTVCC and EXTVCC The LTM4650A-1 module has an internal 5V low dropout regulator that is derived from the input voltage. This regu- lator is used to power the control circuitry and the power MOSFET drivers. This regulator can source up to 70mA, and typically uses ~30mA for powering the device at the maximum frequency. This internal 5V supply is enabled by either RUN1 or RUN2. EXTV CC allows an external 5V supply to power the LTM4650A-1 and reduce power dissipation from the in - ternal low dropout 5V regulator . The power loss savings can be calculated by: (VIN – 5V) • 30mA = PLOSS EXTVCC has a threshold of 4.7V for activation, and a maximum rating of 6V. When using a 5V input, connect this 5V input to EXTVCC also to maintain a 5V gate drive level. EXTVCC must sequence on after V IN, and EXTV CC must sequence off before VIN. Differential Remote Sense Amplifier An accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. This is especially true for high current loads. The amplifier can be used on one of the two channels, or on a single parallel output. It is very important that the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to either V OUTS1 or V OUTS2. In parallel operation, the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to one of the V OUTS pins. Review the parallel schematics in Figure 35 and review Figure 4. Please note Diffamp can be used for ≤3.3V outputs. SW Pins The SW pins are generally for testing purposes by moni- toring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combina - tion is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance.

4650a1f For more information www.linear.com/LTM4650A-1 APPLICATIONS INFORMATION expression while measuring the forward voltage over temperature will provide a general temperature monitor . Connect a resistor between TEMP and V IN to set the cur- rent to 100µA. See Figure 35 for an example. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those param- eters defined by JESD51-9 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per formed on a µModule package mounted to a hardware test board —also defined by JESD51-9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regulator’s thermal performance in their ap- plication at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Con- figuration section are in-and-of themselves not relevant to providing guidance of thermal performance ; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section typically gives four thermal coefficients explicitly defined in JESD 51-12; these coef- ficients are quoted or paraphrased below: θJA, the thermal resistance from junction to ambi - ent, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition. θJCbottom, the thermal resistance from junction to the bottom of the product case, is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical µModule, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θJCTOP, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCBOTTOM, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule and into the board, and is really the sum of the θ JCbottom and the thermal re- sistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9. A graphical representation of the aforementioned thermal resistances is given in Figure 12; blue resistances are contained within the µModule regulator , whereas green resistances are external to the µModule. As a practical matter , it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclu- sively through the top or exclusively through bottom of the

Figure 12. Graphical Representation of JESD51-12 Thermal Coefficients

Table 6. Output Voltage Response vs Component Matrix (Refer to Figure 35) Load Step Typical Measured Values Notes 1 and 2. Different Bulk COUT1 used. See Part Number in Table 6. Note 3. CIN (BULK) may be required with long PCB traces.

Figure 34. Typical 4.5VIN to 16VIN, 1.5V and 1.2V at 25A Outputs

Figure 35. LTM4650A-1 2-Phase, 1V at 50A Design with ±3% T ransient Response

Figure 36. LTM4650A-1 2.5V and 3.3V Output with T racking Function

Figure 37. LTM4650A-1 4-Phase, 1.2V at 100A

4650a1f For more information www.linear.com/LTM4650A-1 LTM4650A-1 Component BGA Pinout PACKAGE DESCRIPTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 V OUT1 B1 V OUT1 C1 V OUT1 D1 GND E1 GND F1 GND A2 V OUT1 B2 V OUT1 C2 V OUT1 D2 GND E2 GND F2 GND A3 V OUT1 B3 V OUT1 C3 V OUT1 D3 GND E3 GND F3 GND A4 V OUT1 B4 V OUT1 C4 V OUT1 D4 GND E4 GND F4 MODE_PLLIN A5 V OUT1 B5 V OUT1 C5 V OUT1S D5 VFB1 E5 TRACK1 F5 RUN1 A6 GND B6 GND C6 f SET D6 SGND E6 COMP1 F6 SGND A7 GND B7 GND C7 SGND D7 VFB2 E7 COMP2 F7 SGND A8 V OUT2 B8 V OUT2 C8 V OUT2S D8 TRACK2 E8 DIFFP F8 DIFFOUT A9 V OUT2 B9 V OUT2 C9 V OUT2 D9 GND E9 DIFFN F9 RUN2 A10 V OUT2 B10 V OUT2 C10 V OUT2 D10 GND E10 GND F10 GND A11 V OUT2 B11 V OUT2 C11 V OUT2 D11 GND E11 GND F11 GND A12 V OUT2 B12 V OUT2 C12 V OUT2 D12 GND E12 GND F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND G2 SW1 H2 GND J2 V IN K2 V IN L2 V IN M2 V IN G3 GND H3 GND J3 V IN K3 V IN L3 V IN M3 V IN G4 PHASEMD H4 GND J4 V IN K4 V IN L4 V IN M4 V IN G5 CLKOUT H5 GND J5 GND K5 GND L5 V IN M5 V IN G6 SGND H6 GND J6 TEMP K6 GND L6 VIN M6 V IN G7 SGND H7 GND J7 EXTV CC K7 GND L7 V IN M7 V IN G8 PGOOD2 H8 INTV CC J8 GND K8 GND L8 V IN M8 V IN G9 PGOOD1 H9 GND J9 V IN K9 V IN L9 V IN M9 V IN G10 GND H10 GND J10 V IN K10 V IN L10 V IN M10 V IN G11 SW2 H11 GND J11 V IN K11 V IN L11 V IN M11 V IN G12 GND H12 GND J12 GND K12 GND L12 GND M12 GND

4650a1fFor more information www.linear.com/LTM4650A-1 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTM4650A-1#packaging for the most recent package drawings. 144-Lead (16mm × 16mm × 5.01mm) (Reference L TC DWG # 05-08-1523 Rev Ø) PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES D E b e e b F G BGA 144 1215 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PIN 1 L K J H G F E D C BM A SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.630 ±0.025 Ø 144x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL A Øb (144 PLACES) A DETAIL B PACKAGE SIDE VIEW Z M X Y Z ddd M Z eee DETAIL B SUBSTRATE ccc Z MOLD CAP SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 144 // bbb Z Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES

4650a1f For more information www.linear.com/LTM4650A-1  LINEAR TECHNOLOGY CORPORATION 2017 LT 0417 • PRINTED IN USA www.linear.com/LTM4650A-1 RELATED PARTS PACKAGE PHOTO DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

Selector Guides
Demo Boards and Gerber Files
Free Simulation Tools Manufacturing:
Quick Start Guide
PCB Design, Assembly and Manufacturing Guidelines
Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. PART NUMBER DESCRIPTION COMMENTS LTM4630A Lower Current than LTM4650A-1 with Internal Compensation; Up to 5.3V OUT, Dual 18A or Single 36A 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 5.3V; 16mm × 16mm × 4.41mm (LGA) LTM4630-1 Lower Current and Lower VOUT(MAX) than LTM4650A-1; Dual 18A or Single 36A; ±0.8% (–1A) or ±1.5% (–1B) DC VOUT Accuracy Pin Compatible with LTM4650A-1; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V; 16mm × 16mm × 5.01mm (BGA) LTM4630 Lower Current and Lower VOUT(MAX) than LTM4650A-1 with Internal Compensation; Dual 18A or Single 36A 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V; 16mm × 16mm × 4.41mm (LGA),16mm x 16mm x 5.01mm (BGA) LTM4620A Lower Current than LTM4650A-1 with Internal Compensation; Up to 5.3V OUT; Dual 13A or Single 26A 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V; 15mm 15mm × 4.41mm (LGA), 15mm × 15mm × 5.01mm (BGA) LTM4636 Single 40A µModule Regulator 4.7V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 3.3V; 16mm × 16mm x 7.07mm (BGA) LTM4677 Dual 18A or Single 36A with PSM 4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 1.8V; 16mm × 16mm × 5.01mm (BGA) LTM4644 Quad 4A 4V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V; 9mm × 15mm × 5.01mm (BGA) LTM4639 Lower VIN (2.375V ≤ VIN ≤ 7V), 20A 0.6V ≤ VOUT ≤ 5.5V; 15mm × 15mm × 4.92mm (BGA)

Summary

Dual 25A or Single 50A DC/DC 關Module Regulator with 1% DC Accuracy

Description