LS7210 LSI | Alldatasheet

Document overview

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Technical content

  • Programmable Delay from 6 ms to "Infinity"
  • Can be Cascaded for Sequential Events or Extended Delay
  • +4.75V to +15V Operation (Vss -V DD )
  • On Chip Oscillator or External Clock time base
  • High Noise Immunity
  • LS7210 (DIP), LS7210-S (SOIC)-See Figure 1 DESCRIPTION: The LS7210 is a monolithic MOS integrated circuit programmable digital timer that can generate a delay in the range of 6ms to infinity. The delay is programmed by 5 binary weighted input bits in combina- tion with the time base provided. The chip can be operated in four different modes: Delayed Operate, Delayed Release, Dual Delay and One Shot. These modes are selected by the control inputs A and B. INPUT/OUTPUT DESCRIPTION: OSCILLATOR Input (Pin 5) The frequency of the internal oscillator is set by an RC network con- nected to the OSC input, as shown in Figure 2. The nominal os- cillator frequency, f, at room temperature is given by f≈1/RC where R values range from a minimum of 47KΩ to a maximum 3MΩ . NOTE: Oscillation accuracy from chip to chip for a fixed value of RC, is + 10%. (Parts can supplied to tighter tolerances.) EXTERNAL CLOCK Input (Pin 6) If the internal oscillator is not used, the chip can be driven by an ex- ternal clock applied to this input. CLOCK SELECT Input (Pin 4) The internal oscillator or the external clock is selected by the proper logic level applied to this input. A logic 1 selects the external clock and logic 0 selects the internal oscillator. (See Note 1) TRIGGER Input (Pin 3) A positive or a negative transition at the trigger input initiates a delay in turning on or off the output. A negative transition always turns on the output with or without delay depending on the selected mode. A positive transition at the trigger input always turns off the output (with the exception of one-shot mode) with or without delay depending on the selected mode. The delay is a function of the time base fre- quency and the weighting factor programmed at the weighting bit in- puts. The trigger input is clocked into the input latch with the neg- ative edge of the selected time base clock. All timings begin after the latch has been set up. (See Note 1) WEIGHTING FACTOR Inputs, WB0-WB4 (Pins 12-8) A delay from the trigger input to the output is programmed by ap- plying 1's complement binary weighted numbers at these 5 inputs. (See Note 1) The exact equation for the delay is: Delay = (1 + 1, 023N) f = Oscillation Frequency f N = Weighting Factor

TABLE 1. WEIGHTING BITS ASSIGNMENTS WB0 should be programmed to logic 0. Table 2. The mode select inputs are clocked into the input latch- TABLE 2. MODE SELECTION verted with respect to the trigger input. Supply voltage positive, negative terminals. NOTE 1 : These inputs have internal pullup resistors.

This mode causes a retriggerable delay in turning off the output whenever there is a positive transition at the trigger input. The out- put is turned on without delay in response to a negative transition at the trigger input. ONE-SHOT MODE In this mode, the chip functions like a retriggerable monostable multi-vibrator. The output is turned on whenever there is a negative transition at the trigger input. At the end of the programmed delay, the output is turned off automatically. If there is a negative transition at the trigger input before the delay is over, the delay is restarted. A positive transition at the trigger input has no effect on the output in this mode. NOTE : In One-Shot mode, the TRIGGER input must be held at logic 1 during a power-up. ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to VDD ) SYMBOL VALUE UNIT DC Supply Voltage VSS +18 V Voltage (Any Pin) VIN 0 to VSS +.3 V Operating Temperature TA -25 to +70 °C Storage Temperature TSTG -65 to +150 °C DC ELECTRICAL CHARACERISTICS: (-25°C ≤TA ≤+70°C unless otherwise specified. All voltages referenced to VDD ) PARAMETER SYMBOL MIN MAX UNIT CONDITION Suppy Voltage VSS +4.75 +15.0 V Supply Current ISS - 3.0 mA VSS = +15V, output off Trigger Input Logic 1 VTH VSS -1 VSS V - Logic 0 VTL 0 .2VSS V - All Other Inputs Logic 1 VIH .8VSS VSS V - Logic 0 VIL 0 .2VSS V - Output Source Current Io +1.0 - mA VSS = + 5V for Vo = Vss - 1V Io +2.8 - mA VSS = +10V Io +4.2 - mA VSS = +15V SWITCHING CHARACTERISTICS: (See Figure 4) PARAMETER SYMBOL MIN MAX UNIT Oscillator Frequency fOSC - 50 KHz External Clock Frequency fext DC 160 KHz External Clock, Positive Pulse Width tH 3 - µs External Clock, Negative Pulse Width tL 3 - µs A,B and Trigger Input Set-Up Time tS - 300 ns Time-base Clock to Output Delay (turn-on delay in Delayed Release mode and turn-off delay in Delayed Operate mode) tnd - 1 µs Time-base Clock to Output Delay at the End of Time Out tod - 1.6 µs Time-base Clock to Output Delay tsd - 600 ns (turn-on delay in One- Shot Mode) MODE DEFINITION TIMING DIAGRAM : (See Figure 3) DUAL DELAY MODE Thls is the Default Mode when the inputs A and B are left un- programmed. The function of the Dual Delay mode is to provide a time delay on both the turn-on and turn-off of the output. Once turned on, the output will remain on as long as the trigger input is Logic 0. Once turned off, the output will remain off as long as the trigger input is a logic 1. DELAYED OPERATE MODE This mode causes a retriggerable delay in turning the output on in re- sponse to a negative edge at the trigger input. The output is turned off without delay in response to a positive transition at the trigger in- put.