LS7223 LSI | Alldatasheet
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Technical content
KEYPAD PROGRAMMABLE DIGITAL LOCK FEATURES :
- Stand alone lock logic
- 38416, 4-digit combinations
- 3 different user programmable codes
- Momentary and static lock control outputs
- Internal key debounce circuit
- Tamper detection output
- Status outputs
- Low current consumption
- +4V to +15V operation (VDD -VSS )
- LS7223 (DIP), LS7223-S (SOIC) - See Figure 1 GENERAL DESCRIPTION: The LS7223 is a programmable electronic lock implemented in a monolithic CMOS integrated circuit. The circuit contains all the necessary memory, decoder and control logic to make a programmable "keyless" lock system to control electro- mechanical locks. Input is provided by a matrix keypad whose maximum allowable size is 4 x 4. The LS7223 can be programmed to recognize 3 different codes: one to toggle an output and generate a pulse (Primary), one to toggle an output (Secondary), and one to toggle an output and trigger an alarm (Duress). Programming is done via the keypad inputs. Any entry from the keypad (when not in the program mode) which does not match one of the 3 programmed codes causes the Tamper output to become active. The monolithic, low power CMOS design of the LS7223 enables it to be designed into typical battery backed-up and automotive type security systems. DETAILED DESCRIPTION : CODES - There are 3 different function codes which the LS7223 can store in memory. Each code consists of a 4 digit number which must be entered in exact sequence and before the keypad entry enable time expires. The 3 codes and their functions are explained below. 1.The Primary code, when entered from the keypad, causes the Lock 1 output to toggle and the Momentary output to momentarily go high. Whenever power is first applied to the LS7223, the circuit defaults to the Primary code corresponding to the keys X1 Y1, X1 Y2, X2 Y2, X2 Y1. The code can then be altered to any other 4 digit code by entering the Program mode and keying in the new code. 2.The Secondary code, when entered from the key- pad, causes the Lock 2 output to toggle. The first 3 digits of the Secondary code must be identical to the first 3 digits of the Primary code; the 4th digit may or may not be identical for the two codes. When the two codes are the same in all 4 digits, the entry of the code will cause both the Lock 1 and the Lock 2 outputs to toggle. Whenever power is first applied to the LS7223, the circuit defaults to the Secondary code corresponding to the keys X1 Y1, X1 Y2, X2 Y2, X1 Y1. The code can then be altered by entering the Program mode. 3.The Duress code, when entered from the keypad, causes the Lock 1 output to toggle; at the same time the Alarm output will latch high to enable an external alarm. The first 3 digits of the Duress code must be identical to the first 3 digits of the Primary and Secondary codes; the 4th digit must be different to activate the Alarm output. Whenever power is first applied to the LS7223, the circuit defaults to the Duress code corresponding to the keys X1 Y1, X1 Y2, X2 Y2, X1 Y2. The code can then be altered the same way as the other two codes. 10 11 LSI CONNECTION DIAGRAM - TOP VIEW V DD (+V) CAP-K LOCK DISPLAY LOCK 1 LOCK 2 ALARM TAMPER CAP-M PROGRAM MOM V SS (-V) RC-OSC FIGURE 1 LS7223 December 2002 LSI/CSI LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 LS7223 7223-121102-1 U L® A3800
- Enter the current Secondary code causing the Lock 2 output
- Before the keypad entry enable time expires, enter the key
enable timer is disabled during the Program mode.
- Enter a 6-digit number from the keypad. The Program Mode
LS7223 and a new 6-digit number can be entered. the maximum matrix size of 4 by 4 does not have to be utilized. provides the LS7223 with very high noise immunity. high; this indicates that an illegal code entry was attempted. reset so that entry of the code can be attempted again. TABLE 1. PIN DESCRIPTIONS 1 Vss Supply voltage negative.
2 RC-OSC Determines the LS7223's internal clock frequency, which is used for keypad scanning and
10KHz and the internal anti-bounce is typically 25ms. 7, 8, 9, 10 Y1, Y2, Y3, Y4 whose maximum allowable size is 4 by 4. digit Primary/Secondary/Duress combination code has been programmed.
12 CAP-M A capacitor connected between this input and Vss controls the duration of the Momentary
13 TAMPER Whenever a key is entered that is not a valid code element, this output goes high for a
period determined by the capacitor on the CAP-M input. duration of this output is determined by the capacitor on the CAP-M input. to indicate the lock status.
19 CAP-K A capacitor connected between this input and Vss sets the time limit for entering a 4 digit
20 VDD Supply voltage positive.
FIGURE 2. Typical Application
- Keypad is typical 4 x 3 matrix type. Switch resistance should be ≤ 1kΩ .
- Configuration shown is typical. The outputs of the LS7223 are functionally designed
to provide either status or display information.
- Resistors may be added in series with X inputs to provide protection against ESD from the keypad. R = 10kΩ , 1/4 W