80220 LSI | Alldatasheet
Document overview
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Technical content
Features
n Single Chip 100Base-TX / 10Base-T Physical Layer Solution n Dual Speed - 100/10 Mbps n Half And Full Duplex n MII Interface To Ethernet Controller n MI Interface For Configuration & Status n Optional Repeater Interface n AutoNegotiation: 10/100, Full/Half Duplex n Meets All Applicable IEEE 802.3, 10Base-T, 100Base-TX Standards n On Chip Wave Shaping - No External Filters Required n Adaptive Equalizer n Baseline Wander Correction n Interface to External 100Base-T4 PHY n LED Outputs - Link - Activity - Collision - Full Duplex - 10/100 - User Programmable n Many User Features And Options n Few External Components n Pin configuration - 44L PLCC - 80220 - 64L LQFP - 80221 98184
Description
The 80220/80221 are highly integrated analog interface IC's for twisted pair Ethernet applications. The 80220/ 80221 can be configured for either 100 Mbps (100Base- TX) or 10 Mbps (10Base-T) Ethernet operation. The 80220 is packaged in a 44L package, while the 80221 is packaged in a 64L package and contains a few more features. The 80220/80221 consist of 4B5B/Manchester encoder/ decoder, scrambler/descrambler, 100Base-TX/10Base-T twisted pair transmitter with wave shaping and output driver, 100Base-TX/10Base-T twisted pair receiver with on chip equalizer and baseline wander correction, clock and data recovery, AutoNegotiation, controller interface (MII), and serial port (MI). The addition of internal output waveshaping circuitry and on-chip filters eliminates the need for external filters nor- mally required in 100Base-TX and 10Base-T applications. The 80220/80221 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with the on-chip AutoNegotiation algorithm. The 80220/80221 can access eleven 16-bit registers though the Management Interface (MI) serial port. These registers contain configuration inputs, status outputs, and device capabilities. The 80220/80221 are ideal as media interfaces for 100Base-TX/10Base-T adapter cards, motherboards, re- peaters, switching hubs, and external PHY's. Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, at www.lsilogic.com. This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic.
MDINT (MDA4) RX_DV CRS COL MDIO MDC RX_ER / RXD4 GND5 RXD1 RXD2 RXD3 GND6 RX_EN / JAM RX_CLK VCC5 44
40 REXT
PLED1 (MDA1) PLED0 (MDA0) TPI+ TPI- GND2 TX_CLK TXD0 TX_ER / TXD4 TXD1 TXD2 TXD3 TRFADJ0 TRFADJ1 OSCIN GND4 TX_EN VCC4 RXD0 VCC6 (MDA2) (MDA3) PLED2 PLED3 NC PLED4 PLED3 (MDA3) MDINT (MDA4) VCC4 VCC3 GND3 NC PLED2 (MDA2) MDIO COL RX_DV NC CRS MDC NC TX_EN GND4 OSCIN NC NC NC NC TRFADJ0 TRFADJ1 TX_CLK NC TX_ER / TXD4 TXD3 TXD2 TXD1 TXD0 VCC2 TPI+ TPI– GND2 PLED0 (MDA0) PLED5 NC REXT NC VCC1 TPO– NC NC TPO+ PLED1 (MDA1) GND1 NC RX_ER / R4D4 RPTR GND5 RXD0 RXD1 19RXD3 RXD2 VCC5 25 RX_CLK RX_EN / JAM T4ADV T4LINK VCC6 GND6 T4OE
80220 / 80221 TABLE OF CONTENTS
1.0 Pin Description
2.0 Block Diagram
3.0 Functional Description
3.1 General
3.2 Differences between 80220 and 80221
3.3 Controller Interface
3.3.1 General
3.3.2 MII - 100 Mbps
3.3.3 MII - 10 Mbps
3.3.4 FBI - 100 Mbps
3.3.5 Selection of MII or FBI
3.3.6 MII Disable
3.3.7 Receive Output High Impedance Control
3.3.8 TXEN to CRS Loopback Disable
3.4 Encoder
3.4.1 4B5B Encoder - 100 Mbps
3.4.2 Manchester Encoder - 10 Mbps
3.4.3 Encoder Bypass
3.5 Decoder
3.5.1 4B5B Decoder
3.5.2 Manchester Decoder
3.5.3 Decoder Bypass
3.5 Clock and Data Recovery
3.5.1 Clock Recovery - 100 Mbps
3.5.2 Data Recovery - 100 Mbps
3.5.3 Clock Recovery - 10 Mbps
3.5.4 Data Recovery - 10 Mbps
3.6 Scrambler
3.6.1 100 Mbps 3.6.2 10 Mbps
3.6.3 Scrambler Bypass
3.7 Descrambler
3.7.1 100 Mbps 3.7.2 10 Mbps
3.7.3 Descrambler Bypass
3.8 Twisted Pair Transmitter
3.8.1 100 Mbps 3.8.2 10 Mbps
3.8.3 Transmit Level Adjust
3.8.4 Transmit Rise and Fall Time Adjust
3.8.5 STP (150 Ohm) Cable Mode
3.8.6 Transmit Activity Indication
3.8.7 Transmit Disable
3.8.8 Transmit Powerdown
3.9 Twisted Pair Receiver
3.9.1 Receiver - 100 Mbps
3.9.2 Receiver - 10 Mbps
3.9.3 TP Squelch - 100 Mbps
3.9.4 TP Squelch - 10 Mbps
3.9.5 Equalizer Disable
3.9.6 Receive Level Adjust
3.9.7 Receive Activity Indication
3.10 Collision
3.10.1 100 Mbps 3.10.2 10 Mbps
3.10.3 Collision Test
3.10.4 Collision Indication
3.11 Start of Packet
3.11.1 100 Mbps 3.11.2 10 Mbps
3.12 End of Packet
3.12.1 100 Mbps 3.12.2 10 Mbps
3.13 Link Integrity & AutoNegotiation
3.13.1 General
3.13.2 10BaseT Link Integrity Algorithm - 10 Mbps 3.13.3 100BaseTX Link Integrity Algorithm - 100 Mbps
3.13.4 AutoNegotiation Algorithm
3.13.5 AutoNegotiation Outcome Indication
3.13.6 AutoNegotiation Status
3.13.7 AutoNegotiation Enable
3.13.8 AutoNegotiation Reset
3.13.9 Link Indication
3.13.10 Link Disable
3.13.11 100BaseT4 Capability
3.14 Jabber
3.14.1 100 Mbps 3.14.2 10 Mbps
3.14.3 Jabber Disable
3.15 Receive Polarity Correction
3.15.1 100 Mbps 3.15.2 10 Mbps
3.15.3 Autopolarity Disable
3.16 Full Duplex Mode
3.16.1 100 Mbps 3.16.2 10 Mbps
3.16.3 Full Duplex Indication
3.17 100 / 10 Mbps Selection
3.17.1 General
3.17.2 100 / 10 Mbps Indication
3.18 Loopback
3.18.1 Internal CRS Loopback
3.18.2 Diagnostic Loopback
3.19 Automatic JAM
3.19.1 100 Mbps 3.19.2 10 Mbps
3.20 Reset
3.21 Powerdown
3.22 Oscillator
3.23 LED Drivers
3.24 100Base-T4 Interface
3.25 Repeater Mode
3.26 MI Serial Port
3.26.1 Signal Description
3.26.2 Timing
3.26.3 Multiple Register Access
3.26.4 Bit Types
3.26.5 Frame Structure
3.26.6 Register Structure
3.26.7 Interrupt
4.0 Register Description
5.0 Application Information
5.1 Example Schematics
5.2 TP Transmit Interface
5.3 TP Receive Interface
5.4 TP Transmit Output Current Set
5.5 Cable Selection
5.6 Transmitter Droop
5.7 MII Controller Interface
5.7.1 General
5.7.2 Clocks
5.7.3 Output Drive
5.7.4 MII Disable
5.7.5 Receive Output Enable
5.8 FBI Controller Interface
5.9 Repeater Applications
5.9.1 MII Based Repeaters
5.9.2 Non-MII Based Repeaters
5.9.3 Clocks
5.10 Serial Port
5.10.1 General
5.10.2 Polling vs. Interrupt
5.10.3 Multiple Register Access
5.10.4 Serial Port Addressing
5.11 Long Cable
5.12 Automatic JAM
5.13 Oscillator
5.14 Programmable LED Drivers
5.15 Power Supply Decoupling
6.0 Specifications
7.0 Ordering Information
7.1 44 Pin PLCC 7.2 64 Pin LQFP
8.0 Package Diagrams
8.1 44 Pin PLCC 8.2 64 Pin LQFP
9.0 Addendum
80220 / 80221 TABLE OF CONTENTS continued
Pin# Pin I/O Description 44L 64L 28 32 VCC6 — Positive Supply. 5 ± 5% Volts 24 25 VCC5 11 8 VCC4 10 7 VCC3 1 57 VCC2 44 56 VCC1 27 31 GND6 — Ground. 0 Volts 23 23 GND5 36 41 GND4 9 6 GND3 4 60 GND2 41 52 GND1 42 54 TPO+ O Twisted Pair Transmit Output, Positive. 43 55 TPO - O Twisted Pair Transmit Output, Negative. 2 58 TPI+ I Twisted Pair Receive Input, Positive. 3 59 TPI - I Twisted Pair Receive Input, Negative. 40 50 REXT — Transmit Current Set. An external resistor connected between this pin and GND will set the output current level for the twisted pair outputs. 37 42 OSCIN I Clock Oscillator Input. There must be either a 25 Mhz crystal between this pin and GND or a 25 Mhz clock applied to this pin. TX_CLK output is generated from this input. 29 34 TX_CLK O Transmit Clock Output. This controller interface output provides a clock to an external controller. Transmit data from the controller on TXD, TX_EN, and TX_ER is clocked in on rising edges of TX_CLK and OSCIN. 35 40 TX_EN I Transmit Enable Input. This controller interface input has to be asserted active high to indicate that data on TXD and TX_ER is valid, and it is clocked in on rising edges of TX_CLK and OSCIN. 33 38 TXD3 I Transmit Data Input. These controller interface inputs contain input nibble data to be 32 37 TXD2 transmitted on the TP outputs, and they are clocked in on rising edges of TX_CLK and OSCIN 31 36 TXD1 when TX_EN is asserted. 30 35 TXD0 34 39 TX_ER / I Transmit Error Input. This controller interface input causes a special pattern to be TXD4 transmitted on the twisted pair outputs in place of normal data, and it is clocked in on rising edges of TX_CLK when TX_EN is asserted. If the device is placed in the Bypass 4B5B Encoder mode, this pin is reconfigured to be the fifth TXD transmit data input, TXD4. 25 26 RX_CLK O Receive Clock Output. This controller interface output provides a clock to an external controller. Receive data on RXD, RX_DV, and RX_ER is clocked out on falling edges of RX_CLK. 16 13 CRS O Carrier Sense Output. This controller interface output is asserted active high when valid data is detected on the receive twisted pair inputs, and it is clocked out on falling edges of RX_CLK. 17 14 RX_DV O Receive Data Valid Output. This controller interface output is asserted active high when valid decoded data is present on the RXD outputs, and it is clocked out on falling edges of RX_CLK. 19 19 RXD3 O Receive Data Output. These controller interface outputs contain receive nibble data from 20 20 RXD2 the TP input, and they are clocked out on falling edges of RX_CLK. 21 21 RXD1 22 22 RXD0 Name
Programmable LED Output/Management Interface Address Input. The default func- tion of this pin is to be a 100 Mbps Link Detect output. This pin can also be programmed through the MI serial port to indicate other events or be user controlled. This pin can drive an LED from VCC. When programmed as 100 Mbps Link Detect Output (default): 1= No Detect 0 = 100 Mbps Link Detected During powerup or reset, this pin is high impedance and the value on this pin is latched in as the physical device address MDA3 for the MI serial port. Programmable LED Output/Management Interface Address Input. The default func- tion of this pin is to be an Activity Detect output. This pin can also be programmed through the MI serial port to indicte other events or be user controlled. This pin can drive an LED from VCC. When programmed as an Activity Detect Output (default): 1 = No Activity 0 = Transmit Or Receive Packet Occurred, Hold Low for 100 mS During powerup or reset, this pin is high impedance and the value on this pin is latched in as the physical device address MDA2 for the MI serial port. Programmable LED Output/Management Interface Address Input. The default func- tion of this pin is to be a Full Duplex Detect output. This pin can also be programmed through the MI serial port to indicate other events or be user controlled. This pin can drive an LED from both VCC and GND. When programmed as Full Duplex Detect Output (default). 1 = Half Duplex 0 = Full Duplex During powerup or reset, this pin is high impedance and the value on this pin is latched in as the physical address device address MDA1 for the MI serial port. 18 18 RX_ER / O Receive Error Output. This controller interface output is asserted active high when a RXD4 coding or other specified errors are detected on the receive twisted pair inputs and it is clocked out on falling edges of RX_CLK. If the device is placed in the Bypass 4B5B Decoder mode, this pin is reconfigured to be the fifth RXD receive data output, RXD4. 15 12 COL O Collision Output. This controller interface output is asserted active high when a collision between transmit and receive data is detected. 13 10 MDC I Management Interface (MI) Clock Input. This MI clock shifts serial data into and out of MDIO on rising edges. 14 11 MDIO I/O Management Interface (MI) Data Input/Output. This bidirectional pin contains serial MI data that is clocked in and out on rising edges of the MDC clock. 12 9 MDINT I/O Management Interface Interrupt Output/Management Interface Address Input. This (MDA4) O.D. pin is an interrupt output and is asserted active low whenever there is a change in certain Pullup MI serial port register bits, and deasserted after all changed bits have been read out. During powerup or reset, this pin is high impedance and the value on this pin is latched in as the physical device address MDA4 for the MI serial port 8 4 PLED3 I/O (MDA3) O.D. Pullup 7 3 PLED2 I/O (MDA2) O.D. Pullup 6 62 PLED1 I/O (MDA1) Pullup Pin Description continued Pin# Pin I/O Description 44L 64L Name
(MDA0) Pullup 38 45 TRFADJ1 I Twisted Pair Output Rise/Fall Time adjust Input. These digital inputs adjust the 39 46 TRFADJ0 Pullup rise/fall time on the TPO± outputs. Pulldown 11 = Rise/Fall Time Changed -0.25 nS 10 = Rise/Fall Time Changed in MI Serial Port (Default = 0.0 nS) 01 = Rise/Fall Time Changed +0.25 nS 00 = Rise/Fall Time Changed +0.50 nS 26 27 RX_EN/ I Receive Enable Input JAM 1 = All Outputs Enabled 0 = Receive Controller Outputs are High Impedance (RX_CLK, RXD[3:0], RX_DV, RX_ER, COL). I Automatic Jam Input 1 = Normal 0 = Jam Packet Transmitted when Receive Activity Detected — 63 PLED5 O Receive LED Output. The function of this pin is to be a Receive O.D. Activity Detect output and this pin can drive an LED from VCC. Pullup 1 = No Receive Activity 0 = Receive Packet Occurred, Hold Low for 100 mS — 2 PLED4 O Transmit LED Output. The function of this pin is to be a Transmit O.D. Activity Detect output and this pin can drive an LED from VCC. Pullup 1 = No Transmit Activity 0 = Transmit Packet Occurred, Hold Low for 100 mS — 30 T4ADV I 100Base-T4 AutoNegotiation Advertise Input. This input causes the AutoNegotiation Pulldown algorithm to advertise 100Base-T4 as one of the operating modes. 1 = Advertise 100Base-T4 Capability During AutoNegotiation 0 = No Advertise — 29 T4OE O 100Base-T4 Output Enable. This output indicates that the AutoNegotiation algorithm has selected 100Base-T4 as the operating mode and can be used to enable and external 100Base-T4 PHY. When asserted, the TP outputs are high impedance. — 24 RPTR I Repeater Mode Enable Input. Pulldown 1 = Repeater Mode Enabled 0 = Normal Operation Pin# Pin I/O Description 44L 64L Name Pin Description continued Programmable LED Output/Management Interface Address Input. The default function of this pin is to be a 10 Mbps Link Detect output. This pin can also be programmed through the MI serial port to indicate other events or be user controlled. This pin can drive an LED from both VCC and GND. When programmed as 10 Mbps Link Detect Output (default): 1 = No Detect 0 = 10 Mbps Link Detected During powerup or reset, this pin is high impedance and the value on this pin is latched in as the address MDA0 for the MI serial port.
— 28 T4LNK I 100Base-T4 Link Detect Input. This input indicates to the device the link status of Pullup an external 100Base-T4 PHY. 1 = No Detect 0 = 100Base-T4 link Detected from external PHY —1N C No Connect. Pin# Pin I/O Description 44L 64L Pin Description continued
Note 1: These pins available on 64L 80221 version only. Figure 1. 80220 / 80221 Block Diagram
AutoNegotiation. A block diagram is shown in Figure 1. mode is data rate, signalling protocol, and allowed wiring. drives the twisted pair cable. Figure 2. Twisted Pair Frame Format
100 BASE-TX TP DATA SYMBOLS
10 BASE-T TP DATA SYMBOLS
- 1st preamble nibble transmitted.
- 1st sfd nibble transmittted.
- 1st data nibble transmitted.
- D0 thru D7 are the first 8 bits of the data field.
- 1st preamble nibble received. Depending on mode, device may eliminate
either all or some of the preamble nibbles, up to 1st SFD nibble.
- 1st data nibble received.
- D0 thru D7 are the first 8 bits of the data field.
Figure 3. MII Frame Format
Ethernet controller by the controller interface.
10 Mbps operation is similar to the 100 Mbps operation
detected from a remote device. Table 1. 80220 vs. 80221 MII) and Five Bit interface (referred to as the FBI). MII frame format is shown in Figure 3. operate at 25 MHz in 100 Mbps mode.
- When all data on TXD[3:0] has been latched into the
in IEEE 802.3 and shown in Table 2. data and is specified in IEEE 802.3 and shown in Figure 3.
When the end of packet is detected, CRS and RX_DV are deasserted, and RXD[3:0] is held low. CRS and RX_DV also stay deasserted if the device is in the Link Fail State. RX_ER is a receive error output which is asserted when certain errors are detected on a data nibble. RX_ER is asserted on the falling edge of RX_CLK for the duration of that RX_CLK clock cycle during which the nibble contain- ing the error is being outputted on RXD[3:0]. The collision output, COL, is asserted whenever the colli- sion condition is detected.
10 Mbps operation is identical to the 100 Mbps operation
except, (1) TX_CLK and RX_CLK clock frequency is reduced to 2.5 MHZ, (2) TX_ER is ignored, (3) RX_ER is disabled and always held low, and (4) receive operation is modified as follows: On the receive side, when the squelch circuit determines that invalid data is present on the TP inputs, the receiver is idle. During idle, RX_CLK follows TX_CLK, RXD[3:0] is held low, and CRS and RX_DV are deasserted. When a start of packet is detected on the TP receive inputs, CRS is asserted and the clock recovery process starts on the incoming TP input data. After the receive clock has been recovered from the data, the RX_CLK is switched over to the recovered clock and the data valid signal RX_DV is asserted on a falling edge of RX_CLK. Once RX_DV is asserted, valid data is clocked out on RXD[3:0] on falling edges of the RX_CLK clock. The RXD[3:0] data has the same packet structure as the TXD[3:0] data and is formatted on RXD[3:0] as specified in IEEE 802.3 and shown in Figure 3. When the end of packet is detected, CRS and RX_DV are deasserted. CRS and RX_DV also stay deasserted as long as the device is in the Link Fail State. The Five Bit Interface (also referred to as the FBI) is a five bit wide interface that is produced when the 4B5B encoder/ decoder is bypassed. The FBI is primarily used for repeat- ers or Ethernet controllers which have integrated encoder/ decoders. The FBI is identical to the MII except, (1) the FBI data path is five bits wide, not nibble wide like the MII, (2) TX_ER pin is reconfigured to be the fifth transmit data bit, TXD4, and (3) RX_ER pin is reconfigured to be the fifth receive data bit RXD4, (4) CRS is asserted as long as the device is in the Link Pass State, (5) COL is not valid, (6) RX_DV is not valid, and (7) TX_EN is ignored.
3.3.5 FBI - 10 Mbps
The FBI is not available in 10 Mbps mode.
3.3.6 Selection Of MII Or FBI
The FBI is automatically enabled when the 4B5B encoder/ decoder is bypassed. Bypassing the encoder/decoder passes the 5B symbols between the receiver/transmitter directly to the FBI without any alteration or substitutions noted in the Encoder and Decoder sections. The 4B5B encoder/decoder can be bypassed by setting the bypass encoder bit in the MI serial port Configuration 1 register. When the FBI is enabled, it may also be desirable to bypass the scrambler/descrambler and disable the inter- nal CRS loopback function. The scrambler/descrambler can be bypassed by setting the bypass scrambler bit in the MI serial port Configuration 1 register. The internal CRS loopback can be disabled by setting the TX_EN to CRS loopback disable bit in the MI serial port Configuration 1 register.
3.3.7 MII Disable
The MII and FBI inputs and outputs can be disabled by setting the MII disable bit in the MI serial port Control register. When the MII is disabled, the MII/FBI inputs are ignored, the MII/FBI outputs are placed in high impedance state, and the TP output is high impedance. If the MI address lines, MDA[4:0], are pulled high during reset or powerup, the 80220/80221 powers up and resets with the MII and FBI disabled. Otherwise, the 80220/ 80221 powers up and resets with the MII and FBI enabled.
3.3.8 Receive Output High Impedance Control
The RX_EN/JAM pin can be configured to be RX_EN, a high impedance control for the receive controller output signals, by setting the R/J Configuration select bit in the MI serial port Configuration 2 register. When this pin is configured to be RX_EN and is deasserted active low, the following outputs will be placed in the high impedance state: RX_CLK, RXD[3:0], RX_DV, RX_ER, and COL.
3.3.9 TX_EN to CRS Loopback Disable
The internal TX_EN to CRS loopback can be disabled by appropriately setting the TXEN to CRS loopback disable bit in the MI serial port Configuration 1 register.
100Base-TX requires that the data be 4B5B encoded. words is specified in IEEE 802.3 and shown in Table 2. ous stream of idle symbols, as shown in Figure 2. Figure 2. The Manchester encoding process is only done is not Manchester encoded and filled with link pulses. Table 2. 4B/5B Symbol Mapping
0 Data 0 11110 0000
1 Data 1 01001 0001
2 Data 2 10100 0010
3 Data 3 10101 0011
4 Data 4 01010 0100
5 Data 5 01011 0101
6 Data 6 01110 0110
7 Data 7 01111 0111
8 Data 8 10010 1000
9 Data 9 10011 1001
encoded to 5B 11110, as shown in symbol Data 0.
The 4B5B encoder can be bypassed by setting the bypass encoder/decoder bit in the MI serial port Configuration 1 register. When this bit is set to bypass the encoder/ decoder, 5B code words are passed directly from the controller interface to the scrambler without any of the alterations described in the 4B5B Encoder section. Setting this bit automatically places the device in the FBI mode as described in the Controller Interface section.
3.4 DECODER
3.4.1 4B5B Decoder - 100 Mbps Since the TP input data is 4B5B encoded on the transmit side, it must also be decoded by the 4B5B decoder on the receive side. The mapping of the 5B nibbles to the 4B code words is specified in IEEE 802.3 and shown in Table 2. The 4B45 decoder on the 80220/80221 takes the 5B code words from the descrambler, converts them into 4B nibbles per Table 2, and sends the 4B nibbles to the controller interface. The 4B5B decoder also strips off the SSD delimiter (a.k.a. /J/K/ symbols) and replaces them with two 4B Data 5 nibbles (a.k.a /5/ symbol), and strips off the ESD delimiter (a.k.a /T/R/ symbols) and replaces it with two 4B Data 0 nibbles (a.k.a /I/ symbol), per IEEE 802.3 specifications and shown in Figure 2. The 4B5B decoder detects SSD, ESD and, codeword errors in the incoming data stream as specified in IEEE 802.3. These errors are indicated by asserting RX_ER output while the errors are being transmitted across RXD[3:0], and they are also indicated in the serial port by setting SSD, ESD, and codeword error bits in the MI serial port Status Output register.
3.4.2 Manchester Decoder - 10 Mbps
In Manchester coded data, the first half of the data bit contains the complement of the data, and the second half of the data bit contains the true data. The Manchester decoder in the 80220/80221 converts the Manchester encoded data stream from the TP receiver into NRZ data for the controller interface by decoding the data and stripping off the SOI pulse. Since the clock and data recovery block has already separated the clock and data from the TP receiver, the Manchester decoding process to NRZ data is inherently performed by that block.
3.4.3 Decoder Bypass
The 4B5B decoder can be bypassed by setting the bypass encoder/decoder bit in the MI serial port Configuration 1 register. When this bit is set to bypass the encoder/ decoder, (1) 5B code words are passed directly to the controller interface from the descrambler without any of the alterations described in the 4B5B Decoder section, and (2) CRS is continuously asserted whenever the device is in the Link Pass state. Setting this bit automatically places the device in the FBI mode as described in the Controller Interface section. Clock recovery is done with a PLL. If there is no valid data present on the TP inputs, the PLL is locked to the 25 MHz TX_CLK. When valid data is detected on the TP inputs with the squelch circuit and when the adaptive equalizer has settled, the PLL input is switched to the incoming data on the TP input. The PLL then recovers a clock by locking onto the transitions of the incoming signal from the twisted pair wire. The recovered clock frequency is a 25 MHz nibble clock, and that clock is outputted on the controller interface signal RX_CLK. Data recovery is performed by latching in data from the TP receiver with the recovered clock extracted by the PLL. The data is then converted from a single bit stream into nibble wide data word according to the format shown in Figure 3. The clock recovery process for 10 Mbps mode is identical to the 100 Mbps mode except, (1) the recovered clock frequency is 2.5 MHz nibble clock, (2) the PLL is switched from TX_CLK to the TP input when the squelch indicates valid data, (3) The PLL takes up to 12 transitions (bit times) to lock onto the preamble, so some of the preamble data symbols are lost, but the clock recovery block recovers enough preamble symbols to pass at least 6 nibbles of preamble to the receive controller interface as shown in Figure 3. The data recovery process for 10 Mbps mode is identical to the 100 Mbps mode. As mentioned in the Manchester Decoder section, the data recovery process inherently performs decoding of Manchester encoded data from the TP inputs. 3.6.1 100 Mbps 100Base-TX requires scrambling to reduce the radiated emissions on the twisted pair. The 80220/80221 scram- bler takes the encoded data from the 4B5B encoder, scrambles it per the IEEE 802.3 specifications, and sends it to the TP transmitter.
3.6.2 10 Mpbs A scrambler is not used in 10 Mbps mode. The scrambler can be bypassed by setting the bypass scrambler/descrambler bit in the MI serial port Configura- tion 1 register. When this bit is set, the 5B data bypasses the scrambler and goes directly from the 4B5B encoder to the twisted pair transmitter. 3.7.1 100 Mbps The 80220/80221 descrambler takes the scrambled data from the data recovery block, descrambles it per the IEEE 802.3 specifications, aligns the data on the correct 5B word boundaries, and sends it to the 4B5B decoder. The algorithm for synchronization of the descrambler is the same as the algorithm outlined in the IEEE 802.3 specification. Once the descrambler is synchronized, it will maintain synchronization as long as enough descrambled idle pattern 1's are detected within a given interval. To stay in synchronization, the descrambler needs to detect at least 25 consecutive descrambled idle pattern 1's in a 1 mS interval. If 25 consecutive descrambled idle pattern 1's are not detected within the 1 mS interval, the descrambler goes out of synchronization and restarts the synchronization process. If the descrambler is in the unsynchronized state, the descrambler loss of synchronization detect bit is set in the MI serial port Status Output register to indicate this condi- tion. Once this bit is set, it will stay set until the descrambler achieves synchronization. 3.7.2 10 Mpbs A descrambler is not used in 10 Mbps mode. The descrambler can be bypassed by setting the bypass scrambler/descrambler bit in the MI serial port Configura- tion 1 register. When this bit is set, the data bypasses the descrambler and goes directly from the TP receiver to the 4B5B decoder.
3.8.1 Transmitter - 100 Mbps
The transmitter consists of a MLT-3 encoder, waveform generator and line driver. The MLT-3 encoder converts the NRZ data from the scrambler into a three level MLT-3 code required by IEEE 802.3. MLT-3 coding uses three levels and converts 1's to transitions between the three levels, and converts 0's to no transitions or changes in level. The purpose of the waveform generator is to shape the transmit output pulse. The waveform generator takes the MLT-3 three level encoded waveform and uses an array of switched current sources to control the rise/fall time and level of the signal at the output. The output of the switched current sources then goes through a low pass filter in order to "smooth" the current output and remove any high frequency components. In this way, the waveform gen- erator preshapes the output waveform transmitted onto the twisted pair cable to meet the pulse template require- ments outlined in IEEE 802.3. The waveform generator eliminates the need for any external filters on the TP transmit output. The line driver converts the shaped and smoothed wave- form to a current output that can drive 100 meters of category 5 unshielded twisted pair cable or 150 Ohm shielded twisted pair cable.
3.8.2 Transmitter - 10 Mbps
The transmitter operation in 10 Mbps mode is much different than the 100 Mbps transmitter. Even so, the transmitter still consists of a waveform generator and line driver. The purpose of the waveform generator is to shape the output transmit pulse. The waveform generator consists of a ROM, DAC, clock generator, and filter. The DAC generates a stair-stepped representation of the desired output waveform. The stairstepped DAC output then goes through a low pass filter in order to "smooth" the DAC output and remove any high frequency components. The DAC values are determined from the ROM outputs; the ROM contents are chosen to shape the pulse to the desired template and are clocked into the DAC at high speed by the clock generator. In this way, the waveform generator preshapes the output waveform to be transmit- ted onto the twisted pair cable to meet the pulse template requirements outlined in IEEE 802.3 Clause 14 and also shown in Figure 4. The waveshaper replaces and elimi- nates external filters on the TP transmit output. The line driver converts the shaped and smoothed wave- form to a current output that can drive 100 meters of category 3/4/5 100 Ohm unshielded twisted pair cable or
150 Ohm shielded twisted pair cable tied directly to the TP
output pins without any external filters. During the idle period, no output signal is transmitted on the TP outputs (except link pulse).
Figure 4. TP Output Voltage Template-10 Mbps
reference voltage and the external resistor on REXT pin. mately -14% to +16% in 2% steps. Table 3. Transmit Level Adjust
- The adjustment range is -0.25 nS to +0.5 nS in 0.25 nS
and the TRFADJ[1:0] bits are disabled. justed to comply with IEEE 802.3 levels. serted low for 100 mS every time a transmit packet occurs. disable bit in the MI serial port Configuration 1 register. pulses are transmitted, and internal loopback is disabled. 3 decoder. The TP inputs first go to an adaptive equalizer.
Figure 5. The inputs are biased by internal resistors. The recovery in the Manchester decoder. determines if the receive input data on that channel is valid. If the data is invalid, the receiver is in the squelched state.
3.9.4 TP Squelch, 10 Mbps
ments defined in IEEE 802.3 Clause 14. device may be able to support longer cable lengths. Figure 5. TP Input Voltage Template-10Mbps
Receive activity can be programmed to appear on some of the PLED[5:0] pins by appropriately setting the program- mable LED output select bits in the MI serial port LED Configuration 2 register as shown in Table 5. When one or more of the PLED[5:0] pins is programmed to be an receive activity or activity detect output, that pin is asserted low for 100 mS every time a receive packet occurs. The PLED[5:0] outputs are open drain with pullup resistor and can drive an LED from VCC or can drive another digital input. 3.10.1 100 Mbps Collision occurs whenever transmit and receive occur simultaneously while the device is in Half Duplex. Collision is sensed whenever there is simultaneous trans- mission (packet transmission on TPO±) and reception (non idle symbols detected on TP input). When collision is detected, the COL output is asserted, TP data continues to be transmitted on twisted pair outputs, TP data continues to be received on twisted pair inputs, and internal CRS loopback is disabled. Once collision starts, CRS is as- serted and stays asserted until the receive and transmit packets that caused the collision are terminated. The collision function is disabled if the device is in the Full Duplex mode, is in the Link Fail state, or if the device is in the diagnostic loopback mode. 3.10.2 10 Mbps Collision in 10 Mbps mode is identical to the 100 Mbps mode except, (1) reception is determined by the 10 Mbps squelch criteria, (2) RXD[3:0] outputs are forced to all 0's, (3) collision is asserted when the SQE test is performed, (4) collision is asserted when the jabber condition has been detected. The controller interface collision signal, COL, can be tested by setting the collision test register bit in the MI serial port Control register. When this bit is set, TX_EN is looped back onto COL and the TP outputs are disabled. Collision can be programmed to appear on the PLED2 pin by appropriately setting the programmable LED output select bits in the MI serial port Configuration 2 register, as shown in Table 5. When the PLED2 pin is programmed to be a collision detect output, this pin is asserted low for 100 mS every time a collision occurs. The PLED2 output is open drain with pullup resistor and can drive an LED from VCC or can drive another digital input. 3.11.1 100 Mbps Start of packet for 100 Mbps mode is indicated by a unique Start of Stream Delimiter (referred to as SSD). The SSD pattern consists of the two /J/K/ 5B symbols inserted at the beginning of the packet in place of the first two preamble symbols, as defined in IEEE 802.3 Clause 24 and shown in Figure 2. The transmit SSD is generated by the 4B5B encoder and the /J/K/ symbols are inserted by the 4B4B encoder at the beginning of the transmit data packet in place of the first two 5B symbols of the preamble, as shown in Figure 2. The receive pattern is detected by the 4B5B decoder by examining groups of 10 consecutive code bits (two 5B words) from the descrambler. Between packets, the re- ceiver will be detecting the idle pattern, which is 5B /I/ symbols. While in the idle state, CRS and RX_DV are deasserted. If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of the /J/K/ symbols, the start of packet is detected, data reception is begun, CRS and RX_DV are asserted, and /5/5/ symbols are substituted in place of the /J/K/ symbols. If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /I/ I/ nor /J/K/ symbols but contains at least 2 non contiguous 0's, then activity is detected but the start of packet is considered to be faulty and a False Carrier Indication (also referred to as bad SSD) is signalled to the controller interface. When False Carrier is detected, then CRS is asserted, RX_DV remains deasserted, RXD[3:0]=1110 while RX_ER is asserted, and the bad SSD bit is set in the MI serial port Status Output register. Once a False Carrier Event is detected, the idle pattern (two /I/I/ symbols) must be detected before any new SSD's can be sensed. If the receiver is in the idle state and 10 consecutive code bits from the receiver consist of a pattern that is neither /I/ I/ nor /J/K/ symbols but does not contain at least 2 non- contiguous 0's, the data is ignored and the receiver stays in the idle state. 3.11.2 10 Mbps Since the idle period in 10 Mbps mode is defined to be the period when no data is present on the TP inputs, then the
the end of the transmit data packet, as shown in Figure 2. to determine if there is an ESD. in place of the /T/R/ symbols. Clause 14 and shown in Figure 6.
0.5 V/ns
Figure 6. SOI Output Voltage Template - 10 Mbps
(2) to establish an active link to and from a remote device. Figure 7. Refer to IEEE 802.3 Clause 14 for more details algorithms for more details. rithm that is defined in IEEE 802.3 Clause 28. templated specified in IEEE 802.3 and shown in Figure 7. Figure 7. Link Pulse Output Voltage Template _ NLP, FLP
802.3 Clause 28 for more details. serial port Status Output register. been initiated and successfully completed. Figure 8. NLP vs. FLP Link Pulse
The AutoNegotiation algorithm can be enabled (or re- started) by setting the AutoNegotiation enable bit in the MI serial port Control register. When the AutoNegotiation algorithm is enabled, the device halts all transmissions including link pulses for 1200-1500 mS, enters the Link Fail State, and restarts the negotiation process. When the AutoNegotiation algorithm is disabled, the selection of 100 Mbps or 10 Mbps modes is determined by the speed select bit in the MI serial port Control register, and the selection of Half or Full Duplex is determined by the duplex select bit in the MI serial port Control register. The AutoNegotiation algorithm can be initiated at any time by setting the AutoNegotiation reset bit in the MI serial port Control register. Receive link detect activity can be monitored through the link detect bit in the MI serial port Status and Status Output registers or it can also be programmed to appear on the PLED3 or PLED0 pin by appropriately setting the pro- grammable LED output select bits in the MI serial port Configuration 2 register as shown in Table 5. When either the PLED3 or PLED0 pins are programmed to be a link detect output, these pins are asserted low whenever the device is in the Link Pass State. The PLED3 output is open drain with pullup resistor and can drive an LED from VCC; The PLED0 output has both pullup and pulldown driver transistors in addition to a weak pullup resistor, so it can drive an LED from either VCC or GND. Both PLED3 and PLED0 can also drive another digital input. Refer to the LED Driver Section (3.23) for a description on how to program the PLED[3:0] pins and their defaults. The link integrity function can be disabled by setting the link disable bit in the MI serial port Configuration 1 register. When the link integrity function is disabled, the device is forced into the Link Pass state, configures itself for Half/ Full Duplex based on the value of the duplex bit in the MI serial port Control register, configures itself for 100/10 Mbps operation based on the values of the speed bit in the MI serial port Control register, and continues to transmit NLP's or TX idle patterns, depending on whether the device is in 10 or 100 Mbps mode. 3.13.11 100Base-T4 Capability The 80221 has the ability to advertise and detect 100Base- T4 capability in addition to 100Base-TX Full/Half Duplex and 10Base-T Full/Half Duplex capability. Refer to the 100Base-T4 Interface section for more details. 3.14.1 100 Mbps Jabber function is disabled in the 100 Mbps mode. 3.14.2 10 Mbps Jabber condition occurs when the transmit packet ex- ceeds a predetermined length. When jabber is detected, the TP transmit outputs are forced to the idle state, collision is asserted, and register bits in the MI serial port Status and Status Output registers are set. The jabber function can be disabled by setting the jabber disable bit in the MI serial port Configuration 2 register. 3.15.1 100 Mbps No polarity detection or correction is needed in 100 Mbps mode. 3.15.2 10 Mbps The polarity of the signal on the TP receive input is continuously monitored. If either 3 consecutive link pulses or one SOI pulse indicates incorrect polarity on the TP receive input, the polarity is internally determined to be incorrect, and a reverse polarity bit is set in the MI serial port Status Output register. The 80220/80221 will automatically correct for the reverse polarity condition provided that the autopolarity feature is not disabled. The autopolarity feature can be disabled by setting the autopolarity disable bit in the MI serial port Configuration 2 register.
in detail in the Link Integrity and AutoNegotiation section. Table 5. When the PLED1 pin is programmed to be a Full VCC or GND and can also drive a digital input. the Link Integrity & AutoNegotiation section. select bits in the MI serial port Configuration 2 register. and can also drive a digital input. loopback is also disabled when jabber is detected.
A diagnostic loopback mode can also be selected by setting the loopback bit in the MI serial port Control register. When diagnostic loopback is enabled, TXD[3:0] data is looped back onto RXD[3:0], TX_EN is looped back onto CRS, RX_DV operates normally, the TP receive and transmit paths are disabled, the transmit link pulses are halted, and the Half/Full Duplex modes do not change. Diagnostic loopback mode can not be enabled when the FBI interface is selected. 3.19.1 100 Mbps The 80220/80221 has an automatic JAM feature which will cause the device to automatically transmit a JAM packet if receive activity is detected. If automatic JAM is enabled, then the following JAM packet will be transmitted on TPO± when the JAM pin is asserted active low and receive activity is detected on TP inputs (expressed in 5B code words): This automatic JAM feature is enabled when the RX_EN/ JAM pin is programmed to be a JAM input . RX_EN/JAM can be configured to be a JAM input by appropriately setting the R/J configuration bit in the MI serial port Configuration 2 register. 3.19.2 10 Mbps The JAM feature for 10 Mbps mode is identical to 100 Mbps mode except: (1) the JAM packet transmitted on TPO ± is composed of standard 62 bit preamble (alternat- ing 1,0) followed by SFD (11) followed by 32 bits of alternating 1,0 pattern. The 80220/80221 is reset when either (1) VCC is applied to the device, or (2) the reset bit is set in the MI serial port Control register. When reset is initiated, an internal power-on reset pulse is generated which resets all internal circuits, forces the MI serial port bits to their default values, and latches in new values for the MI address. After the power-on reset pulse has finished, the reset bit in the MI serial port Control register is cleared and the device is ready for normal operation. The device is guaranteed to be ready for normal operation 500 mS after the reset was initiated. The 80220/80221 can be powered down by setting the powerdown bit in the MI serial port Control register. In powerdown mode, the TP outputs are in high impedance state, all functions are disabled except the MI serial port, and the power consumption is reduced to a minimum. The device is guaranteed to be ready for normal operation 500 mS after powerdown is deasserted. The 80220/80221 requires a 25 Mhz reference frequency for internal signal generation. This 25 Mhz reference frequency is generated by either connecting an external 25 MHz crystal between OSCIN and GND or by applying an external 25Mhz clock to OSCIN. The PLED[5:2] outputs are open drain with a pullup resis- tor and can drive LED's tied to VCC. The PLED[1:0] outputs have both pullup and pulldown driver transistors with a pullup resistor, so PLED[1:0] can drive LED's tied to either VCC or GND. The PLED[5:0] outputs can be programmed through the MI serial port to do 4 different functions: (1) Normal Function (2) On, (3) Off, and (4) Blink. PLED[5:0] can be programmed with the LED output select bits and the LED Normal Function select bits in the MI serial port Configura- tion 2 register. When PLED[5:0] are programmed for their Normal Func- tions, these outputs indicate specific events. There are four sets of specific events that these outputs can indicate, and they are described in Tables 5 and 6. The selection of which set of events that these outputs indicate is deter- mined by appropriately setting the LED Normal Function select bits in the MI serial port Configuration 2 register. The default Normal Functions for PLED[5:0] are Transmit Activity, Receive Activity, Link 100, Activity, Full Duplex, and Link 10, respectively. PLED5 and PLED4 are only available on the 64L 80221 version. When PLED[3:0] is programmed to be On, the LED output driver go low, thus turning on the LED under user control. When PLED[3:0] is programmed to be Off, the LED output driver will turn off, thus turning off the LED under user control. When PLED[3:0] is programmed to Blink, the LED output driver will continuously blink at a rate of 100 mS on, 100 mS off.
Table 5. LED Normal Function Definition
11 RCV XMT LINK COL FDX 10/100
10 RCV XMT LINK ACT FDX 10/100
01 RCV XMT LINK COL FDX 10/100
00 RCV XMT LINK ACT FDX LINK10
Device powers up with default set to 00. Table 6. LED Event Definition over control of the TP cable to the external T4 transceiver. deasserted and 80220/80221 transmitter activated. is a bidirectional data I/O pin. MDINT is an interrupt output. MDA[4:0] are address pins for the MI serial port.
Figure 9. The MI serial port is idle when at least 32 port access cycle with the multiple register access feature. address to 11111 during the first 16 MDC clock cycles. Table 7. MI Register Bit Type Definition
Figure 9. MI Serial Port Frame Timing Diagram
The structure of the serial port frame is shown in Table 8 and a timing diagram of a frame is shown in Figure 9. Each serial port access cycle consists of 32 bits (or 192 bits if multiple register access is enabled and REGAD[4:0]=11111), exclusive of idle. The first 16 bits of the serial port cycle are always write bits and are used for addressing. The last 16/176 bits are from one/all of the 11 data registers. The first 2 bits in Table 8 and Figure 9 are start bits and need to be written as a 01 for the serial port cycle to continue. The next 2 bits are a read and write bit which determine if the accessed data register bits will be read or write. The next 5 bits are device addresses and they must match the inverted values latched in from pins MDA[4:0] during the power-on reset time for the serial port access to continue. The next 5 bits are register address select bits which select one of the five data registers for access. The next 1 bit is a turnaround bit which is not an actual register bit but extra time to switch MDIO from write to read if necessary, as shown in Figure 2. The final 16 bits of the MI serial port cycle (or 176 bits if multiple register access is enabled and REGAD[4:0]=11111) come from the spe- cific data register designated by the register address bits REGAD[4:0]. The 80220/80221 has eleven internal 16 bit registers. Ten registers are available for setting configuration inputs and reading status outputs, and one register is reserved for factory use. A map of the registers is shown in Table 9. The ten accessible registers consist of six registers that are defined by IEEE 802.3 specifications (Registers 0-5) and four registers that are unique to the 80220/80221 (Registers 16-19). The structure and bit definition of the Control register is shown in Table 10. This register stores various configura- tion inputs and its bit definition complies with the IEEE 802.3 specifications. The structure and bit definition of the Status register is shown in Table 11. This register contains device capabili- ties and status output information. and its bit definition complies with the IEEE 802.3 specifications. The structure and bit definition of the PHY ID #1 and #2 registers is shown in Tables 12 and 13, respectively. These registers contain an identification code unique to the 80220/80221 and their bit definition complies with the IEEE 802.3 specifications. The structure and bit definition of the AutoNegotiation Advertisement and AutoNegotiation Remote End Capabil- ity registers is shown in Tables 14 and 15, respectively. These registers are used by the AutoNegotiation algorithm and their bit definition complies with the IEEE 802.3 specifications. The structure and bit definition of the Configuration 1 and Configuration 2 registers is shown in Table 16 and 17, respectively. These registers store various configuration inputs. The structure and bit definition of the Status Output regis- ter is shown in Table 18. This register contains output status information. The structure and bit definition of the Mask register is shown in Table 19. This register allows each R/LT bit in the Status Output register to be masked out or removed as a bit that will set interrupt. Register 20 is reserved for factory use. All bit values must be set to the defaults for normal operation. The 80220/80221 has hardware and software interrupt capability. The interrupt is triggered by certain output status bits (also referred to as interrupt bits) in the serial port. As indicated previously, R/LT bits are read bits that latch on transition. R/LT bits are also interrupt bits if they are not masked out with the Mask register bits. Interrupt bits automatically latch themselves into their register loca- tions and assert the interrupt indication when they change state. Interrupt bits stay latched until they are read. When interrupt bits are read, the interrupt indication is deasserted and the interrupt bits that caused the interrupt to happen are updated to their current value. Each interrupt bit can be individually masked and subsequently be removed as an interrupt bit by setting the appropriate mask register bits in the Mask register. Interrupt indication is done in three ways: (1) MDINT pin, (2) INT bit in the MI serial port Status Output register, and (3) interrupt pulse on MDIO. The MDINT pin is an active low interrupt output indication. The INT bit is an active high interrupt register bit that resides in the Status Output register. The interrupt pulse on MDIO also indicates interrupt and is available when the interrupt pulse select bit is set in the MI serial port Configuration 2 register. When
Table 8. MI Serial Port Frame Structure MI cycle until it detects at least 32 1's. Address Port is selected for operation. registers are read/written in a single cycle. selected by register address bits REGAD[4:0].
Table 9. MI Serial Port Register Map
Table 10. MI Register 0 (Control) Structure And Bit Definition Bit Symbol Name Definition R/W Def.
0.15 RST Reset 1 = Reset, Bit Self Clearing After Reset Completed R/W 0
0.14 LPBK Loopback Enable 1 = Loopback Mode Enabled R/W 0
0.13 SPEED Speed Select 1 = 100 Mbps Selected (100BaseTX) R/W 1
0.12 ANEG_EN AutoNegotiation 1 = AutoNegotiation Enabled R/W 1
0.11 PDN Powerdown Enable 1 = Powerdown R/W 0
0.10 MII_DIS MII Interface 1 = MII Interface Disabled R/W 1 1
0.9 ANEG_RST AutoNegotiation 1 = Restart AutoNegotiation Process, Bit Self R/W 0
0.8 DPLX Duplex Mode 1 = Full Duplex R/W 0
0.7 COLTST Collision Test 1 = Collision Test Enabled R/W 0
0.6 Reserved R/W 0
Table 11. MI Register 1 (Status) Structure And Bit Definition
0 CAP_SUPR ANEG_ACK REM_FLT CAP_ANEG LINK JAB EXREG
Bit Symbol Name Definition R/W Def.
1.15 CAP_T4 100Base-T4 0 = Not Capable of 100Base-T4 Operation R 0
1.14 CAP_TXF 100Base-TX Full 1 = Capable Of 100Base-TX Full Duplex R 1
1.13 CAP_TXH 100Base-TX Half 1 = Capable Of 100Base-TX Half Duplex R 1
1.12 CAP_TF 10Base-T Full 1 = Capable Of 10Base-T Full Duplex R 1
1.11 CAP_TH 10Base-T Half 1 = Capable Of 10Base-T Half Duplex R 1
1.10 Reserved R 0
1.6 CAP_SUPR MI Preamble 0 = Not Capable of Accepting MI Frames with MI R 0
1.5 ANEG_ACK AutoNegotiation 1 = AutoNegotiation Acknowledgement Process Complete R 0
iation Remote Fault Bit 5.13 is set.
1.3 CAP_ANEG AutoNegotiation 1 = Capable of AutoNegotiation Operation R 1
1.0 EXREG Extended 1 = Extended Registers Exist R 1
Table 12. MI Register 2 (PHY ID #1) Structure And Bit Definition Bit Symbol Name Definition R/W Def.
2.15 OUI3 Company ID, SEEQ OUI = 00-A0-7D R 0
2.14 OUI4 Bits 3-18 0
2.13 OUI5 0
2.12 OUI6 0
2.11 OUI7 0
2.10 OUI8 0
2.9 OUI9 0
2.8 OUI10 0
2.7 OUI11 0
2.6 OUI12 0
2.5 OUI13 0
2.4 OUI14 1
2.3 OUI15 0
2.2 OUI16 1
2.1 OUI17 1
2.0 OUI18 0
Table 13. MI Register 3 (PHY ID #2) Structure And Bit Definition Bit Symbol Name Definition R/W Def.
3.15 OUI19 Company ID, SEEQ OUI = 00-A0-7D R 1
3.14 OUI20 Bits 19-24 1
3.13 OUI21 1
3.12 OUI22 1
3.11 OUI23 1
3.10 OUI24 0
3.9 PART5 Manufacturer's 03 H R0
3.8 PART4 Part Number 0
3.7 PART3 0
3.6 PART2 0
3.5 PART1 1
3.4 PART0 1
3.3 REV3 Manufacturer's R –
3.2 REV2 Revision Number –
3.1 REV1 –
3.0 REV0 –
Table 14. MI Register 4 (AutoNegotiation Advertisement) Structure Bit Symbol Name Definition R/W Def.
4.15 NP Next Page Enable 1 = Next Page Exists [1] R/W 0
4.14 ACK Acknowledge 1 = Received AutoNegotiation Word Recognized R 0
4.13 RF Remote Fault 1 = AutoNegotiation Remote Fault Detected R/W 0
4.12 Reserved R/W 0
4.9 T4 100Base-T4 1 = Capable Of 100Base-T4 R/W 0
4.8 TX_FDX 100Base-TX Full 1 = Capable of 100Base-TX Full Duplex R/W 1
4.7 TX_HDX 100Base-TX Half 1 = Capable Of 100Base-TX Half Duplex R/W 1
4.4 Reserved R/W 0
Note 1. Next Page currently not supported.
Table 15. MI Register 5 (AutoNegotiation Remote End Capability) Structure Bit Symbol Name Definition R/W Def.
5.15 NP Next Page Enable 1 = Next Page Exists R 0
5.14 ACK Acknowledge 1 = Received AutoNegotiation Word Recognized R 0
5.13 RF Remote Fault 1 = AutoNegotiation Remote Fault Detected R 0
5.12 Reserved R 0
5.9 T4 100Base-T4 1 = Capable Of 100Base-T4 R 0
5.8 TX_FDX 100Base-TX Full 1 = Capable of 100Base-TX Full Duplex R 0
5.7 TX_HDX 100Base-TX Half 1 = Capable Of 100Base-TX Half Duplex R 0
5.4 Reserved R 0
Table 16. MI Register 16 (Configuration 1) Structure And Bit Definition Bit Symbol Name Definition R/W Def.
16.15 LNK_DIS Link Disable 1 = Receive Link Detect Function Disabled R/W 0
16.14 XMT_DIS TP Transmit 1 = TP Transmitter Disabled R/W 0
16.13 XMT_PDN TP Transmit 1 = TP Transmitter Powered Down R/W 0
16.12 TXEN_CRS TXEN to CRS 1 = TX_EN to CRS Loopback Disabled R/W 0
16.11 BYP_ENC Bypass 1 = Bypass 4B5B Encoder/Decoder R/W 0
16.10 BYP_SCR Bypass 1 = Bypass Scrambler/Descrambler R/W 0
16.9 UNSCR_DIS Unscrambled Idle 1 = Disable AutoNegotiation with devices that R/W 0
16.8 EQLZR Receive Equalizer 1 = Receive Equalizer Disabled, Set To 0 Length R/W 0
16.7 CABLE Cable Type Select 1 = STP (150 Ohm) R/W 0
16.5 TLVL3 Transmit Output See Table 3 R/W 1
16.4 TLVL2 Level Adjust 0
16.3 TLVL1 0
16.2 TLVL0 0
Table 17. MI Register 17 (Configuration 2) Structure And Bit Definition Bit Symbol Name Definition R/W Def.
17.15 PLED3_1 Programmable LED 11 = Normal (PLED3 Is Determined By R/W 11
17.14 PLED3_0 Output Select, Pin Bits 17.7-17.6 And Table 5.
17.13 PLED2_1 Programmable LED 11 = Normal (PLED2 Is Determined By R/W 11
17.12 PLED2_0 Output Select, Pin Bits 17.7-17.6 And Table 5.
17.11 PLED1_1 Programmable LED 11 = Normal (PLED1 Is Determined By R/W 11
17.10 PLED1_0 Output Select, Pin Bits 17.7-17.6 And Table 5.
17.9 PLED0_1 Programmable LED 11 = Normal (PLED0 Is Determined By R/W 11
17.8 PLED0_0 Output Select, Pin Bits 17.7-17.6 And Table 5.
17.7 LED_DEF1 LED Normal See Table 5 R/W 0
17.6 LED_DEF0 Function Select
17.5 APOL_DIS Auto Polarity 1 = Auto Polarity Correction Function Disabled R/W 0
17.4 JAB_DIS Jabber Disable 1 = Jabber Disabled R/W 0
17.3 MREG Multiple Register 1 = Multiple Register Access Enabled R/W 0
17.2 INT_MDIO Interrupt Scheme 1 = Interrupt Signaled With MDIO Pulse During Idle R/W 0
17.1 R/J_CFG R/J Configuration 1 = RX_EN/JAM Pin Is Configured To Be JAM R/W 0
17.0 Reserved R/W 0
Table 18. MI Register 18 (Status Output) Structure And Bit Definition Bit Symbol Name Definition R/W Def.
18.15 INT Interrupt Detect 1 = Interrupt Bit(s) Have Changed Since Last R 0
18.14 LNK_FAIL Link Fail Detect 1 = Link Not Detected R/LT 0
18.13 LOSS_SYNC Descrambler 1 = Descrambler Has Lost Synchronization R/LT 0
18.12 CWRD Codeword Error 1 = Invalid 4B5B Code Detected On Receive Data R/LT 0
18.11 SSD Start Of Stream 1 = No Start Of Stream Delimiter Detected on R/LT 0
18.10 ESD End Of Stream 1 = No End Of Stream Delimiter Detected on R/LT 0
18.9 RPOL Reverse Polarity 1 = Reverse Polarity Detected R/LT 0
18.8 JAB Jabber Detect 1 = Jabber Detected R/LT 0
18.7 SPD_DET 100/10 Speed 1 = Device in 100 Mbps Mode (100Base-TX) R/LT 1
18.6 DPLX_DET Duplex Detect 1 = Device In Full Duplex R/LT 0
18.5 Reserved for Factory Use R 0
Table 19. MI Register 19 (Mask) Structure And Bit Definition Bit Symbol Name Definition R/W Def.
19.15 MASK_ INT Interrupt Mask - 1 = Mask Interrupt For INT In Register 18 R/W 1
19.14 MASK_ Interrupt Mask - 1 = Mask Interrupt For LNK_FAIL In Register 18 R/W 1
19.13 MASK_ Interrupt Mask - 1 = Mask Interrupt For LOSS_SYNC In Register 18 R/W 1
19.12 MASK_ Interrupt Mask - 1 = Mask Interrupt For CWRD In Register 18 R/W 1
19.11 MASK_ Interrupt Mask - Start 1 = Mask Interrupt For SSD In Register 18 R/W 1
19.10 MASK_ Interrupt Mask -End 1 = Mask Interrupt For ESD In Register 18 R/W 1
19.9 MASK_ Interrupt Mask - 1 = Mask Interrupt For RPOL In Register 18 R/W 1
19.8 MASK_ Interrupt Mask - 1 = Mask Interrupt For JAB In Register 18 R/W 1
19.7 MASK_ Interrupt Mask - 1 = Mask Interrupt For SPD_DET In Register 18 R/W 1
19.6 MASK_ Interrupt Mask - 1 = Mask Interrupt For DPLX_DET In Register 18 R/W 1
19.4 Normal Operation
19.3 Reserved R 0
Table 20. MI Register 20 (Reserved) Structure And Bit Definition Bit Symbol Name Definition R/W Def.
20.14 Normal Operation 0
The interface between the TP outputs on TPO± and the twisted pair cable is typically transformer coupled and terminated with the two resistors as shown in Figures 11- 13. The transformer for the transmitter is recommended to have a winding ration of 2:1 with a center tap on the 2x winding tied to VCC, as shown in Figures 11-13. The specifications for such a transformer are shown in Table 21. Sources for the transformer are listed in Table 22. The transmit output needs to be terminated with two external termination resistors in order to meet the output impedance and return loss requirements of IEEE 802.3. It is recommended that these two external resistors be connected from VCC to each of the TPO± outputs, and their value should be chosen to provide the correct termi- nation impedance when looking back through the trans- former from the twisted pair cable, as shown in Figures 11- 13. The value of these two external termination resistors depends on the type of cable driven by the device. Refer to the Cable Selection section for more details on choosing the value of these resistors. To minimize common mode output noise and to aid in meeting radiated emissions requirements, it may be nec- essary to add a common mode choke on the transmit outputs as well as add common mode bundle termination. The qualified transformers mentioned in Table 22 all contain common mode chokes along with the transform- ers on both the transmit and receive sides, as shown in Figures 11-13. Common mode bundle termination may be needed and can be achieved by tying the unused pairs in the RJ45 to chassis ground through 75 Ohm resistors and a 0.01 uF capacitor, as shown in Figures 11-13. To minimize noise pickup into the transmit path in a system or on a PCB, the loading on TPO± should be minimized and both outputs should always be loaded equally. A typical example schematic of the 80220/80221 used in an adapter card application is shown in Figure 11, a hub application is shown in Figure 12, and an external PHY application is shown in Figure 13. Receive data is typically transformer coupled into the receive inputs on TPI± and terminated with external resistors as shown in Figures 11-13. The transformer for the receiver is recommended to have a winding ration of 1:1, as shown in Figures 11-13. The specifications for such a transformer are shown in Table 21. Sources for the transformer are listed in Table 22. The receive input needs to be terminated with the correct termination impedance meet the input impedance and return loss requirements of IEEE 802.3. In addition, the receive TP inputs need to be attenuated. It is recom- mended that both the termination and attenuation be accomplished by placing four external resistors in series across the TPI± inputs as shown in Figures 11-13. The resistors should be 15%/35%/35%/15% of the total series resistance, and the total series resistance should be equal to the characteristic impedance of the cable (100 Ohms for UTP, 150 Ohms for STP). It is also recommended that a 0.01µF capacitor be placed between the center of the series resistor string and VCC in order to provide an AC ground for attenuating common mode signal at the input. This capacitor is also shown in Figures 11-13. To minimize common mode input noise and to aid in meeting susceptibility requirements, it may be necessary to add a common mode choke on the receive input as well as add common mode bundle termination. The qualified transformers mentioned in Table 22 all contain common mode chokes along with the transformers on both the transmit and receive sides, as shown in Figures 11-13. Common mode bundle termination may be needed and can be achieved by tying the receive secondary center tap and the unused pairs in the RJ45 to chassis ground through 75 Ohm resistors and a 0.01 µF capacitor, as shown in Figures 11-13. In order to minimize noise pickup into the receive path in a system or on a PCB, loading on TPI± should be minimized and both inputs should be loaded equally.
Figure 11. Typical Network Interface Card Schematic Using 80220
25 MHz
Figure 12. Typical Switching Port Schematic Using 80220
Figure 13. Typical External PHY Schematic Using 80220
Table 21. TP Transformer Specification Table 22. TP Transformer Sources a 1% resistor in order to meet IEEE 802.3 specified levels. UTP120/STP150 modes are selected. in order to reduce noise pickup into the transmitter. by -14% to +16% in 2% steps as described in Table 3.
100 Ohm unshielded twisted pair, Category 5, or (2) 150
register that sets the output current level for the cable type. needed to meet the level and return loss requirements. Figures 11-13. These resistors should be 1% tolerance. Table 23. Cable Configuration
150 Ohm STP STP 300 150
or used for some other purpose. terminations resistors are not needed. Figure 14. MII Output Driver Characteristics
mission is inhibited. The default value of this bit when the device powers up or is reset is dependent on the physical device address. If the device address latched into MDA[4:0] at reset is 11111, it is assumed that the device is being used in applications where there maybe more than one device sharing the MII bus, like external PHY's or adapter cards, so the device powers up with the MII interface disabled. If the device address latched into MDA[4:0] at reset is not 11111, it is assumed that the device is being used in application where it is the only device on the MII bus, like hubs, so the device powers up with the MII interface enabled. The receive output enable pin, RX_EN, forces the receive and collision MII/FBI outputs into the high impedance state. More specifically, when RX_EN is deasserted, RX_CLK, RXD[3:0], RX_DV, RX_ER, and COL are placed in high impedance. RX_EN can be used to "wire OR" the outputs of many 80220/80221 devices in multiport applications where only one device may be receiving at a time, like a repeater. By monitoring CRS from each individual port, the repeater can assert only the one RX_EN to that 80220/80221 device which is receiving data. The method will reduce, by 8 per device, the number of pins and PCB traces required by a repeater core IC. The RX_EN function can be enabled by appropriately setting the R/J Configuration select bit in the MI serial port Configuration 2 register. When this bit is set, the RX_EN/ JAM pin becomes RX_EN. The FBI (Five Bit Interface) controller interface has the same characteristics of the MII except that the data path is five bits wide, instead of 4 bits wide per the MII. The five bit wide data path is automatically enabled when the 4B5B encoder is bypassed. Because of this encoder/decoder bypass, the FBI is used primarily for repeaters or other applications where the full PHY is not needed. For more details about the FBI, see the Repeater Applications section. The 80220/80221 can be used as the physical interface for MII based repeaters by using the standard MII as the interface to the repeater core. For most repeaters, it is necessary to disable the internal CRS loopback. This can be done be setting the TX_EN to CRS loopback disable bit in the MI serial port Configura- tion 1 register. For some particular types of repeaters, it may be desirable to either enable or disable AutoNegotiation, force Half Duplex operation, and enable either 100 Mbps or 10 Mbps operation. All of these modes can be configured by setting the appropriate bits in the MI serial port Control register. The 80221 has a RPTR pin which will automatically configure the device for one common type of repeater application. When the RPTR pin is asserted, (1) TX_EN to CRS loopback is disabled, (2) AutoNegotiation is disabled, (3) Half Duplex operation is selected, and (4) 100 Mbps operation is selected. The MII requires 16 signals between the 80220/80221 and a repeater core. The MII signal count to a repeater core will be 16 multiplied by the number of ports, which can be quite large. The signal count between the 80220/80221 and repeater core can be reduced by 8 per device by sharing the receive output pins and using RX_EN to enable only that port where CRS is asserted. Refer to the Controller Interface section within the Applications section for more details about RX_EN. The FBI interface available on the 80220/80221 can be used to connect to non-MII based repeaters that employ the industry popular five bit wide interface. Since the FBI is a 5 bit wide interface, it requires that the 4B5B encoder/decoder be bypassed. The FBI is automati- cally selected on the 80220/80221 when the 4B5B en- coder/decoder is bypassed. The 4B5B encoder/decoder can be bypassed by setting the bypass encoder/decoder select bit in the MI serial port Configuration 1 register. Some applications may also require the scrambler/ descrambler to be bypassed. This can be done by setting the bypass scrambler/descrambler select bit in the MI serial port Configuration 1 register. For most repeaters, it is necessary to disable the internal CRS loopback. This can be done be setting the TX_EN to CRS loopback disable bit in the MI serial port Configura- tion 1 register. For some particular types of repeaters, it may be desirable to either enable or disable AutoNegotiation, force Half Duplex operation, and enable either 100 Mbps or 10 Mbps operation. All of these modes can be configured by setting the appropriate bits in the MI serial port Control register.
The FBI requires 16 signals between the 80220/80221 and a repeater core. The FBI signal count to a repeater core will be 16 multiplied by the number of ports, which can be quite large. The signal count between the 80220/80221 and repeater core can be reduced by 8 per device by sharing the receive output pins and using RX_EN to enable only that port where CRS is asserted. Refer to the Controller Interface section within the Applications section for more details on RX_EN. Normally, transmit data over the MII/FBI is clocked into the 80220/80221 with edges from the output clock TX_CLK. It may be desireable or necessary in some repeater applica- tions to clock in the transmit data from a master clock from the repeater core. This would require that transmit data be clocked in on edges of an input clock. An input clock is available for clocking in data on TXD with the OSCIN pin. Notice from the timing diagrams that OSCIN generates TX_CLK, and TXD data is clocked in on TX_CLK edges. This means that TXD data is also clocked in on OSCIN edges as well. Thus, an external clock driving the OSCIN input can also be used as the clock for TXD. The 80220/80221 has a MI serial port to access the devices's configuration inputs and read out the status outputs. Any external device that has a IEEE 802.3 compliant MI interface can connect directly to the 80220/ 80221 without any glue logic, as shown in Figures 11-13. As described earlier, the MI serial port consists of 8 lines: MDC, MDIO, MDINT, and MDA[4:0]. However, only 2 lines, MDC and MDIO, are needed to shift data in and out; MDINT and MDA[4:0] are not needed but are provided for convenience only. Note that the MDA[4:0] addresses are inverted inside the 80220/80221 before going to the MI serial port block. This means that the MDA[4:0] pins would have to be pin strapped to 11111 externally in order to successfully match the MI physical address of 00000 on the PHYAD[4:0] bits internally. 5.10.2 Polling vs. Interrupt The status output bits can be monitored by either polling the serial port or with interrupt. If polling is used, the registers can be read at regular intervals and the status bits can be checked against their previous values to determine any changes. To make polling simpler, all the registers can be accessed in a single read or write cycle by setting the register address bits REGAD[4:0] to 11111 and adding enough clocks to read- out out all the bits, provided the multiple register access feature has been enabled. The interrupt feature offers the ability to detect changes in the status output bits without register polling. Assertion of interrupt indicates that one or more of the status output bits has changed since the last read cycle. There are three interrupt output indicators on the 80220/80221: (1) MDINT pin, (2) INT bit in the MI serial port Status Output register, and (3) interrupt pulse on MDIO. These interrupt signals can be used by an external device to initiate a read cycle. Then when an interrupt is detected, the individual registers (or multiple registers) can be read out and the status bits compared against their previous values to determine any changes. After the interrupt its have been read out, the interrupt signals are automatically deasserted. A mask register bit exists for every status output bit in the Mask register so that the interrupt bits can be individually pro- grammed for each application. If the MI serial port needs to be constantly polled in order to monitor changes in status output bits, or if it is desired that all registers be read or written in a singleserial port access cycle, multiple register access mode can be used. Multiple register access allows access to all registers in a single MI serial port access cycle. When multiple register access is enabled, then all the registers are read/written when the register address REGAD[4:0]=11111. This eliminates the need to read or write registers individually. Multiple register access mode is normally disabled but it can be enabled by setting the multiple register access enable bit in the MI serial port Configuration 2 register. The device address for the MI serial port are selected by tying the MDA[4:0] pins to the desired value. MDA[4:0] share the same pins as the MDINT and PLED[3:0] out- puts, respectively, as shown Figure 15a. At powerup or reset, the output drivers are tristated for an interval called the power-on reset time. During the power-on reset interval, the value on these pins is latched into the device, inverted, and used as the MI serial port address. The LED outputs are open drain with internal resistor pullup to VCC. If an LED is desired on the LED outputs, then an LED and resistor are tied to VCC as shown in Figures 15b. If a high address is desired, then the LED to VCC automatically makes the latched address value a high. If a low value for
added as shown in Figure 15b. outputs under normal conditions. Figure 15. Serial Device Port Address Selection between 0-125 meters of cable. for the system FIFO to empty itself. MI serial port Configuration 2 register. applying an external 25 Mhz clock to OSCIN. OSCIN are kept to a minimum. Table 24. Crystal Specifications
The PLED[5:0] outputs can all drive LED's tied to VCC as shown in Figures 11-13. In addition, PLED1 and PLED0 can drive an LED tied to GND as well as VCC. The PLED[3:0] outputs can be programmed through the MI serial port to do 4 different functions: (1) Normal Function (2) On, (3) Off, and (4) Blink. PLED[3:0] can be programmed to indicate 4 different sets of events with the LED Normal Function select bits in the MI serial port Configuration 2 register. In addition, PLED[3:0] can be user controlled by appropriately setting the LED output select bits in the MI serial port Configuration 2 register. When PLED[3:0] is programmed for its Normal function, these outputs indicate the specific functions described in Table 5 and determined by the LED Normal Function select bits. When PLED[3:0] is programmed to be On, the LED output driver go low, thus turning on the LED under user control. When PLED[3:0] is programmed to be Off, the LED output driver will turn off, thus turning off the LED under user control. When PLED[3:0] is programmed to Blink, the LED output driver will continuously blink at a rate of 100 mS on, 100 mS off. The On and Off functions allow the LED driver to be controlled directly through the MI serial port to indicate any function that is desired under external control. The Blink function allows the same external control of the LED driver and also offers the provision to blink the LED without the need for any external timers. The PLED[5:0] outputs can also drive other digital inputs. Thus, PLED[5:0] can also be used as digital outputs whose function can be user defined and controlled through the MI serial port. Note that PLED1 and PLED0 pins have both pullup and pulldown transistors. This allows these pins to drive an LED from VCC or to GND. When PLED0 is programmed to be 10/100 Mbps select, two LED’s can be connected to this pin, one to VCC to indicated 100 Mbps mode is enabled, the other to GND to indicate 10 Mbps mode is enabled. Similarly, when PLED1 is programmed to be a Half/Full Duplex Mode indication, two LED’s can be con- nected to this pin, one to VCC to indicate Full Duplex Mode is enabled, the other to GND to indicate Half Duplex Mode is enabled. There are six VCC's on the 80220/80221 (VCC[6:1]) and six GND's (GND[6:1]). All six VCC's should be connected together as close as possible to the device with a large VCC plane. If the VCC's vary in potential by even a small amount, noise and latchup can result. The VCC's should be kept to within 50 mV of each other. All six GND's should also be connected together as close as possible to the device with a large ground plane. If the GND's vary in potential by even a small amount, noise and latchup can result. The VCC's should be kept to within 50 mV of each other. A 0.01-0.1µF decoupling capacitor should be connected between each VCC/GND set as close as possible to the device pins, preferably within 0.5". The value should be chosen on whether the noise from VCC-GND is high or low frequency. A conservative approach would be to use two decoupling capacitors on each VCC/GND set, one 0.1µf for low frequency and one 0.001µf for high frequency noise on the power supply. The VCC connection to the transmit transformer center tap shown in Figures 11-13 has to be well decoupled in order to minimize common mode noise injection from the supply into the twisted pair cable. And is recommended that a 0.01 µF decoupling capacitor be placed between the center tap VCC to the S004 GND plane. This decoupling capacitor should be physically placed as close as possible to the transformer center tap, preferably within 0.5" The PCB layout and power supply decoupling discussed above should provide sufficient decoupling to achieve the following when measured at the device: (1) The resultant AC noise voltage measured across each VCC/GND set should be less than 100 mVpp, (2) All VCC's should be within 50 mVpp of each other, and (3) All GND's should be within 50 mVpp of each other.
Absolute maximum ratings are limits beyond which may cause permanent damage to the device or affect device reliability. All voltages are specified with respect to GND, unless otherwise specified. All Inputs and Outputs DC ELECTRICAL CHARACTERISTICS Unless otherwise noted, all test conditions are as follows: 1. TA= 0 to +70°C 2. VCC = 5V +/-5% 4. REXT = 10K +/- 1%, no load LIMIT SYM PARAMETER MIN TYP MAX UNIT CONDITIONS V IL Input Low Voltage 0.8 Volt All except OSCIN, MDA[4:0] VCC -1.0 Volt MDA[4:0]
1.5 Volt OSCIN
VIH Input High Voltage 2 Volt All except OSCIN, MDA[4:0] VCC - 0.5 Volt MDA[4:0]
3.5 Volt OSCIN
IIL Input Low Current ±1 µAV IN = GND All Except OSCIN, MDA[4:0], TRFADJ [1:0], T4LNK, TPI± ± 10 µAV IN = GND, TRFADJ0 -4 -25 µAV IN = GND, MDA[4:0] -12 -120 µAV IN = GND, TRFADJ1, T4LNK -150 µAV IN = GND, OSCIN IIH Input High Current ±1 µAV IN = VCC All Except OSCIN, TRFADJ[1:0], T4ADV, TPI±, RPTR ± 10 µAV IN = VCC , TRFADJ1 12 120 µAV IN = VCC , TRFADJ0, T4ADV, RPTR 150 µAV IN = VCC , OSCIN VOL Output Low Voltage 0.4 Volt I OL = -4 mA All Except PLED[5:0], TPO±
1 Volt I OL = -20 mA, PLED[5:0]
VOH Output High Voltage V CC -1.0 Volt I OH = 4 mA All Except PLED[5:0], MDINT, TPO±
2.4 Volt I OH = 4 µA, PLED[5:2], MDINT
VCC -1.0 Volt I OH = 10 mA, PLED[1:0] C IN Input Capacitance 5 pF ICC VCC Supply Current 170 200 mA Transmitting ISS GND Supply Current 250 mA Transmitting 1 mA Powerdown Mode
TWISTED PAIR CHARACTERISTICS, TRANSMIT Unless otherwise noted, all test conditions are as follows: 1. TA= 0 to +70°C 2. VCC = 5V +/-5% 4. REXT = 10K +/- 1%, no load 5. TPO± loading shown in Figure 11 or equivalent. LIMIT SYM PARAMETER MIN TYP MAX UNIT CONDITIONS T OV TP Differential Output 0.950 1.000 1.050 V pk 100 Mbps, UTP Mode, 100 Ohm Load Voltage 1.165 1.225 1.285 V pk 100 Mbps, STP Mode, 150 Ohm Load 2.2 2.5 2.8 V pk 10 Mbps, UTP Mode, 100 Ohm Load 2.694 3.062 3.429 V pk 10 Mbps, STP Mode, 150 Ohm Load T OVS TP Differential Output 98 102 % 100 Mbps, Ratio of Positive And Voltage Symmetry Negative Amplitude Peaks on TPO ± TORF TP Differential Output 3.0 5.0 nS 100 Mbps Rise And Fall Time TRFADJ [1:0] = 10 TORFS TP Differential Output +/- 0.5 nS 100 Mbps, Difference Between Rise Rise And Fall Time And Fall Times on TPO ± Symmetry TRFADJ [1:0] = 10 TODC TP Differential Output +/- nS 100 Mbps, Output Data=0101... NRZ Duty Cycle Distortion 0.25 Pattern Unscrambled, Measure At 50% Points TOJ TP Differential Output +/- 1.4 nS 100 Mbps, Output Data=scrambled /H/ Jitter TOO TP Differential Output 5.0 % 100 Mbps Overshoot TOVT TP Differential Output See Figure 4 10 Mbps Voltage Template TSOI TP Differential Output See Figure 6 10 Mbps SOI Voltage Template TLPT TP Differential Output See Figure 7 10 Mbps, NLP and FLP Link Pulse Voltage Template T OIV TP Differential Output +/- 50 mV 10 Mbps. Measured on Secondary Idle Voltage Side of Xfmr in Figure 11.
TOIA TP Output Current 19 20 21 mA pk 100 Mbps, UTP with TLVL[3:0]=1000 15.53 16.33 17.13 mA pk 100 Mbps, STP with TLVL[3:0]=1000 44 50 56 mA pk 10 Mbps, UTP with TLVL[3:0]=1000 35.93 40.82 45.72 mA pk 10 Mbps, STP with TLVL[3:0]=1000 TOIR TP Output Current 0.80 1.2 V CC =5V, Adjustable with REXT, Adjustment Range relative to T OIA with REXT=10K 0.86 1.16 V CC =5V, Adjustable with TLVL[3:0] See Section 5.4 Relative to Value at TLVL[3:0]=1000 T ORA TP Output Current +/-50 % Relative to Ideal Values in Table 3. TLVL Step Accuracy Table 3 Values Relative to Output with TLVL[3:0]=1000. TOR TP Output Resistance 10K Ohm TOC TP Output Capacitance 15 pF TWISTED PAIR CHARACTERISTICS, TRANSMIT (continued) LIMIT SYM PARAMETER MIN TYP MAX UNIT CONDITIONS
TWISTED PAIR CHARACTERISTICS, RECEIVE Unless otherwise noted, all test conditions are as follows: 1. TA= 0 to +70°C 2. VCC = 5V +/-5% 4. REXT = 10K +/- 1%, no load 5. 62.5/10 Mhz Square Wave on TP inputs in 100/10 Mbps LIMIT SYM PARAMETER MIN TYP MAX UNIT CONDITIONS R ST TP Input Squelch 166 500 mV pk 100 Mbps, RLVL=0 Threshold 310 540 mV pk 10 Mbps, RLVL=0 60 200 mV pk 100 Mbps, RLVL=1 186 324 mV pk 10 Mbps, RLVL=1 R UT TP Input Unsquelch 100 300 mV pk 100 Mbps, RLVL=0 Threshold 186 324 mV pk 10 Mbps, RLVL=0 R OCV TP Input Open Circuit V CC ± 0.5 Volt Voltage on Either TPI+ or TPI– Voltage with Respect to GND. R CMR TP Input Common R OCV Volt Voltage on TPI ± Mode Voltage Range ± 0.25 with Respect to GND. R DR TP Input Differential V CC Volt Voltage Range R IR TP Input Resistance 5K Ohm R IC TP Input Capacitance 10 pF
25 Mhz INPUT / OUTPUT CLOCK TIMING CHARACTERISTICS
Figure 16. 25 Mhz Output Timing Refer to Figure 16 for Timing Diagram.
TRANSMIT TIMING CHARACTERISTICS Refer to Figure 17-18 for Timing Diagram LIMIT SYM PARAMETER MIN TYP MAX UNIT CONDITIONS t11 TX_CLK Period 39.996 40 40.004 nS 100 Mbps 399.96 400 400.04 nS 10 Mbps t12 TX_CLK Low Time 16 20 24 nS 100 Mbps 160 200 240 nS 10 Mbps t13 TX_CLK High Time 16 20 24 nS 100 Mbps 160 200 240 nS 10 Mbps t14 TX_CLK Rise/Fall Time 10 nS t15 TX_EN Setup Time 15 nS t16 TX_EN Hold Time 0 nS t17 CRS During Transmit 40 nS 100 Mbps 400 nS 10 Mbps t18 CRS During Transmit 160 nS 100 Mbps 900 nS 10 Mbps t19 TXD Setup Time 15 nS t20 TXD Hold Time 0 nS t21 TX_ER Setup Time 15 nS t22 TX_ER Hold Time 0 nS t23 Transmit Propagation Delay 60 140 nS 100 Mbps, MII 140 nS 100 Mbps, FBI 600 nS 10 Mbps t 24 Transmit Output Jitter ±0.7 nS pk-pk 100 Mbps ±5.5 nS pk-pk 10 Mbps t25 Transmit SOI Pulse 250 nS 10 Mbps Width To 0.3V t26 Transmit SOI Pulse 4500 nS 10 Mbps Width to 40 mV t27 PLEDn Delay Time 25 mS PLEDn Programmed For Activity t28 PLEDn Pulse Width 80 105 mS PLEDn Programmed For Activity Assert Time Deassert Time
Figure 17. Transmit Timing - 100 Mbps
Figure 18. Transmit Timing - 10 Mbps
RECEIVE TIMING CHARACTERISTICS Refer to Figures 19-23 for Timing Diagrams LIMIT SYM PARAMETER MIN TYP MAX UNIT CONDITIONS t31 Start Of Packet To CRS 200 nS 100 Mbps, MII Assert Delay 200 nS 100 Mbps, FBI 700 nS 10 Mbps t
32 End Of Packet To CRS 130 240 nS 100 Mbps, MII
Deassert Delay 240 nS 100 Mbps, FBI 600 nS 10 Mbps. Relative To Start Of SOI Pulse t
33 Start Of Packet To 240 nS 100 Mbps
RX_DV Assert Delay 3600 nS 10 Mbps t
34 End Of Packet To 280 nS 100 Mbps
RX_DV Deassert Delay 1000 nS 10 Mbps. Relative To Start Of SOI Pulse t37 RX_CLK To RX_DV, -8 8 nS 100 Mbps RXD, RX_ER Delay -80 80 nS 10 Mbps t38 RX_CLK High Time 18 20 22 nS 100 Mbps 180 200 600 nS 10 Mbps t39 RX_CLK Low Time 18 20 22 nS 100 Mbps 180 200 600 nS 10 Mbps t40 SOI Pulse Minimum 125 200 nS 10 Mbps Width Required for Idle Measure TPI ± from last zero cross Detection to 0.3V point. t41 Receive Input Jitter ±3.0 nS pk - pk 100 Mbps ±13.5 nS pk -pk 10 Mbps t43 PLEDn Delay Time 25 mS PLEDn Programmed for Activity t44 PLEDn Pulse Width 80 105 mS PLEDn Programmed for Activity t45 RX_CLK, RXD, CRC, 10 nS RX_DV, RX_ER Output Rise and Fall Times t
46 RX_EN Deassert to Rcv 40 nS
t47 RX_EN Assert to Rcv 40 nS MII Output Active Delay
Figure 19. Receive Timing, Start of Packet - 100 Mbps
Figure 20. Receive Timing, End of Packet - 100 Mbps
Figure 21. Receive Timing, Start of Packet - 10 Mbps
COLLISION AND JAM TIMING CHARACTERISTICS Refer to Figures 24-27 for Timing Diagrams LIMIT SYM PARAMETER MIN TYP MAX UNIT CONDITIONS t51 Rcv Packet Start to 200 nS 100 Mbps COL Assert Time 700 nS 10 Mbps t
52 Rcv Packet Stop to 130 240 nS 100 Mbps
COL Deassert Time 300 nS 10 Mbps t53 Xmt Packet Start to 200 nS 100 Mbps COL Assert Time 700 nS 10 Mbps t54 Xmt Packet Stop to 240 nS 100 Mbps COL Deassert Time 300 nS 10 Mbps. t
55 PLEDn Delay Time 25 mS PLEDn Programmed for Collision
t56 PLEDn Pulse Time 80 105 mS PLEDn Programmed for Collision t57 Collision Test Assert 5120 nS Time t58 Collision Test Deassert 40 nS Time t59 CRS Assert to Transmit 300 nS 100 Mbps JAM Packet Start 800 nS 10 Mbps During JAM t60 COL Rise and Fall Time 10 nS
Figure 24. Collision Timing, Receive
Figure 25. Collision Timing, Transmit
Figure 26. Collision Test Timing
Figure 27. Jam Timing
LINK PULSE TIMING CHARACTERISTICS Refer to Figures 28-30 for Timing Diagrams LIMIT SYM PARAMETER MIN TYP MAX UNIT CONDITION t61 NLP Transmit Link See Figure 7 ns Pulse Width t62 NLP Transmit Link 8 24 mS Pulse Period t63 NLP Receive Link Pulse 50 nS Width Required For Detection t
64 NLP Receive Link Pulse 6 7 mS link_test_min
t
65 NLP Receive Link Pulse 50 150 mS link_test_max
t
66 NLP Receive Link 3 3 3 Link lc_max
Pulses Required To Exit Pulses Link Fail State t 63a T4LP Receive Link 40 nS Pulse Width Required For Detection t 64a T4LP Receive Link 0.15 0.45 mS Pulse Minimum Period Required For Detection t 65a T4LP Receive Link 5 6 mS Pulse Maximum Period Required For Detection t 66a T4LP Receive Link 31 Link 31 Link Pulses Are Required To Exit Pulses Required To Exit Pulses Link Fail to Link Ready Link Fail State t
67 FLP Transmit Link 100 150 nS
t68 FLP Transmit Clock 55.5 62.5 69.5 µS interval_timer Pulse To Data Pulse Period t
69 FLP Transmit Clock 111 125 139 µS
t
70 FLP Transmit Link 8 22 mS transmit_link_burst_timer
t71 FLP Receive Link Pulse 50 nS Width Required For Detection
t72 FLP Receive Link Pulse 5 25 µS flp_test_min_timer Minimum Period Required For Clock Pulse Detection t
73 FLP Receive Link Pulse 165 185 µS flp_test_max_timer
t
74 FLP Receive Link Pulse 15 47 µS data_detect_min_timer
t
75 FLP Receive Link Pulse 78 100 µS data_detect_max_timer
t
76 FLP Receive Link 17 17 Link
t
77 FLP Receive Link Pulse 5 7 mS nlp_test_min_timer
t
78 FLP Receive Link Pulse 50 150 mS nlp_test_max_timer
t
79 FLP Receive Link 3 3 3 Link
Pulses Bursts Required Pulse To Detect AutoNegotiation Capability t
80 FLP Receive 1200 1500 mS
t
81 FLP Transmit 1200 1500 mS break_link_timer
t
82 NLP Receive Link 750 1000 mS link_fail_inhibit_timer
LINK PULSE TIMING CHARACTERISTICS continued LIMIT SYM PARAMETER MIN TYP MAX UNIT CONDITION
Figure 28. NLP Link Pulse Timing
Figure 29. FLP Link Pulse Timing
Figure 30. T4LP Link Pulse Timing
Figure 31. Jabber Timing
Figure 32. LED Driver Timing
MI SERIAL PORT TIMING CHARACTERISTICS Refer to Figures 33-34 for Timing Diagrams LIMIT SYM PARAMETER MIN TYP MAX UNIT CONDITIONS t101 MDC High Time 20 nS t102 MDC Low Time 20 nS t103 MDIO Setup Time 10 nS Write Bits t104 MDIO Hold Time 10 nS Write Bits t105 MDC To MDIO Delay 20 nS Read Bits t106 MDIO Hi-Z To Active 20 nS Write-Read Bit Transition Delay t107 MDIO Active To HI-Z 20 nS Read-Write Bit Transition Delay t108 Frame Delimiter (Idle) 32 Clocks # of Consecutive MDC Clocks With MDIO=1 t109 End Of Frame To 100 nS MDINT Transition t110 MDC To MDIO 100 nS Interrupt Pulse Assert Delay t
111 MDC To MDIO 100 nS
Figure 33. MI Serial Port Timing
Figure 34. MDIO Interrupt Pulse Timing
N PACKAGE TYPE TEMPERATURE RANGE PART TYPE Q – 0°C to +70°C 100 Base-TX/10 Base-T Ethernet Media Interface Adapter 80220Q Chip Carrier N = Plastic Leaded 7.1 44 Pin PLCC 7.2 64 Pin LQFP
Revision History
- 2/20/97 initial release. 6/30/97 6/30/97 Document Revision changed to MD400159/B Page 2, Pin Configuration 80221 80 PQFP: - Pin #30 changed from NC to RPTR Page 4, Table of Contents: - 3.25 Repeater Mode, has been added to Table of Contents. - All previous references to 3.25 have been changed to 3.26 - Reference to 5.7 Return Loss has been removed. L PACKAGE TYPE TEMPERATURE RANGE PART TYPE Q – 0°C to +70°C 100 Base-TX/10 Base-T Ethernet Media Interface Adapter 80221Q L = Low Profile Quad Flat Pack
Page 7, Pin Configuration continued: - Pin Name PLED5 Description, all references to Transmit have been changed to Receive. - Pin Name PLED4 Description, all references to Receive have been changed to Transmit. - New reference to Pin #30 including Pin name, I/O and Description, has been added. Page 8, Pin Description continued: - 80 PQFP reference to Pin #30 has been deleted. Page 9, Figure 1. 80220/80221 Block Diagram: - Reference to RPTR [1] has been added. Page 12, Table 1 80220 vs. 80221: - Repeater Mode Pin has been added. Page 13, Section 3.3.4 FBI - 100 Mbps: Page 19, Section 3.9.4 TP Squelch, 10 Mbps: - Reference to 75-250 nS has been changed to 50-250 nS. Page 24, Section 3.13.9 Link Indication: - Copy change, copy has been changed to...The PLED3 output is open drain with resistor pullup and can drive an LED from VCC; The PLED0 output has both pullup and pulldown driver transistors in addition to a weak pullup resistor, so it can drive an LED from either VCC or GND. Both PLED3 and PLED0 can also drive another digital input. Refer... Page 25, Section 3.15.2 10 Mbps: - Copy change, copy has been changed to...If either 3 consecutive link pulses or one SOI pulse indicates incorrect polarity on the TP receive input, ... Section 3.16.3 Full Duplex Indication: - Copy change, copy has been changed to...The PLED1 output has both pullup and pulldown driver transistors and a weak pullup resistor, ... Section 3.17.2 10/100 Mbps Indication: - Copy change, copy has been changed to...The PLED0 output has both pullup and pulldown driver transistors and a weak pullup resistor, ... Section 3.18.1 Internal CRS Loopback: - Copy change, copy has been changed to... in Link Fail State, and when the transmit disable bit is set in the MI serial port Configuration 1 register. In 10 Mbps mode, ... Page 26, Section 3.18.2 Diagnostic Loopback: - Copy addition, copy has been changed to...do not change. Diagnostic loopback mode can not be enabled when the FBI interface is selected. Section 3.23 LED DRIVERS: - First paragraph has changed to ...The PLED[5:2] outputs are open drain with a pullup resistor and can drive LED's tied to VCC. The PLED[1:0] outputs have both pullup and pulldown driver transistors with a pullup resistor, so PLED[1:0] can drive LED's tied to either VCC or GND. Page 27, Table 5. LED Normal Function Definition: - Columns PLED5 and PLED4 references to XMT and RCV have been switched, XMT is now RCV etc. - Section 3.25 Repeater Mode has been added. - Reference to Sections 3.25 have been changed to 3.26. Page 28, Reference to Sections 3.25 have been changed to 3.26. Table 7. MI Register Bit Type Definition:
- R/WS C Column, Write Cycle, Clears Itself After Operation Completed is now under Column Read Cycle.
Page 29, Figure 9 MI Serial Port Frame Timing Diagram: - References to ST, OP, PHYAD, REGAD, TA, DATA have been changed to ST[1:0], OP[1:0], PHYAD[4:0], REGAD[4:0], TA[1:0], DATA[15:0], for both Write Cycle and Read Cycle. Page 30, Reference to Sections 3.25 have been changed to 3.26. Page 38, Table 14. MI Register 4 (AutoNegotiation Advertisement ) Structure: - Bit 4.15, reference to Note 1 has been added. Note 1. Next Page currently not supported. Page 43, Table 19. MI Register 19 (Mask) Structure and Bit Definition: Page 49, Section 5.4 TP TRANSMIT OUTPUT CURRENT SET: - Copy change ...Where I Ref = 33.4 mA (10 Mbps, STP) has been changed to IRef = 40.8 mA (10 Mbps, STP) General: - Section 5.7 Return Loss has been removed, all references to 5.8 have been changed to 5.7. All following Page 51, Section 5.9.1 MII Based Repeaters: - Paragraph 2 copy has been changed to ...For most repeaters, it is necessary to disable the internal CRS loopback. This ... - New paragraph 3 and paragraph 4 have been added to section. Section 5.9.2 Non_MII Based Repeaters: - Paragraph 3 copy has been changed to ...For most repeaters, it is necessary to disable the internal CRS loopback. This ... - New paragraph 4 have been added to section. Page 54, Section 5.14 PROGRAMMABLE LED DRIVERS: - Paragraph 1 has been changed to ...The PLED[5:0] outputs can all drive LED's tied to VCC as shown in Figures 11-13. In addition, PLED1 and PLED0 can drive an LED tied to GND as well as VCC. - Paragraph 6 references to PLED[3:0] have been changed to PLED[5:0] and pulldown transistors. This... Page 55, DC Electrical Characteristics: - I IL Conditions TRFAD1, T4LNK, has been changed to TRFAD[1:0], T4LNK, TPI±. - New IIL row has been added, Conditions = TRFADJ0, Unit = µA, and LIMIT (MAX) = ±10. - IIL Conditions MDA[4:0] LIMIT (MIN) has been changed from -6 to 4. - IIL Conditions MDA[4:0] LIMIT (TYP), has been made blank. - IIL Conditions TRFADJ1, T4LNK LIMIT (TYP), has been made blank. - IIL Conditions TRFADJ1, T4LNK LIMIT (MAX), has been changed from -50 to -120 - IIH Conditions, All Except OSCIN, TRFADJ0, T4ADV, has been changed to All Except OSCIN, TRFADJ[1:0], T4ADV, TPI± - New IIH row has been added Conditions = TRFADJ1, Unit = µA, and LIMIT (MAX) = ±10. - IIL Conditions TRFADJ0, T4ADV LIMIT (TYP), has been made blank. - IIL Conditions TRFADJ0, T4ADV LIMIT (MAX), has been changed from 50 to 120. - VOH Conditions IOH = 6 µA PLED[5:0], MDINT has been changed to IOH = 4 µA PLED[5:2], MDINT. - New VOH row has been added LIMIT (MIN) = VCC - 1.0, Unit = Volt, IOH = 10 mA, PLED[1:0] - IIL Conditions TRFADJ0, has been changed to VIN = GND, TRFADJ0 - IIL Conditions MDA[4:0], has been changed to VIN = GND, MDA[4:0] - IIL Conditions TRFADJ1, T4LNK, has been changed to VIN = GND, TRFADJ1, T4LNK
Page 55, DC Electrical Characteristics: - IIL Conditions OSCIN, has been changed to VIN = GND, OSCIN - IIH Conditions TRFADJ1, has been changed to VIN = VCC , TRFADJ1 - IIH Conditions TRFADJ0, T4ADV, RPTR, has been changed to VIN = VCC , TRFADJ0, T4ADV, RPTR - IIH Conditions OSCIN, has been changed to VIN = VCC , OSCIN - ICC LIMIT (TYP) is now 170 - ICC LIMIT (MAX) has been changed form 250 to 200 - ICC Conditions Powerdown Mode row has been deleted - New ISS row, Conditions, Transmitting LIMIT (MAX) = 250, UNIT = mA - New ISS row, Conditions Powerdown Mode LIMIT (MAX) = 1, UNIT = mA. Page 56, Twisted Pair Characteristics Transmit: - TOV , LIMIT (MIN) has been changed form 2.2 to 2.694 - TOV , LIMIT (TYP) has been changed form 2.5 to 3.062 - TOV , LIMIT (MAX) has been changed form 2.8 to 3.429 Page 57, Twisted Pair Characteristics Transmit (continued): - TOV , LIMIT (MIN) has been changed form 29.4 to 35.93 - TOV , LIMIT (TYP) has been changed form 33.4 to 40.82 - TOV , LIMIT (MAX) has been changed form 37.4 to 45.72 Page 58, Twisted Pair Characteristics Receive: - ROCV , LIMIT (TYP), has been changed from VCC - 0.1 to VCC /3 ± 0.5 - RCMR , LIMIT (TYP), has been changed from VCC ± 1.0 to ROCV ± 0.25 Page 59, 25 MHz Input/Output Clock Timing Characteristics: - t4 LIMIT (MAX) 10, Conditions is now 100 Mbps - t4 new row Conditions is 10 Mbps, LIMIT (MAX) = 20, UNIT = nS. Page 60, Transmit Timing Characteristics: - t17, LIMIT (MAX) 40, Conditions is now 100 Mbps - t17, new row Conditions is 10 Mbps, LIMIT (MAX) = 400, UNIT = nS. - t18, LIMIT (MAX) 160, Conditions is now 100 Mbps - t18, new row Conditions is 10 Mbps, LIMIT (MAX) = 400, UNIT = nS. - t18, LIMIT (MAX) has been changed from 400 to 900 Page 63, Receive Timing Characteristics: - t34, LIMIT (MAX) has changed form 900 to 1000 - t37, LIMIT (MIN) has changed from -50 to -80 - t37, LIMIT (MAX) has changed from 50 to 80 Page 67, Figure 23. RX_EN Timing: - Timing TX_EN has changed to TX_EN. - Timing TX_EN has changed Page 79, Figure LED Driver Timing: - t 97 reference end of t97 cycle is a falling edge.
Page 81, Figure 33. MI Serial Port Timing: - Reference to t104 now extends to MDC timing. - MDIO (Read) and MDIO (Write), Timing labels have changed. - MDIO (Write) Data 0 rising edge is now rising falling. 9/15/97 9/15/97 Document Revision changed to MD400159/C General: All references to 80 pin PQFP have been changed to 64 LQFP. General: All references to Pin 26 Configuration have been changed to R/J Configuration. Page 2, 80 Pin Configuration illustration has been changed to 64 Pin Configuration illustration. Page 5, 1.0 Pin Description - All Pin Number references to 80 pin PQFP has been changed to 64 pin LQFP for this table. Page 7, 1.0 Pin Description - Pin Name PLED 5, Description, Programmable has been changed to Receive. - Pin Name PLED 4, Description, Programmable has been changed to Transmit. Page 23, Section 3.13.6 AutoNegotiation Status Page 24, Table 4 has been deleted. Page 33, Table 9, MI Serial Port Register Map - 4 AutoNegot. Advertisement, Def. Bits 3,2,1,0 have been changed from 0 to –. - 16 Configuration Bit 9 has been changed to UNSCR_DIS - 18 Status Output, Bit 5 has been changed to 0, Bit 4 has been changed to 0. Page 37, Table 13, MI Register 3(PHY ID #2) Structure and Bit Definition - Name, Manufacturer's Revision Number Definition has been changed from 0H to –H, all Def, have been changed from 0 to –. Page 40, Table 16. MI Register 16 (Configuration 1) Structure and Bit Definition. - Bit 16.9 Symbol is now UNSCR_DIS, Name is now, Unscrambled Idle Reception Disable. - Bit 16.9 Definition has been changed to: 1 = Disable AutoNegotiation with devices that transmit unscrambled idle on powerup and various instances 0 = Enables AutoNegotiation with devices that transmit unscramblled idle on powerup and various instances Page 42, Table 18 MI Register 18 (Status Output) Structure and Bit Definition - Bit 18.4, and 18.5, Symbol is now blank, Name is now blank, Definition has been changed to Reserved. Page 55, 6.0 Specifications - Package Power Dissipation, (80220) has been changed from 2.2 Watt @ 70° C to 2.0 Watt @ 70° C. - Package Power Dissipation (80221) has been deleted. Page 58, Twisted Pair Characteristics, Receive - R ST , 100 Mbps, RLVL = 1, (MIN) has been changed from 100 to 60. - RST , 100 Mbps, RLVL = 1, (MAX) has been changed from 300 to 200. - RUT , 100 Mbps, RLVL = 1, (MIN) has been changed from 60 to 20. - RUT , 100 Mbps, RLVL = 1, (MAX) has been changed from 180 to 90.
Page 83, 7.0 Ordering Information - 7.2 80 Pin PQFP, has been changed to 64 LQFP Page 90, 8.0 Surface Mount Packages - 80 Pin PQFP Dimension Diagram has been changed to 64 Pin LQFP Dimension Diagram. 3/15/98 3/15/98 Document Revision changed to MD400159/D Page 1: Features List, 64 PQFP has been changed to 64 LQFP 7/2/98 7/2/98 Document Revision changed to MD400159/E register ... Page 33: Table 9. MI Serial Port Register Map - 1 Status, x.6, has been changed from 0 to CAP_SUPR - 19 Mask, x.5 has been changed from MASK ANEG_ST1 to 1 - 19 Mask, x.4 has been changed from MASK ANEG_ST2 to 1 - 19 Mask, x.3, x.2, x.1, x.0 have been changed from 1 RW 1 to 0 R 0 - 18 Status Output, x.5, x.4 have been changed from R/LT to R Page 35: Table 11. MI Register 1 (Status) Structure and Bit Definition - Bit 1.6 has been changed from 0 to CAP_SUPR Page 37: Table 13. MI Register 3 (PHY ID#2) Structure and Bit Definition - Symbol, Part 6,5,4,3,2,1 has been changed to Part 5,4,3,2,1,0 - Definition, _ H has been deleted. Page 42: Table 18. MI Register 18 (Status Output) Structure and Bit Definition - Bit 18.5 Symbol is now blank. - Bit 18.4 Symbol is now blank. - Bit 18.5, 18.4 Definition has been changed from Reserved to Reserved for Factory Use. - Bit 18.5 and 18.4 have been changed from R/LT to 0 R/LT Page 43: Table 19. MI Register 19 (Mask) Structure and Bit Definition - Bits 19.5, and 19.4 have been changed to 1 - 19.5, and 19.4 Definition has been changed to Reserved. Must be Written to 1 or Left at Default for Normal Operation. Page 46: Figure 11. Typical Network Interface Card Schematic using 80220 - Addition of 75 ohm resistor - Reference 2KV has been added to capacitor Page 47: Figure 12. Typical Switching Port Schematic Using 80220 - Addition of 75 ohm resistor - Reference 2KV has been added to capacitor
Page 48: Figure 13. Typical external PHY Schematic Using 80220 - Addition of 75 ohm resistor - Reference 2KV has been added to capacitor Page 58: Twisted Pair Characteristics Receive - R UT , Row Conditions, 100 Mbps, RLVL = 1 and 10 Mbps RLVL = 1 have been deleted page 59: AC Test Timing Conditions - 50 pF has been changed to 25 pF Page 60: Transmit Timing Characteristics - Symbol t15, t19, t21 (MIN) has been changed from 10 to 15. - Symbol t15, t19, t21 Note 1 has been added to Conditions.
8.0 Surface Mount Packages
8.1 44 Pin Plastic Leaded Chip Carrier Notes 1. All dimensions are in inches and (millimeters). 3. Formed leads shall be planar with respect to one another within 0.004 inches. PIN NO. 1 PIN NO. 1 IDENTIFIER.048 (1.22) x 45° .042 (1.07) x 45° .656 (16.66) .650 (16.51) .695 (17.65) .685 (17.40) .656 (16.66) .650 (16.51) .695 (17.65) .685 (17.40) .021 (0.53) .013 (0.33) R .045 (1.14) R .025 (.64) .056 (1.42) .042 (1.07) .112 (2.84) .100 (2.54) .180 (4.57) .165 (4.19) .0103 (.261) .0097 (.246) .630 (16.00) .590 (14.99) .020 (0.51) min. .050 (1.27) BSC .500 (12.70) REF. .500 (12.70) REF. NQ80220
8.2 64 LQFP Notes 1. All dimensions are in millimeters. 2. Dimensions do not include mold flash. Maximum allowable flash is 0.25. Symbol Dimensions b 0.17 - 0.27 e 0.50 Basic ccc Max. 0.08 ddd Max. 0.08 D 11.85 - 12.15 E 11.85 - 12.15 L 0.45 - 0.75 L1 1.0 Ref R 0.08 - 0.20 R1 Min. 0.08 A Max. 1.60 A1 0.05 - 0.15 A2 1.292 - 1.508 c 0.09 - 0.20 D1 9.90 - 10.10 E1 9.90 - 10.10 @0 ° - 7° @1 Min. 0 ° @2 12 ° Dimension Table b e D E A See Detail ASee Detail B b Detail B c Pin 1 L R Detail A A L1@1 ccc ddd Thl I t d LQ80221