LP62S1024AU-55LLT

LP62S1024A-T AMICC | Alldatasheet

Document overview

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Technical content

Features

n Power supply range: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating:(70NS)30mA(max.) (55NS)40mA(max.) Standby:5uA (max.) n Full static operation, no clock or refreshing require d n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm) forward type and 36-pin CSP packages General Description The LP62S1024A-T is a low operating current 1,048,576 - bit static random access memory organized as 131,072 words by 8 bits and operates on a low power voltage: 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three -state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER -DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations nn SOP nn TSOP/TSSOP nn CSP (Chip Size Package) 36-pin Top View NC A16 A14 A12 I/O1 I/O2 I/O3 I/O4GND I/O5 I/O6 I/O7 I/O8 A10 A13 CE2 A15 VCC A11 LP62S1024AM-T 16 17 OE LP62S1024AV-T (LP62S1024AX-T) 116 17 32 Pin No. Pin Name Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 302928272625242219 2120 231817 A8 A13 CE2 A15 VCC NC I/O8 A16 A14 A12 A7 A6 A3 A2 A1 A0 I/O1 I/O2 GND I/O4 I/O5 I/O6 I/O7I/O3 A11 WE CE1 15 16 31 32 A5 A4 A10 OE CE1 WE I/O5 I/O6 GND VCC I/O7 I/O8 A9 A10 OE A11 CE1 A12 A13 A14 A16 NC NC A15 I/O4 I/O3 I/O2 I/O1 GND VCC CE2 WE NC A5 A3 A6 654321 A B C D E F G H

(August, 2001, Version 1.0) 2 AMIC Technology, Inc. Block Diagram ROW DECODER

512 X 2048

Pin No. Symbol Description

1 NC No Connection

2 - 12, 23, 25 - 28, 31 A0 - A16 Address Inputs 13 - 15, 17 - 21 I/O1 - I/O8 Data Input/Outputs

16 GND Ground

22 CE1 Chip Enable

24 OE Output Enable

29 WE Write Enable

30 CE2 Chip Enable

32 VCC Power Supply

Pin Description – TSOP/TSSOP Pin No. Symbol Description 1 - 4, 7, 10 - 20, 31 A0 - A16 Address Inputs

5 WE Write Enable

6 CE2 Chip Enable

8 VCC Power Supply

9 NC No Connection

21 - 23, 25 - 29 I/O1 - I/O8 Data Input/Outputs

24 GND Ground

30 CE1 Chip Enable

32 OE Output Enable

(August, 2001, Version 1.0) 3 AMIC Technology, Inc. Pin Description - CSP Symbol Description Symbol Description A0 - A16 Address Inputs NC No Connection WE Write Enable I/O1 - I/O8 Data Input/Output OE Output Enable VCC Power Supply CE1 Chip Enable GND Ground CE2 Chip Enable -- -- Recommended DC Operating Conditions (TA = -25°C to +85°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 2.7 3.0 3.6 V GND Ground 0 0 0 V VIH Input High Voltage 2.0 - VCC + 0.3 V VIL Input Low Voltage -0.3 - +0.6 V CL Output Load - - 30 pF TTL Output Load - - 1 -

(August, 2001, Version 1.0) 4 AMIC Technology, Inc. Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter LP62S1024A-55LLT/70LLT Unit Conditions Min. Max. ILI Input Leakage Current - 1 µA VIN = GND to VCC ILO Output Leakage Current - 1 µA CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC ICC Active Power Supply Current - 3 mA CE1 = VIL, CE2 = VIH II/O = 0mA - -70NS:30 ICC1 Dynamic Operating - -55NS:40 mA Min. Cycle, Duty = 100% CE1 = VIL, CE2 = VIH II/O = 0mA ICC2 Current - 5 mA CE1 = VIL, CE2 = VIH VIH = VCC, VIL = 0V f = 1 MHZ, II/O = 0mA

(August, 2001, Version 1.0) 5 AMIC Technology, Inc. Symbol Parameter LP62S1024A-55LLT/70LLT Unit Conditions Min. Max. ISB - 0.5 mA CE1 = VIH or CE2 =VIL ISB1 Standby Power Supply Current - 5 µA CE1 ≥ VCC - 0.2V CE2 ≥ VCC - 0.2V VIN ≥ 0V ISB2 - 5 µA CE2 ≤ 0.2V VIN ≥ 0V VOL Output Low Voltage - 0.4 V IOL = 2.1mA VOH Output High Voltage 2.2 - V IOH = -1.0mA Truth Table Mode CE1 CE2 OE WE I/O Operation Supply Current Standby H X X X High Z ISB, ISB1 X L X X High Z ISB, ISB2 Output Disable L H H H High Z ICC, ICC1, ICC2 Read L H L H DOUT ICC, ICC1, ICC2 Write L H X L DIN ICC, ICC1, ICC2 Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF VIN = 0V CI/O* Input/Output Capacitance 8 pF VI/O = 0V * These parameters are sampled and not 100% tested.

(August, 2001, Version 1.0) 6 AMIC Technology, Inc. AC Characteristics (TA = -25°C to +85°C, VCC = 2.7V to 3.6V) Symbol Parameter LP62S1024A-55LLT LP62S1024A-70LLT Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 55 - 70 - ns tAA Address Access Time - 55 - 70 ns tACE1 Chip Enable Access Time CE1 - 55 - 70 ns tACE2 CE2 - 55 - 70 ns tOE Output Enable to Output Valid - 30 - 35 ns tCLZ1 Chip Enable to Output in Low Z CE1 10 - 10 - ns tCLZ2 CE2 10 - 10 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ1 Chip Disable to Output in High Z CE1 0 20 0 25 ns tCHZ2 CE2 0 20 0 25 ns tOHZ Output Disable to Output in High Z 0 20 0 25 ns tOH Output Hold from Address Change 5 - 10 - ns Write Cycle tWC Write Cycle Time 55 - 70 - ns tCW Chip Enable to End of Write 50 - 60 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 50 - 60 - ns tWP Write Pulse Width 40 - 50 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 25 0 25 ns tDW Data to Write Time Overlap 25 - 30 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Notes: tCHZ1, t CHZ2, t OHZ, and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.

(August, 2001, Version 1.0) 7 AMIC Technology, Inc. Timing Waveforms Read Cycle 1 (1, 2, 4) tRC tOH tAA tOH Address DOUT Read Cycle 2 (1, 3, 4, 6) tCLZ15 tACE1 tCHZ15 CE1 DOUT Read Cycle 3 (1, 4, 7, 8) tCLZ25 tACE2 tCHZ25 CE2 DOUT

(August, 2001, Version 1.0) 8 AMIC Technology, Inc. Timing Waveforms (continued) Read Cycle 4 (1) tRC Address CE2 DOUT tAA tOE tOLZ5 tACE1 tCLZ15 tACE2 tCLZ25 tCHZ25 tOHZ5 tCHZ15 tOH OE CE1 Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high. 7. CE1 is low. 8. Address valid prior to or coincident with CE2 transition high.

(August, 2001, Version 1.0) 9 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1 (6) (Write Enable Controlled) tWC Address CE1 CE2 DIN tOW tDHtDW tWHZ tWP2tAS1 (4) tCW5 tAW tWR3 WE DOUT (4)

(August, 2001, Version 1.0) 10 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address CE1 CE2 DIN tDHtDW (4) (4) tCW5 tAW tWR3 WE DOUT tWHZ7 tWP2 tCW5 tAS1 Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP) of a low CE1, a high CE2 and a low WE . 3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. 4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

(August, 2001, Version 1.0) 11 AMIC Technology, Inc.

• Including scope and jig. * Including scope and jig.

Figure 1. Output Load Figure 2. Output Load for tCLZ1,

(August, 2001, Version 1.0) 12 AMIC Technology, Inc. Low VCC Data Retention Waveform (1) ( CE1 Controlled) VCC CE1 tCDR VIH 3.0V tR VIH 3.0V DATA RETENTION MODE VDR ≥ 2V CE1 ≥ VDR - 0.2V Low VCC Data Retention Waveform (2) (CE2 Controlled) VCC CE2 tCDR VIL 3.0V tR VIL 3.0V DATA RETENTION MODE VDR ≥ 2V CE2 ≤ 0.2V

(August, 2001, Version 1.0) 13 AMIC Technology, Inc.

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mmA) Package LP62S1024AM-55LLT 40 5 32L SOP LP62S1024AV-55LLT 40 5 32L TSOP LP62S1024AX-55LLT 40 5 32L TSSOP LP62S1024AU-55LLT 40 5 36L CSP LP62S1024AM-70LLT 30 5 32L SOP LP62S1024AV-70LLT 30 5 32L TSOP LP62S1024AX-70LLT 30 5 32L TSSOP LP62S1024AU-70LLT 30 5 36L CSP

(August, 2001, Version 1.0) 14 AMIC Technology, Inc.

Package Information

SOP (W.B.) 32L Outline Dimensions unit: inches/mm E HE L LE c See Detail F Detail F 1732 A1 A2 A s D Seating Plane D y e b Symbol Dimensions in inches Dimensions in mm A 0.118 Max. 3.00 Max. A1 0.004 Min. 0.10 Min. A2 0.106±0.005 2.69±0.13 b 0.016 +0.004 0.41 +0.10 -0.002 -0.05 c 0.008 +0.004 0.20 +0.10 -0.002 -0.05 E 0.445±0.010 11.30±0.25 e 0.050 ±0.006 1.27±0.15 e1 0.525 NOM. 13.34 NOM. HE 0.556±0.010 14.12±0.25 LE 0.055±0.008 1.40±0.20 S 0.044 Max. 1.12 Max. y 0.004 Max. 0.10 Max. Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.

(August, 2001, Version 1.0) 15 AMIC Technology, Inc. TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e LE L GAUGE PLANE A c 0.25 BSC Detail "A" D y Detail "A" S b HD D E 0.10(0.004) M °12.0 θ Symbol Dimensions in inches Dimensions in mm A 0.047 Max. 1.20 Max. A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 D 0.724±0.004 18.40±0.10 e 0.020 TYP. 0.50 TYP. HD 0.787±0.007 20.00±0.20 LE 0.031 TYP. 0.80 TYP. S 0.0167 TYP. 0.425 TYP. Y 0.004 Max. 0.10 Max. θ 0° ~ 6° 0° ~ 6° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.

(August, 2001, Version 1.0) 16 AMIC Technology, Inc. TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm e Detail "A" D 0.10MM Detail "A" S b E D LE L GAUGE PLANE A c 0.25 BSC Detail "A" SEATING PLANE °12.0 θ Symbol Dimensions in inches Dimensions in mm A 0.049 Max. 1.25 Max. A1 0.002 Min. 0.05 Min. A2 0.039±0.002 1.00±0.05 c 0.006±0.0003 0.15±0.008 e 0.020 TYP. 0.50 TYP. D 0.528±0.008 13.40±0.20 D1 0.465±0.004 11.80±0.10 LE 0.0266 Min. 0.675 Min. S 0.0109 TYP. 0.278 TYP. y 0.004 Max. 0.10 Max. θ 0° ~ 6° 0° ~ 6° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.

(August, 2001, Version 1.0) 17 AMIC Technology, Inc. 36LD CSP (6 x 8 mm) Outline Dimensions unit: mm A B C D E F G H TOP VIEW Ball#A1 CORNER SIDE VIEW C SEATING PLANE // 0.25 C A (0.36) A B C D E F G H 1 2 3 4 5 6 123456 C 0.10 CS

0.25 S A B

b (36X) BOTTOM VIEW Ball*A1 CORNER E e B e D A 0.20(4X) 0.10 C Dimensions in mm Symbol MIN. NOM. MAX. A 1.00 1.10 1.20 A1 0.16 0.21 0.26 A2 0.48 0.53 0.58 D 5.80 6.00 6.20 E 7.80 8.00 8.20 D1 --- 3.75 --- E1 --- 5.25 --- e --- 0.75 --- b 0.25 0.30 0.35 Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. 4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE.