A426316BV-40L

A426316B AMICC | Alldatasheet

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Preliminary 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE PRELIMINARY ( November , 2000, Version 0.0) AMIC Technology, Inc. Document Title 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue November 15, 2000 Preliminary

Preliminary 64K X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE PRELIMINARY ( November , 2000, Version 0 .0) 1 AMIC Technology, Inc.

Features

n Organization: 65,536 words X 16 bits n Part Identification: - A426316B - A426316B - L (with self - refr esh mode) n High speed - 30/35/40 ns RAS access time - 16/18/20 ns column address access time - 10/11/12 ns CAS access time n Low power consumption - Operating: 75mA ( - 30 max) - Standby: 3 mA (TTL) n Separate CAS ( UCAS , LCAS ) for byte selection n Self refresh mode n 256 refresh cycles, 4 ms refresh interval n Read - modify - write, RAS - only, CAS - before - RAS , Hidden refresh capability n TTL - compatible, three - state I/O n JEDEC standard packages - 400mil, 40 - pin SOJ - 400mil, 40/44 TSOP type II package n Single 5V power supply/built - in VBB generator Pin Configuration Pin Descriptions nn SOJ nnTSOP VCC I/O 0 I/O 1 NC VCC NC I/O 13 I/O 14 I/O 15 VSS A426316BS WE RAS I/O 12 OE I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 A 0 NC NC VCC VSS UCAS LCAS NC I/O 8 I/O 9 I/O 10 I/O 11 VSS VCC I/O 0 I/O 1 NC A3 A4 NC I/O 13 I/O 14 I/O 15 VSS A426316BV WE RAS I/O 12 OE I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 A 0 NC NC VCC VSS UCAS LCAS NC I/O 8 I/O 9 I/O 10 I/O 11 VSS VCC Symbol Description A0 – A7 Address Inputs I/O 0 - I/O 15 Data Input/Output RAS Row Address Strobe UCAS Column Address Strobe/Upper Byte Control LCAS Column Address Strobe/Low er Byte Control WE Write Enable OE Output Enable VCC +5V Power Supply VSS Ground NC No Connection

PRELIMINA RY ( November , 2000, Version 0.0) 2 AMIC Technology, Inc. Selection Guide Symbol Description -30 -35 -40 Unit tRAC Maximum RAS Access Time 30 35 40 ns tAA Maximum Column Address Access Time 16 18 20 ns tCAC Maximum CAS Access Time 10 11 12 ns tOEA Maximum Output Enable ( OE ) Access Time 10 11 12 ns tRC Minimum Read or Write Cycle Time 65 70 75 ns tPC Mi nimum EDO Page Mode Cycle Time 12 14 15 ns ICC1 Maximum Operating Current 95 85 75 mA ICC6 Maximum CMOS Standby Current 2 2 2 mA Functional Description The A426316B is a high performance CMOS Dynamic Random Access Memory organized as 65,536 words X 1 6 bits. The A426316B is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The A426316B features a high speed page mode operation in which high speed read, write and read - write are performed on any of the bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints asso ciated with multiplexed addressing. Output is tri - stated by a column address strobe ( UCAS and LCAS ) which acts as an output enable independent of RAS . Very EDO UCAS and LCAS to output access time eases system design. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 256 X 16 bits within a page, with cycle time as short as 12/14/15 ns. The A426316B is best suited for graphics, di gital signal processing and high performance peripherals. The A426316B is available in JEDEC standard 40 - pin plastic SOJ package and 40/44 TSOP type II package.

PRELIMINA RY ( November , 2000, Version 0.0) 3 AMIC Technology, Inc. Block Diagram RAS CLOCK GENERATOR UPPER BYTE DATA I/O BUFFER SENSE AMP COLUMN DECODER REFRESH CONTROLLERADDRESS BUFFERS WE CLOCK GENERATOR UCAS CLOCK GENERATOR SUBSTRATE BIAS GENERATOR

256 X 256 X 16

256 X 16

Recommended Operating Conditions (Ta = 0 °C to +70 °C) Symbol Description Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V VSS 0.0 0.0 0.0 V V IH Input Voltage 2.4 - VCC + 1 V V IL - 1.0 - 0.8 V

PRELIMINA RY ( November , 2000, Version 0.0) 4 AMIC Technology, Inc. Truth Table Function RAS UCAS LCAS WE OE Address I/Os Notes Standby H H H X X X High - Z Read: Word L L L H L Row/Col. Data Out Read: Lower Byte L H L H L Row/Col. I/O 0-7 = Data Out I/O 8-15 = High - Z Read: Upper Byte L L H H L Row/Col. I/O 0-7 = H igh - Z I/O 8-15 = Data Out Write: Word(Early) L L L L X Row/Col. Data In Write: Lower Byte(Early) L H L L X Row/Col. I/O 0-7 = Data In I/O 8-15 = X Write: Upper Byte(Early) L L H L X Row/Col. I/O 0-7 = X I/O 8-15 = Data In Read - Write L L L H → L L → H Row/Co l. Data Out → Data In 1.2 EDO - Page - Mode Read: Hi - Z - First cycle - Subsequent Cycles L L H → L H → L H → L H → L H H H → L H → L Row/Col. Col. Data Out Data Out EDO - Page - Mode Write(Early) - First cycle - Subsequent Cycles L L H → L H → L H → L H → L L L X X Row/Col. Col. Data In Data In EDO - Page - Mode Read - Write - First cycle - Subsequent Cycles L L H → L H → L H → L H → L H → L H → L L → H L → H Row/Col. Col. Data In Data In 1, 2 1, 2 Hidden Refresh Read L → H → L L L H L Row/Col. Data Out 2 Hidden Refresh Write L → H → L L L L X Row/Col. Data In → High - Z 1 RAS - Only Refresh L H H X X Row High - Z CBR Refresh H → L L L X X X High - Z 3 Self Refresh (L - ver only) H → L L L X X X High - Z Note: 1. Byte Write ma y be executed with either UCAS or LCAS active. 2. Byte Read may be executed with either UCAS or LCAS active. 3. Only one CAS signal ( UCAS or LCAS ) must be active.

PRELIMINARY ( November , 2000, Version 0.0) 5 AMIC Technology, Inc. Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the oper ational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. (VCC = 5V ± 10%, VSS = 0V, Ta = 0 °C to +70 °C) Symbol Parameter -30 -35 -40 Unit Test Conditions Notes IIL Input Leakage Current - 10 +10 - 10 +10 - 10 +10 µA 0V ≤ Vin ≤ +5.5V Pins not under test = 0V IOL Output Leakage Current - 10 +10 - 10 +10 - 10 +10 µA DOUT disabled, 0V ≤ Vout ≤ +5.5V ICC1 Operating Current - 95 - 85 - 75 mA RAS , UCAS , LCAS Addr ess cycling t RC = min. 1, 2 ICC2 TTL Standby Power Supply Current - 3 - 3 - 3 mA RAS = CAS ≥ V IH All other inputs ≥ VSS ICC3 Refresh Current ( RAS only Refresh) - 95 - 85 - 75 mA RAS cycling, UCAS = LCAS = V IH, t RC = min. ICC4 EDO Page Mode Current - 95 - 85 - 75 mA RAS = V IL, UCAS , LCAS Address cycling t PC = min. 1, 2 ICC5 Refre sh Current ( CAS - before - RAS Refresh ) - 95 - 85 - 75 mA RAS , UCAS , LCAS cycling t RC = min. ICC6 CMOS Standby Power Supply Current - 2 - 2 - 2 m A RAS = CAS ≥ VCC - 0.2V All other inputs ≥ VSS ICC7 Self Refresh Mode Current - 3 - 3 - 3 mA RAS = CAS ≤ VSS + 0.2V All other inputs ≥ VSS V OH Output High Voltage 2.4 - 2.4 - 2.4 - V I OUT = - 5.0mA V OL Output Low Voltage - 0.4 - 0.4 - 0.4 V I OUT = 4.2mA

PRELIMINARY ( November , 2000, Version 0.0) 6 AMIC Technology, Inc. AC Characteristics (VCC = 5V ± 10%, VSS = 0V, Ta = 0 °C to +70 °C) Std Symbol Parameter -30 -35 -40 Unit Notes 1 tRC Random Read or Write Cycle Time 65 - 70 - 75 - ns 2 tRP RAS Precharge Time 25 - 25 - 25 - ns 3 tRAS RAS Pulse Width 30 75K 35 75K 40 75K ns 4 tCAS CAS Pulse Width 5 - 6 - 7 - ns 5 tRCD RAS to CAS Delay Time 15 20 16 24 17 28 ns 6 6 tRAD RAS to Column Address Delay Time 10 14 11 17 12 20 ns 7 7 tRSH CAS to RAS Hold Time 10 - 10 - 10 - ns 8 tCSH CAS Hold Time 30 - 35 - 40 - ns 9 tCRP CAS to RAS Precharge Time 5 - 5 - 5 - ns 10 tASR Row Address Setup Time 0 - 0 - 0 - ns 11 tRAH Row Address Hold Time 5 - 6 - 7 - ns tT Transition Tim e (Rise and Fall) 2 50 2 50 2 52 ns 4, 5 tREF Refresh Period - 4 - 4 - 4 ms 3 12 tCLZ CAS to Output in Low Z 0 - 0 - 0 - ns 8 13 tRAC Access Time from RAS - 30 - 35 - 40 ns 6,7 14 tCAC Access Time from CAS - 10 - 11 - 12 ns 6, 13 15 tAA Access Time from Column Address - 16 - 18 - 20 ns 7, 13 16 tAR Column Address Hold Time from RAS 26 - 28 - 30 - ns 17 tRCS Read Command Setup Time 0 - 0 - 0 - ns

PRELIMINA RY ( November , 2000, Version 0.0) 7 AMIC Technology, Inc. AC Characteristics (continued) (VCC = 5V ± 10%, VSS = 0V, Ta = 0 °C to +70 °C) Std Symbol Parameter -30 -35 -40 Unit Notes 18 tRCH Read Command Hold Time 0 - 0 - 0 - ns 9 19 tRRH Read Command Hold Time Reference to RAS 0 - 0 - 0 - ns 9 20 tRAL Column Address to RAS Lead Time 16 - 18 - 20 - ns 21 tCOH Output Hold After CAS Low 5 - 5 - 5 - ns 22 tODS Output Disable Setup Time 0 - 0 - 0 - ns 23 tOFF Output Buffer Turn - Off Delay Time 0 6 0 6 0 6 ns 8, 10 24 tASC Column Address Setup Time 0 - 0 - 0 - ns 25 tCAH Column Address Hold Time 5 - 5 - 5 - ns 26 tRPS RAS Precharge Setup Time 50 - 60 - 70 - ns 27 tWCS Write Command Setup Time 0 - 0 - 0 - ns 11 28 tWCH Write Command Hold Time 5 - 5 - 5 - ns 11 29 tWCR Write Command Hold Time to RAS 26 - 28 - 30 - ns 30 tWP Write Command Pulse Width 5 - 5 - 5 - ns 31 tRWL Write Command to RAS Lead Time 10 - 11 - 12 - ns 32 tCWL Write Command to CAS Lead Time 10 - 11 - 12 - ns 33 tDS Data - in setup Time 0 - 0 - 0 - ns 12 34 tDH Data - in Hold Time 5 - 5 - 5 - ns 12 35 tDHR Data - in Hold Time to RAS 26 - 28 - 30 - ns 36 tRMW Read - Modify - Write Cycle Time 100 - 105 - 100 - ns 37 tRWD RAS to WE Delay Time (Read - Modify - Write) 50 - 54 - 58 - ns 11

PRELIMINA RY ( November , 2000, Version 0.0) 8 AMIC Technology, Inc. AC Characteristics (continued) (VCC = 5V ± 10%, VSS = 0V, Ta = 0 °C to +70 °C) Std Symbol Parameter -30 -35 -40 Unit Notes 38 tCWD CAS to WE Delay Time (Read - Modify - Write) 26 - 28 - 30 - ns 11 39 tAWD Column Address to WE Delay Time (Read - Modify - Write) 32 - 35 - 35 - ns 11 40 tRASS RAS Pulse Width (Self Refresh Mode) 300 - 300 - 300 - µs 41 tCPN CAS Precharge Time ( CAS before RAS ) 10 100K 10 100K 10 100K ns 42 tPC Read or Write Cycle Time (EDO Page) 12 - 14 - 15 - ns 14 43 tCPA Access Time from CAS Precharge (EDO Page) - 19 - 21 - 23 ns 13 44 tCP CAS Precharge Time (EDO Page) 3 - 4 - 5 - ns 45 tPRM EDO Page Mode RMW Cycle Time 56 - 58 - 60 - ns 46 tCRW EDO Page Mode CAS Pulse Width (RMW) - 44 - 46 - 48 ns 47 tRASP RAS Pulse Width (EDO Page) 30 75K 3 5 75K 40 75K ns 48 tCSR CAS Setup Time ( CAS - before - RAS ) 0 - 0 - 0 - ns 3 49 tCHR CAS Hold Time ( CAS - before - RAS ) 7 - 8 - 8 - ns 3 50 tRPC RAS to CAS Precharge Time ( CAS - before - RAS ) 0 - 0 - 0 - ns 51 tROH RAS Hold Time Reference to OE 6 - 7 - 8 - ns 52 tOEA OE Access Time - 10 - 11 - 12 ns 53 tOED OE to Data Delay 5 - 5 - 5 - ns 54 tOEZ Output Buffer Turn - off Delay from OE 0 5 0 6 0 6 ns 8

PRELIMINA RY ( November , 2000, Version 0.0) 9 AMIC Technology, Inc. AC Characteristics (continued) (VCC = 5V ± 10%, VSS = 0V, Ta = 0 °C to +70 °C) Std Symbol Parameter -30 -35 -40 Unit Notes 55 tOEH OE Command Hold Time 10 - 10 - 10 - ns 56 tCPT CAS Precharge Time ( CAS - before - RAS Counter Test) 20 - 20 - 20 - ns Notes: 1. ICC1, I CC3, I CC4, and I CC5 depend on cycle rate. 2. ICC1 and I CC4 depend on output loading. Specified values are obtained with the outputs open. 3. An ini tial pause of 200 µs is required after power - up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS - before - RAS initialization cyc les instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8ms). 4. AC Characteristics assume t T = 3ns. All AC parameters are measured with a load equival ent to one TTL loads and 50pF, V IL (min.) ≥ GND and V IH (max.) ≤ VCC. 5. V IH (min.) and V IL (max.) are reference levels for measuring timing of input signals. Transition times are measured between V IH and V IL. point only. If t RCD is greater than the specified t RCD (max.) limit, then access time is controlled exclusively by t CAC. point only. If t RAD is greater than the specified t RAD (max.) limit, then access time is controlled exclusively by t AA. 8. Assumes three state test load (5pF and a 380 Ω Thevenin equivalent). 9. Either t RCH or t RRH must be satisfied for a read cycle. 10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. tWCS, t WCH, t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS ≥ t WCS (min.) and t WCH ≥ t WCH (min.), the cycle is an early write cycle and data - out pins will remain open circuit, high impedance, throughout the entire cycle. If t RWD ≥ t RWD (min.) , t CWD ≥ tCWD (min.) and t AWD ≥ t AWD (min.), the cycle is a read - modify - write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. These parameters are referenced to UCAS and LCAS leading edge in early write cycles and to WE leading edge in read - modify - write cycle s. 13. Access time is determined by the longer of t AA or t CAC or t CPA. 14. tASC ≥ t CP to achieve t PC (min.) and t CPA (max.) values. 15. These parameters are sampled and not 100% tested.

PRELIMINA RY ( November , 2000, Version 0.0) 10 AMIC Technology, Inc. tRAS(3) tRP(2) tRC(1) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tCAS(4) tASR(10) tCRP(9) tRAH(11) tASC(24) tCAH(25) tRAD(6) tRAL(20) tRCH(18) tRRH(19) tAR(16) tRCS(17) tROH(51) tOEA(52) tRAC(13) tAA(15) tCAC(14) tCLZ(12) tOEZ(54) tOFF(23) High-Z : High or Low Valid Data-out Row Address Column Address I/O 0 ~ I/O 15 OE WE A0 ~ A7 UCAS LCAS RAS Word Read Cycle

PRELIMINA RY ( November , 2000, Version 0.0) 11 AMIC Technology, Inc. Word Write Cycle (Early Write) tRAS(3) tRP(2) tRC(1) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tCAS(4) tASR(10) tCRP(9) tRAH(11) tASC(24) tCAH(25) tRAD(6) tRAL(20) tWCH(28) : High or Low Row Address Column Address I/O 0 ~ I/O 15 OE A0 ~ A7 UCAS LCAS RAS tAR(16) tCWL(32) tRWL(31) tWP(30) tWCS(27) Valid Data-in tDS(33) tDH(34) WE tWCR(29) tDHR(35)

PRELIMINA RY ( November , 2000, Version 0.0) 12 AMIC Technology, Inc. Word Write Cycle (Late Write) tRAS(3) tRP(2) tRC(1) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tCAS(4) tASR(10) tCRP(9) tASC(24) tCAH(25) tRAD(6) tRAL(20) Row Address Column AddressA0 ~ A7 UCAS LCAS RAS tAR(16) tCWL(32) tRWL(31) tWP(30) tRAH(11) tOEH(55) tOED(54) tDS(33) tDH(34) I/O 0 ~ I/O 15 : High or Low OE WE High-Z Vaild Data-in tWCR(29) tDHR(35)

PRELIMINA RY ( November , 2000, Version 0.0) 13 AMIC Technology, Inc. Word Read-Modify-Write Cycle tRAS(3) tRP(2) tRWC(36) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tCAS(4) tASR(10) tCRP(9) tRAH(11) tCAH(25) tRAD(6) Row Address Column AddressA0 ~ A7 RAS tAR(16) t RWL(31) tASC(24) tCWL(32) tAWD(39) tCWD38) tRWD(37) tWP(30) tOEA(52) tOEZ(54) tCLZ(12) tCAC(14) tOED(53) tAA(15) tRAC(13) tDS(33) tDH(34) High-Z Data-out Data-in : High or Low I/O 0 ~ I/O 15 OE UCAS tOEH(55) tRCS(17) LCAS WE

PRELIMINA RY ( November , 2000, Version 0.0) 14 AMIC Technology, Inc. EDO Page Mode Word Read Cycle tRASP(47) tRP(2) RAS tCAS(4)tCAS(4)tCAS(4) tRCD(5) tCSH(8) tCRP(9) tCRP(9) tPC(42) tRSH(7) tASR(10) tRAH(11) tRAD(6) tAR(16) tRAL(20) A0 ~ A7 OE UCAS I/O 0 ~ I/O 15 : High or Low tASC(24) tCP(44) tCSH(8) tASC(24) tCAH(25) tCAH(25) Row Column Column Column tRCH(25)tRCS(17)tRCS(17) tRCH(25) tRCS(17) tCAH(25) tRRH(19) tOFF(23) tOEZ(54) tAA(15) tOEA(52) tOEP(41) tCAC(14) tCLZ(12) tOEZ(54) tCPA(43) tOES(26) tAA(15) tOEA(52) tCOH(21) tCAC(14 )tRAC(13) tCAC(14) tCLZ(12) Data-out Data-out Data-out LCAS WE

PRELIMINA RY ( November , 2000, Version 0.0) 15 AMIC Technology, Inc. EDO Page Mode Early Word Write Cycle tRASP(47) tRP(2) RAS UCAS LCAS tCAS(4)tCP(44)tCAS(4)tCP(44)tCAS(4) tRCD(5) tCSH(8) tCRP(9) tCRP(9) tPC(42) tRSH(7) tASR(10) tRAH(11) tRAD(6) tASC(24) tCAH(25) tASC(24) tCAH(25) tCAH(25) tASC(24) tRAL(20) Row Column ColumnA0 ~ A7 WE tCWL(32) tWCH(28) tWCS(27) tWCS(27) Column tCWL(32) tWCH(28) tWCS(27) tWCH(28) tCWL(32) tRWL(31) tWP(30) tWP(30) tWP(30) tDH(34) tDS(33) tDH(34) tDS(33) tDS(33) tDH(34) Data-in Data-in Data-in I/O 0 ~ I/O 15 OE : High or Low

PRELIMINA RY ( November , 2000, Version 0.0) 16 AMIC Technology, Inc. EDO Page Mode Word Read-Modify-Write Cycle tRASP(47) RAS tCAS(4)tCP(44)tCAS(4)tCP(44)tCAS(4) tRCD(5) tCSH(8) tCRP(9) tCRP(9) tPCM(45) tRSH(7) tRP(2) tASR(10) tRAH(11) tRAD(6) tASC(24) tCAH(25) t ASC(24) tCAH(25) tASC(24) tCAH(25) tRAL(20) tRCS(17) t CWD(38) tRWD(37) tCWL(32) tCWD(38) tCWL(32) tCWD(38) tCWL(32) tRWL(31) tOEA(52) tOEA(52) tOEA(52) tWP(30) tWP(30) tWP(30) tAWD(39) tAWD(39) tAWD(39) tROH(51) tCAC(14) tAA(15) tRAC(13) tOED(53) tOEZ(54) tDS(33) tAA(15) tCPA(43) tDH(34) tOEZ(54) tOED(53) tDS(33) tDH(34) tOEZ(54) tDS(33) t OED(53) tDH(34) tAA(15) tCPA(43) tCLZ(12) tCLZ(12) tCLZ(12) High-Z : High or Low I/O 0 ~ I/O 15 OE UCAS A0 ~ A7 Data-out Data-in Data-out Data-in Data-out Data-in Row Column Column Column tOEH(55) LCAS WE

PRELIMINA RY ( November , 2000, Version 0.0) 17 AMIC Technology, Inc. RAS Only Refresh Cycle CAS Before RAS Refresh Cycle tRAS(3) tRP(2) tRC(1) RAS tCRP(9) tRPC(50) tASR(10) tRAH(11) A0 ~ A7 UCAS LCAS : High or Low Row Note: WE, OE = Don't care. tRAS(3) tRP(2) tRC(1) RAS tRP(2) tRPC(50) tCPN(41) tCSR(48) tCHR(49) tOFF(23) I/O 0 ~ I/O 15 UCAS LCAS High-Z : High or LowNote: WE, OE, A0 ~ A7 = Don't care.

PRELIMINA RY ( November , 2000, Version 0.0) 18 AMIC Technology, Inc. Timing Waveform of CAS -before- RAS Refresh Counter Test Cycle tCAC (14) tRAS (3) tRSH (7) tRP (2) tCPT (56)tCHR (49) tCAS (4) tRAL (20) tCAH (25) tAA (15) tCAC (14) tCLZ (12) tOFF (23) tRCH (18)tRCS (17) tRRH (19) tRWL(31) tCWL(32) tWP(30) tWCH(28)tWCS(27) tDH (34)tDS (33) tWP (30) tCWL(32) tAWD(39) tCWD(38) tOED (53)tOEA(52) tDH (34) tCLZ (12) tAA (15) Col Address Data Out Data In Data InData Out RAS CAS Address WE I/O OE I/O I/O WE OE WE OE Read CycleWrite CycleRead-Write Cycle tOEA (52) tROH (53) tCSR (48) tRCS (17) tDS (33)tOEZ(54)

PRELIMINA RY ( November , 2000, Version 0.0) 19 AMIC Technology, Inc. Hidden Refresh Cycle (Word Read) tRAS(3) tRP(2) tRC(1) tCRP(9) tAR(16) tRCD(5) tASR(10) tCRP(9) tASC(24) tCAH(25) tRAD(6) A0 ~ A7 UCAS LCAS RAS tRAH(11) tRRH(19)tRCS(17) I/O 0 ~ I/O 15 : High or Low OE High-Z tRAS(3) tRP(2) tCHR(49) tRC(1) tRSH(7) tRAL(20) tCAC(14) tOFF(23) tAA(15) tCLZ(12) tRAC(13) WE Row Column Valid Data-out

PRELIMINA RY ( November , 2000, Version 0.0) 20 AMIC Technology, Inc. Hidden Refresh Cycle (Early Word Write) tRAS(3) tRP(2) tRC(1) tCRP(9) tAR(16) tRCD(5) tASR(10) tCRP(9) tASC(24) tCAH(25) tRAD(6) A0 ~ A7 RAS tRAH(11) : High or Low OE tRAS(3) tRP(2) tCHR(49) tRC(1) tRSH(7) tRAL(20) WE Row Column tWCS(27) tWCH(28) tWP(30) tDS(33) tDH(34) Valid Data-in I/O 0 ~ I/O 15 UCAS LCAS

PRELIMINA RY ( November , 2000, Version 0.0) 21 AMIC Technology, Inc. Self Refresh Mode (A426316B-L Only) n Self Refr esh Mode. a. Entering the Self Refresh Mode: The A426316B - L Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal “low” longer than 300 µs. b. Cont inuing the Self Refresh Mode: The Self Refresh Mode is continued by holding RAS “low” after entering the Self Refresh Mode. It does not depend on CAS being “high” or “low” after entering the Self Refresh Mode continu e the Self Refresh Mode. c. Exiting the Self Refresh Mode: The A426316B exits the Self Refresh Mode when the RAS signal is brought “high”. tRASS(40)tPR(2) tCRP(9)tCSR(48)tRPC(50) RAS tRPS(26) tCHS(21) tASR(10) tCPN(41) tOFF(23) A0 ~ A7 : High or Low High-Z I/O 0 ~ I/O 15 UCAS LCAS ROW COL Note: WE, OE = Don't care.

PRELIMINA RY ( November , 2000, Version 0.0) 22 AMIC Technology, Inc. Capacitance15 (f = 1MHz, Ta = Room Temperature, VCC = 5V ± 10%) Symbol Signals Parameter Max. Unit Test Conditions C IN1 A0 – A7 5 pF Vin = 0V C IN2 RAS , UCAS , LCAS , WE , OE Input Capacitance 7 pF Vin = 0V C I/O I/O 0 - I/O 15 I/O Capacitance 7 pF Vin = V out = 0V Ordering Codes Package\\ RAS Access Time 30ns 35ns 40ns Self-Refresh 40L SOJ (400 mil) A426316BS - 30 A426316BS - 35 A426316BS - 40 No 40/44L TSOP type II (400mil) A426316BV - 30 A426316BV - 35 A426316BV - 40 No 40L SOJ (400mil) A42631 6BS - 30L A426316BS - 35L A426316BS - 40L Yes 40/44L TSOP II (400mil) A426316BV - 30L A426316BV - 35L A426316BV - 40L Yes

PRELIMINA RY ( November , 2000, Version 0.0) 23 AMIC Technology, Inc.

Package Information

SOJ 40L Outline Dimensions unit: inches/mm Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e 1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. E H E 2140 A 1 A 2 e e 1 C S D Seating Plane D y L A b b θ

PRELIMINA RY ( November , 2000, Version 0.0) 24 AMIC Technology, Inc. TSOP 40/44L (Type II) Outline Dimensions unit: inches/mm E H E L 1 L 1 c A 1 A 2 A S D ye D B L L θ Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A 1 0.002 - 0.006 0.05 - 0.15 e 0.031 BSC 0.80 BSC Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.