A42U0616

A42U0616 AMICC | Alldatasheet

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Preliminary 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE Preliminary (June, 2001, Version 0.0) AMIC Technology, Inc. Document Title 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue June 13, 2001 Preliminary

Preliminary 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE PRELIMINARY (June, 2001, Version 0.0) 1 AMIC Technology, Inc.

Features

n Organization: 1,048,576 words X 16 bits n Part Identification - A42U0616 (1K Ref.) n Single 2.5V power supply/built-in VBB generator n Low power consumption - Operating: 120mA (-50 max) - Standby: 1mA (TTL), 0.2mA (CMOS), 250µA (Self-refresh current) n High speed - 50/60/80 ns RAS access time - 25/30/40 ns column address access time - 13/15/20 ns CAS access time - 20/25/35 ns EDO Page Mode Cycle Time n Separate CAS (UCAS ,LCAS ) for byte selection n Fast Page Mode with Extended Data Out n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 400mil, 42-pin SOJ - 400mil, 50/44 TSOP type II package General Description The A42U0616 is a new generation randomly accessed memory for graphics, organized in a 1,048,576 -word by 16-bit configuration. This product can execute Write and Read operation via CAS pin. The A42U0616 offers an accelerated Fast Page Mode cycle with a feature called Extended Data Out (EDO). Pin Configuration nn SOJ nn TSOP VCC I/O0 I/O1 NC NC A3 A4 I/O13 I/O14 I/O15 VSS A42U0616S WE RAS I/O12 OE I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 NC NC VCC UCAS LCAS NC I/O8 I/O9 I/O10 I/O11 VSS VCC I/O0 I/O1 NC I/O13 I/O14 I/O15 VSS A42U0616V WE RAS I/O12 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 NC NC NC VCC VSS LCAS UCAS NC I/O8 I/O9 I/O10 I/O11 VSS VCC OE 21 22 VSSVCC 22 23 NC 34NC This allow random access of up to 1024(1K Ref.) words within a row at a 50/40/28 MHz EDO cycle, making the A42U0616 ideally sui ted for graphics, digital signal processing and high performance computing systems. Pin Descriptions Symbol Description A0 - A9 Address Inputs (1K product) I/O0 - I/O15 Data Input/Output RAS Row Address Strobe LCAS Column Address Strobe for Lower Byte (I/O0 – I/O7) UCAS Column Address Strobe for Upper Byte (I/O8 – I/O15) WE Write Enable OE Output Enable VCC 2.5V Power Supply VSS Ground NC No Connection

PRELIMINARY (June, 2001, Version 0.0) 2 AMIC Technology, Inc. Selection Guide Symbol Description -50 -60 -80 Unit tRAC Maximum RAS Access Time 50 60 80 ns tAA Maximum Column Address Access Time 25 30 40 ns tCAC Maximum CAS Access Time 13 15 20 ns tOEA Maximum Output Enable ( OE ) Access Time 13 15 20 ns tRC Minimum Read or Write Cycle Time 84 104 134 ns tPC Minimum EDO Cycle Time 20 25 35 ns Functional Description The A42U0616 reads and writes data by multiplexing an 20-bit address into a 10-bit row and 10-bit column address. RAS and CAS are used to strobe the row address and the column address, respectively. The A42U0616 has two CAS inputs: LCAS controls I/O0- I/O7, and UCAS controls I/O 8 - I/O15, UCAS and LCAS function in an identical manner to CAS in that either will generate an internal CAS signal. The CAS function and timing are determined by the first CAS ( UCAS or LCAS ) to transition low and by the last to transition high. Byte Read and Byte Write are controlled by using LCAS and UCAS separately. A Read cycle is performed by holding the WE signal high during RAS /CAS operation. A Write cycle is executed by holding the WE signal low during RAS / CAS operation; the input data is latched by the falling edge of WE or CAS , whichever occurs later. The data inputs and outputs are routed through 16 co mmon I/O pins, with RAS , CAS , WE and OE controlling the in direction. EDO Page Mode operation all 1024(1K) columns within a selected row to be randomly accessed at a high da ta rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS . While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A42U0616 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data -out will remain valid as long as RAS and OE are lo w, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A memory cycle is terminated by returning both RAS and CAS high. Memory cell data will retain its correct state by maintaining power and accessing all 1024(1K) combinations of the 10 -bit row addresses, regardless of sequence, at least once every 16ms through any RAS cycle (Read, Write) or RAS Refresh cycle ( RAS -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller. Power-On The initial application of the VCC supply requir es a 200 µs wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power -On, the VCC current is dependent on the input levels of RAS and CAS . It is recommende d that RAS and CAS track with VCC or be held at a valid V IH during Power -On to avoid current surges.

PRELIMINARY (June, 2001, Version 0.0) 3 AMIC Technology, Inc. Block Diagram Recommended Operating Conditions (Ta = 0°C to +70°C) Symbol Description Min. Typ. Max. Unit VCC Power Supply 2.25 2.5 2.75 V VSS Input High Voltage 0 0 0 V VIH Input High Voltage 1.8 - VCC + 0.2 V VIL Input Low Voltage -1.0 - 0.8 V Control Clocks VBB Generator Refresh Timer Refresh control Refresh Counter Row Address Buffer Col. Address Buffer Row Decoder Column Decoder Memory Array 1,048,576 x 16 Cells Sense Amps & I/O Lower Data in Buffer Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer Vcc Vss RAS UCAS LCAS WE A0~A9 A0~A9 I/O0 to I/O7 I/O8 to I/O15 OE

PRELIMINARY (June, 2001, Version 0.0) 4 AMIC Technology, Inc. Truth Table Function RAS UCAS LCAS WE OE Address I/Os Notes Standby H X X X X X High-Z Read: Word L L L H L Row/Col. Data Out Read: Lower Byte L H L H L Row/Col. I/O0-7 = Data Out I/O8-15 = High-Z Read: Upper Byte L L H H L Row/Col. I/O0-7 = High-Z I/O8-15 = Data Out Write: Word L L L L H Row/Col. Data In Write: Lower Byte L H L L H Row/Col. I/O0-7 = Data In I/O8-15 = X Write: Upper Byte L L H L H Row/Col. I/O0-7 = X I/O8-15 = Data In Read-Write L L L H→ L L→ H Row/Col. Data Out → Data In 1,2 EDO-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles L L H→ L H→ L H→ L H→ L H H H→ L H→ L Row/Col. Col. Data Out Data Out EDO-Page-Mode Write -First cycle -Subsequent Cycles L L H→ L H→ L H→ L H→ L L L H H Row/Col. Col. Data In Data In EDO-Page-Mode Read-Write -First cycle -Subsequent Cycles L L H→ L H→ L H→ L H→ L H→ L H→ L L→ H L→ H Row/Col. Col. Data Out → Data In Data Out → Data In 1, 2 1, 2 Hidden Refresh Read L→ H→ L L L H L Row/Col. Data Out 2 Hidden Refresh Write L→ H→ L L L L X Row/Col. Data In → High-Z 1 RAS -Only Refresh L H H X X Row High-Z CBR Refresh H→ L L L X X X High-Z 3 Self Refresh H→ L L L H X X High-Z Note: 1. Byte Write may be executed with either UCAS or LCAS active. 2. Byte Read may be executed with either UCAS or LCAS active. 3. Only one CAS signal (UCAS or LCAS ) must be active.

PRELIMINARY (June, 2001, Version 0.0) 5 AMIC Technology, Inc. Absolute Maximum Ratings* *Comments Stresses above thos e listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. -50 -60 -80 Symbol Parameter Unit Test Conditions Notes IIL Input Leakage Current -5 +5 -5 +5 -5 +5 µA 0V ≤ Vin ≤ Vin + 0.2V Pins not under Test = 0V IOL Output Leakage Current -5 +5 -5 +5 -5 +5 µA DOUT disabled, 0V ≤ Vout ≤ + VCC ICC1 Operating Power Supply Current - 120 - 110 - 100 mA RAS ,UCAS ,LCAS Address cycling; tRC = min. 1, 2 ICC2 TTL Standby Power Supply Current - 1 - 1 - 1 mA RAS =UCAS =LCAS=VIH ICC3 Average Power Supply Current, RAS Refresh Mode - 120 - 110 - 100 mA RAS cycling, UCAS =LCAS = VIH, tRC = min. ICC4 EDO Page Mode Average Power Supply Current - 100 - 90 - 80 mA RAS = VIL, UCAS ,LCAS Address cycling; tPC = min. 1, 2 ICC5 CAS -before-RAS Refresh Power Supply Current - 110 - 100 - 90 mA RAS , UCAS , LCAS cycling; tRC = min. ICC6 CMOS Standby Power Supply Current RAS =UCAS =LCAS = VCC - 0.2V ICC7 Self Refresh Mode Current - 250 - 250 - 250 µA RAS = CAS ≤ VSS+0.2V All other input high levels are VCC-0.2V or input low levels are VSS +0.2V VOH 2.0 - 2.0 - 2.0 - V IOUT = -2mA VOL Output Voltage - 0.4 - 0.4 - 0.4 V IOUT = 2mA

PRELIMINARY (June, 2001, Version 0.0) 6 AMIC Technology, Inc. AC Characteristics (VCC = 2.5V ±10%, VSS = 0V, Ta = 0°C to +70°C) Test Conditions: Input timing reference level: VIH/VIL=1.8V/0.8V Output reference level: VOH/VOL=1.6V/0.8V Output Load: 1TTL gate + CL (100pF) Assumed tT=2ns -50 -60 -80 Std Symbol Parameter Unit Notes tT Transition Time (Rise and Fall) 1 50 1 50 1 50 ns 4, 5 tREF Refresh Period - 16 - 16 - 16 ms 3 1 tRC Random Read or Write Cycle Time 84 - 104 - 134 - ns 2 tRP RAS Precharge Time 30 - 40 - 50 - ns 3 tRAS RAS Pulse Width 50 10K 60 10K 80 10K ns 4 tCAS CAS Pulse Width 7 10K 10 10K 15 10K ns 5 tRCD RAS to CAS Delay Time 11 37 14 45 20 60 ns 6 6 tRAD RAS to Column Address Delay Time 9 25 12 30 15 40 ns 7 7 tRSH CAS to RAS Hold Time 7 - 10 - 10 - ns 8 tCSH CAS Hold Time 37 - 40 - 50 - ns 9 tCRP CAS to RAS Precharge Time 5 - 5 - 5 - ns 10 tASR Row Address Setup Time 0 - 0 - 0 - ns 11 tRAH Row Address Hold Time 7 - 10 - 10 - ns 12 tCLZ CAS to Output in Low Z 0 - 0 - 0 - ns 8 13 tRAC Access Time from RAS - 50 - 60 - 80 ns 6,7 14 tCAC Access Time from CAS - 13 - 15 - 20 ns 6, 12 15 tAA Access Time from Column Address - 25 - 30 - 40 ns 7, 12 16 tAR Column Address Hold Time from RAS 44 - 55 - 70 - ns 17 tRCS Read Command Setup Time 0 - 0 - 0 - ns 18 tRCH Read Command Hold Time 0 - 0 - 0 - ns 9 19 tRRH Read Command Hold Time Reference to RAS 0 - 0 - 0 - ns 9

PRELIMINARY (June, 2001, Version 0.0) 7 AMIC Technology, Inc. AC Characteristics (continued) (VCC = 2.5V ±10%, VSS = 0V, Ta = 0°C to +70°C) Test Conditions: Input timing reference level: VIH/VIL=1.8V/0.8V Output reference level: VOH/VOL=1.6V/0.8V Output Load: 1TTL gate + CL (100pF) Assumed tT=2ns -50 -60 -80 Std Symbol Parameter Unit Notes 20 tRAL Column Address to RAS Lead Time 25 - 30 - 40 - ns 21 tCOH Output Hold After CAS Low 5 - 5 - 3 - ns 22 tODS Output Disable Setup Time 0 - 0 - 0 - ns 23 tOFF Output Buffer Turn-Off Delay Time 0 13 0 15 0 20 ns 8, 10 24 tASC Column Address Setup Time 0 - 0 - 0 - ns 25 tCAH Column Address Hold Time 7 - 10 - 10 - ns 26 tOES OE Low to CAS High Set Up 5 - 5 - 10 - ns 27 tWCS Write Command Setup Time 0 - 0 - 0 - ns 11 28 tWCH Write Command Hold Time 7 - 10 - 10 - ns 11 29 tWCR Write Command Hold Time to RAS 44 - 55 - 70 - ns 30 tWP Write Command Pulse Width 7 - 10 - 10 - ns 31 tRWL Write Command to RAS Lead Time 13 - 15 - 20 - ns 32 tCWL Write Command to CAS Lead Time 7 - 10 - 10 - ns 33 tDS Data-in setup Time 0 - 0 - 0 - ns 34 tDH Data-in Hold Time 7 - 10 - 15 - ns 35 tDHR Data-in Hold Time to RAS 44 - 55 - 70 - ns 36 tRWC Read-Modify-Write Cycle Time 110 - 135 - 180 - ns 37 tRWD RAS to WE Delay Time (Read -Modify- Write) 67 - 79 - 107 - ns 11 38 tCWD CAS to WE Delay Time (Read-Modify- Write) 30 - 34 - 47 - ns 11 39 tAWD Column Address to WE Delay Time (Read-Modify-Write) 42 - 49 - 67 - ns 11

PRELIMINARY (June, 2001, Version 0.0) 8 AMIC Technology, Inc. AC Characteristics (continued) (VCC = 2.5V ± 10%, VSS = 0V, Ta = 0°C to +70°C) Test Conditions: Input timing reference level: VIH/VIL=1.8V/0.8V Output reference level: VOH/VOL=1.6V/0.8V Output Load: 1TTL gate + CL (100pF) Assumed tT=2ns -50 -60 -80 Std Symbol Parameter Unit Notes 40 tOEH OE Hold Time from WE 7 - 10 - 20 - ns 41 tOEP OE High Pulse Width 2 - 2 - 5 - ns 42 tPC Read or Write Cycle Time (EDO Page) 20 - 25 - 35 - ns 13 43 tCPA Access Time from CAS Precharge (EDO Page) - 28 - 33 - 45 ns 12 44 tCP CAS Precharge Time (EDO Page) 7 - 10 - 10 - ns 45 tPCM EDO Page Mode RMW Cycle Time 58 - 68 - 80 - ns 46 tCRW EDO Page Mode CAS Pulse Width (RMW) 34 - 38 - 42 - ns 47 tRASP RAS Pulse Width (EDO Page) 50 100K 60 100K 80 100K ns 48 tCSR CAS Setup Time ( CAS -before-RAS ) 5 - 5 - 5 - ns 3 49 tCHR CAS Hold Time ( CAS -before-RAS ) 10 - 10 - 15 - ns 3 50 tRPC RAS to CAS Precharge Time ( CAS -before-RAS ) 5 - 5 - 5 - ns 51 tROH RAS Hold Time Reference to OE 5 - 5 - 5 - ns 52 tOEA OE Access Time - 13 - 15 - 20 ns 53 tOED OE to Data Delay 13 - 15 - 20 - ns 54 tOEZ Output Buffer Turn-off Delay from OE 0 13 0 15 0 20 ns 8 55 tRASS RAS pulse width ( C -B-R self-refresh) 100 - 100 - 100 - µs 56 tRPS RAS precharge time (C -B-R self-refresh) 84 - 104 - 134 - ns 57 tCHS CAS hold time ( C -B-R self-refresh) - 50 - 50 - 50 ns

PRELIMINARY (June, 2001, Version 0.0) 9 AMIC Technology, Inc. Notes: 1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate. 2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open. 3. An initial pause of 200 µs is requi red after power -up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before-RAS initialization cycles instead of 8RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks. 4. AC Characteristics assume t T = 2ns. All AC parameters are measured with a load equivalent to one TTL load and 100pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC. 5. VIH (min.) and V IL (max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by t CAC. point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by t AA. 8. Assumes three state test load (5pF and a 500 Ω Thevenin equivalent). 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. tWCS, t WCH, t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in th e data sheet as electrical characteristics only. If t WCS ≥ t WCS (min.) and t WCH ≥ t WCH (min.), the cycle is an early write cycle and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If t RWD ≥ tRWD (min.) , t CWD ≥ tCWD (min.) and t AWD ≥ tAWD (min.), the cycle is a read -modify-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. Access time is determined by the longer of t AA or tCAC or tCPA. 13. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values.

PRELIMINARY (June, 2001, Version 0.0) 10 AMIC Technology, Inc. Word Read Cycle tRAS(3) tRP(2) tRC(1) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tCAS(4) tASR(10) tCRP(9) tRAH(11) tASC(24) tCAH(25) tRAD(6) tRAL(20) tRCH(18) tRRH(19) tAR(16) tRCS(17) tROH(51) tOEA(52) tRAC(13) tAA(15) tCAC(14) tCLZ(12) tOEZ(54) tOFF(23) High-Z : High or Low Valid Data-out Row Address Column Address I/O0 ~ I/O15 OE WE Address UCAS LCAS RAS

PRELIMINARY (June, 2001, Version 0.0) 11 AMIC Technology, Inc. Word Write Cycle (Early Write) tRAS(3) tRP(2) tRC(1) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tCAS(4) tASR(10) tCRP(9) tRAH(11) tASC(24) tCAH(25) tRAD(6) tRAL(20) tWCH(28) : High or Low Row Address Column Address I/O0 ~ I/O15 OE Address UCAS LCAS RAS tAR(16) tCWL(32) tRWL(31) tWP(30) tWCS(27) Valid Data-in tDS(33) tDH(34) WE tWCR(29) tDHR(35)

PRELIMINARY (June, 2001, Version 0.0) 12 AMIC Technology, Inc. Word Write Cycle (Late Write) tRAS(3) tRP(2) tRC(1) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tCAS(4) tASR(10) tCRP(9) tASC(24) tCAH(25) tRAD(6) tRAL(20) Row Address Column AddressAddress UCAS LCAS RAS tAR(16) tCWL(32) tRWL(31) tWP(30) tRAH(11) tOEH(40) tOED(53) tDS(33) tDH(34) I/O0 ~ I/O15 : High or Low OE WE High-Z Vaild Data-in tWCR(29) tDHR(35)

PRELIMINARY (June, 2001, Version 0.0) 13 AMIC Technology, Inc. Word Read-Modify-Write Cycle tRAS(3) tRP(2) tRWC(36) tCRP(9) tCSH(8) tRCD(5) tRSH(7) tCAS(4) tASR(10) tCRP(9) tRAH(11) tCAH(25) tRAD(6) Row Address Column AddressAddress UCAS LCAS RAS tAR(16) tRWL(31) tASC(24) tCWL(32) tAWD(39) tCWD38) tRWD(37) tWP(30) tOEA(52) tOEZ(54) tCLZ(12) tCAC(14) tOED(53) tAA(15) tRAC(13) tDS(33) tDH(34) High-Z Data-out Data-in : High or Low I/O0 ~ I/O15 OE WE tOEH(40) tRCS(17)

PRELIMINARY (June, 2001, Version 0.0) 14 AMIC Technology, Inc. EDO Page Mode Word Read Cycle tRASP(47) tRP(2) RAS UCAS LCAS tCAS(4)tCAS(4)tCAS(4) tRCD(5) tCSH(8) tCRP(9) tCRP(9) tPC(42) tRSH(7) tASR(10) tRAH(11) tRAD(6) tAR(16) tRAL(20) Address OE WE I/O0 ~ I/O15 : High or Low tASC(24) tCP(44) tCSH(8) tASC(24) tCAH(25) tCAH(25) Row Column Column Column tRCH(25)tRCS(17)tRCS(17) tRCH(25) tRCS(17) tCAH(25) tRRH(19) tOFF(23) tOEZ(54) tAA(15) tOEA(52) tOEP(41) tCAC(14) tCLZ(12) tOEZ(54) tCPA(43) tOES(26) tAA(15) tOEA(52) tCOH(21) tCAC(14)tRAC(13) tCAC(14) tCLZ(12) Data-out Data-out Data-out

PRELIMINARY (June, 2001, Version 0.0) 15 AMIC Technology, Inc. EDO Page Mode Early Word Write Cycle tRASP(47) tRP(2) RAS UCAS LCAS tCAS(4)tCP(44)tCAS(4)tCP(44)tCAS(4) tRCD(5) tCSH(8) tCRP(9) tCRP(9) tPC(42) tRSH(7) tASR(10) tRAH(11) tRAD(6) tASC(24) tCAH(25) tASC(24) tCAH(25) tCAH(25) tASC(24) tRAL(20) Row Column ColumnAddress WE tCWL(32) tWCH(28) tWCS(27) tWCS(27) Column tCWL(32) tWCH(28) tWCS(27) tWCH(28) tCWL(32) tRWL(31) tWP(30) tWP(30) tWP(30) tDH(34) tDS(33) tDH(34) tDS(33) tDS(33) tDH(34) Data-in Data-in Data-in I/O0 ~ I/O15 OE : High or Low

PRELIMINARY (June, 2001, Version 0.0) 16 AMIC Technology, Inc. EDO Page Mode Word Read-Modify-Write Cycle tRASP(47) RAS tCAS(4)tCP(44)tCAS(4)tCP(44)tCAS(4) tRCD(5) tCSH(8) tCRP(9) tCRP(9) tPCM(45) tRSH(7) tRP(2) tASR(10) tRAH(11) tRAD(6) tASC(24) tCAH(25) tASC(24) tCAH(25) tASC(24) tCAH(25) tRAL(20) tRCS(17) tCWD(38) tRWD(37) tCWL(32) tCWD(38) tCWL(32) tCWD(38) tCWL(32) tRWL(31) tOEA(52) tOEA(52) tOEA(52) tWP(30) tWP(30) tWP(30) tAWD(39) tAWD(39) tAWD(39) tROH(51) tCAC(14) tAA(15) tRAC(13) tOED(53) tOEZ(54) tDS(33) tAA(15) tCPA(43) tDH(34) tOEZ(54) tOED(53) tDS(33) tDH(34) tOEZ(54) tDS(33) tOED(53) tDH(34) tAA(15) tCPA(43) tCLZ(12) tCLZ(12) tCLZ(12) High-Z : High or Low I/O0 ~ I/O15 OE WE Address UCAS LCAS Data-out Data-in Data-out Data-in Data-out Data-in Row Column Column Column tOEH(40)

PRELIMINARY (June, 2001, Version 0.0) 17 AMIC Technology, Inc. RAS Only Refresh Cycle CAS Before RAS Refresh Cycle tRAS(3) tRP(2) tRC(1) RAS tCRP(9) tRPC(50) tASR(10) tRAH(11) Address UCAS : High or Low Row Note: WE, OE = Don't care. LCAS tRAS(3) tRP(2) tRC(1) RAS tRP(2) tRPC(50) tPC(42) tCSR(48) tCHR(49) tOFF(23) I/O0 ~ I/O15 UCAS High-Z : High or LowNote: WE, OE, Address = Don't care. LCAS

PRELIMINARY (June, 2001, Version 0.0) 18 AMIC Technology, Inc. Hidden Refresh Cycle (Word Read) tRAS(3) tRP(2) tRC(1) tCRP(9) tAR(16) tRCD(5) tASR(10) tCRP(9) tASC(24) tCAH(25) tRAD(6) Address UCAS RAS tRAH(11) tRRH(19)tRCS(17) I/O0 ~ I/O15 : High or Low OE High-Z tRAS(3) tRP(2) tCHR(49) tRC(1) tRSH(7) tRAL(20) tCAC(14) tOFF(23) tAA(15) tCLZ(12) tRAC(13) WE Row Column Valid Data-out LCAS

PRELIMINARY (June, 2001, Version 0.0) 19 AMIC Technology, Inc. Hidden Refresh Cycle (Early Word Write) tRAS(3) tRP(2) tRC(1) tCRP(9) tAR(16) tRCD(5) tASR(10) tCRP(9) tASC(24) tCAH(25) tRAD(6) Address RAS tRAH(11) : High or Low OE tRAS(3) tRP(2) tCHR(49) tRC(1) tRSH(7) tRAL(20) WE Row Column tWCS(27) tWCH(28) tWP(30) tDS(33) tDH(34) Valid Data-in I/O0 ~ I/O15 UCAS LCAS

PRELIMINARY (June, 2001, Version 0.0) 20 AMIC Technology, Inc. EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write) RAS : High or Low I/O0 ~ I/O15 OE WE Address UCAS tRP(2)tRASP(47) tCRP(9) tCSH(8) tRCD(5) tCAS(4) tCP(44) tCAS(4) tCP(44) tCAS(4) tCPR(9) tRSH(7)tPC(42)tPC(42) Row Column Column tRAL(20) tCAH(25)tASC(24)tCAH(25)tASC(24) tCAH(25)tASC(24) tASR(10) tRAH(11) tRAD(6) tRAD(6) Column tRCS(17) tRCH(18) tWCS(27) tWCH(28) Data-out Data-out Data-in tDH(34) tDS(33) tAA(15) tCAP(43) tCAC(14) tCOH(21) tAA(15) tRAC(13) tCAC(14) tOEA(52) LCAS

PRELIMINARY (June, 2001, Version 0.0) 21 AMIC Technology, Inc. Self Refresh Mode n Self Refresh Mode. a. Entering the Self Refresh Mode: The A42U0616 Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal "low" longer than 100µs. b. Continuing the Self Refresh Mode: The Self Refresh Mode is continued by holding RAS "low" after entering the Self Refresh Mode. It does not depend on CAS being "high" or "low" after entering the Self Refresh Mode continue the Self Refresh Mode. c. Exiting the Self Refresh Mode: The A42U0616 exits the Self Refresh Mode when the RAS signal is brought "high". tRASS(55)tRP(2) tCRP(9)tCSR(48)tRPC(50) RAS tRPS(56) tCHS(57) tASR(10) tCPN(42) tOFF(23) A0 ~ A7 : High or Low High-Z I/O0 ~ I/O15 UCAS LCAS ROW COL Note: WE, OE = Don't care.

PRELIMINARY (June, 2001, Version 0.0) 22 AMIC Technology, Inc. Capacitance (Ta = Room Temperature, VCC = 2.5V ± 10%) Symbol Signals Parameter Max. Unit Test Conditions CIN1 A0 – A9 5 pF Vin = 0V CIN2 RAS , CAS, WE , OE Input Capacitance 7 pF Vin = 0V CI/O I/O0 - I/O15 I/O Capacitance 10 pF Vin = Vout = 0V Ordering Codes Package\\ RAS Access Time 50ns 60ns 80ns Refresh Cycle Self- Refresh 42L SOJ (400mil) A42U0616S-50 A42U0616S-60 A42U0616S-80 1K Yes 50(44)L TSOP type II (400mil) A42U0616V-50 A42U0616V-60 A42U0616V-80 1K Yes

PRELIMINARY (June, 2001, Version 0.0) 23 AMIC Technology, Inc.

Package Information

SOJ 42L Outline Dimensions unit: inches/mm Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. E HE 2242 A1 A2 e e1 C S D Seating Plane D y L A b b θ

PRELIMINARY (June, 2001, Version 0.0) 24 AMIC Technology, Inc. TSOP 50/44L (Type II) Outline Dimensions unit: inches/mm E HE c A1 A2 A S D ye D B L θ Detail "A" Detail "A" Seating Plane RAD R1 RAD R Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A1 0.002 - 0.006 0.05 - 0.15 B 0.012 - 0.018 0.30 - 0.45 c 0.005 - 0.008 0.12 - 0.21 E 0.400 BSC 10.16 BSC HE 0.463 BSC 11.76 BSC L1 0.031 REF 0.80 REF e 0.031 BSC 0.80 BSC R 0.005 - 0.010 0.12 - 0.25 S 0.0435 REF 0.875 BSC θ 0° - 5° 0° - 5° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.