AD120 AMICC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 13
Technical content
Preliminary 3-Level / 258 Outputs TFT LCD Gate Driver PRELIMINARY (August, 2001, Version 0.0) AMIC Technology, Inc. Document Title 3-Level / 258 Outputs TFT LCD Gate Driver
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue August 10, 2001 Preliminary
Important Notice: AMIC reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMIC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life -support applications, devices or systems or other critical applications. Use of AMIC products in such applications is understood to be fully at the risk of the customer.
Preliminary 3-Level / 258 Outputs TFT LCD Gate Driver PRELIMINARY (August, 2001, Version 0.0) 1 AMIC Technology, Inc
Features
n 40V max. for each output n -15V min. for each output n 2.7V~3.6V logic input/output level n Bi-directional data shift control n Output waveform control n TCP available AD120 is a gate driver for TFT LCD panel. There are 258 outputs in the chip. Three -level output allows voltage correction for better switching noise rejection. It can be used for XGA / SXGA panels. Block Diagram Shift Register Decoder Output ST1X ST2X ST2 ST1 CP XOFF XON OGW VH VOFF VL VDD VSS OUT0 OUT1 OUT2 OUT255 OUT256 OUT257 R/L
PRELIMINARY (August, 2001, Version 0.0) 2 AMIC Technology, Inc TCP Pinout 275 274 273 272 271 OUT254 OUT257 OUT253 OUT255 OUT256 OUT1 OUT4 OUT0 OUT2 OUT3 VL VOFF VH ST1 ST2 VSS CP VDD XOFF XON R/L OGW ST2X ST1X VH VOFF VL AD120
PRELIMINARY (August, 2001, Version 0.0) 3 AMIC Technology, Inc Input/Output Pin Function Pin No. Symbol I/O Description
11 CP I Clock pulse
7 R /L I Right / left direction control for shift register
When R /L is LOW, data are shifted to the right, or ST1 / ST2 output0 output1 .… output257. When R /L is HIGH, data are shifted to the left, or ST1X / ST2X output257 8 XON I XON to force all the outputs to VH voltage. It is not synchronous to CP. 9 XOFF I XOFF to force all the outputs to VOFF voltage. It is not synchronous to CP. 6 OGW I Output Gate pulse Width to select output_waveform format. 4,5, 13,14 ST1, ST2, ST1X, ST2X I/O When R /L is LOW, ST1 / ST2 are defined as inputs while ST1X / ST2X are defined as outputs . The synchronized ST1 / ST2 signals are placed at ST1X / ST2X after 256 CP pulses. When R /L is HIGH, ST1X / ST2X are defined as inputs, while ST1/ST2 are defined as outputs. The synchronized ST1X / ST2X signals are placed at ST1 / ST2 after 256 CP pulses. 18 - 275 OUT0~ OUT257 O Output drivers These outputs are synchronized to CP pulses. The output format and voltage level are controlled by OGW, XON, XOFF, ST1 / ST2, ST1X / ST2X and R /L correspondingly as shown in the diagram.
12 VSS PWR Reference voltage
10 VDD PWR Supply voltage for logic operation
VDD and VSS are voltage levels of input / output logic signals 3, 15 VH PWR High voltage for output drivers 1, 17 VL PWR Low voltage for output drivers 2, 16 VOFF PWR OFF voltage for output drivers
PRELIMINARY (August, 2001, Version 0.0) 4 AMIC Technology, Inc
Description
Output signals OUT0~OUT257 are used fo r control of the TFT gates of the LCD panel. A bi -directional shift register is implemented to sequentially output signals OUT0~OUT257. A clock pulse CP is applied to the bi -directional shift register and the direction of the register is controlled by R /L signal. When R /L is LOW and either starting signal ST1 or ST2 goes to HIGH, the shift register starts shifting from OUT0 to OUT257. The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the diagram. The outputs of the starting signals ST1X / ST2X switch accordingly after 256 CP pulses following start of the shift register which allows expansion of the outputs by cascading more devices. When R /L is HIGH and either starting signal ST1X or ST2X goes to HIGH, the shift register starts shifting from OUT257 to OUT0. The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the diagram. The outputs of the starting signals ST1/ST2 switch accordingly after 256 CP pulses following start of the shift register which allows expansion of the outputs by cascading more devices. 3-Level Output VH - VL = 40V(max.) VOFF - VL = 0~10V VH - VSS = 17~28V OUT Level VH VDD VSS VOFF VL
PRELIMINARY (August, 2001, Version 0.0) 5 AMIC Technology, Inc Operation Diagram 1 (R /L = L, OGW = L) CP ST1 ST2 OUT0 OUT1 OUT2 OUT3 OUT256 OUT257 ST1X ST2X VH VOFF VL VH VOFF VL VH VOFF VL VH VOFF VL VH VOFF VL VH VOFF VL 1 2 3 256 257 VDD VSS VDD VSS VDD VSS VDD VSS
PRELIMINARY (August, 2001, Version 0.0) 6 AMIC Technology, Inc Operation Diagram 2 (R /L = L, OGW = H) CP ST1 ST2 1 2 3 XON OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 VDD VSS XOFF VDD VSS VH VOFF VL VH VOFF VL
Table 1. Function of XON and XOFF
- The outputs are asynchronous to CP.
Table 2. Control of OUT1~OUT256
- The outputs are synchronous to CP.
Table 3. Control of OUT0 and OUT257
- The outputs are synchronous to CP.
PRELIMINARY (August, 2001, Version 0.0) 8 AMIC Technology, Inc Absolute Maximum Ratings Over Operating Free-air Temperature Range Parameter Symbol Ratings Unit Supply Voltage VDD -0.3 ~ +7.0 V Supply Voltage VH -0.3 ~ 42.0 V Supply Voltage VL -20.0 ~ +0.3 V Supply Voltage VOFF VL-0.3 ~ VL+11.0 V Supply Voltage VH - VL -0.3 ~ 42.0 V Input Voltage VIN -0.3 ~ VDD+0.3 V Storage Temperature Tstg -55 ~ 125 °C Power_on Sequence and Voltage Levels VH VOFF VL VDD VSS VDD Logic Signal VSS Out0~Out257 Operating Voltage Range Parameter Symbol Min. Typ. Max. Unit Supply Voltage VDD 2.7 3.3 3.6 V Supply Voltage VH 17 - 28 V Supply Voltage VL -15 - -5 V Supply Voltage VOFF - VL 0 - 10.0 V Supply Voltage VH - VL 22 - 40 V Clock Frequency fCP - - 100 KHz Operating Free-air Temperature Ta -20 - +75 °C
PRELIMINARY (August, 2001, Version 0.0) 9 AMIC Technology, Inc DC Charactertics Parameter Symbol Condition Min. Max. Unit Applicable Pin Note Low Level Input Voltage VIL VSS 0.2 X VDD V All input pins High Level Input Voltage VIH 0.8 X VDD VDD V All input pins Low Level Output Voltage VOL IOL = 40µA VSS VSS + 0.4 V High Level Output Voltage VOH IOH = 40µA VDD -0.4 VDD V ST1, ST2, ST1X, ST2X Output Resistance (1) RL VOUT = VL + 0.5 1000 Ù OUT0~OUT257 1 Output Resistance (2) ROFF VOUT = VOFF + 0.5 1000 Ù OUT0~OUT257 1 Output Resistance (3) RH VOUT = VH - 0.5 1000 Ù OUT0~OUT257 1 Input Current II VI = VDD / VSS -5.0 +5.0 µA All input pins Operating Current (1) IDD 1500 µA VDD 1, 2 Operating Current (2) IH 100 µA VH 1, 2 Notes: 1. VH = 25V, VOFF = 0V, VL = -10V 2. CP = 50KHz AC Charactertics Parameter Symbol Condition Min. Max. Unit Clock Frequency fCP 100 KHz CP High Pulse Width tCPH 1 µs CP Low Pulse Width tCPL 4 µs Input Rise Time tr 10% ~ 90% 50 ns Input Fall Time tf 90% ~ 10% 50 ns Gate Off Time tWOFF 1 µs Data Setup Time tSU 700 ns Data Hold Time thd 700 ns Delay Time 1 tpd1 CL = 20pF 800 ns Delay Time 2 tpd2 CL = 300pF 1000 ns Delay Time 3 tpd3 CL = 300pF 1000 ns Delay Time 4 tpd4 CL = 300pF 1000 ns Delay Time 5 tpd5 CL = 300pF 1000 ns
PRELIMINARY (August, 2001, Version 0.0) 10 AMIC Technology, Inc Timing Waveform (OGW = H) CP OUT0~257 tpd2 tpd2 80% 20% 20% 20% 80%80% tpd2 tpd2 tpd2 tpd2 VH VOFF VL 0.5 x VDD (OGW = L) CP 0.5 x VDD 0.5 x VDD 0.5 x VDD 0.5 x VDD 20% 0.5 x VDD OUT0~OUT257 tpd2 tpd2 tpd2 tpd2 tpd2 80% 20% 80%20% VH VOFF VL CP ST1, ST2 STX1, STX2 OUT0~OUT257 tCPH tCPL 0.5 x V DD 0.5 x VDD 0.5 x VDD 2 256 0.5 x VDD 0.5 x V DD 257 0.5 x V DD tSU thd 0.5 x V DD 0.5 x VDD tpd1 tpd1 tpd2 tpd2 80% 20% 50%50% Input Output
PRELIMINARY (August, 2001, Version 0.0) 11 AMIC Technology, Inc Timing Waveform (continued) XOFF 0.5 x VDD OUT0~OUT257 0.5 x VDD VOFF twOFF tpd3 tpd3 VH VL 80%80% 20% 20% XON 0.5 x VDD OUT0~OUT257 0.5 x VDD tpd4 80% VH 20% tpd4
PRELIMINARY (August, 2001, Version 0.0) 12 AMIC Technology, Inc
Ordering Information
Part No. Package AD120T TCP