LP62E16512-I

LP62E16512-I AMICC | Alldatasheet

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Technical content

Preliminary 512K X 16 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (April, 2002, Version 0.0) AMIC Technology, Inc. Document Title 512K X 16 BIT LOW VOLTAGE CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue April 26, 2002 Preliminary

Preliminary 512K X 16 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (April, 2002, Version 0.0) 1 AMIC Technology, Inc.

Features

n Operating voltage: 1.65V to 2.2V n Access times: 70 ns (max.) n Current: Very low power version: Operating: 40mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 1.2V (min.) n Available in 48-ball CSP (8×10mm) packages General Description The LP62E16512-I is a low operating current 8,388,608 - bit static random access memory organized as 524,288 words by 16 bits and operates on low power voltage from 1.65V to 2.2V. It is built using AMIC's high performance CMOS process. Inputs and three -state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable input is provided for POWER -DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 1.2V. Product Family Power Dissipation Product Family Operating Temperature VCC Range Speed Data Retention (ICCDR, Typ.) Standby (ISB1, Typ.) Operating (ICC2, Typ.) Package Type LP62E16512 -40°C ~ +85°C 1.65V~2.2V 70ns 0.1µA 0.5µA 3mA 48 CSP 1. Typical values are measured at VCC = 1.8V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 1.2V. Pin Configurations nn CSP (Chip Size Package) 48-pin Top View I/O9 I/O10 GND VCC I/O15 I/O16 A18 A8 NC A12 A10 A11 NC A13 A14 A15 I/O8 I/O7 I/O3 I/O1 GND VCC A5 A6 A1 A2 CS2 654321 A B C D E F G H I/O14 I/O13 I/O12 I/O11 A17 NC A16 I/O2 I/O4 I/O5 I/O6 LB HB WE OE CS1

PRELIMINARY (April, 2002, Version 0.0) 2 AMIC Technology, Inc. Block Diagram DECODER

1024 X 8192

PRELIMINARY (April, 2002, Version 0.0) 3 AMIC Technology, Inc. Pin Description - CSP Symbol Description Symbol Description A0 - A18 Address Inputs HB Higher Byte Enable Input (I/O9 - I/O16) 1CS , CS2 Chip Enable OE Output Enable I/O1 - I/O16 Data Input/Output VCC Power Supply WE Write Enable Input GND Ground LB Byte Enable Input (I/O1 - I/O8) NC No Connection Recommended DC Operating Conditions (TA = -40°C to + 85°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 1.65 1.8 2.2 V GND Ground 0 0 0 V VIH Input High Voltage 1.4 - VCC + 0.3 V VIL Input Low Voltage -0.3 - +0.4 V CL Output Load - - 30 pF TTL Output Load - - 1 -

PRELIMINARY (April, 2002, Version 0.0) 4 AMIC Technology, Inc. Absolute Maximum Ratings* *Comments Stresses above those listed under "Absol ute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or in tended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter LP62E16512-70LLI Unit Conditions Min. Max. ILI Input Leakage Current - 1 µA VIN = GND to VCC ILO Output Leakage Current µA 1CS = VIH or CS2 = VIL or LB = HB = VIH VI/O = GND to VCC ICC Active Power Supply Current - 5 mA 1CS = VIL , CS2 = VIH , LB = VIL or HB = VIL , II/O = 0mA ICC1 Dynamic Operating - 40 mA Min. Cycle, Duty = 100%, 1CS = VIL , CS2 = VIH , LB = VIL or HB = VIL II/O = 0mA ICC2 Current - 5 mA 1CS ≤ 0.2V, CS2 ≥ VCC-0.2V , LB ≤ 0.2V or HB ≤ 0.2V f = 1MHz , II/O = 0mA ISB - 1 mA 1CS = VIH or CS2 = VIL or LB = HB = VIH ISB1 Standby Current - 10 µA 1CS ≥ VCC - 0.2V or CS2 ≤ 0.2V or LB = HB ≥ VCC-0.2V VIN ≥ VCC-0.2V or VIN ≤ 0.2V VOL Output Low Voltage - 0.2 V IOL = 0.1 mA VOH Output High Voltage 1.4 - V IOH = -1.0 mA

PRELIMINARY (April, 2002, Version 0.0) 5 AMIC Technology, Inc. Truth Table 1CS CS2 OE WE LB HB I/O1 to I/O8 Mode I/O9 to I/O16 Mode VCC Current H X X X X X High - Z High - Z ISB1, ISB X L X X X X High - Z High - Z ISB1, ISB X X X X H H High - Z High - Z ISB1, ISB L L Read Read ICC1, ICC2, ICC L H L H L H Read High - Z ICC1, ICC2, ICC H L High - Z Read ICC1, ICC2, ICC L L Write Write ICC1, ICC2, ICC L H X L L H Write High - Z ICC1, ICC2, ICC H L High - Z Write ICC1, ICC2, ICC L H H H L X High - Z High - Z ICC1, ICC2, ICC L H H H X L High - Z High - Z ICC1, ICC2, ICC Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF VIN = 0V CI/O* Input/Output Capacitance 8 pF VI/O = 0V * These parameters are sampled and not 100% tested.

PRELIMINARY (April, 2002, Version 0.0) 6 AMIC Technology, Inc. AC Characteristics (TA = -40°C to +85°C, VCC = 1.65V to 2.2V) Symbol Parameter LP62E16512-70LLI Unit Min. Max. Read Cycle tRC Read Cycle Time 70 - ns tAA Address Access Time - 70 ns tAcs1 , tAcs2 Chip Enable Access Time - 70 ns tBE Byte Enable Access Time - 70 ns tOE Output Enable to Output Valid - 35 ns tCLZ1 , tCLZ2 Chip Enable to Output in Low Z 10 - ns tBLZ Byte Enable to Output in Low Z 10 - ns tOLZ Output Enable to Output in Low Z 5 - ns tCHZ1 , tCHZ2 Chip Disable to Output in High Z - 25 ns tBHZ Byte Disable to Output in High Z - 25 ns tOHZ Output Disable to Output in High Z - 25 ns tOH Output Hold from Address Change 5 - ns Write Cycle tWC Write Cycle Time 70 - ns tCW1 , tCW2 Chip Enable to End of Write 60 - ns tBW Byte Enable to End of Write 60 - ns tAS Address Setup Time 0 - ns tAW Address Valid to End of Write 60 - ns tWP Write Pulse Width 50 - ns tWR Write Recovery Time 0 - ns tWHZ Write to Output in High Z - 25 ns tDW Data to Write Time Overlap 30 - ns tDH Data Hold from Write Time 0 - ns tOW Output Active from End of Write 5 - ns Note: tCLZ1 , tCLZ2 , tBLZ , t OLZ , t CHZ1, tCHZ2 , tBHZ and t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.

PRELIMINARY (April, 2002, Version 0.0) 7 AMIC Technology, Inc. Timing Waveforms Read Cycle 1(1, 2, 4) tRC tOH tAA tOH Address DOUT Read Cycle 2(1, 2, 3) tRC tAA Address CS1 tACS1 , tACS2 tCHZ1 , tCHZ2 HB, LB tBHZ5 OE tBE tBLZ5 tOE tOLZ5 tOHZ5 DOUT tCLZ1 , tCLZ2 CS2 Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled 1CS = VIL, or CS2 = VIH ,HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with 1CS and ( HB and, or LB ) transition low or CS2 transition High. 4. OE = VIL. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (April, 2002, Version 0.0) 8 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC tAW Address CS1 tWR3 tCW DATA IN DATA OUT WE HB, LB tBW tAS1 tWP2 tDW tDH tOW tWHZ4 CS2

PRELIMINARY (April, 2002, Version 0.0) 9 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC tAW Address CS1 tWR3 tCW1 , tCW2tAS1 DATA IN DATA OUT WE HB, LB tBW tWP tDW tDH tOW tWHZ4 CS2

PRELIMINARY (April, 2002, Version 0.0) 10 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) tWC tAW Address CS1 tWR3 tCW1 , tCW2 tBW2tAS1 DATA IN DATA OUT WE HB, LB tWP tDW tDH tOW tWHZ4 CS2 Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP, tBW) of a low 1CS , WE and ( HB and , or LB ) or a high CS2. 3. tWR is measured from the earliest of 1CS or WE or ( HB and , or LB ) going high or CS2 going Low to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (April, 2002, Version 0.0) 11 AMIC Technology, Inc.

• Including scope and jig. * Including scope and jig.

Figure 1. Output Load Figure 2. Output Load for tCLZ1, tCLZ2 , tBHZ , tBLZ ,

PRELIMINARY (April, 2002, Version 0.0) 12 AMIC Technology, Inc. Low VCC Data Retention Waveform (1) ( CS1 Controlled) VCC CS1 tCDR VIH 1.65V tR VIH 1.65V DATA RETENTION MODE tVR VDR ≥ 1.2V CS1 ≥ VDR - 0.2V Low VCC Data Retention Waveform (2) (CS2 Controlled) VCC CS2 tCDR VIL 1.65V tR VIL 1.65V DATA RETENTION MODE tVR VDR ≥ 1.2V 0.2VCS2 ≤

Ordering Information

Part No. Access Time(ns) Operating Current Max.(mA) Standby Current Max.(uA) Package LP62E16512U-70LLI 70 40 10 48L CSP

PRELIMINARY (April, 2002, Version 0.0) 13 AMIC Technology, Inc.

Package Information

48LD CSP ( 8 x 10 mm ) Outline Dimensions unit: mm (48TFBGA) A B C D E F G H TOP VIEW Ball#A1 CORNER SIDE VIEW C SEATING PLANE A A B C D E F G H 1 2 3 4 5 6 123456 C 0.10 CS

0.25 S A B

b (48X) BOTTOM VIEW Ball*A1 CORNER E e B e D A 0.20(4X) 0.10 C Dimensions in mm Symbol MIN. NOM. MAX. A --- --- 1.20 A1 0.20 0.25 0.30 A2 0.48 0.53 0.58 D 7.90 8.00 8.10 E 9.90 10.00 10.10 D1 --- 3.75 --- E1 --- 5.25 --- e --- 0.75 --- b 0.30 0.35 0.40 Notes: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. 4. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE. 5. BALL PAD OPENING OF SUBSTRATE IS Φ 0.3mm (SMD) SUGGEST TO DESIGN THE PCB LAND SIZE AS Φ 0.3mm (NSMD)