LP62E16256E-T AMICC | Alldatasheet

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Preliminary 256K X 16 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (July, 2002, Version 0.0) AMIC Technology, Inc. Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue July 4, 2002 Preliminary

256K X 16 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (July, 2002, Version 0.0) 1 AMIC Technology, Inc. Features General Description n Operating voltage: 1.65V to 2.2V n Access times: 70ns (max.) n Current: Very low power version: Operating: 30mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Data retention voltage: 1.2V (min.) n Available in 44-pin TSOP and 48-ball CSP packages The LP 62E16256E-T is a low operating current 4,194,304-bit static random access memory organized as 262,144 words by 16 bits and operates on low power voltage from 1.65V to 2.2V. It is built using AMIC's high performance CMOS process. Inputs and three -state outp uts are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER -DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 1.2V. Product Family Power Dissipation Product Family Operating Temperature VCC Range Speed Data Retention (ICCDR, Typ.) Standby (ISB1, Typ.) Operating (ICC2, Typ.) Package Type LP62E16256E -25°C ~ +85°C 1.65V~2.2V 70ns 0.2µA 1.4µA 2mA 44L TSOP 48B CSP 1. Typical values are measured at VCC = 2.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 1.2V. Pin Configurations nn TSOP nn CSP (Chip Size Package) 48-pin Top View I/O9 I/O10 GND VCC I/O15 I/O16 NC A8 NC A12 A10 A11 NC A13 A14 A15 I/O8 I/O7 I/O3 I/O1 GND VCC A5 A6 A1 A2 NC 654321 A B C D E F G H I/O14 I/O13 I/O12 I/O11 A17 NC A16 I/O2 I/O4 I/O5 I/O6 LB HB WE OE CE CE I/O1 I/O2 I/O3 I/O4 VCC GND I/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A11 A10 NC I/O9 I/O10 I/O11 I/O12 VCC GND I/O13 I/O14 I/O15 I/O16 LB HB OE LP62E16256EV-T A13 A5A4 A12

PRELIMINARY (July, 2002, Version 0.0) 2 AMIC Technology, Inc. Block Diagram DECODER

512 X 8192

Pin No. Symbol Description 1 - 5, 18 - 27, 42 - 44 A0 - A17 Address Inputs

6 CE Chip Enable Input

7 - 10, 13 - 16, 29 - 32, 35 - 38 I/O1 - I/O16 Data Inputs/Outputs

17 WE Write Enable Input

39 LB Lower Byte Enable Input (I/O1 to I/O8)

40 HB Higher Byte Enable Input (I/O9 to I/O16)

41 OE Output Enable Input

11, 33 VCC Power 12, 34 GND Ground

28 NC No Connection

PRELIMINARY (July, 2002, Version 0.0) 3 AMIC Technology, Inc. Pin Description - CSP Symbol Description Symbol Description A0 - A17 Address Inputs HB Higher Byte Enable Input (I/O9 - I/O16) CE Chip Enable OE Output Enable I/O1 - I/O16 Data Input/Output VCC Power Supply WE Write Enable Input GND Ground LB Byte Enable Input (I/O1 - I/O8) NC No Connection Recommended DC Operating Conditions (TA = -25°C to + 85°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 1.65 1.8 / 2.0 2.2 V GND Ground 0 0 0 V VIH Input High Voltage 1.4 - VCC + 0.2 V VIL Input Low Voltage -0.2 - +0.4 V CL Output Load - - 30 pF TTL Output Load - - 1 -

PRELIMINARY (July, 2002, Version 0.0) 4 AMIC Technology, Inc. Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolu te Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or int ended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter LP62E16256E-70LLT Unit Conditions Min. Max. ILI Input Leakage Current - 1 µA VIN = GND to VCC ILO Output Leakage Current µA CE = VIH HB = VIH or OE = VIH or WE = VIH VI/O = GND to VCC ICC Active Power Supply Current - 5 mA CE = VIL, II/O = 0mA ICC1 - 30 mA * Min. Cycle, Duty = 100% Dynamic Operating CE = VI, II/O = 0mA ICC2 Current - 10 mA CE = VIL, VIH = VCC, VIL = 0V, f = 1MHz, II/O = 0 mA ISB - 0.5 mA CE = VIH ISB1 Standby Current - 10 µA CE ≥ VCC - 0.2V, VIN ≥ 0V VOL Output Low Voltage - 0.2 V IOL = 0.1 mA VOH Output High Voltage 1.4 - V IOH = -0.1 mA

PRELIMINARY (July, 2002, Version 0.0) 5 AMIC Technology, Inc. Truth Table CE OE WE LB HB I/O1 to I/O8 Mode I/O9 to I/O16 Mode VCC Current H X X X X Not selected Not selected ISB1, ISB X X X H H High - Z High - Z ISB1, ISB L L Read Read ICC1, ICC2, ICC L L H L H Read High - Z ICC1, ICC2, ICC H L High - Z Read ICC1, ICC2, ICC L L Write Write ICC1, ICC2, ICC L X L L H Write High - Z ICC1, ICC2, ICC H L High - Z Write ICC1, ICC2, ICC L H H L X High - Z High - Z ICC1, ICC2, ICC L H H X L High - Z High - Z ICC1, ICC2, ICC Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF VIN = 0V CI/O* Input/Output Capacitance 8 pF VI/O = 0V * These parameters are sampled and not 100% tested.

PRELIMINARY (July, 2002, Version 0.0) 6 AMIC Technology, Inc. AC Characteristics (TA = -25°C to +85°C, VCC = 1.65V to 2.2V) Symbol Parameter LP62E16256E-70LLT Unit Min. Max. Read Cycle tRC Read Cycle Time 70 - ns tAA Address Access Time - 70 ns tACE Chip Enable Access Time - 70 ns tBE Byte Enable Access Time - 70 ns tOE Output Enable to Output Valid - 35 ns tCLZ Chip Enable to Output in Low Z 10 - ns tBLZ Byte Enable to Output in Low Z 10 - ns tOLZ Output Enable to Output in Low Z 5 - ns tCHZ Chip Disable to Output in High Z - 25 ns tBHZ Byte Disable to Output in High Z - 25 ns tOHZ Output Disable to Output in High Z - 25 ns tOH Output Hold from Address Change 5 - ns Write Cycle tWC Write Cycle Time 70 - ns tCW Chip Enable to End of Write 60 - ns tBW Byte Enable to End of Write 60 - ns tAS Address Setup Time 0 - ns tAW Address Valid to End of Write 60 - ns tWP Write Pulse Width 55 - ns tWR Write Recovery Time 0 - ns tWHZ Write to Output in High Z - 25 ns tDW Data to Write Time Overlap 30 - ns tDH Data Hold from Write Time 0 - ns tOW Output Active from End of Write 5 - ns Note: tCHZ, tBHZ and t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.

PRELIMINARY (July, 2002, Version 0.0) 7 AMIC Technology, Inc. Timing Waveforms Read Cycle 1(1, 2, 4) tRC tOH tAA tOH Address DOUT Read Cycle 2(1, 2, 3) tRC tAA Address tACE tCHZ5 CE HB, LB tBHZ5 OE tCLZ5 tBE tBLZ5 tOE tOLZ5 tOHZ5 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (July, 2002, Version 0.0) 8 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC tAW Address DATA IN DATA OUT WE HB, LB CE tWR3 tCW tBW tAS1 tWP2 tDW tDH tOW tWHZ4

PRELIMINARY (July, 2002, Version 0.0) 9 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC tAW Address DATA IN DATA OUT WE HB, LB CE tWR3 tCW2 tBW tAS1 tWP tDW tDH tOW tWHZ4

PRELIMINARY (July, 2002, Version 0.0) 10 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) tWC tAW Address DATA IN DATA OUT WE HB, LB CE tWR3 tCW tBW2tAS1 tWP tDW tDH tOW tWHZ4 Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP, tBW) of a low CE , WE and ( HB and , or LB ). 3. tWR is measured from the earliest of CE or WE or ( HB and , or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (July, 2002, Version 0.0) 11 AMIC Technology, Inc.

  • Including scope and jig. * Including scope and jig.

Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,

PRELIMINARY (July, 2002, Version 0.0) 12 AMIC Technology, Inc. Low VCC Data Retention Waveform VCC CE tCDR VIH 1.65V tR VIH 1.65VDATA RETENTION MODE tVR VDR ≥ 1.2V CE ≥ VDR - 0.2V

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mmA) Package LP62E16256EV-70LLT 70 30 10 44L TSOP LP62E16256EU-70LLT 30 10 48L CSP

PRELIMINARY (July, 2002, Version 0.0) 13 AMIC Technology, Inc.

Package Information

TSOP 44L TYPE II Outline Dimensions unit: inches/mm D E HE 0.254 L A1 A2 A S B e D y c L Symbol Dimension in inch Dimension in mm θ 0° - 5° 0° - 5° Notes: 1. Dimension D&E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash.

PRELIMINARY (July, 2002, Version 0.0) 14 AMIC Technology, Inc. 48LD CSP ( 6 x 8 mm ) Outline Dimensions unit: mm (48TFBGA) A B C D E F G H TOP VIEW Ball#A1 CORNER SIDE VIEW C SEATING PLANE // 0.25 C A (0.36) A B C D E F G H 1 2 3 4 5 6 123456 C 0.10 CS

0.25 S A B

b (48X) BOTTOM VIEW Ball*A1 CORNER E e B e D A 0.20(4X) 0.10 C Dimensions in mm Symbol MIN. NOM. MAX. A 1.04 1.14 1.24 A1 0.20 0.25 0.30 A2 0.48 0.53 0.58 D 5.90 6.00 6.10 E 7.90 8.00 8.10 D1 --- 3.75 --- E1 --- 5.25 --- e --- 0.75 --- b 0.30 0.35 0.40 Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE.