LP62E16128A-I AMICC | Alldatasheet

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Preliminary 128K X 16 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (December, 2003, Version 0.0) 1 AMIC Technology, Corp. Document Title 128K X 16 BIT LOW VOLTAGE CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue Decem ber 11, 2003 Preliminary

Preliminary 128K X 16 BIT LOW VOLTAGE CMOS SRAM PRELIMINARY (December, 2003, Version 0.0) 2 AMIC Technology, Corp.

Features

„ Operating voltage: 1.65V to 2.2V „ Access times: 70 ns (max.) „ Current: Very low power version: Operating: 25mA (max.) Standby: 10 µA (max.) „ Full static operation, no cl ock or refreshing required „ All inputs and outputs are directly TTL-compatible „ Common I/O using three-state output „ Data retention voltage: 1.2V (min.) „ Available in 44-pin TSOP and 48-ball CSP (6 x 8mm) packages General Description The LP62E16128A-I is a low operating current 2,097,152- bit static random access memory organized as 131,072 words by 16 bits and operates on low power voltage from 1.65V to 2.2V. It is built using AMIC's high performance CMOS process. Inputs and three-st ate outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN, device enable. Two byte enable inputs and an output enable input are included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 1.2V. Pin Configurations „ TSOP „ CSP (Chip Size Package) 48-pin Top View I/O9 I/O10 GND VCC I/O15 I/O16 NC A8 NC A12 A10 A11 NC A13 A14 A15 I/O8 I/O7 I/O3 I/O1 GND VCC A5 A6 A1 A2 NC 654321 A B C D E F G H I/O14 I/O13 I/O12 I/O11 NC NC A16 I/O2 I/O4 I/O5 I/O6 LB HB WE OE CE CE I/O I/O2 I/O3 I/O4 VCC GND I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A11 A10 NC I/O I/O10 I/O11 I/O12 VCC GND I/O I/O14 I/O15 I/O16 LB HB OE LP62E16128AV-T A12 A5A4 NC

PRELIMINARY (December, 2003, Version 0.0) 3 AMIC Technology, Corp. Block Diagram DECODER

1024 X 2048

Pin No. Symbol Description 1 - 5, 18 - 22, 24 – 27, 42 - 44 A0 - A16 Address Inputs

6 CE Chip Enable Input

7 - 10, 13 - 16, 29 - 32, 35 - 38 I/O1 - I/O16 Data Inputs/Outputs

17 WE Write Enable Input

39 LB Lower Byte Enable Input (I/O1 to I/O8)

40 HB Higher Byte Enable Input (I/O9 to I/O16)

41 OE Output Enable Input

11, 33 VCC Power 12, 34 GND Ground 23, 28 NC No Connection

PRELIMINARY (December, 2003, Version 0.0) 4 AMIC Technology, Corp. Pin Description - CSP Symbol Description Symbol Description A0 - A16 Address Inputs HB Higher Byte Enable Input (I/O9 - I/O16) CE Chip Enable OE Output Enable I/O1 - I/O16 Data Input/Output VCC Power Supply WE Write Enable Input GND Ground LB Lower Byte Enable Input (I/O1 - I/O8) NC No Connection Recommended DC Operating Conditions (TA = -40°C to + 85°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 1.65 2 2.2 V GND Ground 0 0 0 V VIH Input High Voltage 1.4 - VCC + 0.2 V VIL Input Low Voltage -0.2 - +0.4 V CL Output Load - - 30 pF TTL Output Load - - 1 -

PRELIMINARY (December, 2003, Version 0.0) 5 AMIC Technology, Corp. Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any ot her conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter LP62E16128A-70LLI Unit Conditions Min. Max. ⏐ILI⏐ Input Leakage Current - 1 µA VIN = GND to VCC ⏐ILO⏐ Output Leakage Current µA CE = VIH or LB = VIH or HB = VIH or OE = VIH or WE = VIH VI/O = GND to VCC ICC Active Power Supply Current - 5 mA CE = VIL , II/O = 0mA ICC1 Dynamic Operating - 25 mA Min. Cycle, Duty = 100% CE = VIL, II/O = 0mA ICC2 Current - 10 mA CE = VIL, VIH = VCC, VIL = 0V, f = 1MHz, II/O = 0 mA ISB1 Standby Power - 10 µA CE ≥ VCC - 0.2V, VIN ≥ 0V VOL Output Low Voltage - 0.2 V I OL = 0.1 mA VOH Output High Voltage 1.4 - V I OH = -0.1 mA

PRELIMINARY (December, 2003, Version 0.0) 6 AMIC Technology, Corp. Truth Table CE OE WE LB HB I/O1 to I/O8 Mode I/O 9 to I/O16 Mode VCC Current H X X X X Not selected Not selected I SB1, ISB X X X H H High-Z High-Z I SB1, ISB L L Read Read I CC1, ICC2, ICC L L H L H Read High - Z I CC1, ICC2, ICC H L High - Z Read I CC1, ICC2, ICC L L Write Write I CC1, ICC2, ICC L X L L H Write Not Write/Hi - Z I CC1, ICC2, ICC H L No Write/Hi - Z Write I CC1, ICC2, ICC L H H X L High - Z High - Z I CC1, ICC2, ICC L X High - Z High - Z I CC1, ICC2, ICC Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF V IN = 0V CI/O* Input/Output Capacitance 8 pF V I/O = 0V * These parameters are sampled and not 100% tested.

PRELIMINARY (December, 2003, Version 0.0) 7 AMIC Technology, Corp. AC Characteristics (TA = -40°C to +85°C, VCC = 1.65V to 2.2V) LP62E16128A-70LLI Unit Symbol Parameter Min. Max. Read Cycle tRC Read Cycle Time 70 - ns tAA Address Access Time - 70 ns tACE Chip Enable Access Time - 70 ns tBE Byte Enable Access Time - 70 tOE Output Enable to Output Valid - 35 ns tCLZ Chip Enable to Output in Low Z 10 - ns tBLZ Byte Enable to Outupt in Low Z 10 - ns tOLZ Output Enable to Output in Low Z 5 - ns tCHZ Chip Disable to Output in High Z - 25 ns tBHZ Byte Disable to Output in High Z - 25 ns tOHZ Output Disable to Output in High Z - 25 ns tOH Output Hold from Address Change 5 - ns Write Cycle tWC Write Cycle Time 70 - ns tCW Chip Enable to End of Write 60 - ns tBW Byte Enable to End of Write 60 - ns tAS Address Setup Time 0 - ns tAW Address Valid to End of Write 60 - ns tWP Write Pulse Width 55 - ns tWR Write Recovery Time 0 - ns tWHZ Write to Output in High Z - 25 ns tDW Data to Write Time Overlap 30 - ns tDH Data Hold from Write Time 0 - ns tOW Output Active from End of Write 5 - ns Note: t CHZ, tBHZ and t OHZ and t WHZ are defined as the time at which the out puts achieve the open circuit condition and are not referred to output voltage levels.

PRELIMINARY (December, 2003, Version 0.0) 8 AMIC Technology, Corp. Timing Waveforms Read Cycle 1(1, 2, 4) tRC tOH tAA tOH Address DOUT Read Cycle 2(1, 2, 3) tRC tAA Address tACE tCHZ5 CE HB, LB tBHZ5 OE tCLZ5 tBE tBLZ5 tOE tOLZ5 tOHZ5 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VIL , HB = VIL and, or LB = VIL. 3. Address valid prior to or coincident with CE and (HB and, or LB ) transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (December, 2003, Version 0.0) 9 AMIC Technology, Corp. Timing Waveforms (continued) Write Cycle 1 (Write Enable Controlled) tWC tAW Address DATA IN DATA OUT WE HB, LB CE tWR3 tCW tBW tAS1 tWP2 tDW tDH tOW tWHZ4

PRELIMINARY (December, 2003, Version 0.0) 10 AMIC Technology, Corp. Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC tAW Address DATA IN DATA OUT WE HB, LB CE tWR3 tCW2 tBW tAS1 tWP tDW tDH tOW tWHZ4

PRELIMINARY (December, 2003, Version 0.0) 11 AMIC Technology, Corp. Timing Waveforms (continued) Write Cycle 3 (Byte Enable Controlled) tWC tAW Address DATA IN DATA OUT WE HB, LB CE tWR3 tCW tBW2tAS1 tWP tDW tDH tOW tWHZ4 Notes: 1. t AS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP, tBW) of a low CE , WE and (HB and , or LB ). 3. t WR is measured from the earliest of CE or WE or (HB and , or LB ) going high to the end of the Write cycle. 4. OE level is high or low. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (December, 2003, Version 0.0) 12 AMIC Technology, Corp.

  • Including scope and jig. * Including scope and jig.

Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,

PRELIMINARY (December, 2003, Version 0.0) 13 AMIC Technology, Corp. Low VCC Data Retention Waveform VCC CE tCDR VIH 1.8V tR VIH 1.8V DATA RETENTION MODE VDR ≥ 1.2V CE ≥ VDR - 0.2V tVR

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (µA) Package LP62E16128AV-70LLI 25 10 44L TSOP LP62E16128AU-70LLI 25 10 48L CSP

PRELIMINARY (December, 2003, Version 0.0) 14 AMIC Technology, Corp.

Package Information

TSOP 44L TYPE II Outline Dimensions unit: inches/mm 1 D E HE 0.254 L A1 A2 A S B e D y c L Symbol Dimension in inch Dimension in mm Notes: 1. Dimension D&E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash.

PRELIMINARY (December, 2003, Version 0.0) 15 AMIC Technology, Corp. 48LD CSP (6 x 8 mm) Outline Dimensions unit: mm (48TFBGA) A B C D E F G H TOP VIEW Ball#A1 CORNER SIDE VIEW C SEATING PLANE // 0.25 C A (0.36) A B C D E F G H 123456 123456 C 0.10 CS

0.25 S A B

b (48X) BOTTOM VIEW Ball*A1 CORNER E e B e D A 0.20(4X) 0.10 C Dimensions in mm Symbol MIN. NOM. MAX. A 1.00 1.10 1.20 A1 0.20 0.25 0.30 A2 0.48 0.53 0.58 D 5.90 6.00 6.10 E 7.90 8.00 8.10 D1 --- 3.75 --- E1 --- 5.25 --- e --- 0.75 --- b 0.30 0.35 0.40 Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE.