LP621024D-T_15 AMICC | Alldatasheet
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(July, 2005, Version 1.2) AMIC Technology, Corp. Document Title 128K X 8 BIT CMOS SRAM
Revision History
Rev. No. History Issue Date Remark
1.1 Add Pb-Free package type August 19, 2004 Final
1.2 Remove non-Pb-free package type July 3, 2006
(July, 2005, Version 1.2) 1 AMIC Technology, Corp. Features General Description Single +5V power supply Access times: 55/70 ns (max.) Current: Very low power version: Operating: 70mA (max.) Standby: 50 µA (max.) Full static operation, no cl ock or refreshing required All inputs and outputs are directly TTL-compatible Common I/O using three-state output Output enable and two chip enable inputs for easy application Data retention voltage: 2V (min.) Available in 32-pin DIP, SOP TSOP and TSSOP (8 X 13.4mm) packages Pb-Free package only All Pb-free (Lead-free) products are RoHS compliant The LP621024D-T is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 5V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Product Family Power Dissipation Product Family Operating Temperature VCC Range Speed Data Retention (ICCDR, Typ.) Standby (ISB1, Typ.) Operating (ICC2, Typ.) Package Type LP621024D -25°C to +85°C 4.5V~5.5V 55ns / 70ns 0.5µA 2 µA 10mA 32L DIP/ SOP/TSOP/ TSSOP 1. Typical values are measured at VCC = 5.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V. Pin Configurations DIP SOP TSOP/(TSSOP) NC A16 A14 A12 I/O1 I/O2 I/O3 I/O4GND I/O5 I/O6 I/O7 I/O8 A10 A13 CE2 A15 VCC A11 LP621024D-T 16 17 OE NC A16 A14 A12 I/O1 I/O2 I/O3 I/O4GND I/O5 I/O6 I/O7 I/O8 A10 A13 CE2 A15 VCC A11 LP621024DM-T 16 17 OE LP621024DV-T (LP621024DX-T) 116 17 32 Pin No. Pin Name Pin No. Pin Name 3 4 5 6 7 8 9 10 11 12 13 14 302928272625242219 21 20 231817 A8 A13 CE2 A15 VCC NC I/O8 A16 A14 A12 A7 A6 A3 A2 A1 A0 I/O 1 I/O2 GND I/O 4 I/O5 I/O6 I/O7I/O3 A11 WE CE1 15 16 31 32 A5 A4 A10 OE CE1 WE CE1 WE
(July, 2005, Version 1.2) 2 AMIC Technology, Corp. Block Diagram ROW DECODER
512 X 2048
Pin Descriptions - DIP/SOP Pin No. Symbol Description
1 NC No Connection
2 - 12, 23, 25 - 28, 31 A0 - A16 Address Inputs 13 - 15, 17 - 21 I/O1 - I/O8 Data Input/Outputs
16 GND Ground
22 CE1 Chip Enable
24 OE Output Enable
29 WE Write Enable
30 CE2 Chip Enable
32 VCC Power Supply (+5V)
Pin Description - TSOP/TSSOP Pin No. Symbol Description 1 - 4, 7, 10 - 20, 31 A0 - A16 Address Inputs
5 WE Write Enable
6 CE2 Chip Enable
8 VCC Power Supply
9 NC No Connection
21 - 23, 25 - 29 I/O1 - I/O8 Data Input/Outputs
24 GND Ground
30 CE1 Chip Enable
32 OE Output Enable
(July, 2005, Version 1.2) 3 AMIC Technology, Corp. Recommended DC Operating Conditions (TA = -25°C to + 85°C) Symbol Parameter Min. Typ. Max. Unit Supply Voltage 4.5 5.0 5.5 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 3.5 VCC + 0.3 V VIL Input Low Voltage -0.3 0 +0.8 V CL Output Load - - 30 pF TTL Output Load - - 1 - Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any ot her conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter LP621024D-55LLT LP621024D-70LLT Unit Conditions Min. Max. Min. Max. ⎜ILI⎥ Input Leakage Current - 1 - 1 µA VIN = GND to VCC ⎜ILO⎥ Output Leakage Current - 1 - 1 µA CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC ICC Active Power Supply Current - 15 - 15 mA CE1 = VIL, CE2 = VIH II/O = 0mA ICC1 Dynamic Operating - 70 - 70 mA Min. Cycle, Duty = 100% CE1 = VIL, CE2 = VIH II/O = 0mA ICC2 Current - 15 - 15 mA CE1 = VIL, CE2 = VIH VIH = VCC, VIL = 0V f = 1MHZ, II/O = 0mA
(July, 2005, Version 1.2) 4 AMIC Technology, Corp. Symbol Parameter LP621024D-55LLT LP621024D-70LLT Unit Conditions Min. Max. Min. Max. ISB - 2 - 2 mA CE1 = VIH or CE2 =VIL ISB1 Standby Power Supply Current - 50 - 50 µA CE1 ≥ VCC - 0.2V CE2 ≥ VCC - 0.2V VIN ≥ 0V ISB2 - 50 - 50 µA CE2 ≤ 0.2V VIN ≥ 0V VOL Output Low Voltage - 0.4 - 0.4 V I OL = 2.1mA VOH Output High Voltage 2.4 - 2.4 - V I OH = -1.0mA Truth Table Mode CE1 CE2 OE WE I/O Operation Supply Current Standby H X X X High Z I SB, ISB1 X L X X High Z I SB, ISB2 Output Disable L H H H High Z I CC, ICC1, ICC2 Read L H L H D OUT I CC, ICC1, ICC2 Write L H X L D IN I CC, ICC1, ICC2 Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF V IN = 0V CI/O* Input/Output Capacitance 8 pF V I/O = 0V * These parameters are sampled and not 100% tested.
(July, 2005, Version 1.2) 5 AMIC Technology, Corp. AC Characteristics (TA = -25°C to + 85°C, VCC = 5V ± 10%) Symbol Parameter LP621024D-55LLT LP621024D-70LLT Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 55 - 70 - ns tAA Address Access Time - 55 - 70 ns tACE1 Chip Enable Access Time CE1 - 55 - 70 ns tACE2 CE2 - 55 - 70 ns tOE Output Enable to Output Valid - 30 - 35 ns tCLZ1 Chip Enable to Output in Low Z CE1 10 - 10 - ns tCLZ2 CE2 10 - 10 - ns tOLZ Output Enable to Output in Low Z 5 - 5 - ns tCHZ1 Chip Disable to Output in High Z CE1 0 20 0 25 ns tCHZ2 CE2 0 20 0 25 ns tOHZ Output Disable to Output in High Z 0 20 0 25 ns tOH Output Hold from Address Change 5 - 5 - ns Write Cycle tWC Write Cycle Time 55 - 70 - ns tCW Chip Enable to End of Write 50 - 60 - ns tAS Address Setup Time 0 - 0 - ns tAW Address Valid to End of Write 50 - 60 - ns tWP Write Pulse Width 40 - 50 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 25 0 30 ns tDW Data to Write Time Overlap 25 - 30 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Notes: tCHZ1, t CHZ2, t OHZ, and t WHZ are defined as the time at which the out puts achieve the open circuit condition and are not referred to output voltage levels.
(July, 2005, Version 1.2) 6 AMIC Technology, Corp. Timing Waveforms Read Cycle 1(1, 2, 4) tRC tOH tAA tOH Address DOUT Read Cycle 2 (1, 3, 4, 6) tCLZ15 tACE1 tCHZ15 CE1 DOUT Read Cycle 3 (1, 4, 7, 8) tCLZ25 tACE2 tCHZ25 CE2 DOUT
(July, 2005, Version 1.2) 7 AMIC Technology, Corp. Timing Waveforms (continued) Read Cycle 4 (1) tRC Address CE2 DOUT tAA tOE tOLZ5 tACE1 tCLZ15 tACE2 tCLZ25 tCHZ25 tOHZ5 tCHZ15 tOH OE CE1 Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high. 7. CE1 is low. 8. Address valid prior to or coincident with CE2 transition high. Write Cycle 1 (6) (Write Enable Controlled) tWC Address CE1 CE2 DIN tOW tDHtDW tWHZ tWP2tAS1 (4) tCW5 tAW tWR3 WE DOUT (4)
(July, 2005, Version 1.2) 8 AMIC Technology, Corp. Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address CE1 CE2 DIN tDHtDW (4) (4) tCW5 tAW tWR3 WE DOUT tWHZ7 tWP2 tCW5 tAS1 Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP) of a low CE1, a high CE2 and a low WE . 3. t WR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. 4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. t CW is measured from the later of CE1 going low or CE2 going high to the end of Write. 6. OE is continuously low. (OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(July, 2005, Version 1.2) 9 AMIC Technology, Corp. Figure 1. Output Load Figure 2. Output Load for t CLZ1,
(July, 2005, Version 1.2) 10 AMIC Technology, Corp. Low VCC Data Retention Waveform (1) ( CE1 Controlled) VCC CE1 tCDR VIH 4.5V tR VIH 4.5V DATA RETENTION MODE VDR ≥ 2V CE1 ≥ VDR - 0.2V Low VCC Data Retention Waveform (2) (CE2 Controlled) VCC CE2 tCDR VIL 4.5V tR VIL 4.5V DATA RETENTION MODE VDR ≥ 2V CE2 < 0.2V
(July, 2005, Version 1.2) 11 AMIC Technology, Corp.
Ordering Information
Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (µA) Package LP621024D-55LLTF 70 50 32L Pb-Free DIP LP621024DM-55LLTF 70 50 32L Pb-Free SOP LP621024DV-55LLTF 70 50 32L Pb-Free TSOP LP621024DX-55LLTF 70 50 32L Pb-Free TSSOP LP621024D-70LLTF 70 50 32L Pb-Free DIP LP621024DM-70LLTF 70 50 32L Pb-Free SOP LP621024DV-70LLTF 70 50 32L Pb-Free TSOP LP621024DX-70LLTF 70 50 32L Pb-Free TSSOP
(July, 2005, Version 1.2) 12 AMIC Technology, Corp.
Package Information
P-DIP 32L Outline Dimensions unit: inches/mm S AL E eA D C α B Base Plane Seating Plane Symbol Dimensions in inches Dimensions in mm A 0.210 Max. 5.33 Max. A1 0.010 Min. 0.25 Min. A2 0.155±0.010 3.94±0.25 B 0.018 +0.004 0.46 +0.10 -0.002 -0.05 B1 0.050 +0.004 1.27 +0.10 -0.002 -0.05 C 0.010 +0.004 0.25 +0.11 -0.002 -0.05 E 0.600±0.010 15.24±0.25 e1 0.100±0.010 2.54±0.25 eA 0.655±0.035 16.64±0.89 S 0.090 Max. 2.29 Max. Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash.
(July, 2005, Version 1.2) 13 AMIC Technology, Corp. SOP (W.B.) 32L Outline Dimensions unit: inches/mm E HE L LE c See Detail F Detail F 1732 A1 A2 A s D Seating Plane D y e b Symbol Dimensions in inches Dimensions in mm A 0.118 Max. 3.00 Max. A1 0.004 Min. 0.10 Min. A2 0.106±0.005 2.69±0.13 b 0.016 +0.004 0.41 +0.10 -0.002 -0.05 c 0.008 +0.004 0.20 +0.10 -0.002 -0.05 E 0.445±0.010 11.30±0.25 e 0.050 ±0.006 1.27±0.15 e1 0.525 NOM. 13.34 NOM. HE 0.556±0.010 14.12±0.25 LE 0.055±0.008 1.40±0.20 S 0.044 Max. 1.12 Max. y 0.004 Max. 0.10 Max. Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e 1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
(July, 2005, Version 1.2) 14 AMIC Technology, Corp. TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e LE L GAUGE PLANE A c 0.25 BSC Detail "A" D y Detail "A" S b HD D E 0.10(0.004) M °12.0 θ Symbol Dimensions in inches Dimensions in mm A 0.047 Max. 1.20 Max. A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 D 0.724±0.004 18.40±0.10 e 0.020 TYP. 0.50 TYP. HD 0.787±0.007 20.00±0.20 LE 0.031 TYP. 0.80 TYP. S 0.0167 TYP. 0.425 TYP. Y 0.004 Max. 0.10 Max. Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e 1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
(July, 2005, Version 1.2) 15 AMIC Technology, Corp. TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm e Detail "A" D 0.10MM Detail "A" S b E D LE L GAUGE PLANE A c 0.25 BSC Detail "A" SEATING PLANE °12.0 θ Symbol Dimensions in inches Dimensions in mm A 0.049 Max. 1.25 Max. A1 0.002 Min. 0.05 Min. A2 0.039±0.002 1.00±0.05 c 0.006±0.0003 0.15±0.008 e 0.020 TYP. 0.50 TYP. D 0.528±0.008 13.40±0.20 D1 0.465±0.004 11.80±0.10 LE 0.0266 Min. 0.675 Min. S 0.0109 TYP. 0.278 TYP. y 0.004 Max. 0.10 Max. Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e 1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.