LP61L256C AMICC | Alldatasheet

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Preliminary 32K X 8 BIT HIGH SPEED CMOS SRAM PRELIMINARY (November, 2001, Version 0.0) AMIC Technology, Inc. Document Title 32K X 8 BIT HIGH SPEED CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue November 9, 2001 Preliminary

Preliminary 32K X 8 BIT HIGH SPEED CMOS SRAM PRELIMINARY (November, 2001, Version 0.0) 1 AMIC Technology, Inc.

Features

n Single +3.3V power supply n Access times: 12/15 ns (max.) n Current: Operating: 120mA (max.) Standby: 5mA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Common I/O using three-state output n Data retention voltage: 2V (min.) n Available in 28-pin SOJ package General Description The LP6 1L256C is a high -speed, low -power 262,144 -bit static random access memory organized as 32,768 words by 8 bits and operates on a single 3.3V power supply. It is built using high performance CMOS process. Inputs and three -state outputs are TTL compatible an d allow for direct interfacing with common system bus structures. Minimum standby power is drawn by this device when CE is at a high level, independent of the other input levels. Data retention is guaranteed at a power supply voltage as low as 2V. Pin Configurations n SOJ A14 A12 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE OE A11 A13 WE VCC A10 LP61L256C 14 15

PRELIMINARY (November, 2001, Version 0.0) 2 AMIC Technology, Inc. Block Diagram ROW DECODER

256 X 1024

Pin No. Symbol Description 1 - 10, 21, 23 - 26 A0 - A14 Address Inputs 11 - 13, 15 - 19 I/O0 - I/O7 Data Inputs/Outputs

14 GND Ground

28 VCC Power Supply

20 CE Chip Enable

22 OE Output Enable

27 WE Write Enable

PRELIMINARY (November, 2001, Version 0.0) 3 AMIC Technology, Inc. Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 3.0 3.3 3.6 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 - VCC + 0.3 V VIL Input Low (1) Voltage -0.5 0 +0.8 V CL Output Load - - 30 pF Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at the se or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter LP61L256C-12/15 Unit Conditions Min. Max. ILI Input Leakage - 2 µA VIN = GND to VCC ILO Output Leakage - 2 µA CE = VIH or OE = VIH VI/O = GND to VCC ICC1 (2) Dynamic Operating Current - 120 mA CE = VIL, II/O = 0 mA Min. Cycle, Duty = 100% ISB - 30 mA CE = VIH ISB1 Standby Power Supply Current mA CE ≥ VCC - 0.2V VIN ≥ VCC -0.2V or VIN ≤ 0.2V VOL Output Low Voltage - 0.4 V IOL = 8 mA VOH Output High Voltage 2.4 - V IOH = -4 mA Notes: 1. VIL = -3.0V for pulses less than 20 ns. 2. ICC1 is dependent on output loading, cycle rates, and Read/Write pa tterns.

PRELIMINARY (November, 2001, Version 0.0) 4 AMIC Technology, Inc. Truth Table Mode CE OE WE I/O Operation Supply Current Standby H X X High Z ISB, ISB1 Output Disable L H H High Z ICC1 Read L L H DOUT ICC1 Write L X L DIN ICC1 Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 10 pF VIN = 0V CI/O* Input/Output Capacitance 10 pF VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V ± 10%) Symbol Parameter LP61L256C-12 LP61L256C-15 Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 12 - 15 - ns tAA Address Access Time - 12 - 15 ns tACE Chip Enable Access Time - 12 - 15 ns tOE Output Enable to Output Valid - 6 - 8 ns tCLZ Chip Enable to Output in Low Z 3 - 3 - ns tOLZ Output Enable to Output in Low Z 0 - 0 - ns tCHZ Chip Disable Output in High Z 0 6 - 8 ns tOHZ Output Disable to Output in High Z 0 6 0 8 ns tOH Output Hold from Address Change 3 - 3 - ns

PRELIMINARY (November, 2001, Version 0.0) 5 AMIC Technology, Inc. AC Characteristics (continued) Symbol Parameter LP61L256C-12 LP61L256C-15 Unit Min. Max. Min. Max Write Cycle tWC Write Cycle Time 12 - 15 - ns tCW Chip Enable to End of Write 10 - 12 - ns tAS Address Setup Time of Write 0 - 0 - ns tAW Address Valid to End of Write 10 - 12 - ns tWP Write Pulse Width 10 - 12 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 6 0 8 ns tDW Data to Write Time Overlap 6 - 7 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 3 - 3 - ns Notes: tCHZ, t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levles. Timing Waveforms Read Cycle 1(1) tRC Address DOUT tAA tOE tOLZ5 tACE tCLZ5 tCHZ5 tOH OE tOHZ5 CE

PRELIMINARY (November, 2001, Version 0.0) 6 AMIC Technology, Inc. Timing Waveforms (continued) Read Cycle 2(1, 2, 4) tRC tOH tAA tOH Address DOUT Read Cycle 3(1, 3, 4,) tCLZ5 tACE tCHZ5 DOUT CE Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled, CE = VIL. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (November, 2001, Version 0.0) 7 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1(6) (Write Enable Controlled) tWC Address DIN tOW7 tDHtDW tWHZ7 tWP2tAS1 (4) tCW5 tAW tWR3 DOUT WE CE Write Cycle 2 (Chip Enable Controlled) tWC Address DIN tDW tWHZ7 tAW tWR3 DOUT tDH (4) tWP2 tCW5tAS1 CE WE Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP) of a low CE and a low WE . 3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle 4. If the CE low transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (November, 2001, Version 0.0) 8 AMIC Technology, Inc. Figure 1. Output Load Figure 2. Output Load for tCLZ, tOLZ,

PRELIMINARY (November, 2001, Version 0.0) 9 AMIC Technology, Inc. Low VCC Data Retention Waveform VCC CE tCDR VIH 3.0V tR VIH 3.0V DATA RETENTION MODE VDR ≥ 2.0V CE ≥ VDR - 0.2V

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) Package LP61L256CS-12 12 120 5 28L SOJ LP61L256CS-15 15 120 5 28L SOJ

PRELIMINARY (November, 2001, Version 0.0) 10 AMIC Technology, Inc.

Package Information

SOJ 28L Outline Dimensions unit: inches/mm E HE A1 A2 A e e1 C 1528 S D Seating Plane D y L b Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max b1 0.028 TYP 0.71 TYP b 0.018 TYP 0.46 TYP C 0.010 TYP 0.25 TYP D - 0.710 0.730 - 18.03 18.54 e 0.050 BSC 1.27 BSC Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.