LP61L1024U-12

LP61L1024 AMICC | Alldatasheet

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Technical content

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM (August, 2002, Version 2.1) AMIC Technology, Inc. Document Title 128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM

Revision History

Rev. No. History Issue Date Remark

2.0 Add product family and 32-pin TSSOP package May 9, 2002 Final

2.1 Add 36 ball BGA package type August 22, 2002

128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM (August, 2002, Version 2.1) 1 AMIC Technology, Inc. Features General Description n Single +3.3V power supply n Access times: 12/15 ns (max.) n Current: Operating: 170mA (max.) Standby: 10mA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2.0V (min.) n Available in 32-pin SOJ 300 mil, 32 -pin TSOP and 32 - pin TSSOP and 36-pin CSP packages The LP61L1024 is a low operating current 1,048,576 -bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three -state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enab le inputs are provided for POWER -DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Power Dissipation Product Family Operating Temperature VCC Range Speed Data Retention (ICCDR, Typ.) Standby (ISB1, Typ.) Operating (ICC1, Typ.) Package Type LP61L1024 0°C ~ 70°C 3V ~ 3.6V 12/15 ns 0.4mA 0.5mA 130mA 32L SOJ 32L TSOP 32L TSSOP 36B µBGA 1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V.

(August, 2002, Version 2.1) 2 AMIC Technology, Inc. Pin Configurations nn SOJ nn TSOP / TSSOP nn CSP (Chip Size Package) 36-pin Top View Block Diagram VCC GND DECODER

256 X 4096

Pin No. Symbol Description 2 - 12, 23, 25 - 28, 31 A0 - A16 Address Inputs

29 WE Write Enable

24 OE Output Enable

22 CE1 Chip Enable

30 CE2 Chip Enable

1 NC No Connection

13 - 15, 17 - 21 I/O1 - I/O8 Data Input/Outputs

32 VCC Power Supply

16 GND Ground

LP61L1024V(X) 116 17 32 Pin No. Pin Name Pin No. Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 302928272625242219 2120 231817 A8 A13 CE2 A15 VCC NC I/O8 A16 A14 A12 A7 A6 A3 A2 A1 A0 I/O1 I/O2 GND I/O4 I/O5 I/O6 I/O7I/O3 A11 WE CE1 15 16 31 32 A5 A4 A10 OE I/O4 I/O5 GND VCC I/O6 I/O7 A9 A10 OE A11 CE1 A12 A13 A14 A16 NC NC A15 I/O3 I/O2 I/O1 I/O0 GND VCC NC WE NC A5 A3 A6 654321 A B C D E F G H

(August, 2002, Version 2.1) 3 AMIC Technology, Inc. Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 3.0 3.3 3.6 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 - VCC + 0.3 V VIL Input Low Voltage -0.3 0 +0.8 V CL Output Load - - 30 pF TTL Output Load - - 1 - Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress rat ings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Symbol Parameter LP61L1024-12/15 Unit Conditions Min. Max. ILI Input Leakage Current - 2 µA VIN = GND to VCC ILO Output Leakage Current - 2 µA CE1 = VIH or CE2 = VIL or OE = VIH or WE = VIL VI/O = GND to VCC ICC1 (1) Dynamic Operating Current - 170 mA CE1 = VIL, CE2 = VIH II/O = 0 mA ISB - 30 mA CE1 = VIH or CE2 = VIL ISB1 Standby Power Supply Current - 10 mA CE1 ≥ VCC - 0.2V, CE2 ≥ VCC - 0.2V, VIN ≤ 0.2V or VIN ≥ VCC - 0.2V ISB2 - 10 mA CE1 ≤ 0.2V, CE2 ≤ 0.2V VIN ≤ 0.2V or VIN ≥ VCC - 0.2V VOL Output Low Voltage - 0.4 V IOL = 8 mA VOH Output High Voltage 2.4 - V IOH = -4 mA Note: 1. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns

(August, 2002, Version 2.1) 4 AMIC Technology, Inc. Truth Table Mode CE1 CE2 OE WE I/O Operation Supply Current Standby H X X X High Z ISB, ISB1 X L X X High Z ISB, ISB2 Output Disable L H H H High Z ICC1 Read L H L H DOUT ICC1 Write L H X L DIN ICC1 Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 8 pF VIN = 0V CI/O* Input/Output Capacitance 10 pF VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V + 10, GND = 0V) Symbol Parameter LP61L1024-12 LP61L1024-15 Unit Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 12 - 15 - ns tAA Address Access Time - 12 - 15 ns tACE1 Chip Enable Access Time CE1 - 12 - 15 ns tACE2 CE2 - 12 - 15 ns tOE Output Enable to Output Valid - 7 - 9 ns tCLZ1 Chip Enable to Output in Low Z CE1 3 - 5 - ns tCLZ2 CE2 3 - 5 - ns tOLZ Output Enable to Output in Low Z 2 - 2 - ns tCHZ1 Chip Disable to Output in High Z CE1 - 7 - 10 ns tCHZ2 CE2 - 7 - 10 ns tOHZ Output Disable to Output in High Z 2 7 2 9 ns tOH Output Hold from Address Change 3 - 5 - ns

(August, 2002, Version 2.1) 5 AMIC Technology, Inc. AC Characteristics (continued) Symbol Parameter LP61L1024-12 LP61L1024-15 Unit Min. Max. Min. Max. Write Cycle tWC Write Cycle Time 12 - 15 - ns tCW Chip Enable to End of Write 10 - 12 - ns tAS Address Setup Time of Write 0 - 0 - ns tAW Address Valid to End of Write 10 - 12 - ns tWP Write Pulse Width 8 - 10 - ns tWR Write Recovery Time 0 - 0 - ns tWHZ Write to Output in High Z 0 7 0 8 ns tDW Data to Write Time Overlap 8 - 10 - ns tDH Data Hold from Write Time 0 - 0 - ns tOW Output Active from End of Write 5 - 5 - ns Notes: tCHZ1, t CHZ2, t OHZ, and t WHZ are defined as the time at which the outputs achieve the open circuit con dition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1(1, 2, 4) tRC tOH tAA tOH Address DOUT

(August, 2002, Version 2.1) 6 AMIC Technology, Inc. Read Cycle 2 (1, 3, 4, 6) tCLZ15 tACE1 tCHZ15 CE1 DOUT Read Cycle 3 (1, 4, 7, 8) tCLZ25 tACE2 tCHZ25 CE2 DOUT

(August, 2002, Version 2.1) 7 AMIC Technology, Inc. Timing Waveforms (continued) Read Cycle 4 (1) tRC Address OE tAA tOE tOLZ5 tACE1 tCLZ25 tACE2 tCLZ25 tCHZ25 tOHZ5 tCHZ15 tOH CE1 CE2 DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested. 6. CE2 is high. 7. CE1 is low. 8. Address valid prior to or coincident with CE2 transition high.

(August, 2002, Version 2.1) 8 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1(6) (Write Enable Controlled) tWC Address CE1 CE2 DIN tOW tDHtDW tWHZ tWP2tAS1 (4) (4) tCW5 tAW tWR3 WE DOUT

(August, 2002, Version 2.1) 9 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address CE1 CE2 DIN tDHtDW (4) (4) tCW5 tAW tWR3 WE DOUT tWHZ7 tWP2 tCW5 tAS1 Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP) of a low CE1, a high CE2 and a low WE . 3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle. 4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low or CE2 going high to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

(August, 2002, Version 2.1) 10 AMIC Technology, Inc. Figure 1. Output Load Figure 2. Output Load for tCLZ1,

(August, 2002, Version 2.1) 11 AMIC Technology, Inc. Low VCC Data Retention Waveform (1) ( CE1 Controlled) VCC CE1 tCDR VIH 3.0V tR VIH 3.0V DATA RETENTION MODE VDR ≥ 2V CE1 ≥ VDR - 0.2V Low VCC Data Retention Waveform (2) (CE2 Controlled) VCC CE2 tCDR VIL 3.0V tR VIL 3.0V DATA RETENTION MODE VDR ≥ 2V CE2 ≤ 0.2V

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) Package LP61L1024S-12 12 170 10 32L SOJ (300 mil) LP61L1024V-12 12 170 10 32L TSOP LP61L1024X-12 12 170 10 32L TSSOP LP61L1024U-12 12 170 10 36L CSP LP61L1024S-15 15 170 10 32L SOJ (300 mil) LP61L1024V-15 15 170 10 32L TSOP LP61L1024X-15 15 170 10 32L TSSOP LP61L1024U-15 15 170 10 36L CSP

(August, 2002, Version 2.1) 12 AMIC Technology, Inc.

Package Information

SOJ 32/32LD (300mil BODY) Outline Dimensions unit: inches/mm E MIN 0.026" A2 e e1 1732 s SEATING PLANE D0.004 b D y yy DETAIL "A" HE A DETAIL "A" b c SECTION F-F BASE METAL WITH PLATING F F Symbol Dimensions in inches Dimensions in mm Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E doesn't include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.

(August, 2002, Version 2.1) 13 AMIC Technology, Inc. TSOP 32L TYPE I (8 X 20mm) Outline Dimensions unit: inches/mm e LE L GAUGE PLANE A c 0.25 BSC Detail "A" D y Detail "A" S b HD D E 0.10(0.004) M °12.0 θ Symbol Dimensions in inches Dimensions in mm A 0.047 Max. 1.20 Max. A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05 D 0.724±0.004 18.40±0.10 e 0.020 TYP. 0.50 TYP. HD 0.787±0.007 20.00±0.20 LE 0.031 TYP. 0.80 TYP. S 0.0167 TYP. 0.425 TYP. Y 0.004 Max. 0.10 Max. θ 0° ~ 6° 0° ~ 6° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.

(August, 2002, Version 2.1) 14 AMIC Technology, Inc. TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions unit: inches/mm e Detail "A" D 0.076MM Detail "A" S b E D LE L A c θ SEATING PLANE Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max e 0.020 TYP 0.50 TYP S 0.0109 TYP 0.278 TYP Notes: 1. The maximum value of dimension D1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.

(August, 2002, Version 2.1) 15 AMIC Technology, Inc. 36LD CSP (6 x 8 mm) Outline Dimensions unit: mm A B C D E F G H TOP VIEW Ball#A1 CORNER SIDE VIEW C SEATING PLANE // 0.25 C A (0.36) A B C D E F G H 1 2 3 4 5 6 123456 C 0.10 CS

0.25 S A B

b (36X) BOTTOM VIEW Ball*A1 CORNER E e B e D A 0.20(4X) 0.10 C Dimensions in mm Symbol MIN. NOM. MAX. A 1.00 1.10 1.20 A1 0.16 0.21 0.26 A2 0.48 0.53 0.58 D 5.80 6.00 6.20 E 7.80 8.00 8.20 D1 --- 3.75 --- E1 --- 5.25 --- e --- 0.75 --- b 0.25 0.30 0.35 Note: 1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY). 2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. DIMENSION b IS MEASURED AT THE MAXIMUM. 4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE SOLDER BALL AND THE BODY EDGE.