LP61L1008A AMICC | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 11

Technical content

Features

n Single 3.3V ± 10% power supply n Access times: 8/10/12 ns (max.) n Current: Operating: 160/155/150mA (max.) Standby: 5mA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Center Power/Ground Pin Configuration n Common I/O using three-state output n Output enable and one chip enable inputs for easy application n Data retention voltage: 2.0V (min.) n Available in 32-pin SOJ 300 mil package General Description The LP61L1008 A is a high speed 1,048,576 -bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three -state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER -DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Pin Configuration CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A8A7 A10 A11 A12 I/O5 I/O6 VCC I/O7 I/O8 OE A13 A14 A15 A16 GND LP61L1008AS 16 17

PRELIMINARY (August, 2001, Version 1.0) 2 AMIC Technology, Inc. Block Diagram DECODER

512 X 2048

Pin No. Symbol Description 1 - 4, 13 - 21, 29- 32 A0 - A16 Address Inputs

12 WE Write Enable

28 OE Output Enable

5 CE Chip Enable

6 –7, 10 - 11, 22 – 23, 26 - 27 I/O1 - I/O8 Data Input/Outputs 8, 24 VCC Power Supply 9, 25 GND Ground

PRELIMINARY (August, 2001, Version 1.0) 3 AMIC Technology, Inc. Recommended DC Operating Conditions (TA = 0°C to + 70°C) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 3.0 3.3 3.6 V GND Ground 0 0 0 V VIH Input High Voltage 2.2 - VCC + 0.3 V VIL Input Low Voltage -0.3 0 +0.8 V CL Output Load - - 30 pF TTL Output Load - - 1 - Absolute Maximum Ratings* *Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation o f this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. LP61L1008A- 8/10/12 Symbol Parameter Min. Max. Unit Conditions ILI Input Leakage Current - 2 µA VIN = GND to VCC ILO Output Leakage Current - 2 µA CE = VIH or OE = VIH or WE = VIL VI/O = GND to VCC -8 - 160 -10 - 155 ICC1 (1) Dynamic Operating Current -12 - 150 mA CE = VIL II/O = 0 mA ISB - 20 mA CE = VIH ISB1 Standby Power Supply Current mA CE ≥ VCC - 0.2V, VIN ≤ 0.2V or VIN ≥ VCC - 0.2V VOL Output Low Voltage - 0.4 V IOL = 8 mA VOH Output High Voltage 2.4 - V IOH = -4 mA Note: 1. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns

PRELIMINARY (August, 2001, Version 1.0) 4 AMIC Technology, Inc. Truth Table Mode CE OE WE I/O Operation Supply Current Standby H X X High Z ISB, ISB1 Output Disable L H H High Z ICC1 Read L L H DOUT ICC1 Write L X L DIN ICC1 Note: X = H or L Capacitance (TA = 25°C, f = 1.0MHz) Symbol Parameter Min. Max. Unit Conditions CIN* Input Capacitance 6 pF VIN = 0V CI/O* Input/Output Capacitance 8 pF VI/O = 0V * These parameters are sampled and not 100% tested. AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V ± 10%, GND = 0V) Symbol Parameter LP61L1008A-8 LP61L1008A-10 LP61L1008A-12 Unit Read Cycle tRC Read Cycle Time 8 - 10 - 12 - ns tAA Address Access Time - 8 - 10 - 12 ns tACE Chip Enable Access Time CE - 8 - 10 - 12 ns tOE Output Enable to Output Valid - 4 - 5 - 6 ns tCLZ Chip Enable to Output in Low Z CE 3 - 3 - 5 - ns tOLZ Output Enable to Output in Low Z 0 - 0 - 2 - ns tCHZ Chip Disable to Output in High Z CE - 4 - 5 - 6 ns tOHZ Output Disable to Output in High Z 0 4 0 5 2 6 ns tOH Output Hold from Address Change 3 - 3 - 5 - ns

PRELIMINARY (August, 2001, Version 1.0) 5 AMIC Technology, Inc. AC Characteristics (continued) Symbol Parameter LP61L1008A-8 LP61L1008A-10 LP61L1008A-12 Unit Write Cycle tWC Write Cycle Time 8 - 10 - 12 - ns tCW Chip Enable to End of Write 6 - 7 - 10 - ns tAS Address Setup Time of Write 0 - 0 - 0 - ns tAW Address Valid to End of Write 6 - 7 - 10 - ns tWP Write Pulse Width 6 - 7 - 8 - ns tWR Write Recovery Time 0 - 0 - 0 - ns tWHZ Write to Output in High Z 0 4 0 5 0 5 ns tDW Data to Write Time Overlap 4 - 5 - 8 - ns tDH Data Hold from Write Time 0 - 0 - 0 - ns tOW Output Active from End of Write 3 - 3 - 5 - ns Notes: tCHZ1, tCHZ2, tOHZ, and t WHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. Timing Waveforms Read Cycle 1(1, 2, 4) tRC tOH tAA tOH Address DOUT

PRELIMINARY (August, 2001, Version 1.0) 6 AMIC Technology, Inc. Read Cycle 2 (1, 3, 4, 6) tCLZ5 tACE tCHZ5 CE DOUT Read Cycle 3 (1) tRC Address OE tAA tOE tOLZ5 tACE tCHZ5 tOH CE DOUT Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VI. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured ±500mV from steady state. This parameter is sample d and not 100% tested.

PRELIMINARY (August, 2001, Version 1.0) 7 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 1(6) (Write Enable Controlled) tWC Address CE DIN tOW tDHtDW tWHZ tWP2tAS1 (4) tCW5 tAW tWR3 WE DOUT

PRELIMINARY (August, 2001, Version 1.0) 8 AMIC Technology, Inc. Timing Waveforms (continued) Write Cycle 2 (Chip Enable Controlled) tWC Address CE DIN tDHtDW (4) tCW5 tAW tWR3 WE DOUT tWHZ7 tWP2 tCW5 tAS1 Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (t WP) of a low CE and a low WE . 3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle. 4. If the CE low transition with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

PRELIMINARY (August, 2001, Version 1.0) 9 AMIC Technology, Inc.

  • Including scope and jig.* Including scope and jig.

Figure 1. Output Load Figure 2. Output Load for tCLZ,

PRELIMINARY (August, 2001, Version 1.0) 10 AMIC Technology, Inc. Low VCC Data Retention Waveform ( CE Controlled) VCC CE tCDR VIH 3.0V tR VIH 3.0V DATA RETENTION MODE VDR ≥ 2V CE ≥ VDR - 0.2V

Ordering Information

Part No. Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) Package LP61L1008AS-8 8 160 5 32L SOJ (300 mil) LP61L1008AS-10 10 155 5 32L SOJ (300 mil) LP61L1008AS-12 12 150 5 32L SOJ (300 mil)

PRELIMINARY (August, 2001, Version 1.0) 11 AMIC Technology, Inc.

Package Information

SOJ 32 (300mil BODY) Outline Dimensions unit: inches/mm E MIN 0.026" A2 e e1 1732 s SEATING PLANE D0.004 b D y yy DETAIL "A" HE A DETAIL "A" b c SECTION F-F BASE METAL WITH PLATING F F Symbol Dimensions in inches Dimensions in mm Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E doesn't include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.