LMC555 SS | Alldatasheet
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www.siliconsupplies.com Die Size (Unsawn) 1300 x 1200 51 x 47 µm mils Minimum Bond Pad Size 100 x 100 3.94 x 3.94 µm mils Die Thickness 350 (±20) 13.78 (±0.79) µm mils Top Metal Composition Al 1%Si 1.1µm Back Metal Composition N/A – Bare Si CMOS Low Power Timer – LMC555 Precision Timing Generator / Oscillator in bare die form Wide supply voltage range 2-18V Low Supply Current - 200µA max @ 2V High speed operation – Min 500kHz guaranteed Operates in both astable and monostable modes Adjustable Duty Cycle Output drives TTL/CMOS/MOS at 5V Rev 1.1 21/01/18 Features: The following part suffixes apply: No suffix - MIL-STD-883 /2010B Visual Inspection “ H” - MIL-STD-883 /2010B Visual Inspection + MIL-PRF-38534 Class H LAT “ K” - MIL-STD-883 /2010A Visual Inspection (Space) + MIL-PRF-38534 Class K LAT LAT = Lot Acceptance Test. For further information on LAT process flows see below. www.siliconsupplies.com\\quality\\bare-die-lot-qualification Supply Formats: Mechanical Specification Default – Die in Waffle Pack (400 per tray capacity) Sawn Wafer on Tape – On request Unsawn Wafer – On request Die Thickness <> 350µm(15 Mils) – On request Assembled into Ceramic Package – On request The LMC555 is a highly stable timer for use in precision timing and oscillator applications. As timer (monostable), the device is capable of producing accurate time delays from microseconds through hours using x1 capacitor and x1 resistor. As oscillator (astable), the device can maintain an accurately controlled free running frequency + duty cycle with x2 external resistors and x1 capacitor. The LMC555 may be triggered by the falling edge of the waveform signal. Device output can source or sink up to 200mA current and drive TTL/CMOS circuits. The LMC555 is a CMOS upgraded version of the popular bipolar 555 timer series and is drop-in compatible for most legacy 555 applications. The device also directly replaces TLC555 and ICM7555.
Description
Ordering Information Die Dimensions in µm (mils) 1300 (51) 1200 (47) For compatibility and improvements versus LM555, NE555, SE555, MC1455 and MC1555 products please see application notes. PART OBSOLETE - DISCONTINUED
d CMOS Low Power Timer – LMC555 Rev 1.1 21/01/18 Pad Layout and Functions COORDINATES (mm) PAD FUNCTION X Y 1 GND 1.084 0.119 2 TRIGGER 1.084 0.4015 3 OUTPUT 1.0735 0.9545 4 RESET 0.845 0.984
5 CONTROL
VOLTAGE 0.3335 0.984 6 THRESHOLD 0.116 0.8995 7 DISCHARGE 0.116 0.6965 8 VDD 0.1535 0.116 CHIP BACK POTENTIAL IS GND OR FLOAT Truth Table 1300µm (51.18 mils) 1200µm (47.24 mils) 0,0 8 1 3 5 DIE ID THRESHOLD TRIGGER RESET OUTPUT DISCHARGE X X L L ON > 2/3·VDD > 1/3·VDD H L ON < 2/3·VDD > 1/3·VDD H STABLE STABLE X < 1/3·VDD H H OFF NOTE: RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD Page 2 of 8 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com CMOS Low Power Timer – LMC555 Rev 1.1 21/01/18 PARAMETER SYMBOL MIN MAX UNITS DC Supply Voltage VDD 2 18 V Output Current IO - 20 mA Input Voltage VTH, VTRIG,VRESET -0.3 VDD +0.3 V Recommended Operating Conditions (Voltages referenced to GND) Absolute Maximum Ratings1 PARAMETER SYMBOL VALUE UNIT DC Supply Voltage VDD 18 V Output Current IO 100 mA Input Voltage VTH, VTRIG,VRESET,VCTRL VDD ±0.3 V Operating Temperature Range TJ -55 to 125 °C Storage Temperature Range TSTG -65 to 150 °C Power Dissipation in Still Air2 P D 300 mW LIMITS PARAMETER SYMBOL VDD CONDITIONS MIN TYP MAX UNITS TJ = 25°C 3.25 3.35 3.50 Threshold Voltage VTH 5V TJ = -55°C to +125°C 3 - 0.80 V 18V TJ = 25°C 0.4 0.7 1 2V Reset Voltage VRESET 18V TJ = -55°C to +125°C 0.2 - 1.5 V TJ = 25°C 2.9 3.3 3.8 Control Voltage VCTRL 5V TJ = -55°C to +125°C - - - V 5V IOL = 3.2mA, TJ = 25°C - - 0.40 15V IOL = 20mA, TJ = 25°C - - 1.00 5V IOL = 3.2mA, TJ = 125°C - - 0.60 Low-Level Output Voltage VOL 15V IOL = 20mA, TJ = 125°C - - 1.50 V 5V 4.00 - - 15V IOH = -0.8mA, TJ = 25°C 14.30 - - 5V 3.50 - - High-Level Output Voltage VOH 15V IOH = -0.8mA, V 2V - - 200 18V TJ = 25°C - - 300 2V - - 600 Supply Current2 ICC 18V TJ = -55°C to +125°C - - 1000 µA 1. Operation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability. 2. Measured in plastic package at 25°C, results in die form are dependent on die attach and assembly method. 2. Essentially independent of VTH, VTRIG,VRESET voltages. PART OBSOLETE - DISCONTINUED
CMOS Low Power Timer – LMC555 Rev 1.1 21/01/18 LIMITS PARAMETER SYMBOL VDD CONDITIONS TYP MAX UNITS MIN RL = 10MΩ, CL = 10pF 35 TJ = 25°C - 75 Rise/Fall output time ns (Figure 1) tTHL, tTLH 5V RL = 10MΩ, CL = 1pF TJ = -55°C to +125°C 70 - 150 TJ = 25°C 500 - - Guaranteed OSC freq Astable operation fMIN 2-18V TJ = -55°C to +125°C 200 - - kHz Initial Accuracy Error - - - - - 5 % 5V - - 0.02 10V - - 0.03 RL = 1-100kΩ Drift with Temperature αf 15V CL = 0.1µF %/°C TJ = 25°C 3 Drift with Supply Voltage Δf 5V TJ = -55°C to +125°C - - %/B 3. Not production tested in die form, characterized by chip design and tested in package LAT. Application Notes The LMC555 is in most instances a direct replacement for the NE555, SE555 and LM555. Produced using a CMOS process this device offers the possibility to reduce the external passive component count and also delivers improved electrical performance. All unused inputs must be tied to an appropriate logic level to prevent false triggering. Supply decoupling capacitor All legacy bipolar 555 devices produce large crowbar currents in the output driver necessitating power supply decoupling via an external capacitor located close to the device. The LMC555 produces supply current spikes of only 2-3mA instead of 300-400mA, therefore supply decoupling is not normally necessary and optional. Control Voltage decoupling capacitors For most applications capacitors are not required and optional since the input impedance of the CMOS comparators is very high versus the legacy bipolar 555. Supply Current The supply current consumed by LMC555 is very low versus legacy 555. However, total system supply will be high unless the timing components are high impedance. Therefore, use high values for R and low values for C. Output Drive Capability The output driver consists of a CMOS inverter capable of driving most logic families including CMOS and TTL. As such, if driving CMOS, the output swing at all supply voltages will equal the supply voltage. At a supply voltage of 4.5V or more the LMC555 will drive at least x2 standard TTL loads. Page 4 of 8 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
CMOS Low Power Timer – LMC555 Rev 1.1 21/01/18 Application Notes Continued Astable Mode The circuit can be connected to trigger itself & free-run as a multivibrator (Figure 3). The output swings from rail-to-rail and is a true 50% duty cycle square wave. Less than a 1% frequency variation is observed over a voltage range of +5V to +15V. Duty Cycle is configurable by setting the ratio of resistors RA + RB (Figure 4), the external capacitor charges through RA + RB and discharges through RB. Monostable Mode The timer functions as a one-shot. Initially the external capacitor (C) is held discharged by a transistor inside the timer. Upon application of a negative TRIGGER pulse to pin 2 the internal flip-flop is set which releases the short circuit across the external capacitor and drives the OUTPUT high. The voltage across the capacitor now increases exponentially with a time constant t=RAC. When the voltage across the capacitor equals 2/3 VDD, the comparator resets the flip-flop, which in turn discharges the capacitor rapidly & drives the OUTPUT to its low state. TRIGGER must return to a high state before the OUTPUT can return to a low state (Figure 2). Control Voltage The CONTROL VOLTAGE terminal permits the two trip voltages for the THRESHOLD and TRIGGER internal comparators to be controlled. This provides the possibility of oscillation frequency modulation in the astable mode or even inhibition of oscillation, depending on the applied voltage. In the monostable mode, delay times can be changed by varying the applied voltage to the CONTROL VOLTAGE pin. RESET The RESET terminal is designed to have essentially the same trip voltages as the standard bipolar 555 i.e. 0.6V to 0.7V. At all supply voltages it represents an extremely high input impedance. The mode of operation of the RESET function is much improved over the standard bipolar 555 in that it controls only the internal flip-flop, which in turn controls simultaneously the state of the OUTPUT and DISCHARGE pins. This avoids the multiple threshold problems sometimes encountered with slow falling edges in the legacy bipolar 555 devices. If RESET is not used tie to VDD. Figure 1 – Switching Waveform Page 5 of 8 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
CMOS Low Power Timer – LMC555 Rev 1.1 21/01/18 Application Notes Continued f = 1.44 / (RA + 2RB) C VDD RA GND 1 8 TRIGGER CONTROL THRESHOLD DISCHARGE 2 7 Figure 4 – Astable Operation (Adjustable Duty Cyle) C RB OUTPUT VDD Optional Capacitor Duy Cycle is controlled by D = (RA + RB) / (RA + 2RB) Page 7 of 8 www.siliconsupplies.com PART OBSOLETE - DISCONTINUED
www.siliconsupplies.com CMOS Low Power Timer – LMC555 Rev 1.1 21/01/18Application Notes Continued R = 100kΩ ± 20% Typ, Tie down unused inputs TRIGGER VDD R COMPARATOR A COMPARATOR B CONTROL VOLTAGE THRESHOLD R R OUTPUT DISCHARGE RESET FLIP-FLOP n OUTPUT DRIVERS Figure 4 – Block Diagram DISCLAIMER: The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Silicon Supplies Ltd hereby disclaims any and all warranties and liabilities of any kind. LIFE SUPPORT POLICY: Silicon Supplies Ltd components may be used in life support devices or systems only with the express written approval of Silicon Supplies Ltd, if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. PART OBSOLETE - DISCONTINUED