LCC-32P-M19

MB95650L CYPRESS | Alldatasheet

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Datasheet sections

Features

Instruction set optimized for controllers ■ Multiplication and division instructions ■ 16-bit arithmetic operations ■ Bit test branch instructions ■ Bit manipulation instructions, etc. Clock ■ Selectable main clock source ❐ Main oscillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz) ❐ External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz) ❐ Main CR clock (4 MHz 2%) ❐ Main CR PLL clock

• The main CR PLL clock frequency becomes 8 MHz 2% when the PLL multiplication rate is 2.
• The main CR PLL clock frequency becomes 10 MHz 2% when the PLL multiplication rate is 2.5.
• The main CR PLL clock frequency becomes 12 MHz 2% when the PLL multiplication rate is 3.
• The main CR PLL clock frequency becomes 16 MHz 2% when the PLL multiplication rate is 4. ❐ Main PLL clock (maximum machine clock frequency:

16 MHz)

■ Selectable subclock source ❐ Suboscillation clock (32.768 kHz) ❐ External clock (32.768 kHz) ❐ Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz) Timer ■ 8/16-bit composite timer  2 channels ■ Time-base timer  1 channel ■ Watch prescaler  1 channel UART/SIO  1 channel (The channel can be used either as a UART/SIO channel or as an I2C bus interface channel.) ■ The function of this channel can be switched between UART/SIO and I2C bus interface. ■ Full duplex double buffer ■ Capable of clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data transfer I2C bus interface  2 channels (One of the two channels can be used either as an I2C bus interface channel or as a UART/SIO channel.) ■ Supports Standard-mode and Fast-mode (400 kHz). ■ Built-in wake-up function LIN-UART ■ Full duplex double buffer ■ Capable of clock asynchronous serial data transfer and clock synchronous serial data transfer External interrupt  6 channels ■ Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) ■ Can be used to wake up the device from different low power consumption (standby) modes 8/12-bit A/D converter  6 channels 8-bit or 12-bit resolution can be selected. Low power consumption (standby) modes There are four standby modes as follows: ■ Stop mode ■ Sleep mode ■ Watch mode ■ Time-base timer mode I/O port ■ MB95F652E/F653E/F654E/F656E (number of I/O ports: 21) ❐ General-purpose I/O ports (CMOS I/O) : 17 ❐ General-purpose I/O ports (N-ch open drain) : 4 ■ MB95F652L/F653L/F654L/F656L (number of I/O ports: 20) ❐ General-purpose I/O ports (CMOS I/O) : 17 ❐ General-purpose I/O ports (N-ch open drain) : 3 On-chip debug ■ 1-wire serial control ■ Serial writing supported (asynchronous mode) Hardware/software watchdog timer ■ Built-in hardware watchdog timer ■ Built-in software watchdog timer

Document Number: 002-04696 Rev. *A Page 2 of 105 MB95650L Series Power-on reset A power-on reset is generated when the power is switched on. Low-voltage detection reset circuit and low-voltage detection interrupt circuit (only available on MB95F652E/F653E/F654E/F656E) Built-in low-voltage detection function Clock supervisor counter Built-in clock supervisor counter Dual operation Flash memory The program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. Flash memory security function Protects the content of the Flash memory.

Document Number: 002-04696 Rev. *A Page 4 of 105 MB95650L Series 1. Product Line-up (Continued) Part number Parameter MB95F652E MB95F653E MB95F654E MB95F656E MB95F652L MB95F653L MB95F654L MB95F656L Type Flash memory product Clock supervisor counter It supervises the main clock oscillation and the subclock oscillation. Flash memory capacity 8 Kbyte 12 Kbyte 20 Kbyte 36 Kbyte 8 Kbyte 12 Kbyte 20 Kbyte 36 Kbyte RAM capacity 256 bytes 512 bytes 1024 bytes 1024 bytes 256 bytes 512 bytes 1024 bytes 1024 bytes Power-on reset Yes Low-voltage detection reset Yes No Reset input Selected through software With dedicated reset input CPU functions

• Number of basic instructions : 136
• Instruction bit length : 8 bits
• Instruction length : 1 to 3 bytes
• Data bit length : 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time : 0.6 µs (machine clock frequency = 16.25 MHz) General-purpose I/O
• I/O port : 21
• CMOS I/O : 17
• N-ch open drain : 4
• I/O port : 20
• C M O S I / O : 1 7
• N-ch open drain : 3 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) Hardware/software watchdog timer
• Reset generation cycle Main oscillation clock at 10 MHz: 105 ms (Min)
• The sub-CR clock can be used as the source clock of the software watchdog timer. Wild register It can be used to replace 3 bytes of data. LIN-UART
• A wide range of communication speed can be selected by a dedicated reload timer.
• It has a full duplex double buffer.
• Both clock synchronous serial data transfer and clock asynchronous serial data transfer are enabled.
• The LIN function can be used as a LIN master or a LIN slave. 8/12-bit A/D converter 6 channels 8-bit or 12-bit resolution can be selected. 8/16-bit composite timer 2 channels
• The timer can be configured as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”.
• It has the following functions: interval timer function, PWC function, PWM function and input capture function.
• Count clock: it can be selected from internal clocks (seven types) and external clocks.
• It can output square wave. External interrupt 6 channels
• Interrupt by edge detection (The rising edge, falling edge, and both edges can be selected.)
• It can be used to wake up the device from different standby modes. On-chip debug • 1-wire serial control
• It supports serial writing (asynchronous mode).

Document Number: 002-04696 Rev. *A Page 5 of 105 MB95650L Series (Continued) Part number Parameter MB95F652E MB95F653E MB95F654E MB95F656E MB95F652L MB95F653L MB95F654L MB95F656L UART/SIO 1 channel (The channel can be used either as a UART/SIO channel or as an I2C bus interface channel.)

• Data transfer with UART/SIO is enabled.
• It has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an error detection function.
• It uses the NRZ type transfer format.
• LSB-first data transfer and MSB-first data transfer are available to use.
• Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data transfer are enabled. I2C bus interface 2 channels (One of the two channels can be used either as an I2C bus interface channel or as a UART/SIO channel.)
• Master/slave transmission and reception
• It has the following functions: bus error function, arbitration function, transmission direction detection function, wake-up function, and functions of generating and detecting repeated START conditions. Watch prescaler Eight different time intervals can be selected. Flash memory
• It supports automatic programming (Embedded Algorithm), and program/erase/erase-suspend/erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
• Flash security feature for protecting the content of the Flash memory Standby mode There are four standby modes as follows:
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode Package FPT-24P-M10 FPT-24P-M34 LCC-32P-M19 Number of program/erase cycles 1000 10000 100000 Data retention time 20 years 10 years 5 years

Document Number: 002-04696 Rev. *A Page 6 of 105 MB95650L Series 2. Packages and Corresponding Products : Available Part number Package MB95F652E MB95F653E MB95F654E MB95F656E MB95F652L MB95F653L MB95F654L MB95F656L

Document Number: 002-04696 Rev. *A Page 7 of 105 MB95650L Series 3. Differences among Products and Notes on Product Selection Current consumption When using the on-chip debug function, take account of the current consumption of Flash memory program/erase. For details of current consumption, see “18. Electrical Characteristics”. Package For details of information on each package, see “2. Packages and Corresponding Products” and “22. Package Dimension”. Operating voltage The operating voltage varies, depending on whether the on-chip debug function is used or not. For details of operating voltage, see “18. Electrical Characteristics”. On-chip debug function The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool. For details of the connection method, refer to “Chapter 20 Example Of Serial Programming Connection” in “New 8FX MB95650L Series Hardware Manual”.

Document Number: 002-04696 Rev. *A Page 8 of 105 MB95650L Series 4. Pin Assignment P12/DBG/EC0 P07/INT07/TO10 P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT P02/INT02/AN02/SCK P01/AN01 P00/AN00 P64/EC1 P14/SDA0 P15/SCL0 PF2/RST PF1/X1 PF0/X0 Vss PG2/X1A PG1/X0A Vcc C P17/SCL1/UI0 P16/SDA1/UO0 P62/TO10/UCK0 P63/TO11 (TOP VIEW) TSSOP24 FPT -24P-M10 SOP24 FPT -24P-M34 PF0/X0 PF1/X1 NC NC NC NC P07/INT07/TO10 P12/DBG/EC0 P06/INT06/TO01 P05/INT05/AN05/TO00 P04/INT04/AN04/SIN/EC0 P03/INT03/AN03/SOT Vss PG2/X1A PG1/X0A Vcc C P17/SCL1/UI0 P16/SDA1/UO0 (TOP VIEW) QFN32 LCC-32P-M19 P02/INT02/AN02/SCK P01/AN01 P00/AN00 P64/EC1 P63/TO11 P62/TO10/UCK0 NC NC NC NC P14/SDA0 P15/SCL0 16 PF2/RST

Document Number: 002-04696 Rev. *A Page 9 of 105 MB95650L Series 5. Pin Functions (Continued) Pin no. Pin name I/O circuit type*4 Function I/O type SOP24*1, TSSOP24*2 QFN32*3 Input Output OD*5 PU*6 13 2 PF0 B General-purpose I/O port Hysteresis CMOS — — X0 Main clock input oscillation pin 23 1 PF1 B General-purpose I/O port Hysteresis CMOS — — X1 Main clock I/O oscillation pin

31 V SS — Power supply pin (GND) — — — —

C General-purpose I/O port Hysteresis CMOS —  X1A Subclock I/O oscillation pin PG1 C General-purpose I/O port Hysteresis CMOS —  X0A Subclock input oscillation pin

64 V CC — Power supply pin — — — —

7 5 C — Decoupling capacitor connection pin — — — — PF2 A General-purpose I/O port Hysteresis CMOS  — RST Reset pin Dedicated reset pin on MB95F652L/F653L/F654L/F656L P17 J General-purpose I/O port CMOS CMOS —/ *7 —SCL1 I 2C bus interface ch. 1 clock I/O pin UI0 UART/SIO ch. 0 data input pin 10 8 P16 J General-purpose I/O port CMOS CMOS —/ *7 —SDA1 I 2C bus interface ch. 1 data I/O pin UO0 UART/SIO ch. 0 data output pin 11 10 P62 D General-purpose I/O port High-current pin Hysteresis CMOS — TO10 8/16-bit composite timer ch. 1 output pin UCK0 UART/SIO ch. 0 clock I/O pin 12 9 P63 D General-purpose I/O port High-current output Hysteresis CMOS —  TO11 8/16-bit composite timer ch. 1 output pin 13 16 P15 I General-purpose I/O port CMOS CMOS  — SCL0 I 2C bus interface ch. 0 clock I/O pin 14 15 P14 I General-purpose I/O port CMOS CMOS  — SDA0 I 2C bus interface ch. 0 data I/O pin 15 17 P64 D General-purpose I/O port Hysteresis CMOS —  EC1 8/16-bit composite timer ch. 1 clock input pin

Document Number: 002-04696 Rev. *A Page 10 of 105 MB95650L Series (Continued) Pin no. Pin name I/O circuit type*4 Function I/O type SOP24*1, TSSOP24*2 QFN32*3 Input Output OD*5 PU*6 16 18 P00 E General-purpose I/O port Hysteresis/ analog CMOS —  AN00 8/12-bit A/D converter analog input pin 17 18 P01 E General-purpose I/O port Hysteresis/ analog CMOS —  AN01 8/12-bit A/D converter analog input pin 18 20 P02 E General-purpose I/O port Hysteresis/ analog CMOS —  INT02 External interrupt input pin AN02 8/12-bit A/D converter analog input pin SCK LIN-UART clock I/O pin 19 21 P03 E General-purpose I/O port Hysteresis/ analog CMOS —  INT03 External interrupt input pin AN03 8/12-bit A/D converter analog input pin SOT LIN-UART data output pin 20 22 P04 F General-purpose I/O port CMOS/ analog CMOS —  INT04 External interrupt input pin AN04 8/12-bit A/D converter analog input pin SIN LIN-UART data input pin EC0 8/16-bit composite timer ch. 0 clock input pin 21 23 P05 K General-purpose I/O port High-current pin Hysteresis/ analog CMOS — INT05 External interrupt input pin AN05 8/12-bit A/D converter analog input pin TO00 8/16-bit composite timer ch. 0 output pin 22 24 P06 D General-purpose I/O port High-current pin Hysteresis CMOS — INT06 External interrupt input pin TO01 8/16-bit composite timer ch. 0 output pin 23 26 P07 K General-purpose I/O port High-current pin Hysteresis CMOS — INT07 External interrupt input pin TO10 8/16-bit composite timer ch. 1 output pin

Document Number: 002-04696 Rev. *A Page 11 of 105 MB95650L Series (Continued) : Available *1: FPT-24P-M34 *2: FPT-24P-M10 *3: LCC-32P-M19 *4: For the I/O circuit types, see “6. I/O Circuit Type”. *5: N-ch open drain *6: Pull-up *7: In I 2C mode, the pin becomes an N-ch open drain pin. Pin no. Pin name I/O circuit type*4 Function I/O type SOP24*1, TSSOP24*2 QFN32*3 Input Output OD*5 PU*6 24 25 P12 H General-purpose I/O port Hysteresis CMOS  —DBG DBG input pin EC0 8/16-bit composite timer ch. 0 clock input pin NC — It is an internally connected pin. Always leave it unconnected. —— — —

Document Number: 002-04696 Rev. *A Page 12 of 105 MB95650L Series 6. I/O Circuit Type (Continued) Type Circuit Remarks A

• N-ch open drain output
• Hysteresis input
• Reset output B
• Oscillation circuit
• High-speed side Feedback resistance: approx. 1 M
• CMOS output
• Hysteresis input C
• Oscillation circuit
• Low-speed side Feedback resistance: approx. 5 M
• CMOS output
• Hysteresis input
• Pull-up control N-ch Reset output / Digital output Reset input / Hysteresis input Standby control / Port select Clock input Port select Digital output Digital output Standby control Hysteresis input Digital output Digital output Standby control Hysteresis input Port select N-ch P-ch N-ch P-ch Clock input X1A X0A Standby control / Port select N-ch P-ch Port select Digital output Digital output Standby control Hysteresis input N-ch Digital output Digital output Digital output Standby control Hysteresis input P-ch R Pull-up control Port select P-ch R Pull-up control

Document Number: 002-04696 Rev. *A Page 13 of 105 MB95650L Series (Continued) Type Circuit Remarks D

• CMOS output
• Hysteresis input
• Pull-up control
• High current output E
• CMOS output
• Hysteresis input
• Pull-up control
• Analog input F
• CMOS output
• CMOS input
• Pull-up control
• Analog input H • N-ch open drain output
• Hysteresis input I • N-ch open drain output
• CMOS input N-ch P-ch P-ch R Pull-up control Digital output Digital output Standby control Hysteresis input N-ch P-ch P-ch R Pull-up control Digital output Digital output Analog input A/D control Standby control Hysteresis input N-ch P-ch P-ch R Pull-up control Digital output Digital output Analog input A/D control Standby control CMOS input N-ch Standby control Hysteresis input Digital output N-ch Digital output Standby control CMOS input

Document Number: 002-04696 Rev. *A Page 14 of 105 MB95650L Series (Continued) Type Circuit Remarks J

• CMOS output
• CMOS input
• N-ch open drain output in I2C mode K
• CMOS output
• Hysteresis input
• Pull-up control
• Analog input
• High current output N-ch P-ch I2C mode control Digital output Digital output Standby control CMOS input N-ch P-ch P-ch R Pull-up control Digital output Digital output Analog input A/D control Standby control Hysteresis input

Document Number: 002-04696 Rev. *A Page 15 of 105 MB95650L Series 7. Handling Precautions Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor devices.

7.1 Precautions for Product Design

This section describes precautions when designing electronic equipment using semiconductor devices. Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical character- istics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. 2. Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. 3. Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: 1. Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. 2. Be sure that abnormal current flows do not occur during the power-on sequence. Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

Document Number: 002-04696 Rev. *A Page 16 of 105 MB95650L Series Precautions Related to Usage of Devices Cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

7.2 Precautions for Package Mounting

Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under Cypress’s recommended conditions. For detailed information about mount conditions, contact your sales representative. Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to Cypress recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. Cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with Cypress ranking of recommended conditions. Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: 1. Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. 2. Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5°C and 30°C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. 3. When necessary, Cypress packages semiconductor devices in highly moisture-resistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. 4. Avoid storing packages where they are exposed to corrosive gases or high levels of dust. Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Cypress recommended conditions for baking. Condition: 125°C/24 h

Document Number: 002-04696 Rev. *A Page 17 of 105 MB95650L Series Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. 2. Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. Ground all fixtures and instruments, or protect with anti-static measures. 5. Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.

7.3 Precautions for Use Environment

Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: 1. Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. 2. Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. 3. Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. 5. Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of Cypress products in other special environmental conditions should consult with sales representatives.

Document Number: 002-04696 Rev. *A Page 18 of 105 MB95650L Series 8. Notes On Device Handling Preventing latch-ups When using the device, ensure that the voltage applied does not exceed the maximum voltage rating. In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in “18.1 Absolute Maximum Ratings” of “18. Electrical Characteristics” is applied to the VCC pin or the VSS pin, a latch-up may occur. When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. Stabilizing supply voltage Supply voltage must be stabilized. A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the V CC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply. Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode.

Document Number: 002-04696 Rev. *A Page 19 of 105 MB95650L Series 9. Pin Connection Treatment of unused pins If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 k. Set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it unconnected. Power supply pins To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance. It is also advisable to connect a ceramic capacitor of approximately 1.0 µF as a bypass capacitor between the VCC pin and the VSS pin at a location close to this device. DBG pin Connect the DBG pin to an external pull-up resistor of 2 k or above. After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor. RST pin Connect the RST pin to an external pull-up resistor of 2 k or above. To prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnection length between a pull-up resistor and the RST pin and that between a pull-up resistor and the VCC pin when designing the layout of the printed circuit board. The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the PF2/RST pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the general purpose I/O function can be selected by the RSTEN bit in the SYSC register. C pin Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. Note on serial communication In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a printed circuit board to prevent noise from occurring. Taking account of the reception of wrong data, take measures such as adding a checksum to the end of data in order to detect errors. If an error is detected, retransmit the data. C Cs DBG RST DBG/RST/C pins connection diagram

Document Number: 002-04696 Rev. *A Page 20 of 105 MB95650L Series 10. Block Diagram Reset with LVD Dual operation Flash with security function (36/20/12/8 Kbyte) F2MC-8FX CPU RAM (1024/512/256 bytes) Oscillator circuit CR oscillator Clock control On-chip debug Wild register External interrupt LIN-UART Internal bus 8/16-bit composite timer ch. 0 I2C bus interface ch. 0 8/16-bit composite timer ch. 1 8/12-bit A/D converter Port Port PF2*1/RST*2 PF0/X0*2 PF1/X1*2 PG1/X0A*2 PG2/X1A*2 P02/INT02 to P07/INT07 C (P02/SCK) (P03/SOT) (P04/SIN) (P00/AN00 to P05*3/AN05) (P12*1/DBG) (P05/TO00) (P06/TO01) (P04/EC0), P12 *1/EC0 UART/SIO ch. 0 P17/UI0 P62/UCK0 P16/UO0 (P62*3/TO10), P62*3/TO10 P63*3/TO11 P64/EC1 P14*1/SDA0 P15*1/SCL0 I2C bus interface ch. 1 (P16/SDA1) (P17/SCL1) Vcc Vss *1: *2: *3: P12, P14, P15 and PF2 are N-ch open drain pins. Software select P05 to P07, P62 and P63 are high-current pins. Note: Pins in parentheses indicate that those pins are shared among different peripheral functions.

Document Number: 002-04696 Rev. *A Page 21 of 105 MB95650L Series 11. CPU Core Memory space The memory space of the MB95650L Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and a program area. The memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. The memory maps of the MB95650L Series are shown below. Memory maps MB95F653E/F653L MB95F654E/F654LMB95F652E/F652L I/O area Access prohibited RAM 256 bytes Registers Access prohibited Extended I/O area Access prohibited Flash memory 4 Kbyte Flash memory 4 Kbyte 0x0000 0x0080 0x0090 0x0100 0x0190 0x0F80 0x1000 0x2000 0xF000 0xFFFF I/O area Access prohibited 0x0000 0x0080 0x0090 I/O area Access prohibited 0x0000 0x0080 0x0090 Registers0x0100 0x0200 0x0290 Registers0x0100 0x0200 Access prohibited Extended I/O area Flash memory 4 Kbyte 0x0F80 0x1000 0x2000 Flash memory 4 Kbyte 0x1000 0x2000 Flash memory 4 Kbyte Extended I/O area 0x0F80 0x1000 Access prohibited RAM 512 bytes Access prohibited Flash memory 8 Kbyte 0xE000 0xFFFF Access prohibited 0x8000 0x2000 Access prohibited 0xC000 RAM 1024 bytes Flash memory 16 Kbyte 0x0490 0xFFFF MB95F656E/F656L I/O area Access prohibited 0x0000 0x0080 0x0090 Registers0x0100 0x0200 Extended I/O area 0x0F80 Access prohibited RAM 1024 bytes Flash memory 32 Kbyte 0x0490 0xFFFF

Document Number: 002-04696 Rev. *A Page 22 of 105 MB95650L Series 12. Memory Space The memory space of the MB95650L Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and a program area. The memory space includes areas for specific applications such as general-purpose registers and a vector table. I/O area (addresses: 0x0000 to 0x007F)

• This area contains the control registers and data registers for built-in peripheral functions.
• As the I/O area forms part of the memory space, it can be accessed in the same way as the memory. It can also be accessed at high-speed by using direct addressing instructions. Extended I/O area (addresses: 0x0F80 to 0x0FFF)
• This area contains the control registers and data registers for built-in peripheral functions.
• As the extended I/O area forms part of the memory space, it can be accessed in the same way as the memory. Data area
• Static RAM is incorporated in the data area as the internal data area.
• The internal RAM size varies according to product.
• The RAM area from 0x0090 to 0x00FF can be accessed at high-speed by using direct addressing instructions.
• In MB95F656E/F656L, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at high-speed by direct addressing instructions with a direct bank pointer set.
• In MB95F654E/F654L, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at high-speed by direct addressing instructions with a direct bank pointer set.
• In MB95F653E/F653L, the area from 0x0090 to 0x028F is an extended direct addressing area. It can be accessed at high-speed by direct addressing instructions with a direct bank pointer set.
• In MB95F652E/F652L, the area from 0x0090 to 0x018F is an extended direct addressing area. It can be accessed at high-speed by direct addressing instructions with a direct bank pointer set.
• In MB95F653E/F653L/F654E/F654L/F656E/F656L, the area from 0x0100 to 0x01FF can be used as a general-purpose register area.
• In MB95F652E/F652L, the area from 0x0100 to 0x018F can be used as a general-purpose register area. Program area
• The Flash memory is incorporated in the program area as the internal program area.
• The Flash memory size varies according to product.
• The area from 0xFFC0 to 0xFFFF is used as the vector table.
• The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register.

Document Number: 002-04696 Rev. *A Page 23 of 105 MB95650L Series Memory space map Direct addressing area Extended direct addressing area I/O area Access prohibited 0x0000 0x0080 0x0090 Registers (General-purpose register area) 0x0100 0x0200 0x047F Vector table area Extended I/O area0x0F80 0x0FFF 0x1000 Access prohibited Program area Data area 0x048F 0x0490 0xFFFF 0xFFC0

Document Number: 002-04696 Rev. *A Page 24 of 105 MB95650L Series 13. Areas for Specific Applications The general-purpose register area and vector table area are used for the specific applications. General-purpose register area (Addresses: 0x0100 to 0x01FF*1)

• This area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc.
• As this area forms part of the RAM area, it can also be used as conventional RAM.
• When the area is used as general-purpose registers, general-purpose register addressing enables high-speed access with short instructions. Non-volatile register data area (Addresses: 0xFFBB to 0xFFBF)
• The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. For details, refer to “Chapter 23 Non-volatile Register (NVR) Interface” in “New 8FX MB95650L Series Hardware Manual”. Vector table area (Addresses: 0xFFC0 to 0xFFFF)
• This area is used as the vector table for vector call instructions (CALLV), interrupts, and resets.
• The top of the Flash memory area is allocated to the vector table area. The start address of a service routine is set to an address in the vector table in the form of data. “16. Interrupt Source Table” lists the vector table addresses corresponding to vector call instructions, interrupts, and resets. For details, refer to “Chapter 4 Reset”, “Chapter 5 Interrupts” and “A.2 Special Instruction Special Instruction CALLV #vct” in “New 8FX MB95650L Series Hardware Manual”. Direct bank pointer and access area *1: Due to the memory size limit, the available access area is up to “0x018F” in MB95F652E/F652L. *2: Due to the memory size limit, the available access area is up to “0x028F” in MB95F653E/F653L. Direct bank pointer (DP[2:0]) Operand-specified dir Access area 0bXXX (It does not affect mapping.) 0x0000 to 0x007F 0x0000 to 0x007F 0b000 (Initial value) 0x0090 to 0x00FF 0x0090 to 0x00FF 0b001 0x0080 to 0x00FF 0x0100 to 0x017F 0b010 0x0180 to 0x01FF* 0b011 0x0200 to 0x027F 0b100 0x0280 to 0x02FF*2 0b101 0x0300 to 0x037F 0b110 0x0380 to 0x03FF 0b111 0x0400 to 0x047F

Document Number: 002-04696 Rev. *A Page 25 of 105 MB95650L Series 14. I/O Map (Continued) Address Register abbreviation Register name R/W Initial value 0x0000 PDR0 Port 0 data register R/W 0b00000000 0x0001 DDR0 Port 0 direction register R/W 0b00000000 0x0002 PDR1 Port 1 data register R/W 0b00000000 0x0003 DDR1 Port 1 direction register R/W 0b00000000 0x0004 — (Disabled) — — 0x0005 WATR Oscillation stabilization wait time setting register R/W 0b11111111 0x0006 PLLC PLL control register R/W 0b000X0000 0x0007 SYCC System clock control register R/W 0bXXX11011 0x0008 STBC Standby control register R/W 0b00000000 0x0009 RSRR Reset source register R/W 0b000XXXXX 0x000A TBTC Time-base timer control register R/W 0b00000000 0x000B WPCR Watch prescaler control register R/W 0b00000000 0x000C WDTC Watchdog timer control register R/W 0b00XX0000 0x000D SYCC2 System clock control register 2 R/W 0bXXXX0011 0x000E to 0x0015 — (Disabled) — — 0x0016 PDR6 Port 6 data register R/W 0b00000000 0x0017 DDR6 Port 6 direction register R/W 0b00000000 0x0018 to 0x0027 — (Disabled) — — 0x0028 PDRF Port F data register R/W 0b00000000 0x0029 DDRF Port F direction register R/W 0b00000000 0x002A PDRG Port G data register R/W 0b00000000 0x002B DDRG Port G direction register R/W 0b00000000 0x002C PUL0 Port 0 pull-up register R/W 0b00000000 0x002D to 0x0032 — (Disabled) — — 0x0033 PUL6 Port 6 pull-up register R/W 0b00000000 0x0034 — (Disabled) — — 0x0035 PULG Port G pull-up register R/W 0b00000000 0x0036 T01CR1 8/16-bit composite timer 01 status control register 1 R/W 0b00000000 0x0037 T00CR1 8/16-bit composite timer 00 status control register 1 R/W 0b00000000 0x0038 T11CR1 8/16-bit composite timer 11 status control register 1 R/W 0b00000000 0x0039 T10CR1 8/16-bit composite timer 10 status control register 1 R/W 0b00000000 0x003A to 0x0048 — (Disabled) — —

Document Number: 002-04696 Rev. *A Page 26 of 105 MB95650L Series (Continued) Address Register abbreviation Register name R/W Initial value 0x0049 EIC10 External interrupt circuit co ntrol register ch. 2/ch. 3 R/W 0b00000000 0x004A EIC20 External interrupt circuit co ntrol register ch. 4/ch. 5 R/W 0b00000000 0x004B EIC30 External interrupt circuit co ntrol register ch. 6/ch. 7 R/W 0b00000000 0x004C to 0x004E — (Disabled) — — 0x004F LVDC LVD control register R/W 0b00000100 0x0050 SCR LIN-UART serial control register R/W 0b00000000 0x0051 SMR LIN-UART serial mode register R/W 0b00000000 0x0052 SSR LIN-UART serial status register R/W 0b00001000 0x0053 RDR LIN-UART receive data register R/W 0b00000000 TDR LIN-UART transmit data register 0x0054 ESCR LIN-UART extended status control register R/W 0b00000100 0x0055 ECCR LIN-UART extended communica tion control register R/W 0b000000XX 0x0056 SMC10 UART/SIO serial mode c ontrol register 1 ch. 0 R/W 0b00000000 0x0057 SMC20 UART/SIO serial mode c ontrol register 2 ch. 0 R/W 0b00100000 0x0058 SSR0 UART/SIO serial status and data register ch. 0 R/W 0b00000001 0x0059 TDR0 UART/SIO serial output data register ch. 0 R/W 0b00000000 0x005A RDR0 UART/SIO serial input data register ch. 0 R 0b00000000 0x005B to 0x005F — (Disabled) — — 0x0060 IBCR00 I 2C bus control register 0 ch. 0 R/W 0b00000000 0x0061 IBCR10 I 2C bus control register 1 ch. 0 R/W 0b00000000 0x0062 IBSR0 I 2C bus status register ch. 0 R/W 0b00000000 0x0063 IDDR0 I 2C data register ch. 0 R/W 0b00000000 0x0064 IAAR0 I 2C address register ch. 0 R/W 0b00000000 0x0065 ICCR0 I 2C clock control register ch. 0 R/W 0b00000000 0x0066 IBCR01 I 2C bus control register 0 ch. 1 R/W 0b00000000 0x0067 IBCR11 I 2C bus control register 1 ch. 1 R/W 0b00000000 0x0068 IBSR1 I 2C bus status register ch. 1 R/W 0b00000000 0x0069 IDDR1 I 2C data register ch. 1 R/W 0b00000000 0x006A IAAR1 I 2C address register ch. 1 R/W 0b00000000 0x006B ICCR1 I 2C clock control register ch. 1 R/W 0b00000000 0x006C ADC1 8/12-bit A/D converter control register 1 R/W 0b00000000 0x006D ADC2 8/12-bit A/D converter control register 2 R/W 0b00000000 0x006E ADDH 8/12-bit A/D converter data register (upper) R/W 0b00000000 0x006F ADDL 8/12-bit A/D converter data register (lower) R/W 0b00000000 0x0070 ADC3 8/12-bit A/D converter control register 3 R/W 0b01111100

Document Number: 002-04696 Rev. *A Page 27 of 105 MB95650L Series (Continued) Address Register abbreviation Register name R/W Initial value 0x0071 FSR2 Flash memory status register 2 R/W 0b00000000 0x0072 FSR Flash memory status register R/W 0b000X0000 0x0073 SWRE0 Flash memory sector write control register 0 R/W 0b00000000 0x0074 FSR3 Flash memory status register 3 R 0b000XXXXX 0x0075 FSR4 Flash memory status register 4 R/W 0b00000000 0x0076 WREN Wild register address compare enable register R/W 0b00000000 0x0077 WROR Wild register data test setting register R/W 0b00000000 0x0078 — Mirror of register bank pointer (RP) and direct bank pointer (DP) — — 0x0079 ILR0 Interrupt level setting register 0 R/W 0b11111111 0x007A ILR1 Interrupt level setting register 1 R/W 0b11111111 0x007B ILR2 Interrupt level setting register 2 R/W 0b11111111 0x007C ILR3 Interrupt level setting register 3 R/W 0b11111111 0x007D ILR4 Interrupt level setting register 4 R/W 0b11111111 0x007E ILR5 Interrupt level setting register 5 R/W 0b11111111 0x007F — (Disabled) — — 0x0F80 WRARH0 Wild register address setting register (upper) ch. 0 R/W 0b00000000 0x0F81 WRARL0 Wild register address setting register (lower) ch. 0 R/W 0b00000000 0x0F82 WRDR0 Wild register data se tting register ch. 0 R/W 0b00000000 0x0F83 WRARH1 Wild register address setting register (upper) ch. 1 R/W 0b00000000 0x0F84 WRARL1 Wild register address setting register (lower) ch. 1 R/W 0b00000000 0x0F85 WRDR1 Wild register data se tting register ch. 1 R/W 0b00000000 0x0F86 WRARH2 Wild register address setting register (upper) ch. 2 R/W 0b00000000 0x0F87 WRARL2 Wild register address setting register (lower) ch. 2 R/W 0b00000000 0x0F88 WRDR2 Wild register data se tting register ch. 2 R/W 0b00000000 0x0F89 to 0x0F91 — (Disabled) — — 0x0F92 T01CR0 8/16-bit composite timer 01 status control register 0 R/W 0b00000000 0x0F93 T00CR0 8/16-bit composite timer 00 status control register 0 R/W 0b00000000 0x0F94 T01DR 8/16-bit composite timer 01 data register R/W 0b00000000 0x0F95 T00DR 8/16-bit composite timer 00 data register R/W 0b00000000 0x0F96 TMCR0 8/16-bit composite timer 00/01 timer mode control register R/W 0b00000000 0x0F97 T11CR0 8/16-bit composite timer 11 status control register 0 R/W 0b00000000 0x0F98 T10CR0 8/16-bit composite timer 10 status control register 0 R/W 0b00000000 0x0F99 T11DR 8/16-bit composite timer 11 data register R/W 0b00000000 0x0F9A T10DR 8/16-bit composite timer 10 data register R/W 0b00000000 0x0F9B TMCR1 8/16-bit composite timer 10/11 timer mode control register R/W 0b00000000

Document Number: 002-04696 Rev. *A Page 28 of 105 MB95650L Series (Continued) R/W access symbols Initial value symbols Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. Address Register abbreviation Register name R/W Initial value 0x0F9C to 0x0FBB — (Disabled) — — 0x0FBC BGR1 LIN-UART baud rate generator register 1 R/W 0b00000000 0x0FBD BGR0 LIN-UART baud rate generator register 0 R/W 0b00000000 0x0FBE PSSR0 UART/SIO dedicated baud rate generator prescaler select register ch.

0 R/W 0b00000000

0x0FBF BRSR0 UART/SIO dedicated baud rate generator baud rate setting register ch. 0 R/W 0b00000000 0x0FC0 to 0x0FC2 — (Disabled) — — 0x0FC3 AIDRL A/D input disable register (lower) R/W 0b00000000 0x0FC4 to 0x0FE3 — (Disabled) — — 0x0FE4 CRTH Main CR clock trimming register (upper) R/W 0b000XXXXX 0x0FE5 CRTL Main CR clock trimming register (lower) R/W 0b000XXXXX 0x0FE6 SYSC2 System configuration register 2 R/W 0b00000000 0x0FE7 CRTDA Main CR clock temperature dependent adjustment register R/W 0b000XXXXX 0x0FE8 SYSC System configuration register R/W 0b00111111 0x0FE9 CMCR Clock monitoring control register R/W 0b00000000 0x0FEA CMDR Clock monitoring data register R 0b00000000 0x0FEB WDTH Watchdog timer selection ID register (upper) R 0bXXXXXXXX 0x0FEC WDTL Watchdog timer select ion ID register (lower) R 0bXXXXXXXX 0x0FED to 0x0FFF — (Disabled) — — R/W : Readable/Writable R : Read only 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined.

Document Number: 002-04696 Rev. *A Page 29 of 105 MB95650L Series 15. I/O Ports List of port registers R/W : Readable/writable (The read value is the same as the write value.) R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the read-modify-write (RMW) type of instruction.) Register name Read/Write Initial value Port 0 data register PDR0 R, RM/W 0b00000000 Port 0 direction register DDR0 R/W 0b00000000 Port 1 data register PDR1 R, RM/W 0b00000000 Port 1 direction register DDR1 R/W 0b00000000 Port 6 data register PDR6 R, RM/W 0b00000000 Port 6 direction register DDR6 R/W 0b00000000 Port F data register PDRF R, RM/W 0b00000000 Port F direction register DDRF R/W 0b00000000 Port G data register PDRG R, RM/W 0b00000000 Port G direction register DDRG R/W 0b00000000 Port 0 pull-up register PUL0 R/W 0b00000000 Port 6 pull-up register PUL6 R/W 0b00000000 Port G pull-up register PULG R/W 0b00000000 A/D input disable register (lower) AIDRL R/W 0b00000000

Document Number: 002-04696 Rev. *A Page 30 of 105 MB95650L Series

15.1 Port 0

Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95650L Series Hardware Manual”.

15.1.1 Port 0 configuration

Port 0 is made up of the following elements.

• General-purpose I/O pins/peripheral function I/O pins
• Port 0 data register (PDR0)
• Port 0 direction register (DDR0)
• Port 0 pull-up register (PUL0)
• A/D input disable register (lower) (AIDRL)

15.1.2 Block diagrams of port 0

This pin has the following peripheral function:

• 8/12-bit A/D converter analog input pin (AN00) P01/AN01 pin This pin has the following peripheral function:
• 8/12-bit A/D converter analog input pin (AN01) Block diagram of P00/AN00 and P01/AN01 PDR0 Pin PDR0 read PDR0 write Executing bit manipulation instruction DDR0 read DDR0 write PUL0 read PUL0 write AIDRL read AIDRL write DDR0 PUL0 AIDRL Stop mode, watch mode (SPL = 1) A/D analog input Hysteresis Pull-up Internal bus

Document Number: 002-04696 Rev. *A Page 31 of 105 MB95650L Series P02/INT02/AN02/SCK pin This pin has the following peripheral functions:

• External interrupt input pin (INT02)
• 8/12-bit A/D converter analog input pin (AN02)
• LIN-UART clock I/O pin (SCK) P03/INT03/AN03/SOT pin This pin has the following peripheral functions:
• External interrupt input pin (INT03)
• 8/12-bit A/D converter analog input pin (AN03)
• LIN-UART data output pin (SOT) P05/INT05/AN05/TO00 pin This pin has the following peripheral functions:
• External interrupt input pin (INT05)
• 8/12-bit A/D converter analog input pin (AN05)
• 8/16-bit composite timer ch. 0 output pin (TO00) Block diagram of P02/INT02/AN02/SCK, P03/INT03/AN03/SOT and P05/INT05/AN05/TO00 PDR0 Pin PDR0 read PDR0 write Executing bit manipulation instruction DDR0 read DDR0 write PUL0 read PUL0 write AIDRL read AIDRL write DDR0 PUL0 AIDRL Stop mode, watch mode (SPL = 1) Peripheral function input Peripheral function input enable (INT02, INT03 and INT05) Peripheral function output enable Peripheral function output A/D analog input Hysteresis Pull-up Internal bus

Document Number: 002-04696 Rev. *A Page 32 of 105 MB95650L Series P04/INT04/AN04/SIN/EC0 pin This pin has the following peripheral functions:

• External interrupt input pin (INT04)
• 8/12-bit A/D converter analog input pin (AN04)
• LIN-UART data input pin (SIN)
• 8/16-bit composite timer ch. 0 clock input pin (EC0) Block diagram of P04/INT04/AN04/SIN/EC0 PDR0 Pin PDR0 read PDR0 write Executing bit manipulation instruction DDR0 read DDR0 write PUL0 read PUL0 write AIDRL read AIDRL write DDR0 PUL0 AIDRL Stop mode, watch mode (SPL = 1) Peripheral function input Peripheral function input enable (INT04) A/D analog input CMOS Pull-up Internal bus

Document Number: 002-04696 Rev. *A Page 33 of 105 MB95650L Series P06/INT06/TO01 pin This pin has the following peripheral functions:

• External interrupt input pin (INT06)
• 8/16-bit composite timer ch. 0 output pin (TO01) P07/INT07/TO10 pin This pin has the following peripheral functions:
• External interrupt input pin (INT07)
• 8/16-bit composite timer ch. 1 output pin (TO10) Block diagram of P06/INT06/TO01 and P07/INT07/TO10 PDR0 Pin PDR0 read PDR0 write Executing bit manipulation instruction DDR0 read DDR0 write PUL0 read PUL0 write DDR0 PUL0 Stop mode, watch mode (SPL = 1) Peripheral function input Peripheral function input enable (INT06 and INT07) Peripheral function output enable Peripheral function output Hysteresis Pull-up Internal bus

Document Number: 002-04696 Rev. *A Page 34 of 105 MB95650L Series

15.1.3 Port 0 registers

Correspondence between registers and pins for port 0 Register abbreviation Data Read Read by read-modify-write (RMW) instruction Write PDR0 0 Pin state is “L” level. PDR0 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR0 value is “1”. As output port, outputs “H” level. DDR0

0 Port input enabled

1 Port output enabled

0 Pull-up disabled

1 Pull-up enabled

0 Analog input enabled

1 Port input enabled

Correspondence between related register bits and pins Pin name P07 P06 P05 P04 P03 P02 P01 P00 PDR0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DDR0 PUL0 AIDRL - -

Document Number: 002-04696 Rev. *A Page 35 of 105 MB95650L Series

15.1.4 Port 0 operations

Operation as an output port

• A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR0 register to external pins.
• If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set as an output port as it is.
• Reading the PDR0 register returns the PDR0 register value. Operation as an input port
• A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When using a pin shared with the analog input function as an input port, set the corresponding bit in the A/D input disable register (lower) (AIDRL) to “1”.
• If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an input port.
• Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. Operation as a peripheral function output pin
• A pin becomes a peripheral func tion output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR0 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR0 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR0 register corresponding to the input pin of a peripheral function to “0”.
• When using a pin shared with the analog input function as another peripheral function input pin, configure it as an input port by setting the bit in the AIDRL register corresponding to that pin to “1”.
• Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is re- turned. Operation at reset If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin shared with analog input, its port input is disabled because the AIDRL register is initialized to “0”. Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT02 to INT07), the input is enabled and not blocked.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. Operation as an analog input pin
• Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin in the AIDRL register to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions. In addition, set the correspond- ing bit in the PUL0 register to “0”. Operation as an external interrupt input pin
• Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. Operation of the pull-up register Setting the bit in the PUL0 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL0 register.

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15.2 Port 1

Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95650L Series Hardware Manual”.

15.2.1 Port 1 configuration

Port 1 is made up of the following elements.

• General-purpose I/O pins/peripheral function I/O pins
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1) 15.2.2 (2)Block diagrams of port 1 P12/DBG/EC0 pin This pin has the following peripheral functions:
• DBG input pin (DBG)
• 8/16-bit composite timer ch. 0 clock input pin (EC0) Block diagram of P12/DBG/EC0 PDR1 PinPDR1 read PDR1 write Executing bit manipulation instruction DDR1 read DDR1 write DDR1 Stop mode, watch mode (SPL = 1) OD Hysteresis Internal bus Peripheral function input

Document Number: 002-04696 Rev. *A Page 37 of 105 MB95650L Series P14/SDA0 pin This pin has the following peripheral function:

• I 2C bus interface ch. 0 data I/O pin (SDA0) P15/SCL0 pin This pin has the following peripheral function:
• I 2C bus interface ch. 0 clock I/O pin (SCL0) Block diagram of P14/SDA0 and P15/SCL0 PDR1 PDR1 read PDR1 write Executing bit manipulation instruction DDR1 read DDR1 write DDR1 Stop mode, watch mode (SPL = 1) Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output CMOS Pin OD Internal bus

Document Number: 002-04696 Rev. *A Page 38 of 105 MB95650L Series P16/SDA1/UO0 pin This pin has the following peripheral functions:

• I 2C bus interface ch. 1 data I/O pin (SDA1)
• UART/SIO ch. 0 data output pin (UO0) Block diagram of P16/SDA1/UO0 PDR1 PDR1 read PDR1 write Executing bit manipulation instruction DDR1 read DDR1 write DDR1 Stop mode, watch mode (SPL = 1) Internal bus Peripheral function input enable Peripheral function input Peripheral function output enable Peripheral function output I2C function input I2C function input enable I2C function output enable I2C function output UART/SIO function output enable I2C_SEL bit in SYSC2 register UART/SIO function output CMOS Pin N-ch P-ch

Document Number: 002-04696 Rev. *A Page 39 of 105 MB95650L Series P17/SCL1/UI0 pin This pin has the following peripheral functions:

• I 2C bus interface ch. 1 clock I/O pin (SCL1)
• UART/SIO ch. 0 data input pin (UI0) Block diagram of P17/SCL1/UI0 PDR1 PDR1 read PDR1 write Executing bit manipulation instruction DDR1 read DDR1 write DDR1 Stop mode, watch mode (SPL = 1) Internal bus Peripheral function input enable Peripheral function input Peripheral function output enable Peripheral function output I2C function input I2C function input enable I2Cfunction output enable I2C function output UART/SIO function input enable I2C_SEL bit in SYSC2 register UART/SIO function input CMOS Pin N-ch P-ch

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15.2.3 Port 1 registers

*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. Correspondence between registers and pins for port 1 Register abbreviation Data Read Read by read-modify-write (RMW) instruction Write PDR1 0 Pin state is “L” level. PDR1 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR1 value is “1”. As output port, outputs “H” level.* DDR1 Correspondence between related register bits and pins Pin name P17 P16 P15 P14 - P12 - - PDR1 bit7 bit6 bit5 bit4 - bit2 - - DDR1

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15.2.4 Port 1 operations

Operation as an output port

• A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR1 register to external pins.
• If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output port as it is.
• Reading the PDR1 register returns the PDR1 register value. Operation as an input port
• A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an input port.
• Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. Operation as a peripheral function output pin
• A pin becomes a peripheral func tion output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR1 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function to “0”.
• Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. Operation at reset If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled. Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained.

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15.3 Port 6

Port 6 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95650L Series Hardware Manual”.

15.3.1 Port 6 configuration

Port 6 is made up of the following elements.

• General-purpose I/O pins/peripheral function I/O pins
• Port 6 data register (PDR6)
• Port 6 direction register (DDR6)
• Port 6 pull-up register (PUL6)

15.3.2 Block diagrams of port 6

This pin has the following peripheral functions:

• 8/16-bit composite timer ch. 1 output pin (TO10)
• UART/SIO ch. 0 clock I/O pin (UCK0) P63/TO11 pin This pin has the following peripheral function:
• 8/16-bit composite timer ch. 1 output pin (TO11) Block diagram of P62/TO10/UCK0 and P63/TO11 PDR6 Pin PDR6 read PDR6 write Executing bit manipulation instruction DDR6 read DDR6 write PUL6 read PUL6 write DDR6 PUL6 Stop mode, watch mode (SPL = 1) Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Hysteresis Pull-up Internal bus

Document Number: 002-04696 Rev. *A Page 43 of 105 MB95650L Series P64/EC1 pin This pin has the following peripheral function:

• 8/16-bit composite timer ch. 1 clock input pin (EC1) Block diagram of P64/EC1 PDR6 Pin PDR6 read PDR6 write Executing bit manipulation instruction DDR6 read DDR6 write DDR6 Stop mode, watch mode (SPL = 1) Peripheral function input Hysteresis Internal bus

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15.3.3 Port 6 registers

*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. Correspondence between registers and pins for port 6 Register abbreviation Data Read Read by read-modify-write (RMW) instruction Write PDR6 0 Pin state is “L” level. PDR6 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR6 value is “1”. As output port, outputs “H” level.* DDR6 Correspondence between related register bits and pins Pin name - - - P64 P63 P62 - - PDR6 - - - bit4 bit3 bit2 - -DDR6 PUL6

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15.3.4 Port 6 operations

Operation as an output port

• A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDR6 register to external pins.
• If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set as an output port as it is.
• Reading the PDR6 register returns the PDR6 register value. Operation as an input port
• A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an input port.
• Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. Operation as a peripheral function output pin
• A pin becomes a peripheral func tion output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin.
• The pin value can be read from the PDR6 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR6 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. Operation as a peripheral function input pin
• To set a pin as an input port, set the bit in the DDR6 register corresponding to the input pin of a peripheral function to “0”.
• Reading the PDR6 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is re- turned. Operation at reset If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled. Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. Operation of the pull-up register Setting the bit in the PUL6 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL6 register.

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15.4 Port F

Port F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95650L Series Hardware Manual”.

15.4.1 Port F configuration

Port F is made up of the following elements.

• General-purpose I/O pins/peripheral function I/O pins
• Port F data register (PDRF)
• Port F direction register (DDRF)

15.4.2 Block diagrams of port F

This pin has the following peripheral function:

• Main clock input oscillation pin (X0) PF1/X1 pin This pin has the following peripheral function:
• Main clock I/O oscillation pin (X1) Block diagram of PF0/X0 and PF1/X1 PDRF Pin PDRF read PDRF write Executing bit manipulation instruction DDRF read DDRF write DDRF Stop mode, watch mode (SPL = 1) Internal bus Hysteresis

Document Number: 002-04696 Rev. *A Page 47 of 105 MB95650L Series PF2/RST pin This pin has the following peripheral function:

• Reset pin (RST) Block diagram of PF2/RST PDRF PDRF read PDRF write Executing bit manipulation instruction DDRF read DDRF write DDRF Stop mode, watch mode (SPL = 1) Reset input Reset input enable Reset output enable Reset output Pin OD Internal bus Hysteresis

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15.4.3 Port F registers

*: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. Correspondence between registers and pins for port F *: PF2/RST is the dedicated reset pin on MB95F652L/F653L/F654L/F656L. Register abbreviation Data Read Read by read-modify-write (RMW) instruction Write PDRF 0 Pin state is “L” level. PDRF value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRF value is “1”. As output port, outputs “H” level.* DDRF Correspondence between related register bits and pins Pin name - - - - - PF2* PF1 PF0 PDRF ----- b i t 2 b i t 1 b i t 0 DDRF

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15.4.4 Port F operations

Operation as an output port

• A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDRF register to external pins.
• If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output port as it is.
• Reading the PDRF register returns the PDRF register value. Operation as an input port
• A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an input port.
• Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRF register, the PDRF register value is returned. Operation at reset If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled. Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRF register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained.

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15.5 Port G

Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95650L Series Hardware Manual”.

15.5.1 Port G configuration

Port G is made up of the following elements.

• General-purpose I/O pins/peripheral function I/O pins
• Port G data register (PDRG)
• Port G direction register (DDRG)
• Port G pull-up register (PULG)

15.5.2 Block diagram of port G

This pin has the following peripheral function:

• Subclock input oscillation pin (X0A) PG2/X1A pin This pin has the following peripheral function:
• Subclock I/O oscillation pin (X1A) Block diagram of PG1/X0A and PG2/X1A PDRG Pin PDRG read PDRG write Executing bit manipulation instruction DDRG read DDRG write PULG read PULG write DDRG PULG Stop mode, watch mode (SPL = 1) Hysteresis Pull-up Internal bus

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15.5.3 Port G registers

Correspondence between registers and pins for port G Register abbreviation Data Read Read by read-modify-write (RMW) instruction Write PDRG 0 Pin state is “L” level. PDRG value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRG value is “1”. As output port, outputs “H” level. DDRG Correspondence between related register bits and pins Pin name - - - - - PG2 PG1 - PDRG ----- b i t 2 b i t 1 -DDRG PULG

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15.5.4 Port G operations

Operation as an output port

• A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• When a pin is used as an output port, it outputs the value of the PDRG register to external pins.
• If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output port as it is.
• Reading the PDRG register returns the PDRG register value. Operation as an input port
• A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”.
• For a pin shared with other peripheral functions, disable the output of such peripheral functions.
• If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an input port.
• Reading the PDRG register returns the pin va lue. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned. Operation at reset If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled. Operation in stop mode and watch mode
• If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open.
• If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. Operation of the pull-up register Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULG register.

Document Number: 002-04696 Rev. *A Page 53 of 105 MB95650L Series 16. Interrupt Source Table Interrupt source Interrupt request number Vector table address Interrupt level setting register Priority order of interrupt sources of the same level (occurring simultaneously)Upper Lower Register Bit External interrupt ch. 4 IRQ00 0xFFFA 0xFFFB ILR0 L00 [1:0] High Low External interrupt ch. 5 IRQ01 0xFFF8 0xFFF9 ILR0 L01 [1:0] External interrupt ch. 2 IRQ02 0xFFF6 0xFFF7 ILR0 L02 [1:0] External interrupt ch. 6 External interrupt ch. 3 IRQ03 0xFFF4 0xFFF5 ILR0 L03 [1:0] External interrupt ch. 7 Low-voltage detection interrupt circuit IRQ04 0xFFF2 0xFFF3 ILR1 L04 [1:0] UART/SIO ch. 0 8/16-bit composite timer ch. 0 (lower) IRQ05 0xFFF0 0xFFF1 ILR1 L05 [1:0] 8/16-bit composite timer ch. 0 (upper) IRQ06 0xFFEE 0xFFEF ILR1 L06 [1:0] LIN-UART (reception) IRQ07 0xFFEC 0xFFED ILR1 L07 [1:0] LIN-UART (transmission) IRQ08 0xFFEA 0xFFEB ILR2 L08 [1:0] — IRQ09 0xFFE8 0xFFE9 ILR2 L09 [1:0] I 2C bus interface ch. 1 IRQ10 0xFFE6 0xFFE7 ILR2 L10 [1:0] — IRQ11 0xFFE4 0xFFE5 ILR2 L11 [1:0] — IRQ12 0xFFE2 0xFFE3 ILR3 L12 [1:0] — IRQ13 0xFFE0 0xFFE1 ILR3 L13 [1:0] 8/16-bit composite timer ch. 1 (upper) IRQ14 0xFFDE 0xFFDF ILR3 L14 [1:0] — IRQ15 0xFFDC 0xFFDD ILR3 L15 [1:0] I 2C bus interface ch. 0 IRQ16 0xFFDA 0xFFDB ILR4 L16 [1:0] — IRQ17 0xFFD8 0xFFD9 ILR4 L17 [1:0] 8/12-bit A/D converter IRQ18 0xFFD6 0xFFD7 ILR4 L18 [1:0] Time-base timer IRQ19 0xFFD4 0xFFD5 ILR4 L19 [1:0] Watch prescaler IRQ20 0xFFD2 0xFFD3 ILR5 L20 [1:0] — IRQ21 0xFFD0 0xFFD1 ILR5 L21 [1:0] 8/16-bit composite timer ch. 1 (lower) IRQ22 0xFFCE 0xFFCF ILR5 L22 [1:0] Flash memory IRQ23 0xFFC C 0xFFCD ILR5 L23 [1:0]

Document Number: 002-04696 Rev. *A Page 54 of 105 MB95650L Series 17. Pin States in each Mode Pin name Normal operation Sleep mode Stop mode Watch mode On reset SPL=0 SPL=1 SPL=0 SPL=1 PF0/X0 Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z — I/O port*1 I/O port*1 - Previous state kept - Input blocked*1, *2 -H i - Z - Input blocked* 1, *2 - Previous state kept - Input blocked*1, *2 -H i - Z - Input blocked* 1, *2 - Hi-Z - Input enabled* (However, it does not function.) PF1/X1 Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z — I/O port*

1 I/O port*1

• Previous state kept - Input blocked*1, *2 -H i - Z - Input blocked* 1, *2 - Previous state kept - Input blocked*1, *2 -H i - Z - Input blocked* 1, *2 - Hi-Z - Input enabled* (However, it does not function.) PF2/RST Reset input Reset input Reset input Reset input Reset input Reset input Reset input* 4 I/O port*1 I/O port*1 - Previous state kept - Input blocked*1, *2 -H i - Z - Input blocked* 1, *2 - Previous state kept - Input blocked*1, *2 -H i - Z - Input blocked* 1, *2 - Hi-Z - Input enabled* (However, it does not function.) PG1/X0A Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z — I/O port*
• Previous state kept - Input blocked*1, *2 -H i - Z - Input blocked* 1, *2 - Previous state kept - Input blocked*1, *2 -H i - Z - Input blocked* 1, *2 - Hi-Z - Input enabled* (However, it does not function.) PG2/X1A Oscillation input Oscillation input Hi-Z Hi-Z Hi-Z Hi-Z — I/O port*
• Previous state kept - Input blocked*1, *2 -H i - Z - Input blocked* 1, *2 - Previous state kept - Input blocked*1, *2 -H i - Z - Input blocked* 1, *2 - Hi-Z - Input enabled* (However, it does not function.) P00/AN00 I/O port/ peripheral function I/O/ analog input I/O port/ peripheral function I/O/ analog input - Previous state kept - Input blocked* 2, *5 -H i - Z *6 - Input blocked*2, *5 - Previous state kept - Input blocked*2, *5 -H i - Z *6 - Input blocked*2, *5 - Hi-Z - Input blocked*2 P01/AN01 P02/INT02/ AN02/SCK P03/INT03/ AN03/SOT P04/INT04/ AN04/SIN/ EC0 P05/INT05/ AN05/TO00

Document Number: 002-04696 Rev. *A Page 55 of 105 MB95650L Series SPL: Pin state setting bit in the standby control register (STBC:SPL) Hi-Z: High impedance *1: The pin stays at the state shown when configured as a general-purpose I/O port. *2: “Input blocked” means direct input gate operation from the pin is disabled. *3: “Input enabled” means that the input function is enabled. While the input function is enabled, perform a pull-up or pull-down operation in order to prevent leaks due to external input. If a pin is used as an output port, its pin state is the same as that of other ports. *4: The PF2/RST pin stays at the state shown when configured as a reset pin. *5: Though input is blocked, an external interrupt can be input when the external interrupt request is enabled. *6: The pull-up control setting is still effective. *7: The I2C bus interface can wake up the MCU in stop mode or watch mode when its MCU standby mode wakeup function is enabled. For details of the MCU standby mode wakeup function, refer to “Chapter 19 I 2c Bus Interface” in “New 8FX MB95650L Series Hardware Manual”. P06/INT06/ TO01 I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state kept - Input blocked*2, *5 -H i - Z *6 - Input blocked*2, *5 - Previous state kept - Input blocked*2, *5 -H i - Z *6 - Input blocked*2, *5 - Hi-Z - Input blocked*2P07/INT07/ TO10 P14/SDA0 I/O port/ peripheral func- tion I/O I/O port/ peripheral func- tion I/O - Previous state kept - Input blocked* 2, *7 -H i - Z - Input blocked* 2, *7 - Previous state kept - Input blocked*2, *7 -H i - Z - Input blocked* 2, *7 - Hi-Z - Input enabled*3 (However, it does not function.) P15/SCL0 P16/SDA1/ UO0 P17/SCL1/ UI0 P12/DBG/ EC0 I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state kept - Input blocked*2 -H i - Z - Input blocked* - Previous state kept - Input blocked*2 -H i - Z - Input blocked* - Hi-Z - Input enabled*3 (However, it does not function.) P62/TO10/ UCK0 P63/TO11 P64/EC1 Pin name Normal operation Sleep mode Stop mode Watch mode On reset SPL=0 SPL=1 SPL=0 SPL=1

Document Number: 002-04696 Rev. *A Page 56 of 105 MB95650L Series 18. Electrical Characteristics

18.1 Absolute Maximum Ratings

*1: These parameters are based on the condition that VSS is 0.0 V. *2: V1 and V0 must not exceed VCC  0.3 V. V1 must not exceed the rated voltage. However, if the maximum current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating. (Continued) Parameter Symbol Rating Unit Remarks Min Max Power supply voltage*1 VCC VSS 0.3 V SS  6V Input voltage*1 VI VSS 0.3 V SS  6V * 2 Output voltage*1 VO VSS 0.3 V SS  6V * 2 Maximum clamp current I CLAMP 2 2 mA Applicable to specific pins* 3 Total maximum clamp current |ICLAMP| — 20 mA Applicable to specific pins* 3 “L” level maximum output current IOL —1 5 m A “L” level average current IOLAV1 mA Other than P05 to P07, P62 and P63 Average output current = operating current  operating ratio (1 pin) I OLAV2 12 P05 to P07, P62 and P63 Average output current = operating current  operating ratio (1 pin) “L” level total maximum output current IOL —1 0 0 m A “L” level total average output current IOLAV —3 7 m A Total average output current = operating current  operating ratio (Total number of pins) “H” level maximum output current IOH — 15 mA “H” level average current IOHAV1 mA Other than P05 to P07, P62 and P63 Average output current = operating current  operating ratio (1 pin) IOHAV2 8 P05 to P07, P62 and P63 Average output current = operating current  operating ratio (1 pin) “H” level total maximum output current IOH — 100 mA “H” level total average output current IOHAV — 47 mA Total average output current = operating current  operating ratio (Total number of pins) Power consumption P d —3 2 0 m W Operating temperature T A 40 85 C Storage temperature T stg 55 150 C

Document Number: 002-04696 Rev. *A Page 57 of 105 MB95650L Series (Continued) *3: Specific pins: P00 to P07, P14, P15, P62 to P64, PF0, PF1, PG1, PG2

• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the V CC voltage. Always connect a limiting resistor between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption mo des, the HV (High Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit: WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. HV(High Voltage) input (0 V to 16 V) Protective diode VCC N-ch P-ch R Limiting resistor Input/Output equivalent circuit

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18.2 Recommended Operating Conditions

(VSS = 0.0 V) *1: The minimum power supply voltage becomes 2.18 V when a product with the low-voltage detection reset is used or when the on-chip debug mode is used. *2: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. For the connection to a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. WARNING: The recommended operating conditi ons are required in order to ensure th e normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. Parameter Symbol Value Unit Remarks Min Max Power supply voltage V CC 1.8*1 5.5 V In normal operation Decoupling capacitor C S 0.2 10 µF A capacitor of about 1.0 µF is recommended. * 2 Operating temperature T A 40 85 Other than on-chip debug mode 5 35 On-chip debug mode C Cs DBG RST DBG / RST / C pins connection diagram *: Connect the DBG pin to an external pull-up resistor of 2 k  or above. After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor.

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18.3 DC Characteristics

(VCC = 3.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C) (Continued) Parameter Symbol Pin name Condition Value Unit Remarks Min Typ Max “H” level input voltage VIHI1 P04, P16, P17 *1 0.7 V CC —V CC  0.3 V CMOS input level VIHI2 P14, P15 *1 0.7 V CC —V CC  5.5 V CMOS input level VIHS P00 to P03, P05 to P07, P12, P62 to P64, PF0, PF1, PG1, PG2 *1 0.8 V CC —V CC  0.3 V Hysteresis input VIHM PF2 — 0.8 V CC —V CC  0.3 V Hysteresis input “L” level input voltage VILI P04, P14 to P17 *1 V SS 0.3 — 0.3 V CC V CMOS input level VILS P00 to P03, P05 to P07, P12, P62 to P64, PF0, PF1, PG1, PG2 *1 V SS 0.3 — 0.2 V CC V Hysteresis input VILM PF2 — V SS 0.3 — 0.2 V CC V Hysteresis input Open-drain output application voltage VD1 P12, PF2 — V SS 0.3 — V SS  5.5 V VD2 P14, P15 — V SS 0.3 — V SS  5.5 V VD3 P16, P17 — V SS 0.3 — V SS  5.5 V In I 2C mode “H” level output voltage VOH1 Output pins other than P05 to P07, P12, P62, P63 I VOH2 P05 to P07, P62, P63 IOH = 8 mA*3 VCC 0.5 — — V “L” level output voltage VOL1 Output pins other than P05 to P07, P62, P63 I OL = 4 mA*4 —— 0 . 4 V VOL2 P05 to P07, P62, P63 IOL = 12 mA*5 —— 0 . 4 V Input leak current (Hi-Z output leak current) I LI All input pins 0.0 V < V I < VCC 5— 5µ A When the internal pull-up resistor is disabled Internal pull-up resistor RPULL P00 to P07, P62 to P64, PG1, PG2 V I = 0 V 75 100 150 k  When the internal pull-up resistor is enabled Input capacitance C IN Other than VCC and VSS f = 1 MHz — 5 15 pF

Document Number: 002-04696 Rev. *A Page 60 of 105 MB95650L Series (VCC = 3.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C) (Continued) Parameter Symbol Pin name Condition Value Unit Remarks Min Typ*1 Max*6 Power supply current*7 ICC VCC (External clock operation) FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) —4 . 2 6 . 8 m A Except during Flash memory programming and erasing —9 . 3 1 4 . 7 m A During Flash memory programming and erasing — 6 10 mA At A/D conversion ICCS FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) —1 . 7 3m A ICCL FCL = 32 kHz FMPL = 16 kHz Subclock mode (divided by 2) TA = 25 °C —3 56 0 µ A ICCLS FCL = 32 kHz FMPL = 16 kHz Subsleep mode (divided by 2) T A = 25 °C —2 7 µ A ICCT FCL = 32 kHz Watch mode Main stop mode T A = 25 °C —1 6 µ A ICCMCRPLL VCC FMCRPLL = 16 MHz FMP = 16 MHz Main CR PLL clock mode (multiplied by 4) —4 . 3 7 . 7 m A ICCMPLL FMPLL = 16 MHz FMP = 16 MHz Main PLL clock mode (multiplied by 4) —4 . 1 7m A ICCMCR FCRH = 4 MHz FMP = 4 MHz Main CR clock mode —1 . 5 3m A ICCSCR Sub-CR clock mode (divided by 2) T A = 25 °C — 50 100 µA

Document Number: 002-04696 Rev. *A Page 61 of 105 MB95650L Series (VCC = 3.0 V10%, VSS = 0.0 V, TA = 40 °C to 85 °C) *1: VCC = 3.0 V, TA = 25 °C *2: When VCC is smaller than 4.5 V, the condition becomes IOH = 2 mA. *3: When VCC is smaller than 4.5 V, the condition becomes IOH = 4 mA. *4: When VCC is smaller than 4.5 V, the condition becomes IOL = 2 mA. *5: When VCC is smaller than 4.5 V, the condition becomes IOH = 6 mA. *6: VCC = 3.3 V, TA = 85 °C (unless otherwise specified) *7: • The power supply current is determined by the external clock. When the low-voltage detection reset circuit is selected, the power supply current is the sum of adding the current consumption of the low-voltage detection reset circuit (IPLVD) to one of the values from ICC to ICCH. In addition, when the low-voltage detection reset circui t and a CR oscillator are selected, the power supply current is the sum of adding up the current consumption of the low-voltage detection reset circuit (IPLVD), the current consumption of the CR oscillator (I CRH or ICRL) and one of the values from I CC to ICCH. In on-chip debug mode, the main CR oscillator (ICRH) and the low-voltage detection reset circuit are always in operation, and current consumption therefore increases accordingly.

• The power supply current in subclock mode is determined by the external clock. In subclock mode, current consumption in using the crystal oscillator is higher than that in using the external clock. When the crystal oscillator is used, the power supply current is the sum of adding I SOSC (current consumption of the suboscillator) to the power supply current in using the external clock. For details of controlling the subclock, refer to “Chapter 3 Clock Controller” And “chapter 24 System Configuration Register” in “New 8FX MB95650L Series Hardware Manual”. Parameter Symbol Pin name Condition Value Unit Remarks Min Typ*1 Max*6 Power supply current*7 ICCTS VCC (External clock operation) FCH = 32 MHz Time-base timer mode TA = 25 °C — 450 500 µA ICCH Substop mode TA = 25 °C —0 . 7 5µ A IPLVD VCC Current consumption of the low-voltage detection reset circuit in operation —62 6 µ A I ILVD Current consumption of the low-voltage detection interrupt circuit operating in normal mode —61 4 µ A I ILVDL Current consumption of the low-voltage detection interrupt circuit operating in low power consumption mode —31 0 µ A I CRH Current consumption of the main CR oscillator — 270 320 µA ICRL Current consumption of the sub-CR oscillator oscillating at 100 kHz —52 0 µ A ISOSC Current consumption of the suboscillator —0 . 8 7µ A

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18.4 AC Characteristics

18.4.1 Clock Timing

(VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) (Continued) Parameter Symbol Pin name Condition Value Unit Remarks Min Typ Max Clock frequency FCH X0, X1 — 1 — 16.25 MHz When the main oscillation circuit is used X0 — 1 — 32.5 MHz When the main external clock is used X0, X1 — — 4 — MHz When the main PLL clock is used FCRH —— 3.92 4 4.08 MHz Operating conditions

• The main CR clock is used. 3.8 4 4.2 MHz Operating conditions
• The main CR clock is used. FMCRPLL —— 7.84 8 8.16 MHz Operating conditions
• PLL multiplication rate: 2 7.6 8 8.4 MHz Operating conditions
• PLL multiplication rate: 2 9.8 10 10.2 MHz Operating conditions
• PLL multiplication rate: 2.5 9.5 10 10.5 MHz Operating conditions
• PLL multiplication rate: 2.5 11.76 12 12.24 MHz Operating conditions
• PLL multiplication rate: 3 11.4 12 12.6 MHz Operating conditions
• PLL multiplication rate: 3
• 40 15.68 16 16.32 MHz Operating conditions
• PLL multiplication rate: 4 15.2 16 16.8 MHz Operating conditions
• PLL multiplication rate: 4 FMPLL — — 8 — 16 MHz When the main PLL clock is used

Document Number: 002-04696 Rev. *A Page 63 of 105 MB95650L Series (Continued) (VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) Parameter Symbol Pin name Condition Value Unit Remarks Min Typ Max Clock frequency FCL X0A, X1A — — 32.768 — kHz When the suboscillation circuit is used — 32.768 — kHz When the sub-external clock is used FCRL — — 50 100 150 kHz When the sub-CR clock is used Clock cycle time tHCYL X0, X1 — 61.5 — 1000 ns When the main oscillation circuit is used X0 — 30.8 — 1000 ns When an external clock is used X0, X1 — — 250 — ns When the main PLL clock is used t LCYL X0A, X1A — — 30.5 — µs When the subclock is used Input clock pulse width tWH1, tWL1 X0 — 12.4 — — ns When an external clock is used, the duty ratio should range between 40% and 60%. X0, X1 — — 125 — ns When the main PLL clock is used t WH2, tWL2 X0A — — 15.2 — µs When an external clock is used, the duty ratio should range between 40% and 60%. Input clock rising time and falling time tCR, tCF X0, X0A — — — 5 ns When an external clock is used CR oscillation start time tCRHWK — — — — 50 µs When the main CR clock is used tCRLWK — — — — 30 µs When the sub-CR clock is used PLL oscillation start time tMCRPLLWK —— — — 1 0 0 µ s When the main CR PLL clock is used

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0.8 VCC

0.2 VCC 0.2 VCC

0.2 VCC

Input waveform generated when an external clock (main clock) is used X0 X1 FCH FCH When an external clock is used When a crystal oscillator or a ceramic oscillator is used Figure of main clock input port external connection X0A 0.2 VCC 0.2 VCC Input waveform generated when an external clock (subclock) is used When a crystal oscillator or a ceramic oscillator is used When an external clock is used X0A X1A X0A FCL FCL Figure of subclock input port external connection

Document Number: 002-04696 Rev. *A Page 65 of 105 MB95650L Series tCRHWK 1/FCRH Main CR clock Oscillation starts Oscillation stabilizes Input waveform generated when an internal clock (main CR clock) is used tCRLWK 1/FCRL Sub-CR clock Oscillation starts Oscillation stabilizes Input waveform generated when an internal clock (sub-CR clock) is used tMCRPLLWK 1/FMCRPLL Main CR PLL clock Oscillation starts Oscillation stabilizes Input waveform generated when an internal clock (main CR PLL clock) is used

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18.4.2 Source Clock/Machine Clock

(VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) (Continued) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Source clock cycle time*1 tSCLK — 61.5 — 2000 ns When the main external clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 — 250 — ns When the main CR clock is used 62.5 — 250 ns When the main PLL clock is used Min: FCH = 4 MHz, multiplied by 4 Max: FCH = 4 MHz, no division 62.5 — 250 ns When the main CR PLL clock is used Min: FCRH = 4 MHz, multiplied by 4 Max: FCRH = 4 MHz, no division —6 1— µ s When the suboscillation clock is used FCL = 32.768 kHz, divided by 2 —2 0— µ s When the sub-CR clock is used FCRL = 100 kHz, divided by 2 Source clock frequency FSP 0.5 — 16.25 MHz When the main oscillation clock is used — 4 — MHz When the main CR clock is used 4 — 16 MHz When the main PLL clock is used 4 — 16 MHz When the main CR PLL clock is used F SPL — 16.384 — kHz When the suboscillation clock is used — 50 — kHz When the sub-CR clock is used FCRL = 100 kHz, divided by 2 Machine clock cycle time*2 (minimum instruction execution time) t MCLK — 61.5 — 32000 ns When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 250 — 4000 ns When the main CR clock is used Min: FSP = 4 MHz, no division Max: FSP = 4 MHz, divided by 16 62.5 — 4000 ns When the main PLL clock is used Min: FSP = 4 MHz, multiplied by 4 Max: FSP = 4 MHz, divided by 16 62.5 — 4000 ns When the main CR PLL clock is used Min: FSP = 4 MHz, multiplied by 4 Max: FSP = 4 MHz, divided by 16 61 — 976.5 µs When the suboscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 20 — 320 µs When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16

Document Number: 002-04696 Rev. *A Page 67 of 105 MB95650L Series (Continued) (VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be selected from the following.

• Main clock divided by 2
• PLL multiplication of main clock (Select a multiplication rate from 2, 2.5, 3 and 4.)
• Main CR clock
• PLL multiplication of main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.)
• Subclock divided by 2
• Sub-CR clock divided by 2 *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16 Parameter Symbol Pin name Value Unit Remarks Min Typ Max Machine clock frequency FMP 0.031 — 16.25 MHz When the main oscillation clock is used 0.25 — 4 MHz When the main CR clock is used 0.25 — 16 MHz When the main PLL clock is used 0.25 — 16 MHz When the main CR PLL clock is used F MPL 1.024 — 16.384 kHz When the suboscillation clock is used 3.125 — 50 kHz When the sub-CR clock is used FCRL = 100 kHz

Document Number: 002-04696 Rev. *A Page 68 of 105 MB95650L Series FCH (Main oscillation clock) Divided by 2 Divided by 2 Divided by 2 FCRH (Main CR clock) FMCRPLL (Main CR PLL clock) FCL (Suboscillation clock) FCRL (Sub-CR clock) FMPLL (Main PLL clock) SCLK (Source clock) MCLK (Machine clock) Machine clock divide ratio select bits (SYCC:DIV[1:0]) Clock mode select bits (SYCC:SCS[2:0]) Division circuit Schematic diagram of the clock generation block Operating voltage (V) A/D converter operation range 5.5 3 MHz16 kHz 10 MHz 16.25 MHz Source clock frequency (FSP/FSPL) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.8 1.5 0.0 Operating voltage - Operating frequency (TA = 40 °C to 85 °C)

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18.4.3 External Reset

(VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *: See “18.4.2. Source Cl ock/Machine Clock” for tMCLK. Parameter Symbol Value Unit Remarks Min Max RST “L” level pulse width tRSTL 2 tMCLK*  ns

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18.4.4 Power-on Reset

(VSS = 0.0 V, TA = 40 °C to 85 °C) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Power supply rising time dV/dt VCC 0.1 — — V/ms Power supply cutoff time Toff 1— — m s Reset release voltage Vdeth 1.44 1.60 1.76 V At voltage rise Reset detection voltage Vdetl 1.39 1.55 1.71 V At voltage fall Reset release delay time Tond — — 10 ms dV/dt  0.1 mV/µs Reset detection delay time Toffd —— 0 . 4 m s d V / d t  0.04 mV/µs Vdeth VCC Power-on reset Vdetl 0.2 V Toff ToffdTond dV dt 0.2 V

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18.4.5 Peripheral Input Timing

(VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *: See “18.4.2. Source Cl ock/Machine Clock” for tMCLK. Parameter Symbol Pin name Value Unit Min Max Peripheral input “H” pulse width t ILIH INT02 to INT07, EC0, EC1 2 tMCLK*  ns Peripheral input “L” pulse width t IHIL 2 tMCLK*  ns INT02 to INT07, EC0, EC1 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tILIH tIHIL

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18.4.6 LIN-UART Timing

Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “18.4.2. Source Clock/Machine Clock” for tMCLK. Parameter Symbol Pin name Condition Value Unit Min Max Serial clock cycle time t SCYC SCK Internal clock operation output pin: CL = 80 pF  1 TTL 5 tMCLK*3 —n s SCK  SOT delay time t SLOVI SCK, SOT 50 50 ns Valid SIN  SCK tIVSHI SCK, SIN t MCLK*3  80 — ns SCK  valid SIN hold time t SHIXI SCK, SIN 0 — ns Serial clock “L” pulse width t SLSH SCK External clock operation output pin: CL = 80 pF  1 TTL 3 tMCLK*3tR —n s Serial clock “H” pulse width t SHSL SCK t MCLK*3  10 — ns SCK  SOT delay time t SLOVE SCK, SOT — 2 t MCLK*3  60 ns Valid SIN  SCK tIVSHE SCK, SIN 30 — ns SCK  valid SIN hold time t SHIXE SCK, SIN t MCLK*3  30 — ns SCK fall time t F SCK — 10 ns SCK rise time t R SCK — 10 ns

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0.7 VCC

0.3 VCC

0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC tSLOVE tIVSHE tSHIXE

Document Number: 002-04696 Rev. *A Page 74 of 105 MB95650L Series Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2. (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “18.4.2. Source Clock/Machine Clock” for t MCLK. Parameter Symbol Pin name Condition Value Unit Min Max Serial clock cycle time t SCYC SCK Internal clock operation output pin: C L = 80 pF  1 TTL 5 tMCLK*3 —n s SCK  SOT delay time t SHOVI SCK, SOT 50 50 ns Valid SIN  SCK tIVSLI SCK, SIN t MCLK*3  80 — ns SCK valid SIN hold time t SLIXI SCK, SIN 0 — ns Serial clock “H” pulse width t SHSL SCK External clock operation output pin: C L = 80 pF  1 TTL 3 tMCLK*3 tR —n s Serial clock “L” pulse width t SLSH SCK t MCLK*3  10 — ns SCK  SOT delay time t SHOVE SCK, SOT — 2 t MCLK*3  60 ns Valid SIN  SCK tIVSLE SCK, SIN 30 — ns SCK valid SIN hold time t SLIXE SCK, SIN t MCLK*3  30 — ns SCK fall time t F SCK — 10 ns SCK rise time t R SCK — 10 ns

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Document Number: 002-04696 Rev. *A Page 76 of 105 MB95650L Series Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “18.4.2. Source Clock/Machine Clock” for t MCLK. Parameter Symbol Pin name Condition Value Unit Min Max Serial clock cycle time t SCYC SCK Internal clock operation output pin: C L = 80 pF  1 TTL 5 tMCLK*3 —n s SCK SOT delay time t SHOVI SCK, SOT 50 50 ns Valid SIN  SCK tIVSLI SCK, SIN t MCLK*3  80 — ns SCK valid SIN hold time t SLIXI SCK, SIN 0 — ns SOT  SCKdelay time t SOVLI SCK, SOT 3t MCLK*3 70 — ns 0.2 VCC 0.2 VCC tSHOVI tSOVLI tIVSLI tSLIXI

Document Number: 002-04696 Rev. *A Page 77 of 105 MB95650L Series Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2. (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or a falling edge of the serial clock. *2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock. *3: See “18.4.2. Source Clock/Machine Clock” for t MCLK. Parameter Symbol Pin name Condition Value Unit Min Max Serial clock cycle time t SCYC SCK Internal clock operation output pin: C L = 80 pF  1 TTL 5 tMCLK*3 —n s SCK  SOT delay time t SLOVI SCK, SOT 50 50 ns Valid SIN  SCK tIVSHI SCK, SIN t MCLK*3  80 — ns SCK  valid SIN hold time t SHIXI SCK, SIN 0 — ns SOT  SCKdelay time t SOVHI SCK, SOT 3t MCLK*3 70 — ns 0.8 VCC 0.8 VCC tSLOVItSOVHI tIVSHI tSHIXI

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18.4.7 Low-vo ltage Detection

(VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) Parameter Symbol Value Unit Remarks Min Typ Max Reset release voltage V PDL 1.88 2.03 2.18 V At power supply rise Reset detection voltage V PDL 1.8 1.93 2.06 V At power supply fall Interrupt release voltage 0 V IDL0 2.13 2.3 2.47 V At power supply rise Interrupt detection voltage 0 V IDL0 2.05 2.2 2.35 V At power supply fall Interrupt release voltage 1 V IDL1 2.41 2.6 2.79 V At power supply rise Interrupt detection voltage 1 V IDL1 2.33 2.5 2.67 V At power supply fall Interrupt release voltage 2 V IDL2 2.69 2.9 3.11 V At power supply rise Interrupt detection voltage 2 V IDL2 2.61 2.8 2.99 V At power supply fall Interrupt release voltage 3 V IDL3 3.06 3.3 3.54 V At power supply rise Interrupt detection voltage 3 V IDL3 2.98 3.2 3.42 V At power supply fall Interrupt release voltage 4 V IDL4 3.43 3.7 3.97 V At power supply rise Interrupt detection voltage 4 V IDL4 3.35 3.6 3.85 V At power supply fall Interrupt release voltage 5 V IDL5 3.81 4.1 4.39 V At power supply rise Interrupt detection voltage 5 V IDL5 3.73 4 4.27 V At power supply fall Power supply start voltage V off —— 1 . 6 V Power supply end voltage V on 4.39 — — V Power supply voltage change time (at power supply rise) tr 697.5 — — µs Slope of power supply that the reset release signal generates within the rating (VPDL/VIDL) Power supply voltage change time (at power supply fall) tf 697.5 — — µs Slope of power supply that the reset release signal generates within the rating (VPDL/VIDL) Reset release delay time t dp1 — — 30 µs Reset detection delay time t dp2 — — 30 µs Interrupt release delay time t di1 — — 30 µs Interrupt detection delay time t di2 — — 30 µs LVD reset threshold voltage transition stabilization time tstb — — 30 µs

Document Number: 002-04696 Rev. *A Page 79 of 105 MB95650L Series Low power consumption mode (VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) Note: When used for interrupt, the low-voltage detection circ uit can be switched between the normal mode and the low power consumption mode. Compared with the normal mode, while th e low power consumption mode has lower detection voltage accuracy and lower release voltage accuracy, it has the lower power consumption. See “18.3 DC Characteristics” for the difference in current consumption between the normal mode and the low power consumption mode. For details of the method for switching between the normal mode and the low power cons umption mode, refer to “Chapter 17 Low-voltage Detection Circuit” in “New 8FX MB95650L Series Hardware Manual”. Parameter Symbol Value Unit Remarks Min Typ Max Interrupt release voltage 0 V IDLL0 2.06 2.3 2.54 V At power supply rise Interrupt detection voltage 0 V IDLL0 1.98 2.2 2.42 V At power supply fall Interrupt release voltage 1 V IDLL1 2.33 2.6 2.87 V At power supply rise Interrupt detection voltage 1 V IDLL1 2.25 2.5 2.75 V At power supply fall Interrupt release voltage 2 V IDLL2 2.6 2.9 3.2 V At power supply rise Interrupt detection voltage 2 V IDLL2 2.52 2.8 3.08 V At power supply fall Interrupt release voltage 3 V IDLL3 2.96 3.3 3.64 V At power supply rise Interrupt detection voltage 3 V IDLL3 2.88 3.2 3.52 V At power supply fall Interrupt release voltage 4 V IDLL4 3.32 3.7 4.08 V At power supply rise Interrupt detection voltage 4 V IDLL4 3.24 3.6 3.96 V At power supply fall Interrupt release voltage 5 V IDLL5 3.68 4.1 4.52 V At power supply rise Interrupt detection voltage 5 V IDLL5 3.6 4 4.4 V At power supply fall Power supply start voltage V offL —— 1 . 6 V Power supply end voltage V onL 4.52 — — V Power supply voltage change time (at power supply rise) trL 7300 — — µs Slope of power supply that the interrupt release signal generates within the rating (VIDLL) Power supply voltage change time (at power supply fall) tfL 7300 — — µs Slope of power supply that the interrupt detection signal generates within the rating (VIDLL) Interrupt release delay time t diL1 —— 4 0 0 µ s Interrupt detection delay time t diL2 —— 4 0 0 µ s Interrupt threshold voltage transition stabilization time tstbL —— 4 0 0 µ s Interrupt low-voltage detection mode switch time tmdsw —— 4 0 0 µ s Normal mode  Low power consumption mode

Document Number: 002-04696 Rev. *A Page 80 of 105 MB95650L Series tdp2/tdi2/tdiL2 tdp1/tdi1/tdiL1 tr/trLtf/tfL VCC Von/VonL Voff/VoffL VPDL+/VIDL+ VPDL−/VIDL− Time Time Internal reset signal or interrupt signal

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18.4.8 I2C Bus Interface Timing

(VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *1: R represents the pull-up resistor of the SCL0/1 and SDA0/1 lines, and C the load capacitor of the SCL0/1 and SDA0/1 lines. *2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the SCL signal at “L” (tLOW) does not extend. *3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT  250 ns is fulfilled. Parameter Symbol Pin name Condition Value UnitStandard-mode Fast-mode Min Max Min Max SCL clock frequency f SCL SCL0, SCL1 R = 1.7 k, C = 50 pF*1 0 100 0 400 kHz (Repeated) START condition hold time SDA  SCL  tHD;STA SCL0, SCL1, SDA0, SDA1 4.0 — 0.6 — µs SCL clock “L” width t LOW SCL0, SCL1 4.7 — 1.3 — µs SCL clock “H” width t HIGH SCL0, SCL1 4.0 — 0.6 — µs (Repeated) START condition setup time SCL  SDA  tSU;STA SCL0, SCL1, SDA0, SDA1 4.7 — 0.6 — µs Data hold time SCL0, SCL1, SDA0, SDA1 03 . 4 5 *2 00 . 9 *3 µs Data setup time SCL0, SCL1, SDA0, SDA1 0.25 — 0.1 — µs STOP condition setup time SCL   SDA  tSU;STO SCL0, SCL1, SDA0, SDA1 4— 0 . 6 — µ s Bus free time between STOP condition and START condition tBUF SCL0, SCL1, SDA0, SDA1 4.7 — 1.3 — µs SDA0, SDA1 SCL0, SCL1 tWAKEUP tHD;STA tSU;DAT fSCL tHD;STA tSU;STA tLOW tHD;DAT tHIGH tSU;STO tBUF

Document Number: 002-04696 Rev. *A Page 82 of 105 MB95650L Series (VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) (Continued) Parameter Symbol Pin name Condition Value*2 Unit Remarks Min Max SCL clock “L” width tLOW SCL0, SCL1 R = 1.7 k, C = 50 pF*1 (2  nm/2)tMCLK  20 — ns Master mode SCL clock “H” width tHIGH SCL0, SCL1 (nm/2)tMCLK  20 (nm/2)t MCLK  20 ns Master mode START condition hold time t HD;STA SCL0, SCL1, SDA0, SDA1 (-1  nm/2)tMCLK  20 (-1  nm)tMCLK  20 ns Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. STOP condition setup time t SU;STO SCL0, SCL1, SDA0, SDA1 (1  nm/2)tMCLK  20 (1  nm/2)tMCLK  20 ns Master mode START condition setup time t SU;STA SCL0, SCL1, SDA0, SDA1 (1  nm/2)tMCLK  20 (1  nm/2)tMCLK  20 ns Master mode Bus free time between STOP condition and START condition tBUF SCL0, SCL1, SDA0, SDA1 (2 nm  4) tMCLK  20 — ns Data hold time t HD;DAT SCL0, SCL1, SDA0, SDA1 3 t MCLK  20 — ns Master mode

Document Number: 002-04696 Rev. *A Page 83 of 105 MB95650L Series (VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) (Continued) Parameter Symbol Pin name Condition Value*2 Unit Remarks Min Max Data setup time t SU;DAT SCL0, SCL1, SDA0, SDA1 R = 1.7 k C = 50 pF*1 (-2  nm/2) tMCLK  20 (-1  nm/2) tMCLK  20 ns Master mode It is assumed that “L” of SCL is not extended. The minimum value is applied to the first bit of continuous data. Otherwise, the maximum value is applied. Setup time between clearing interrupt and SCL rising t SU;INT SCL0, SCL1 (nm/2) tMCLK  20 (1  nm/2) tMCLK  20 ns The minimum value is applied to the interrupt at the ninth SCL. The maximum value is applied to the interrupt at the eighth SCL. SCL clock “L” width t LOW SCL0, SCL1 4 tMCLK  20 — ns At reception SCL clock “H” width tHIGH SCL0, SCL1 4 tMCLK  20 — ns At reception START condition detection tHD;STA SCL0, SCL1, SDA0, SDA1 2 t MCLK  20 — ns No START condition is detected when 1t MCLK is used at reception. STOP condition detection tSU;STO SCL0, SCL1, SDA0, SDA1 2 t MCLK  20 — ns No STOP condition is detected when 1t MCLK is used at reception. RESTART condition detection condition t SU;STA SCL0, SCL1, SDA0, SDA1 2 t MCLK  20 — ns No RESTART condition is detected when 1 tMCLK is used at reception.

Document Number: 002-04696 Rev. *A Page 84 of 105 MB95650L Series (Continued) (VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *1: R represents the pull-up resistor of the SCL0/SCL1 and SDA0/SDA1 lines, and C the load capacitor of the SCL0/SCL1 and SDA0/SDA1 lines. *2: • See “18.4.2. Source Clock/Machine Clock” for tMCLK.

• m represents the CS[4:3] bits in the I2C clock control register ch. 0/ch. 1 (ICCR0/ICCR1).
• n represents the CS[2:0] bits in the I2C clock control register ch. 0/ch. 1 (ICCR0/ICCR1).
• The actual timing of the I 2C bus interface is determined by the values of m and n set by the machine clock (t MCLK) and the CS[4:0] bits in the ICCR0/ICCR1 register.
• Standard-mode: m and n can be set to values in the following range: 0.9 MHz  tMCLK (machine clock)  16.25 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 MHz < t MCLK  1 MHz (m, n) = (8, 22) : 0.9 MHz < t MCLK  16.25 MHz
• Fast-mode: m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 MHz < t MCLK  4 MHz (m, n) = (1, 22), (5, 4) : 3.3 MHz < t MCLK  8 MHz (m, n) = (5, 8) : 3.3 MHz < t MCLK  16.25 MHz Parameter Symbol Pin name Condition Value*2 Unit Remarks Min Max Bus free time t BUF SCL0, SCL1, SDA0, SDA1 R = 1.7 k, C = 50 pF*1 2 tMCLK  20 — ns At reception Data hold time t HD;DAT SCL0, SCL1, SDA0, SDA1 2 tMCLK  20 — ns At slave transmission mode Data setup time t SU;DAT SCL0, SCL1, SDA0, SDA1 tLOW  3 tMCLK  20 — ns At slave transmission mode Data hold time t HD;DAT SCL0, SCL1, SDA0, SDA1 0 — ns At reception Data setup time t SU;DAT SCL0, SCL1, SDA0, SDA1 tMCLK  20 — ns At reception SDA  SCL (with wakeup function in use) tWAKEUP SCL0, SCL1, SDA0, SDA1 Oscillation stabilization wait time 2 t MCLK  20 —n s

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18.4.9 UART/SIO, Serial I/O Timing

(VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *: See “18.4.2. Source Cl ock/Machine Clock” for tMCLK. Parameter Symbol Pin name Condition Value Unit Min Max Serial clock cycle time t SCYC UCK0 Internal clock operation 4 tMCLK*— n s UCK  UO time t SLOV UCK0, UO0 190 190 ns Valid UI  UCK  tIVSH UCK0, UI0 2 t MCLK*— n s UCK  valid UI hold time t SHIX UCK0, UI0 2 t MCLK*— n s Serial clock “H” pulse width t SHSL UCK0 External clock operation 4 tMCLK*— n s Serial clock “L” pulse width t SLSH UCK0 4 t MCLK*— n s UCK  UO time t SLOV UCK0, UO0 — 190 ns Valid UI  UCK  tIVSH UCK0, UI0 2 t MCLK*— n s UCK  valid UI hold time t SHIX UCK0, UI0 2 t MCLK*— n s 0.2 VCC 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC 0.8 VCC tSLSH tSHSL External shift clock mode

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18.5 A/D Converter

18.5.1 A/D Converter Electrical Characteristics

(VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C) *: See “18.4.2. Notes on Using A/D Converte r” for details of the minimum sampling time. Parameter Symbol Value Unit Remarks Min Typ Max Resolution — — 12 bit Total error 6— 6L S B V CC  2.7 V 10 — 10 LSB V CC  2.7 V Linearity error 3— 3L S B V CC  2.7 V 5— 5L S B V CC  2.7 V Differential linearity error 1.9 — 1.9 LSB V CC  2.7 V 2.9 — 2.9 LSB V CC  2.7 V Zero transition voltage V 0T VSS  6 LSB — V SS  8.2 LSB mV Full-scale transition voltage VFST VCC  6.2 LSB — V CC  9.2 LSB mV Sampling time T S * — 10 µs Compare time T cck 0.861 — 14 µs V CC  2.7 V 2.8 — 14 µs V CC  2.7 V Time of transiting to operation enabled state Tstt 1— — µ s Analog input current I AIN 0.3 — 0.3 µA Analog input voltage V AIN VSS —V CC V

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18.5.2 Notes on Using A/D Converter

External impedance of analog input and its sampling time The A/D converter of the MB95650L Series has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF to the analog input pin. Relationship between external impedance and minimum sampling time The sampling required varies according to external impedance. Ensure that the following condition is met when setting the sampling time. Ts : Sampling time Rin : Input resistance of A/D converter Cin : Input capacitance of A/D converter Rext : Output impedance of external circuit A/D conversion error As |VCC  VSS| decreases, the A/D conversion error increases proportionately. Note: The values are reference values. 4.5 V ≤ VCC ≤ 5.5 V 2.7 V ≤ VCC < 4.5 V 0.9 kΩ (Max) 1.6 kΩ (Max) 13 pF (Max) VCC Rin Cin 13 pF (Max) 1.8 V ≤ VCC < 2.7 V 4.0 kΩ (Max) 13 pF (Max) Comparator Analog input pins (AN00 to AN05)Analog signal source Rin Cin Rext Analog input equivalent circuit

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18.5.3 Definitions of A/D Converter Terms

It indicates the level of analog variation that can be distinguished by the A/D converter. When the number of bits is 12, analog voltage can be divided into 212 = 4096. Linearity error (unit: LSB) It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (“000000000000”   “000000000001”) of a device to the full-scale transition point (“111111111111”   “111111111110”) of the same device. Differential linear error (unit: LSB) It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value. Total error (unit: LSB) It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise. (Continued) VFST Ideal I/O characteristics 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFFDigital output Digital output

2 LSB

1 LSB

0.5 LSB

N VNT : A/D converter digital output value : Voltage at which the digital output transits from 0x(N − 1) to 0xN {1 LSB × (N − 1) + 0.5 LSB} VNT Total error of digital output N VNT − {1 LSB × (N − 1) + 0.5 LSB}

1 LSB LSB=VCC − V SS

4096 V1 LSB =

Document Number: 002-04696 Rev. *A Page 89 of 105 MB95650L Series (Continued) Zero transition error Linearity error Full-scale transition error 0x001 0x002 0x003 0x004 0xFFD 0xFFE 0xFFF Digital output Differential linearity error of digital output N V(N+1)T − V NT

1 LSB − 1=

Linearity error of digital output N VNT − {1 LSB × N + V 0T}

1 LSB=

V0T (measurement value) Actual conversion characteristic Actual conversion characteristic VFST (measurement value) VSS VCC VSS VCC VSS VCC VSS VCC Analog input Digital output Analog input Ideal characteristic {1 LSB × N + V 0T} Actual conversion characteristic Ideal characteristic Actual conversion characteristic V0T (measurement value) VFST (measurement value) VNT Differential linearity error 0x(N−2) 0x(N−1) 0xN 0x(N+1) Digital output Analog input Actual conversion characteristic Ideal characteristic VNT Actual conversion characteristic V(N+1)T N VNT : A/D converter digital output value : Voltage at which the digital output transits from 0x(N − 1) to 0xN V 0T (ideal value) = VSS + 0.5 LSB [V] VFST (ideal value) = VCC − 2 LSB [V] Ideal characteristic

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18.6 Flash Memory Program/Erase Characteristics

*1: VCC = 5.5 V, TA = 25 °C, 0 cycle *2: VCC = 1.8 V, TA = 85 °C, 100000 cycles *3: These values were converted from the result of a technology reliability assessment. (These values were converted from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature being 85 °C.) Parameter Value Unit Remarks Min Typ Max Sector erase time (2 Kbyte sector) —0 . 3 * 1 1.6*2 s The time of writing “0x00” prior to erasure is excluded. Sector erase time (32 Kbyte sector) —0 . 6 * 1 3.1*2 s The time of writing “0x00” prior to erasure is excluded. Byte writing time — 17 272 µs System-level overhead is excluded. Program/erase cycle 100000 — — cycle Power supply voltage at program/erase 1.8 — 5.5 V Flash memory data retention time 20* 3 —— year Average TA = 85 °C Number of program/erase cycles: 1000 or below 10*3 —— Average TA = 85 °C Number of program/erase cycles: 1001 to 10000 inclusive 5*3 —— Average TA = 85 °C Number of program/erase cycles: 10001 or above

Document Number: 002-04696 Rev. *A Page 91 of 105 MB95650L Series 19. Sample Characteristics Power supply current temperature characteristics (Continued) 1234567 ICC[mA] VCC[V] FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz ICC  VCC TA  25 C, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Main clock mode with the external clock operating ICC[mA] FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz −50 0 +50 +100 +150 TA[°C] 1234567 ICCS[mA] VCC[V] FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz ICCS[mA] FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz −50 0 +50 +100 +150 TA[°C] 140 120 100 1234567 ICCL[μA] VCC[V] 140 120 100 ICCL[μA] −50 0 +50 +100 +150 TA[°C] ICC  TA VCC  3.3V, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Main clock mode with the external clock operating ICCS  VCC TA  25 C, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating ICCS  TA VCC  3.3 V, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating ICCL  VCC TA  25 C, FMPL  16 kHz (divided by 2) Subclock mode with the external clock operating ICCL  TA VCC  3.3 V, FMPL  16 kHz (divided by 2) Subclock mode with the external clock operating

Document Number: 002-04696 Rev. *A Page 92 of 105 MB95650L Series ICCT[μA] −50 0 +50 +100 +150 TA[°C] ICCT  TA VCC  3.3 V, FMPL  16 kHz (divided by 2) Watch mode with the external clock operating ICCLS[μA] −50 0 +50 +100 +150 TA[°C] ICCLS  TA VCC  3.3 V, FMPL  16 kHz (divided by 2) Subsleep mode with the external clock operating 1234567 ICCLS[μA] VCC[V] 1234567 ICCT[μA] VCC[V] 200 100 400 300 600 500 1234567 ICCTS[μA] VCC[V] FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 100 300 200 600 500 400 ICCTS[μA] FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz −50 0 +50 +100 +150 TA[°C] ICCLS  VCC TA  25 C, FMPL  16 kHz (divided by 2) Subsleep mode with the external clock operating ICCT  VCC TA  25 C, FMPL  16 kHz (divided by 2) Watch mode with the external clock operating ICCTS  VCC TA  25 C, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Time-base timer mode with the external clock operating ICCTS  TA VCC  3.3 V, FMP  2, 4, 8, 10, 16 MHz (divided by 2) Time-base timer mode with the external clock operating

Document Number: 002-04696 Rev. *A Page 93 of 105 MB95650L Series (Continued) ICCH[μA] −50 0 +50 +100 +150 TA[°C] ICCH  TA VCC  3.3 V, FMPL  (stop) Substop mode with the external clock stopping 1234567 ICCH[μA] VCC[V] 1234567 ICCMCR[mA] VCC[V] ICCMCR[mA] −50 0 +50 +100 +150 TA[°C] 1234567 ICCMCRPLL[mA] VCC[V] ICCMCRPLL[mA] −50 0 +50 +100 +150 TA[°C] ICCH  VCC TA  25 C, FMPL  (stop) Substop mode with the external clock stopping ICCMCR  VCC TA  25 C, FMP  4 MHz (no division) Main CR clock mode ICCMCR  TA VCC  3.3 V, FMP  4 MHz (no division) Main CR clock mode ICCMCRPLL  VCC TA  25 C, FMP  16 MHz (PLL multiplication rate: 4) Main CR PLL clock mode ICCMCRPLL  TA VCC  3.3 V, FMP  16 MHz (PLL multiplication rate: 4) Main CR PLL clock mode

Document Number: 002-04696 Rev. *A Page 94 of 105 MB95650L Series (Continued) 200 150 100 ICCSCR[μA] −50 0 +50 +100 +150 TA[°C] ICCSCR  TA VCC  3.3 V, FMPL  50 kHz (divided by 2) Sub-CR clock mode 100 200 150 1234567 ICCSCR[μA] VCC[V] ICCSCR  VCC TA  25 C, FMPL  50 kHz (divided by 2) Sub-CR clock mode 1234567 ICCMPLL[mA] VCC[V] ICCMPLL[mA] −50 0 +50 +100 +150 TA[°C] ICCMPLL  VCC TA  25 C, FMP  16 MHz (PLL multiplication rate: 4) Main PLL clock mode ICCMPLL  TA VCC  3.3 V, FMP  16 MHz (PLL multiplication rate: 4) Main PLL clock mode

Document Number: 002-04696 Rev. *A Page 95 of 105 MB95650L Series Input voltage characteristics 1 3456 2 VIHI1/VILI[V] VCC[V] VIHI1 VILI 1 3456 2 VIHI2/VILI[V] VCC[V] VIHI2 VILI VIHI1  VCC and VILI  VCC TA  25 C VIHI2  VCC and VILI  VCC TA  25 C 1 3456 2 VIHS/VILS[V] VCC[V] VIHS VILS 1 3456 2 VIHM/VILM[V] VCC[V] VIHM VILM VIHS  VCC and VILS  VCC TA  25 C VIHM  VCC and VILM  VCC TA  25 C

Document Number: 002-04696 Rev. *A Page 96 of 105 MB95650L Series Output voltage characteristics 0.0 0.2 0.4 0.8 1.0 VCC − VOH2[V] IOH[mA] 0.6 VCC = 2.0 V VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V VCC = 4.0 V VCC = 1.8 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V (VCC  VOH2)  IOH TA  25 C VOL1  IOL TA  25 C 0.0 0.2 0.4 0.8 1.0 VCC − VOH1[V] IOH[mA] 0.6 VCC = 2.0 V VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V VCC = 4.0 V VCC = 1.8 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V (VCC  VOH1)  IOH TA  25 C 0.0 0.2 0.4 0.8 1.0 02 13579 4 6 8 1 01 11 21 31 41 5 VOL2[V] IOL[mA] 0.6 VCC = 2.0 V VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V VCC = 4.0 V VCC = 1.8 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V VOL2  IOL TA  25 C 0.0 0.2 0.4 0.8 1.0 02 13579 4 6 8 1 01 11 21 31 41 5 VOL1[V] IOL[mA] 0.6 VCC = 2.0 V VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V VCC = 4.0 V VCC = 1.8 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V

Document Number: 002-04696 Rev. *A Page 97 of 105 MB95650L Series Pull-up characteristics 100 150 300 250 200 21 3456 RPULL[kΩ] VCC[V] RPULL  VCC TA  25 C

Document Number: 002-04696 Rev. *A Page 98 of 105 MB95650L Series 20. Mask Options No. Part number MB95F652E MB95F653E MB95F654E MB95F656E MB95F652L MB95F653L MB95F654L MB95F656L Selectable/Fixed Fixed 1 Low-voltage detection reset/interrupt With low-voltage detection reset/interrupt Without low-voltage detection reset/interrupt

2 Reset Without dedicated reset input With dedicated reset input

Document Number: 002-04696 Rev. *A Page 99 of 105 MB95650L Series 21. Ordering Information Part number Package MB95F652EPFT-G-SNE2 MB95F652LPFT-G-SNE2 MB95F653EPFT-G-SNE2 MB95F653LPFT-G-SNE2 MB95F654EPFT-G-SNE2 MB95F654LPFT-G-SNE2 MB95F656EPFT-G-SNE2 MB95F656LPFT-G-SNE2 24-pin plastic TSSOP (FPT-24P-M10) MB95F652EPF-G-SNE2 MB95F652LPF-G-SNE2 MB95F653EPF-G-SNE2 MB95F653LPF-G-SNE2 MB95F654EPF-G-SNE2 MB95F654LPF-G-SNE2 MB95F656EPF-G-SNE2 MB95F656LPF-G-SNE2 24-pin plastic SOP (FPT-24P-M34) MB95F652EWQN-G-SNE1 MB95F652EWQN-G-SNERE1 MB95F652LWQN-G-SNE1 MB95F652LWQN-G-SNERE1 MB95F653EWQN-G-SNE1 MB95F653EWQN-G-SNERE1 MB95F653LWQN-G-SNE1 MB95F653LWQN-G-SNERE1 MB95F654EWQN-G-SNE1 MB95F654EWQN-G-SNERE1 MB95F654LWQN-G-SNE1 MB95F654LWQN-G-SNERE1 MB95F656EWQN-G-SNE1 MB95F656EWQN-G-SNERE1 MB95F656LWQN-G-SNE1 MB95F656LWQN-G-SNERE1 32-pin plastic QFN (LCC-32P-M19)

Document Number: 002-04696 Rev. *A Page 100 of 105 MB95650L Series 22. Package Dimension (Continued) 24-pin plastic TSSOP Lead pitch 0.65 mm Package width × package length 4.40 mm × 7.80 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.20 mm MAX Weight 0.10 g 24-pin plastic TSSOP (FPT -24P-M10) (FPT-24P-M10) C 2008-2010 FUJITSU SEMICONDUCTOR LIMITED F24033S-c-1-2 0.65(.026) (.173±.004) 4.40±0.10 6.40±0.20 (.252±.008) 0.10(.004) "A" INDEX BTM E-MARK 1 12 24 13 0.22 .008 0.10(.004) .005 0.13 1.20(.047) (.004±.002) 0.60±0.15 (.024±.006) 0~8° Details of "A" part (Stand off) (Mounting height) 0.10±0.05 MAX +0.07 +.003 –0.02 –.001 +0.06 +.002 –0.03 –.001 Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) Pins width and pins thickness include plating thickness. Note 2) Pins width do not include tie bar cutting remainder. Note 3) #: These dimensions do not include resin protrusion.

Document Number: 002-04696 Rev. *A Page 101 of 105 MB95650L Series (Continued) 24-pin plastic SOP Lead pitch 1.27 mm Package width × package length 7.50 mm × 15.34 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 2.80 mm MAX Weight 0.44 g 24-pin plastic SOP (FPT-24P-M34) (FPT-24P-M34) C 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F24034S-c-1-2 0.25(.010) M Details of "A" part INDEX 1.27(.050) 0.10(.004) 0.42±0.07 (.017±.003) 0.27±0.07 (.011±.003) "A" 0.25(.010) 1 12 1324 7.50±0.10 10.20±0.40 (.402±.016) (.295±.004) 2.60 0.15 .006 0.60±0.20 (.024±.008) ø1.20±0.1 DEP0.20 ø.047±.004 DEP.008 .102 –.010 +.008 0~8° –0.25 +0.20 –.002 +.004 –0.05 +0.10 –.004 +.006 –0.10 +0.15 Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) * : These dimensions do not include resin protrusion.

Document Number: 002-04696 Rev. *A Page 102 of 105 MB95650L Series (Continued) 32-pin plastic QFN Lead pitch 0.50 mm Package width × package length 5.00 mm × 5.00 mm Sealing method Plastic mold Mounting height 0.80 mm MAX Weight 0.06 g 32-pin plastic QFN (LCC-32P-M19) (LCC-32P-M19) (.010 ) C 2009-2010 FUJITSU SEMICONDUCTOR LIMITED C32071S-c-1-2 (.197±.004) 5.00±0.10 5.00±0.10 (.197±.004) (3-R0.20) ((3-R.008)) 0.50(.020) 1PIN CORNER (C0.30(C.012)) 0.75±0.05 (0.20(.008)) INDEX AREA 0.40±0.05 (.016±.002) +0.03 –0.02 –.001 +.001 0.02 (.001 ) (.138±.004) 3.50±0.10 3.50±0.10 (.138±.004) (TYP) (.030±.002) +0.05 –0.07 –.003 +.002 0.25 Dimensions in mm (inches). Note: The values in parentheses are reference values.

Document Number: 002-04696 Rev. *A Page 103 of 105 MB95650L Series 23. Major Changes Spansion Publication Number: DS702–00016–3v0-E NOTE: Please see “Document History” about later revised information. Page Section Details

19 Pin Connection

• C p i n Corrected the following statement. The bypass capacitor for the VCC pin must have a capacitance larger than CS. The decoupling capacitor for the VCC pin must have a capacitance equal to or larger than the capacitance of CS.

Electrical Characteristics

1. AC Characteristics (1) Clock Timing Corrected the pin name of the parameter “Input clock rising time and falling time”. X0  X0, X0A

Document Number: 002-04696 Rev. *A Page 104 of 105 MB95650L Series Document History Document Title: MB95650L Series New 8FX 8-bit Microcontrollers Document Number: 002-04696 Revision ECN Orig. of Change Submission Date Description of Change ** — AKIH 06/14/2013 Migrated to Cypress and assigned document number 002-04696. No change to document contents or format. *A 5216808 AKIH 04/12/2016 Updated to Cypress format.

Document Number: 002-04696 Rev. *A Revised April 12, 2016 Page 105 of 105 MB95650L Series © Cypress Semiconductor Corporation, 2012-2016. This document is the property of Cypress Semiconductor Corporation and its subs idiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. Cypress is not liable, in who le or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM® Cortex® Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Lighting & Power Control cypress.com/powerpsoc Memory cypress.com/memory PSoC cypress.com/psoc Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless/RF cypress.com/wireless PSoC®Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support