AM29LV800B_05 AMD | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 49

Technical content

Publication Number 21490 Revision G Amendment 5 Issue Date May 25, 2005 Am29LV800B Data Sheet RETIRED PRODUCT This product has been retired and is not recommended for designs. For new and current designs, S29AL008D supersedes Am29LV800B and is the factory-recommended migration path. Please refer to the S29AL008D datasheet for specifications and ord ering information. Availability of this docu- ment is retained for reference and historical purposes only. July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

THIS PAGE LEFT INTENTIONALLY BLANK.

PRELIMINARY (DRAFT)

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21490 Rev: G Amendment/+5 Issue Date: May 25, 2005 Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS

  • Single power supply operation — 2.7 to 3.6 volt read and write operations for battery-powered applications
  • Manufactured on 0.32 µm process technology — Compatible with 0.5 µm Am29LV800 device
  • High performance — Access times as fast as 70 ns
  • Ultra low power consumption (typical values at 5 MHz) — 200 nA Automatic Sleep mode current — 200 nA standby mode current — 7 mA read current — 15 mA program/e+5rase current
  • Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors
  • Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences
  • Top or bottom boot block configurations available
  • Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses
  • Minimum 1 million write cycle guarantee per sector
  • 20-year data retention at 125 °C — Reliable operation for the life of the system
  • Package option —4 8 - b a l l F B G A — 48-pin TSOP —4 4 - p i n S O — Known Good Die (KGD) (see publication number 21536)
  • Compatibility with JEDEC standards — Pinout and software compatible with single- power supply Flash — Superior inadvertent write protection
  • Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion
  • Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion
  • Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
  • Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data For new designs, S29AL008D supersedes Am29L V800B and is the factory-recommended migration path for this device. Please refer to the S29AL008D Family Datasheet for specifications and ordering information.

4 Am29LV800B

The Am29LV800B is an 8 Mbit, 3.0 volt-only Flash memory organized as 1, 048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The device is also available in Known Good Die (KGD) form. For more information, refer to publication number 21536. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt V CC supply to perform read, program, and erase operations. A stan- dard EPROM programmer can also be used to program and erase the device. This device is manufactured using AMD’s 0.32 µm process technology, and offers all the features and benefits of the Am29LV800, which was manufactured using 0.5 µm process technology. In addition, the Am29LV800B features unlock bypass programming and in-system sector protection/unprotection. The standard device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus conten tion the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the command register using standard microprocessor write timings. Reg ister contents serve as input to an internal state- machine that controls th e erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algo rithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that auto matically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera - tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via pro gramming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any opera - tion in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system micropro cessor to read the boot-up firmware from the Flash memory. The device offers two powe r-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode . Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tun neling. The data is progra mmed using hot electron injection.

6 Am29LV800B

Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part Number Am29LV800B Speed Options Full Voltage Range: VCC = 2.7–3.6 V -70 -90 -120 Max access time, ns (tACC) 70 90 120 Max CE# access time, ns (tCE) 70 90 120 Max OE# access time, ns (tOE) 30 35 50 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA0– A18

This device is also available in Known Good Di e (KGD) form. Refer to publication number 21536 for more information. A15 A18 A14 A13 A12 A11 A10 NC NC WE# RESET# NC NC RY/BY# A17 A16 DQ2 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 A15 A18 A14 A13 A12 A11 A10 NC NC WE# RESET# NC NC RY/BY# A17 A16 DQ2 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 21490G-1 Reverse TSOP Standard TSOP

8 Am29LV800B

This device is also available in Known Good Di e (KGD) form. Refer to publication number 21536 for more information. A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 V SSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5NCNCRESET#WE# DQ11 DQ3DQ10DQ2NCA18NCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# V SSCE#A0A1A2A4A3 RY/BY# A18 A17 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 RESET# WE# A10 A11 A12 A13 A14 A15 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC SO FBGA Top View, Balls Facing Down

Special Handling Instructions for FBGA Package Special handling is required for Flash Memory prod - ucts in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. PIN CONFIGURATION A0–A18 = 19 addresses DQ0–DQ14= 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VSS = Device ground NC = Pin not connected internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A18 CE# OE# WE# RESET# BYTE# RY/BY#

10 Am29LV800B

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Com- bination) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29LV800B T -70 E C TEMPERATURE RANGE C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-free package I = Industrial (–40 °C to +85°C) F = Industrial (–40 °C to +85°C) with Pb-free package E = Extended (–55 °C to +125°C) K = Extended (–55 °C to +125°C) with Pb-free package PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) S = 44-Pin Small Outline Package (SO 044) WB = 48-Ball Fine Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 9 mm package (FBB048) This device is also available in Known Good Die (KGD) form. See publication number 21536 for more information. SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29LV800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP and SO Packages AM29LV800BT-70, AM29LV800BB-70 EC, EI, FC, FI, SC, SI, ED, EF, SD, SF AM29LV800BT-90, AM29LV800BB-90 EC, EI, EE, ED, EF FC, FI, FE, SC, SI, SE, SD, SF, EK, SKAM29LV800BT-120, AM29LV800BB-120 Valid Combinations for FBGA Packages Order Number Package Marking AM29LV800BT-70, AM29LV800BB-70 WBC, WBD, WBI, WBF L800BT70V, L800BB70V C, D, I, F AM29LV800BT-90, AM29LV800BB-90 WBC, WBI, WBD, WBF, WBK, WBE L800BT90V, L800BB90V C, I, D, F K, EAM29LV800BT-120, AM29LV800BB-120 L800BT12V, L800BB12V

describe each of these operations in further detail. Table 1. Am29LV800B Device Bus Operations

  1. Addresses are A18:A0 in word mode (BYTE# = V IH), A18:A-1 in byte mode (BYTE# = VIL).
  2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section. used as an input for the LSB (A-1) address function. memory content occurs during the power transition. command register contents are altered. current specification for reading array data.

0.3 V X X VCC ±

0.3 V X High-Z High-Z High-Z

12 Am29LV800B

The device features an Unlock Bypass mode to facil- itate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the ad dress bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specifica- tion tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteristics” for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at V IH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. In the DC Characteristics table, I CC3 and ICC4 repre- sents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is indepen - dent of the CE#, WE#, and OE# control signals. Stan- dard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all ou tput pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also re sets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (I CC4). If RESET# is held at V IL but not within V SS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algo - rithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase opera tion is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algorithms). The system can read data t RH after the RESET# pin returns to VIH. Refer to the AC Characteri stics tables for RESET# parameters and to Figure 14 for the timing diagram. Output Disable Mode

Table 2. Am29LV800BT Top Boot Block Sector Addresses Table 3. Am29LV800BB Bottom Boot Block Sector Addresses

14 Am29LV800B

tion, through identifier codes output on DQ7–DQ0. accessed in-system through the command register. Table 4. In addition, when verifying sector protection, the corresponding identifier code on DQ7–DQ0. Table 1. This method details on using the autoselect mode. Table 4. Am29LV800B Autoselect Codes (High Voltage Method) The device is shipped with all sectors unprotected. AMD representative for details. ID on address pin A9 and OE#. written for earlier 3.0 volt-only AMD flash devices. contact an AMD representative to request a copy. ously protected sectors to change data in-system.

Figure 1. T emporary Sector Unprotect Operation

  1. All protected sectors unprotected.
  2. All previously protected sectors are protected once

16 Am29LV800B

Figure 2. In-System Sector Protect/

The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 1 for command definitions). In addition, the following hardware data protection measures prevent acci - dental erasure or programming, which might other - wise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When V CC is less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down . The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = V IH or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automat- ically reset to reading array data on power-up. COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 1 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing dia grams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more infor - mation on this mode. The system must issue the reset command to re- enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more infor - mation. The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the opera tion is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase opera - tion, writing the reset command returns the device to reading array data (also applies during Erase Sus - pend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is pro- tected. Table 1 shows the address and data require - ments. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect

18 Am29LV800B

mode (or 02h in byte mode) returns the device code. autoselect mode and return to reading array data. verifies the programmed cell margin. Status” for information on these status bits. reset to reading array data, to ensure data integrity. 20h. The device then enters the unlock bypass mode. sequence, resulting in faster total programming time. Note: See Table 1 for program command sequence. Figure 3. Program Operation

20 Am29LV800B

Sequence” for more information. written after the device has resumed erasing.

  1. See Table 1 for erase command sequence.
  2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

Table 1. Am29LV800B Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A12 uniquely select any sector.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except when reading array or autoselect data, all bus cycles are write operations.
  4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
  5. Address bits A18–A11 are don’t cares for unlock and command cycles, unless PA or SA required.
  6. No unlock or command cycles required when reading array data.
  7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high

(while the device is providing status data).

  1. The fourth cycle of the autoselect command sequence is a read cycle.
  2. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more

10.The Unlock Bypass command is required prior to the Unlock Bypass Program command.

  1. The Unlock Bypass Reset command is requ ired to return to reading array data when the device is in the unlock bypass
  2. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase operation.

  1. The Erase Resume command is valid only during the Erase Suspend mode.

22 Am29LV800B

to read valid status information on DQ7. ignores the selected sectors that are protected. DQ6 while Output Enable (OE#) is asserted low. Table 2 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm.

  1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

  1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm

24 Am29LV800B

might not have been accepted.

  1. Read toggle bit twice to determine whether or not it is
  2. Recheck toggle bit because it may stop toggling as DQ5

Figure 6. T oggle Bit Algorithm

Table 2. Write Operation Status

  1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

  1. DQ7 and DQ2 require a valid address when reading status info rmation. Refer to the appropriate subsection for further de-

26 Am29LV800B

  1. Minimum DC voltage on input or I/O pins is –0.5 V. Duri ng voltage transitions, input or I/O pins may undershoot VSS to –

transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8.

  1. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESET# may

may overshoot to 14.0 V for periods up to 20 ns.

  1. No more than one output may be shorted to ground at a time . Duration of the short circuit should not be greater than one

functionality of the device is guaranteed. Figure 7. Maximum Negative Overshoot Figure 8. Maximum Positive Overshoot

Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enable s the low power mode when addresses remain stable for tACC + 30 ns. 5. Not 100% tested. Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 7 12

1 MHz 2 4

CE# = VIL, OE# = VIH, Word Mode (Notes 2, 3, 5) CE# = VIL, OE# = VIH 15 30 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC±0.3 V 0.2 5 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 VLKO Low VCC Lock-Out Voltage (Note 4) 2.3 2.5 V

28 Am29LV800B

Figure 9. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 10. Ty p i c a l ICC1 vs. Frequency

30 Am29LV800B

Notes: 1. Not 100% tested. 2. See Figure 11 and Table 3 for test specifications. Parameter

Description

JEDEC Std Test Setup -70 -90 -120 Unit tAVAV tRC Read Cycle Time (Note 1) Min 70 90 120 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 70 90 120 ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 120 ns tGLQV tOE Output Enable to Output Delay Max 30 35 50 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 25 30 30 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 25 30 30 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns tCE Outputs WE Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tO

0 VRY/BY#

RESET# tD tO Figure 13. Read Operations Timings

Figure 14. RESET# Timings

32 Am29LV800B

Figure 15. BYTE# Timings for Read Operations Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. BYTE# Timings for Write Operations

Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description -70 -90 -120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 45 45 50 ns tDVWH tDS Data Setup Time Min 35 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 35 50 ns tWHWL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 11 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

34 Am29LV800B

  1. PA = program address, PD = program data, D OUT is the true data at the program address.
  2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

  1. SA = sector address (for Sector Erase), VA = Valid Addr ess for reading status data (see “Write Operation Status”).
  2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

36 Am29LV800B

Figure 19. Data# Polling Timings (During Embedded Algorithms) read cycle, and array data read cycle. Figure 20. T oggle Bit Timings (During Embedded Algorithms)

38 Am29LV800B

Figure 23. Sector Protect/Unprotect

Alternate CE# Controlled Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description -70 -90 -120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 45 50 ns tDVEH tDS Data Setup Time Min 35 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 35 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 11 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

40 Am29LV800B

  1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written
  2. Figure indicates the last two bus cycles of command sequence.
  3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time requ ired to execute the two- or four-bus-cycle sequence for the program command. See Table 1 for further information on command definitions. 6. The device has a guaranteed minimum erase an d program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP AND SO PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 15 s Excludes 00h programming prior to erasure Chip Erase Time 14 s Byte Programming Time 9 300 µs Excludes system level overhead (Note 5) Word Programming Time 11 360 µs Chip Programming Time (Note 3) Byte Mode 9 27 s Word Mode 5.8 17 s Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 6 7.5 pF COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Years 125°C 20 Years

42 Am29LV800B

PHYSICAL DIMENSIONS* TS 048—48-Pin Standard TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. Dwg rev AA; 10/99

TSR048—48-Pin Reverse TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. Dwg rev AA; 10/99

44 Am29LV800B

FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm Dwg rev AF; 10/99

45 Am29LV800B

SO 044—44-Pin Small Outline Package Dwg rev AC; 10/99

Revision E (January 1998) Distinctive Characteristics Changed typical read and program/erase current specifications. Device now has a guaranteed minimum endurance of 1,000,000 write cycles. In-System Sector Protect/Unprotect Algorithm Figure Corrected A6 to 0, Changed wait specification to 150 µs on sector protect and 15 ms on sector unprotect. DC Characteristics Changed typical read and program/erase current specifications. AC Characteristics Alternate CE# Controlled Erase/Program Operations: Changed t CP to 35 ns for 70R, 80, and 90 speed options. Erase and Programming Performance Device now has a guaranteed minimum endurance of 1,000,000 write cycles. Physical Dimensions Corrected dimensions for package length and width in FBGA illustration (standalone data sheet version). Revision E+1 (March 1998) In-System Sector Protect/Unprotect Algorithms Figure In the sector protect algorithm, added a “Reset PLSCNT=1” box in the path from “Protect another sector?” back to setting up the next sector address. DC Characteristics Changed Note 1 to indicate that OE# is at VIH for the listed current. AC Characteristics Erase/Program Operations; Alternate CE# Controlled Erase/Program Operations: Corrected the notes reference for t WHWH1 and tWHWH2. These parameters are 100% tested. Corrected the note reference for t VCS. This parameter is not 100% tested. Temporary Sector Unprotect Table Added note reference for tVIDR. This parameter is not 100% tested. Figure 23, Sector Protect/Unprotect Timing Diagram A valid address is not required for the first write cycle; only the data 60h. Erase and Programming Performance In Note 2, the worst case endurance is now 1 million cycles. Revision F (January 1999) Global Changed references for proc ess technology to “0.32 µm.” Replaced the 70R ns regulated voltage speed option with 70 ns full voltage speed option. Distinctive Characteristics Added 20-year data retention bullet. Connection Diagrams Reverse TSOP: Modified markings. FBGA: Replaced Bump side (bottom) view with top view. Valid Combinations for FBGA Packages: New Table. DC Characteristics—CMOS Compatible ICC1, ICC2, ICC3, ICC4, ICC5: Added Note 2 “Maximum ICC specifications are tested with VCC = VCCmax”. ICC3, ICC4: Deleted VCC = VCCmax. Physical Dimensions Changed package drawing to FBB048. Revision F+1 (February 1999) Physical Dimensions Corrected ball grid layout on FBB048 drawing. Added “048” to drawing title. Revision F+2 (February 1999) Distinctive Characteristics, Operating Ranges Corrected to indicate that the V CC voltage range for all devices is 2.7–3.6 V. Revision F+3 (July 2, 1999) Global Added references to availa bility of device in Known Good Die (KGD) form. Revision F+4 (July 26, 1999) Global Added the 70R speed option, which is available in the extended temperature range. Deleted the extended temperature range from the FBGA valid combinations. Revision G (November 10, 1999) Deleted commercial and industrial temperature ranges from the 70R speed option.

47 Am29LV800B

AC Characteristics—Figure 17. Program Operations Timing and Figure 18. Chip/Sector Erase Operations Deleted tGHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations. Revision G+1 (July 7, 2000) Inserted dashes into ordering part numbers. Deleted burn-in option. Revision G+2 (August 14, 2000) Global Deleted 70R and 80 ns speed options and burn-in option. Revision G+3 (June 4, 2004) Added Lead-free (Pb-free) options to the Tempera - ture range breakout of the OPN table and to the Valid Combinations table. Revision G+4 (January 20, 2005) Added migration statement to cover page and first page of data sheet. Added Colophon. Updated Trademark Revision G+5 (May 25, 2005) Updated migration statement on cover page and first page of data sheet. Updated trademarks. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above- mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies