L6713A HOLTEK | Alldatasheet
Document overview
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- PDF pages: 64
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin settings
- 2.1 Pin connection
- 2.2 Pin description
- 3 Electrical data
- 3.1 Maximum ratings
- 3.2 Thermal data
- 4 Electrical characteristi cs
- 5 VID Tables
- 5.1 Mapping for the Intel VR11 Mode
- 5.2 Voltage identification (VID) for Intel VR11 Mode
- 5.4 Mapping for the AMD 6BIT Mode
- 5.5 Voltage identifications (VID ) codes for AMD 6BIT Mode
- 6 Reference Schematic
- 7 Device description
- 8 Configuring the device
- 8.1 Number of phases selection
- 8.2 DAC Selection
- 9 Power dissipation
- 10 Current reading and current shari ng loop
- 11 Differential remote voltage sensing
Datasheet sections
- 23 Tolerance band (TOB) definition
- 23.1 Controller tolerance (TOB Controller)
- 23.3 Time constant matching error tolerance (TOB TCMatching)
- 23.4 Temperature measurement error (V TC)
- 24 Layout guidelines
- 24.1 Power components and connections
- 24.2 Small signal components and connections
- 25 Embedding L6713A - based VR
- 26 Mechanical data
- 27 Revision history
2/3 Phase controller with embedded drivers for Intel VR10, VR11 and AMD 6 bit CPUs General features ■ Load transient boost (LTB) technology™ to minimize the number of output capacitors (patent pending) ■ Dual-edge asynchronous PWM ■ Selectable 2 or 3 phase operation ■ 0.5% Output voltage accuracy ■ 7/8 bit programmable output up to 1.60000V - Intel VR10.x, VR11 DAC ■ 6 bit programmable output up to 1.5500V - AMD 6 bit DAC ■ High current Integrated gate drivers ■ Full differential current sensing across inductor ■ Embedded VRD thermal monitor ■ Differential remote voltage sensing ■ Dynamic VID management ■ Adjustable voltage offset ■ Low-side-less startup ■ Programmable soft start ■ Programmable over voltage protection ■ Preliminary over voltage protection ■ Programmable over current protection ■ Adjustable switching frequency ■ Output enable ■ SS_END / PGOOD signal ■ TQFP64 10x10mm package with exposed pad
Applications
■ High current VRD for desktop CPUs ■ Workstation and server CPU power supply ■ VRM modules
Description
L6713A implements a two/three phase step-down controller with 180º/120º phase-shift between each phase with integrated high current drivers in a compact 10x10mm body package with exposed pad.The 2 or 3 phase operation can be easily selected through PHASE_SEL pin. Load Transient Boost (LTB) Technology™ (Patent Pending) reduces system cost by providing the fastest response to load transition therefore requiring less bulk and ceramic output capacitors to satisfy load transient requirements. LTB Technology™ can be disabled and in this condition the device works as a dual-edge asynchronous PWM. The device embeds selectable DACs: the output voltage ranges up to 1.60000V (both Intel VR10.x and VR11 DAC) or up to 1.5500V (AMD 6BIT DAC) managing D-VID with ±0.5% output voltage accuracy over line and temperature variations. The controller assures fast protection against load over current and under / over voltage (in this last case also before UVLO). In case of over-current the device turns off all MOSFET and latches the condition. System Thermal Monitor is also provided allowing system protection from over-temperature conditions. TQFP64 (Exposed Pad) Order codes Part number Package Packaging L6713A TQFP64 (Exposed Pad) Tube L6713ATR TQFP64 (Exposed Pad) Tape and reel
1 Block diagram
Figure 1. Block diagram
2 Pin settings
2.1 Pin connection
Figure 2. Pin connection (top view)
2.2 Pin description
Table 1. Pin description 1U G A T E 1 Channel 1 HS driver output. A small series resistors helps in reducing device-dissipated power. 3 N.C. Not internally connected.
4 PHASE3
Channel 3 HS driver return path. 5U G A T E 3 Channel 3 HS driver output. A small series resistors helps in reducing device-dissipated power. 7 N.C. Not internally connected.
8 PHASE2
Channel 2 HS driver return path. the HS driver of channel 2.Leave floating when using 2 Phase operation. A small series resistors helps in reducing device-dissipated power. Leave floating when using 2 Phase operation.
10 BOOT2
Boot capacitor overcharge.Leave floating when using 2 Phase operation. 11 N.C. Not internally connected. 12 N.C. Not internally connected. 13 N.C. Not internally connected. 14 N.C. Not internally connected.
16 PHASE_
SELection Pin.Internally pulled up by 12.5µA(typ) to 5V.
17 OUTEN
OUTput ENable Pin.Internally pulled up by 12.5µA(typ) to 5V. protections are disabled except for Preliminary over voltage. Cycle this pin to recover latch from protections; filter with 1nF (typ) vs. SGND.
18 LTB
20 VSEN
It manages OVP and UVP protections and PGOOD (when applicable). See “Output voltage monitor and protections” Section. pin and VOUT. See “Offset (Optional)” Section for details.
21 DROOP
according to the Current Reading Gain. the current info can be used for other purposes. 23 COMP Error Amplifier Output. Connect with an RF - CF vs. FB. The device cannot be disabled by pulling down this pin. 24 N.C. Not internally connected. 25 N.C. Not internally connected.
26 CS2+
Channel 2 Current Sense Positive Input. Connect through an R-C filter to the phase-side of the channel 2 inductor. Short to SGND or to VOUT when using 2 Phase operation. See “Layout guidelines” Section for proper layout of this connection.
27 CS2-
Channel 2 Current Sense Negative Input. Connect through a Rg resistor to the output-side of the channel 2 inductor. Leave floating when using 2 Phase operation. See “Layout guidelines” Section for proper layout of this connection.
28 CS3+
Channel 3 Current Sense Positive Input. Connect through an R-C filter to the phase-side of the channel 3 inductor. See “Layout guidelines” Section for proper layout of this connection.
29 CS3-
Channel 3 Current Sense Negative Input. Connect through a Rg resistor to the output-side of the channel 3 inductor. See “Layout guidelines” Section for proper layout of this connection.
30 CS1+
Channel 1 Current Sense Positive Input. Connect through an R-C filter to the phase-side of the channel 1 inductor. See “Layout guidelines” Section for proper layout of this connection.
31 CS1-
Channel 1 Current Sense Negative Input. Connect through a Rg resistor to the output-side of the channel 1 inductor. See “Layout guidelines” Section for proper layout of this connection.
32 SS/ LTBG/
Soft Start OSCillator, LTB Gain and AMD selection Pin. It allows selecting between INTEL DACs and AMD DAC. Short to SGND to select AMD DAC otherwise INTEL mode is selected. and See “Load Transient Boost TechnologyTM” Section for details.
33 OVP
Over Voltage Programming Pin. Internally pulled up by 12.5µA(typ) to 5V. Leave floating to use built-in protection thresholds as reported into Table 11. OVP threshold to a fixed voltage according to the ROVP resistor. See “Over voltage and programmable OVP” Section Section for details.
34 VID_SEL
Intel Mode.Internally pulled up by 12.5µA(typ) to 5V. See Table 6) DACs. See “Configuring the device” Section for details. AMD Mode. Not Applicable. Needs to be shorted to SGND.
35 OCSET
also a COCSET capacitor to set a delay for the OCP intervention. See “Over current protection” Section for details. 36 FBG Connect to the negative side of the load to perform remote sense. See “Layout guidelines” Section for proper layout of this connection.
37 OSC/
Frequency is programmed according to the resistor connected from the pin vs. the pin floating programs a switching frequency of 200kHz per phase. condition, cycle VCC or the OUTEN pin. See “Oscillator” Section for details.
38 VID7/DVID
VID7 - Intel Mode. See VID5 to VID0 Section. DVID - AMD Mode. DVID Output. transitions” Section Section for details. 39 VID6 Intel Mode. See VID5 to VID0 Section. AMD Mode. Not Applicable. Needs to be shorted to SGND.
Intel Mode. Voltage IDentification Pins (also applies to VID6, VID7). consequence of the programmed code (See Table 11). more than 1.4V to program a '1'. programmed code (See Table 11). Note. VID6 not used, need to be shorted to SGND.
46 SS_END/
used it can be left floating.
47 VR_HOT
Voltage Regulator HOT. Over Temperature Alarm Signal. Open Drain Output, set free when TM overcomes the Alarm Threshold. Thermal Monitoring Output enabled if Vcc > UVLOVCC. See “Thermal monitor” Section for details and typical connections.
48 VR_FAN
Voltage Regulator FAN. Over Temperature Warning Signal. Open Drain Output, set free when TM overcomes the Warning Threshold. See “Thermal monitor” Section for details and typical connections. VR_FAN and VR_HOT accordingly.Short TM pin to SGND if not used. See “Thermal monitor” Section for details and typical connections. 51 N.C. Not internally connected. 52 N.C. Not internally connected. 53 N.C. Not internally connected.
54 PGND2
Channel 2 LS Driver return path. Connect to Power ground Plane.
55 LGATE2
Leave floating when using 2 Phase operation.
56 VCCDR2
57 VCCDR3
It must be connected to others VCCDRx pins. 59 PGND3 Channel 3 LS Driver return path. Connect to Power ground Plane. 60 PGND1 Channel 1 LS Driver return path. Connect to Power ground Plane.
62 VCCDR1
It must be connected to others VCCDRx pins.
63 PHASE1
Channel 1 HS driver return path. 64 N.C. Not internally connected. with the PCB to dissipate the power necessary to drive the external MOSFETs. Connect to the PGND plane with several VIAs to improve thermal conductivity.
3 Electrical data
3.1 Maximum ratings
3.2 Thermal data
Table 2. Absolute maximum ratings Table 3. Thermal data
4 Electrical characteristics
Table 4. Electrical characteristics
5 VID Tables
5.1 Mapping for the Intel VR11 Mode
5.2 Voltage identification (VID) for Intel VR11 Mode
Table 5. Voltage identification (VID) Mapping for Intel VR11 Mode Table 6. Voltage identification (VID) for Intel VR11 Mode (See Note).
Table 6. Voltage identification (VID) for Intel VR11 Mode (See Note). (continued)
- According to VR11 specs, the device automatically regulates output voltage 19mV lower to avoid any
is than what extracted from the table lowered by 19mV built-in offset. Table 7. Voltage identifications (VID) for Intel VR10 Mode + 6.25mV (See Note).
5.4 Mapping for the AMD 6BIT Mode
5.5 Voltage identifications (V ID) codes for AMD 6BIT Mode
- According to VR10.x specs, the device automaticall y regulates output voltage 19mV lower to avoid any
is than what extracted from the table lowered by 19mVbuilt-in offset. VID7 doesn’t care. Table 8. Voltage identifications (VID) mapping for AMD 6BIT Mode Table 9. Voltage identifications (VID) codes for AMD 6BIT Mode (See Note).
- VID6 Not Applicable, need to be left unconnected.
Table 9. Voltage identifications (VID) codes for AMD 6BIT Mode (See Note). (continued)
6 Reference Schematic
Figure 3. Reference Schematic - Intel VR10.x, VR11 - 3-Phase Operation
Figure 4. Reference Schematic - Intel VR10.x, VR11 - 2-Phase Operation
Figure 5. Reference Schematic - AMD 6BIT - 3-Phase Operation
Figure 6. Reference Schematic - AMD 6BIT - 2-Phase Operation
7 Device description
L6713A is two/three phase PWM controller with embedded high current drivers providing complete control logic and protections for a high performance step-down DC-DC voltage regulator optimized for advanced microprocessor power supply. Multi phase buck is the simplest and most cost-effective topology employable to satisfy the increasing current demand of newer microprocessors and modern high current VRM modules. It allows distributing equally load and power between the phases using smaller, cheaper and most common external power MOSFETs and inductors. Moreover, thanks to the equal phase shift between each phase, the input and output capacitor count results in being reduced. Phase interleaving causes in fact input rms current and output ripple voltage reduction and show an effective output switching frequency increase: the 200kHz free- running frequency per phase, externally adjustable through a resistor, results multiplied on the output by the number of phases. L6713A is a dual-edge asynchronous PWM controller featuring Load Transient Boost (LTB) Technology™ (Patent Pending): the device turns on simultaneously all the phases as soon as a load transient is detected allowing to minimize system cost by providing the fastest response to load transition. Load transition is detected (through LTB pin) measuring the derivate dV/dt of the output voltage and the dV/dt can be easily programmed extending the system design flexibility. Moreover, Load Transient Boost(LTB) Technology™ Gain can be easily modified in order to keep under control the output voltage ring back. LTB Technology™ can be disabled and in this condition the device works as a dual-edge asynchronous PWM. The controller allows to implement a scalable design: a three phase design can be easily downgraded to two phase simply by leaving one phase not mounted and leaving PHASE_SEL pin floating. The same design can be used for more than one project saving development and debug time. In the same manner, a two phase design can be further upgraded to three phase facing with newer and highly-current-demanding applications. L6713A permits easy system design by allowing current reading across inductor in fully differential mode. Also a sense resistor in series to the inductor can be considered to improve reading precision. The current information read corrects the PWM output in order to equalize the average current carried by each phase limiting the error to ±3% over static and dynamic conditions unless considering the sensing element spread. The controller includes multiple DACs, selectable through an apposite pin, allowing compatibility with both Intel VR10,VR11 and AMD 6BIT processors specifications, also performing D-VID transitions accordingly. Low-Side-Less start-up allows soft start over pre-biased output avoiding dangerous current return through the main inductors as well as negative spike at the load side.
L6713A provides a programmable Over-Voltage protection to protect the load from dangerous over stress. It can be externally set to a fixed voltage through an apposite resistor, or it can be set internally, latching immediately by turning ON the lower driver and driving high the FAULT pin. Furthermore, preliminary OVP protection also allows the device to protect load from dangerous OVP when VCC is not above the UVLO threshold. The Over-Current protection is on the total delivered current and causes the device turns OFF all MOSFETs and latches the condition. L6713A provides also system Thermal Monitoring: through an apposite pin the device senses the temperature of the hottest component in the application driving the Warning and the Alarm signal as a consequence. A compact 10 x 10mm body TQFP64 package with exposed thermal pad allows dissipating the power to drive the external MOSFET through the system board.
8 Configuring the device
programming the apposite pin PHASE_SEL and SS/LTBG/AMD pin.
8.1 Number of phases selection
PHASE_SEL pin, as shown in the following table.
8.2 DAC Selection
consequence, the calculated system TOB. ™ Gain (see dedicated sections). Table 10. Number of phases setting. Table 11. DAC Settings (See Note).
according to the selected DAC: See Table 4 for details. according to the selected DAC: See Table 4 for details. Table 12. Intel Mode Configuration (See Note). TechnologyTM” Section for details. (LTB™ Gain = 2, default value). VR10.x + 6.25mV extended DAC. Static info, no dynamic changes allowed. according to Table 6 and Table 7. VID transitions” Section for details. finished. It only indicates soft-start has finished. Table 13. AMD Mode Configuration (See Note). AMD It allows programming AMD 6 BIT DAC. Short to SGND. VID_SEL Not Applicable Need to be shorted to SGND. VID7 / DVID Pulled high when performing a D-VID transition. VID6 Not Applicable Need to be shorted to SGND. VID transitions” Section for details.
9 Power dissipation
L6713A embeds high current MOSFET drivers for both high side and low side MOSFETs: it is then important to consider the power the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. In addition, since the device has an exposed pad to better dissipate the power, the thermal resistance between junction and ambient consequent to the layout is also important: thermal pad needs to be soldered to the PCB ground plane through several VIAs in order to facilitate the heat dissipation. Two main terms contribute in the device power dissipation: bias power and drivers' power. The first one (P DC) depends on the static consumption of the device through the supply pins and it is simply quantifiable as follow (assuming to supply HS and LS drivers with the same VCC of the device): where N is the number of phases. Drivers' power is the power needed by the driver to continuously switch on and off the external MOSFETs; it is a function of the switching frequency and total gate charge of the selected MOSFETs. It can be quantified considering that the total power P SW dissipated to switch the MOSFETs (easy calculable) is dissipated by three main factors: external gate resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance. This last term is the important one to be determined to calculate the device power dissipation. The total power dissipated to switch the MOSFETs results: External gate resistors helps the device to dissipate the switching power since the same power P SW will be shared between the internal driver impedance and the external resistor resulting in a general cooling of the device. When driving multiple MOSFETs in parallel, it is suggested to use one gate resistor for each MOSFET. PDC VCC ICC NI CCDRx⋅ NI BOOTx⋅++()⋅= PSW NF SW QGHS VBOOT⋅ QGLS VCCDRx⋅+()⋅⋅=
Figure 7. L6713A Dissipated power (quiescent + switching).
10 Current reading and current sharing loop
element in different locations without affecting the measurement's accuracy. resistor Rg placed outside the chip between CSx- pin toward the reading points. parallel to the sensing element. PHASEx is the current carried by the relative phase. Figure 8. Current reading connections. INFOx is the current information reproduced internally.
connections are shown in Figure 8. Figure 9. Current sharing loop.
11 Differential remote voltage sensing
be connected directly to the remote sense ground point. compensating motherboard or connector losses. mode coupling for any picked-up noise. Figure 10. Differential remote voltage sensing connections
12 Voltage positioning
obtaining a voltage proportional to the delivered current usable for monitoring purposes. Figure 11. Voltage positioning (left) and droop function (right)
12.1 Offset (Optional)
already introduced during the production stage for the Intel VR10,VR11 Mode. (±0.6% for the AMD DAC) over load and line variations.
Voltage positioning L6713A
12.2 Droop function (Optional)
This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: a static error proportional to the output current causes the output voltage to vary according to the sensed current. As shown in Figure 11, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized.Moreover, more and more high- performance CPUs require precise load-line regulation to perform in the proper way. DROOP function is not then required only to optimize the output filter, but also beacomes a requirement of the load. Connecting DROOP pin and FB pin together, the device forces a current I DROOP, proportional to the read current, into the feedback resistor (RFB+ROFFSET) implementing the load regulation dependence. Since IDROOP depends on the current information about the N phases, the output characteristic vs. load current is then given by (neglecting the OFFSET voltage term): Where DCR is the inductor parasite resistance (or sense resistor when used) and I OUT is the output current of the system. The whole power supply can be then represented by a "real" voltage generator with an equivalent output resistance R DROOP and a voltage value of VREF. RFB resistor can be also designed according to the RDROOP specifications as follow: Droop function is optional, in case it is not desired, the DROOP pin can be disconnected from the FB and an information about the total delivered current becomes available for debugging, and/or current monitoring. When not used, the pin can be shorted to SGND. VOUT VREF RFB ROFFSET+() IDROOP⋅–= VREF RFB ROFFSET+() DCR RFB RDROOP Rg
13 Load Transient Boost Technology TM
immediately after a load transition detection, minimizing the delay intervention. where dVOUT is the output voltage drop due to load transition. keep under control the output voltage ring back. Figure 12. LTB connections (left) and waveform (right). as a dual-edge asynchronous PWM controller.
13.1 LTB Gain modification (Optional)
SS/LTBG/AMD pin has to be modified only after the Soft Start has been finished. a consequence the LTB gain is the default value (LTB Gain = 2). resistors have to be selected to have the desiderated Soft Start time. Figure 13. SS/OSC/LTB connections to mo dify LTB Gain when using INTEL mode.
L6713A Dynamic VID transitions
14 Dynamic VID transitions
The device is able to manage Dynamic VID Code changes that allow Output Voltage modification during normal device operation. OVP and UVP signals (and PGOOD in case of AMD Mode) are masked during every VID transition and they are re-activated after the transition finishes with a 32 clock cycles delay to prevent from false triggering due to the transition. When changing dynamically the regulated voltage (D-VID), the system needs to charge or discharge the output capacitor accordingly. This means that an extra-current I D-VID needs to be delivered, especially when increasing the output regulated voltage and it must be considered when setting the over current threshold. This current can be estimated using the following relationships: where dV OUT is the selected DAC LSB (6.25mV for VR11 and VR10 Extended DAC or 25mV for AMD DAC) and TVID is the time interval between each LSB transition (externally driven). Overcoming the OC threshold during the dynamic VID causes the device to enter the constant current limitation slowing down the output voltage dV/dt also causing the failure in the D-VID test. L6713A checks for VID code modifications (See Figure 14) on the rising edge of an internal additional DVID-clock and waits for a confirmation on the following falling edge. Once the new code is stable, on the next rising edge, the reference starts stepping up or down in LSB increments every VID-clock cycle until the new VID code is reached. During the transition, VID code changes are ignored; the device re-starts monitoring VID after the transition has finished on the next rising edge available. VID-clock frequency (F DVID) depends on the operative mode selected: for Intel Mode it is in the range of 1MHz to assure compatibility with the specifications while, for AMD Mode, this frequency is lowered to about 250kHz. When L6713A performs a D-VID transition in AMD Mode, DVID pin is pulled high as long as the device is performing the transition (also including the additional 32clocks delay) Warning: Warning: if the new VID code is more than 1 LSB different from the previous, the device will execute the transition stepping the reference with the DVID-clock frequency F DVID until the new code has reached: for this reason it is recommended to carefully control the VID change rate in order to carefully control the slope of the output voltage variation especially in Intel Mode. IDV I D– COUT dVOUT dTVID
Figure 14. Dynaminc VID Transitions.
15 Enable and disable
L6713A has three different supplies: VCC pin to supply the internal control logic, VCCDRx to supply the low side drivers and BOOTx to supply the high side drivers. If the voltage at pins VCC and VCCDRx are not above the turn on thresholds specified in the Electrical characteristics, the device is shut down: all drivers keep the MOSFETs OFF to show high impedance to the load. Once the device is correctly supplied, proper operation is assured and the device can be driven by the OUTEN pin to control the power sequencing. Setting the pin free, the device implements a soft start up to the programmed voltage. Shorting the pin to SGND, it resets the device (SS_END/PGOOD is shorted to SGND in this condition) from any latched condition and also disables the device keeping all the MOSFET turned OFF to show high impedance to the load.
16 Soft start
Mode and the output voltage increases accordingly with closed loop regulation. on thresholds and the OUTEN pin is set free. Figure 15. Soft Start
16.1 Intel mode
the main oscillator whose frequency is programmed through the OSC pin. the programmed VID results (See Figure 17 and See Figure 19).
voltage will ramp to the programmed voltage starting from VBOOT.
16.1.1 SS/LTB/AMD connections when using LTB Gain = 2
resistor RSSOSC connected vs. SSEND/PGOOD pin through a signal diode(See Figure 16). Figure 16. SS/LTBG/AMD connections for INTEL mode, when using LTB Gain = 2 connected between SS/LTBG/AMD and SSEND (through a signal diode) in kΩ.
Figure 17. Soft-start time for Intel mode when using R SSOSC, diode versus SSEND.
16.1.2 SS/LTB/AMD connections when using LTB Gain < 2
R1+R2) because until the Soft Start is not finished the Q transistor is OFF (See Figure 18). Figure 18. SS/LTBG/AMD connections for INTEL mode, when using LTB Gain < 2 connected between SS/LTBG/AMD and SGND (RSSOSC = R1 + R2) in kΩ.
Figure 19. Soft-start time for Intel mode when using R SSOSC versus SGND.
16.2 AMD mode
Figure 20. Soft-Start time for AMD mode
16.3 Low-side-less startup
Figure 21. Low-side-less start-up comparison
L6713A Output voltage monitor and protections
17 Output voltage monitor and protections
L6713A monitors through pin VSEN the regulated voltage in order to manage the OVP , UVP and PGOOD (when applicable) conditions. The device shows different thresholds when programming different operation mode (Intel or AMD, See Table 11) but the behavior in response to a protection event is still the same as described below. When using OFFSET funcionality the OVP , UVP and PGOOD thresholds change in according to the OFFSET voltage: Protections are active also during soft-start (See “Soft start” Section) while are masked during D-VID transitions with an additional 32 clock cycle delay after the transition has finished to avoid false triggering.
17.1 Under voltage
If the output voltage monitored by VSEN drops more than -750mV below the programmed reference for more than one clock period, L6713A turns OFF all MOSFETs and latches the condition: to recover it is required to cycle Vcc or the OUTEN pin. This is independent of the selected operative mode.
17.2 Preliminary over voltage
To provide a protection while VCC is below the UVLOVCC threshold is fundamental to avoid damage to the CPU in case of failed HS MOSFETs. In fact, since the device is supplied from the 12V bus, it is basically “blind” for any voltage below the turn-ON threshold (UVLOVCC). In order to give full protection to the load, a preliminary-OVP protection is provided while VCC is within UVLO VCC and UVLOOVP. This protection turns-ON the low side MOSFETs as long as the VSEN pin voltage is greater than 1.800V with a 350mV hysteresis. When set, the protection drives the LS MOSFET with a gate-to-source voltage depending on the voltage applied to VCCDRx and independently by the turn-ON threshold across these pins (UVLO VCCDR). This protection depends also on the OUTEN pin status as detailed in Figure 22. A simple way to provide protection to the output in all conditions when the device is OFF (then avoiding the unprotected red region in Figure 22-Left) consists in supplying the controller through the 5VSB bus as shown in Figure 22-Right: 5VSB is always present before +12V and, in case of HS short, the LS MOSFET is driven with 5V assuring a reliable protection of the load. Preliminary OVP is always active before UVLO VCC for both Intel and AMD Modes. VSEN VOUT ROFFSET() IOFFSET() VOUT TH[]⇒⋅– VSEN TH[] ROFFSET() IOFFSET⋅+==
Figure 22. Output voltage protections and typical principle connections
17.3 Over voltage and programmable OVP
Filter OVP pin with 100pF(max) vs. SGND.
17.4 PGOOD (only for AMD mode)
when the output voltage drops below -300mV of the programmed voltage.
18 Over current protection
supply or OUTEN pin cycling is required to restart operations. Figure 23. OCP Connections (left) and waveforms (right). TYP , See Table 4), the device turns OFF all the MOSFETs and latches the condition. inductor DCR, the process spread and temperature variations of these sensing elements.
19 Oscillator
shift) in order to reduce the input rms current and optimize the output filter definition. load side results in being multiplied by N (number of phases). from (into) the pin considering the internal gain of 6KHz/µA. high switching frequency systems. Figure 24. R
20 Driver section
The integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the equivalent RdsON), maintaining fast switching transition. The drivers for the high-side MOSFETs use BOOTx pins for supply and PHASEx pins for return. The drivers for the low-side MOSFETs use VCCDRx pin for supply and PGNDx pin for return. A minimum voltage at VCCDRx pin is required to start operations of the device. VCCDRx pins must be connected together. The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction time maintaining good efficiency saving the use of Schottky diodes: when the high-side MOSFET turns OFF , the voltage on its source begins to fall; when the voltage reaches 2V, the low-side MOSFET gate drive is suddenly applied. When the low- side MOSFET turns OFF , the voltage at LGATEx pin is sensed. When it drops below 1V, the high-side MOSFET gate drive is suddenly applied. If the current flowing in the inductor is negative, the source of high-side MOSFET will never drop. To allow the turning on of the low-side MOSFET even in this case, a watchdog controller is enabled: if the source of the high-side MOSFET doesn't drop, the low side MOSFET is switched on so allowing the negative current of the inductor to recirculate. This mechanism allows the system to regulate even if the current is negative. The BOOTx and VCCDRx pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND pin) and power ground (PGNDx pin) in order to maximize the switching noise immunity. The separated supply for the different drivers gives high flexibility in MOSFET choice, allowing the use of logic-level MOSFET. Several combination of supply can be chosen to optimize performance and efficiency of the application. Power conversion input is also flexible; 5V, 12V bus or any bus that allows the conversion (See maximum duty cycle limitations) can be chosen freely.
21 System control loop compensation
diagram of the system control loop. Figure 25. Main control loop
- DCR is the Inductor parasitic resistance;
- is the equivalent output resistance determined by the droop function;
- ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR) and the applied load RO;
- ZF(s) is the compensation network impedance;
- ZL(s) is the parallel of the N inductor impedance;
- A(s) is the error amplifier gain;
- is the PWM transfer function where ∆VOSC is the oscillator ramp amplitude and has a typical value of 3V. PWM3 PWM2 PWM1 VREF ERROR AMPLIFIER COMP FB ZF(s) ZFB(s) DROOP IDROOP COUT ROUT CURRENT SHARING DUTY CYCLE CORRECTION IINFO1 IINFO3 IINFO2 (PHASE2 Only applies when using 3-PHASE Operation) GLOOP s() PWM Z F s() RDROOP ZP s()+()⋅⋅ ZP s() ZL s()+[] ZF s() ⎛⎞ RFB⋅+⋅ RDROOP DCR PWM 4 5--- VIN ∆VOSC
LC) and the zero (ωESR) is fixed by ESR and the Droop resistance. Figure 26. Equivalent Control Loop Block Di agram (left) and Bode Diagram (right). C resonance assures a simple -20dB/dec shape of the gain. frequency lower than the above reported zero.
22 Thermal monitor
further temperature increase, also the VR_HOT pin as an alarm condition. system hot-spot in order to be sure to control the hottest point of the VR. thresholds at the desired temperatures. function is enabled if VCC>>UVLOVCC. Figure 27. System thermal monitor typical connections.
L6713A Tolerance band (TOB) definition
23 Tolerance band (TOB) definition
Output voltage load-line varies considering component process variation, system temperature extremes, and age degradation limits. Moreover, individual tolerance of the components also varies among designs: it is then possible to define a Manufacturing Tolerance Band (TOB Manuf) that defines the possible output voltage spread across the nominal load line characteristic. TOBManuf can be sliced into different three main categories: Controller Tolerance, External Current Sense Circuit Tolerance and Time Constant Matching Error Tolerance. All these parameters can be composed thanks to the RSS analysis so that the manufacturing variation on TOB results to be: Output voltage ripple (V P=VPP/2) and temperature measurement error (VTC) must be added to the Manufacturing TOB in order to get the system Tolerance Band as follow: All the component spreads and variations are usually considered at 3σ. Here follows an explanation on how to calculate these parameters for a reference L6713A application.
23.1 Controller tolerance (TOB Controller)
It can be further sliced as follow:
- Reference tolerance. L6713A is trimmed during the production stage to ensure the output voltage to be within k VID = ±0.5% (±0.6% for AMD DAC) over temperature and line variations. In addition, the device automatically adds a -19mV offset (Only for Intel Mode) avoiding the use of any external component. This offset is already included during the trimming process in order to avoid the use of any external circuit to generate this offsets and, moreover, avoiding the introduction of any further error to be considered in the TOB calculation.
- Current Reading Circuit. The device reads the current flowing across the inductor DCR by using its dedicated differential inputs. The current sourced by the VRD is then reproduced and sourced from the DROOP pin scaled down by a proper designed gain as follow: This current multiplied by the R FB resistor connected from FB pin vs. the load allows programming the droop function according to the selected DCR/Rg gain and RFB resistor. Deviations in the current sourced due to errors in the current reading, impacts on the output voltage depending on the size of R FB resistor. The device is trimmed during the production stage in order to guarantee a maximum deviation of kIFB = ±1µA from the nominal value. Controller tolerance results then to be: TOB Manuf TOB Controller
2 TOB CurrSense
++= TOB TOB Manuf VP VTC++= IDROOP DCR TOB Controller VID 19mV–() kVID⋅[] 2 kIDROOP RFB⋅() 2+=
Tolerance band (TOB) definition L6713A 23.2 Ext. current sense circuit tolerance (TOB CurrSense) It can be further sliced as follow:
- Inductor DCR Tolerance (kDCR). Variations in the inductor DCR impacts on the output voltage since the device reads a current that is different from the real current flowing into the sense element. As a results, the controller will source a I DROOP current different from the nominal. The results will be an AVP different from the nominal in the same percentage as the DCR is different from the nominal. Since all the sense elements results to be in parallel, the error related to the inductor DCR has to be divided by the number of phases (N).
- Trans-conductance resistors tolerance (kRg). Variations in the Rg resistors impacts in the current reading circuit gain and so impacts on the output voltage. The results will be an AVP different from the nominal in the same percentage as the Rg is different from the nominal. Since all the sense elements results to be in parallel, and so the three current reading circuits, the error related to the Rg resistors has to be divided by the number of phases (N).
- NTC Initial Accuracy (kNTC_0). Variations in the NTC nominal value at room temperature used for the thermal compensation impacts on the AVP in the same percentage as before. In addition, the benefit of the division by the number of phases N cannot be applied in this case.
- NTC Temperature Accuracy (kNTC). NTC variations from room to hot also impacts on the output voltage positioning. The impact is bigger as big is the temperature variation from room to hot (∆T). All these parameters impacts the AVP , so they must be weighted on the maximum voltage swing from zero load up to the maximum electrical current (V AVP). Total error from external current sense circuit results:
23.3 Time constant matc hing error tolerance (TOBTCMatching)
- Inductance and capacitance Tolerance (kL, kC). Variations in the inductance value and in the value of the capacitor used for the Time Constant Matching causes over/under shoots after a load transient appliance. This impacts the output voltage and then the TOB. Since all the sense elements results to be in parallel, the error related to the time constant mismatch has to be divided by the number of phases (N).
- Capacitance Temperature Variations (kCt). The capacitor used for time constant matching also vary with temperature (∆TC) impacting on the output voltage transients ad before. Since all the sense elements results to be in parallel, the error related to the time constant mismatch has to be divided by the number of phases (N). All these parameters impact the Dynamic AVP , so they must be weighted on the maximum dynamic voltage swing (I dyn). Total error due to time constant mismatch results: TOB CurrSense VAVP 2 kDCR 2 α∆ Tk NTC⋅⋅ ++ +⋅= TOB TCMatching VAVPDyn 2 kL kC kCt ∆TC⋅() 2++
L6713A Tolerance band (TOB) definition
23.4 Temperature me asurement error (VTC)
Error in the measured temperature (for thermal compensation) impacts on the output regulated voltage since the correction form the compensation circuit is not what required to keep the output voltage flat. The measurement error (ε Temp) must be multiplied by the copper temp coefficient (α) and compared with the sensing resistance (RSENSE): this percentage affects the AVP voltage as follow: VTC αε Temp⋅ RSENSE
24 Layout guidelines
Since the device manages control functions and high-current drivers, layout is one of the most important things to consider when designing such high current applications. A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radiation and a proper connection between signal and power ground can optimize the performance of the control loops. Two kind of critical components and connections have to be considered when layouting a VRM based on L6713A: power components and connections and small signal components connections.
24.1 Power components and connections
These are the components and connections where switching and high continuous current flows from the input to the load. The first priority when placing components has to be reserved to this power section, minimizing the length of each connection and loop as much as possible. To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane and anyway realized by wide and thick copper traces: loop must be anyway minimized. The critical components, i.e. the power transistors, must be close one to the other. The use of multi-layer printed circuit board is recommended. Figure 28 shows the details of the power connections involved and the current loops. The input capacitance (C IN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are preferred, MLCC are suggested to be connected near the HS drain. Use proper VIAs number when power traces have to move between different planes on the PCB in order to reduce both parasitic resistance and inductance. Moreover, reproducing the same high-current trace on more than one PCB layer will reduce the parasitic resistance associated to that connection. Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance and resistance associated to the copper trace also adding extra decoupling capacitors along the way to the load when this results in being far from the bulk capacitor bank. Gate traces must be sized according to the driver RMS current delivered to the power MOSFET. The device robustness allows managing applications with the power section far from the controller without losing performances. External gate resistors help the device to dissipate power resulting in a general cooling of the device. When driving multiple MOSFETs in parallel, it is suggested to use one resistor for each MOSFET.
24.2 Small signal components and connections
standard and low-capacitive diodes. Figure 28. Power connections and related connections layout (same for all phases). to get a better precision, to connect the traces as close as possible to the sensing elements. OUT and SGND, on the CSx- line to allow higher layout flexibility.
Embedding L6713A - based VR L6713A
25 Embedding L6713A - based VR
When embedding the VRD into the application, additional care must be taken since the whole VRD is a switching DC/DC regulator and the most common system in which it has to work is a digital system such as MB or similar. In fact, latest MB has become faster and powerful: high speed data bus are more and more common and switching-induced noise produced by the VRD can affect data integrity if not following additional layout guidelines. Few easy points must be considered mainly when routing traces in which high switching currents flow (high switching currents cause voltage spikes across the stray inductance of the trace causing noise that can affect the near traces): Keep safe guarding distance between high current switching VRD traces and data buses, especially if high-speed data bus to minimize noise coupling. Keep safe guard distance or filter properly when routing bias traces for I/O sub-systems that must walk near the VRD. Possible causes of noise can be located in the PHASE connections, MOSFET gate drive and Input voltage path (from input bulk capacitors and HS drain). Also PGND connections must be considered if not insisting on a power ground plane. These connections must be carefully kept far away from noise-sensitive data bus. Since the generated noise is mainly due to the switching activity of the VRM, noise emissions depend on how fast the current switches. To reduce noise emission levels, it is also possible, in addition to the previous guidelines, to reduce the current slope by properly tuning the HS gate resistor and the PHASE snubber network.
26 Mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
Table 14. TQFP64 Mechanical Data Figure 29. Package Dimensions
Table 15. Revision history 03-Mar-2006 1 Initial release.